; -------------------------------------------------------------------------------- ; @Title: AM43xx On-Chip Peripherals ; @Props: Released ; @Author: AMM ; @Changelog: ; 2011-12-14 ; 2013-05-14 ; 2018-10-16 STR ; @Manufacturer: TI - Texas Instruments ; @Doc: xml files and spruhl7.pdf ; @Core: Cortex-A9, PRU ; @Chip: AM43?? ; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: peram43xx.per 12662 2020-12-17 08:09:59Z pegold $ config 16. 8. width 0x0b sif (CPUFAMILY()=="ARM") tree "Core Registers (Cortex-A9MPCore)" width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x0++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" textline " " bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x200++0x0 line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register" rgroup.long c15:0x300++0x0 line.long 0x0 "TLBTR,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries" bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128" textline " " bitfld.long 0x0 0. " nU ,Unified or Separate TLBs" "Unified,Separate" rgroup.long c15:0x500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 8.--11. " ClusterID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "0,1,2,3" rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..." bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported" bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Not supported,Supported,?..." rgroup.long c15:0x0020++0x00 line.long 0x00 "ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..." tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " PARON ,Parity On" "Disabled,Enabled" bitfld.long 0x00 8. " ALIOW ,Enable allocation in one cache way only" "Disabled,Enabled" bitfld.long 0x00 7. " EXCL ,Exclusive cache Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SMP ,Signals if the Cortex-A9 processor is taking part in coherency or not" "0,1" bitfld.long 0x00 3. " FOZ ,Full Of Zero mode Enable" "Disabled,Enabled" bitfld.long 0x00 2. " DP1 ,L1 Dside prefetch Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PH2 ,L2 prefetch hint Enable" "Disabled,Enabled" bitfld.long 0x00 0. " FW ,Cache and TLB maintenance broadcast" "Disabled,Enabled" group.long c15:0x201++0x0 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x11++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 6. " nET ,Not early termination" "Not early,Early" bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" textline " " bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group.long c15:0x111++0x0 line.long 0x0 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted" bitfld.long 0x00 16. " PLE ,NS accesses to the Preload Engine resources control" "Secure,Non-secure" textline " " bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register" "No,Yes" bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted" group.long c15:0x0311++0x00 line.long 0x00 "VCR,Virtualization Control Register" bitfld.long 0x00 8. " AMO ,Abort Mask Override" "0,1" bitfld.long 0x00 7. " IMO ,IRQ Mask Override" "0,1" bitfld.long 0x00 6. " IFO ,FIQ Mask Override" "0,1" group.long c15:0xf++0x0 line.long 0x00 "PCR,Power Control Register" bitfld.long 0x00 8.--10. " MCL ,Max Clock Latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " EDCG ,Enable Dynamic Clock Gating" "Disabled,Enabled" textline " " group.long c15:0x000c++0x00 line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address" group.long c15:0x10c++0x00 line.long 0x0 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address" rgroup.long c15:0x1C++0x0 line.long 0x0 "ISR,Interrupt status Register" bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending" bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending" bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending" group.long c15:0x11c++0x0 line.long 0x00 "VIR,Virtualization Interrupt Register" bitfld.long 0x00 8. " VA ,Virtual Abort" "0,1" bitfld.long 0x00 7. " VI ,Virtual IRQ" "0,1" bitfld.long 0x00 6. " VF ,Virtual FIQ" "0,1" tree.end width 0x0d tree "Memory Management Unit" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" textline " " group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address" bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" textline " " bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address" bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" textline " " bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable" bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable" bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000" textline " " group.long c15:0x3--0x3 line.long 0x0 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" hexmask.long 0x00 0.--31. 1. " DFA ,Data Fault Address" group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " SD ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" hexmask.long 0x00 0.--31. 1. " IFA ,Instruction Fault Address" group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" hexmask.long 0x00 0.--31. 1. " DAFS ,Data Auxiliary Fault Status" group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,AuxiliaryInstruction Fault Status Register" hexmask.long 0x00 0.--31. 1. " IAFS ,Instruction Auxiliary Fault Status" textline " " group.long c15:0xa++0x0 line.long 0x0 "TLBLR,TLB Lockdown Register" bitfld.long 0x0 28.--29. " VICTIM ,Victim Value Increments after Each Tabel Walk" "0,1,2,3" bitfld.long 0x0 0. " P ,Lockdown by Victim or Set Associative Region of TLB" "Associative,Lockdown" group.long c15:0x0047++0x00 line.long 0x00 "PAR,PA Register" hexmask.long 0x00 12.--31. 0x1000 " PA ,Physical Adress" bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable" textline " " bitfld.long 0x00 9. " NS ,Non-secure" "Not secured,Secured" bitfld.long 0x00 7. " SH ,Shareable attribute" "Non-shareable,Shareable" textline " " bitfld.long 0x00 4.--6. " Inner ,Signals region inner attributes" "Noncacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back allocate,Write-through,Write-back" bitfld.long 0x00 2.--3. " Outer ,Signals region outer attributes for normal memory type" "Noncacheable,Write-back allocate,Write-through,Write-back" textline " " bitfld.long 0x00 1. " SS ,Supersection Enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " F ,Translation Successful" "Successful,No successful" textline " " group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attribute 7" "Outer,Inner" bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attribute 6" "Outer,Inner" textline " " bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attribute 5" "Outer,Inner" bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attribute 4" "Outer,Inner" textline " " bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attribute 3" "Outer,Inner" bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attribute 2" "Outer,Inner" textline " " bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attribute 1" "Outer,Inner" bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attribute 0" "Outer,Inner" textline " " bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,?..." textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,?..." bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " group.long c15:0x400f++0x0 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long 0x00 0.--31. 1. " CBA ,Configuration Base Address" textline " " rgroup.long c15:0x000d++0x00 line.long 0x00 "FCSEIDR,FCSE PID Register" hexmask.long.byte 0x00 25.--31. 0x02 " PID ,Process for Fast Context Switch Identification and Specification" group.long c15:0x10d++0x0 line.long 0x0 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID" hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID" group.long c15:0x020d++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRURW ,User Read/Write Thread ID" group.long c15:0x030d++0x00 line.long 0x00 "TPIDRURO,User Read-only Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRURO ,User Read-only Thread ID" group.long c15:0x040d++0x00 line.long 0x00 "TPIDRPRW,Privileged Only Thread ID Register" hexmask.long 0x00 0.--31. 1. " TPIDRPRW ,Privileged Only Thread ID" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 18.--20. " CType7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 15.--17. " CType6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 12.--14. " CType5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 9.--11. " CType4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 6.--8. " CType3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 3.--5. " CType2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 0.--2. " CType1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words" group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction" tree.end width 12. tree "System Performance Monitor" group.long c15:0xC9++0x0 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled" group.long c15:0x1C9++0x0 line.long 0x0 "PMCNTENSET,Count Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x2C9++0x0 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x3C9++0x0 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. " P4 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4C9++0x0 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 5. " P5 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 4. " P4 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" textline " " eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x5C9++0x0 line.long 0x0 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--5. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,CNT4,CNT5,?..." group.long c15:0xD9++0x0 line.long 0x00 "PMCCNTR,Cycle Count Register" hexmask.long 0x00 0.--31. 1. " CCNT ,Cycle Count" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Select Register" hexmask.long.byte 0x00 0.--7. 1. " EVCNT ,Event to count" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" hexmask.long 0x00 0.--31. 1. " PMNX ,Event Count" group.long c15:0xE9++0x0 line.long 0x0 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled" group.long c15:0x1E9++0x0 line.long 0x0 "PMINTENSET,Interrupt Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2E9++0x0 line.long 0x0 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" tree.end width 8. tree "Preload Engine" rgroup.long c15:0x000b++0x00 line.long 0x00 "PLEIDR,PLE ID Register" bitfld.long 0x00 16.--20. " FIFOS ,PLE FIFO size" "Not present,Reserved,Reserved,Reserved,4,Reserved,Reserved,Reserved,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,?..." bitfld.long 0x00 0. " PEP ,Preload Engine presence" "Not present,Present" rgroup.long c15:0x020b++0x00 line.long 0x00 "PLEASR,PLE Activity Status Register" bitfld.long 0x00 0. " R ,PLE Channel running" "Not running,Running" rgroup.long c15:0x040b++0x00 line.long 0x00 "PLEFSR,PLE FIFO Status Register" bitfld.long 0x00 0.--4. " AE ,Number of available entries in the PLE FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x001b++0x00 line.long 0x00 "PLEUAR,Preload Engine User Accessibility Register" bitfld.long 0x00 0. " U ,User accessibility" "Not permited,Permited" group.long c15:0x011b++0x00 line.long 0x00 "PLEPCR,Preload Engine Parameters Control Register" hexmask.long.word 0x00 16.--29. 1. " BSM ,Block size mask" hexmask.long.byte 0x00 8.--15. 1. " BNM ,Block number mask" hexmask.long.byte 0x00 0.--7. 1. " WS ,PLE wait states" tree.end tree "NEON" rgroup.long c15:0x000f++0x00 line.long 0x00 "NEON,NEON busy Register" bitfld.long 0x00 0. " Busy ,NEON busy" "Not busy,Busy" tree.end width 0xb width 9. tree "Debug Registers" tree "Jazelle Register" group.long c14:0x7000++0x0 line.long 0x00 "JIDR,Jazelle ID Register" bitfld.long 0x00 28.--31. " ARCH ,Architecture code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " DESIGN ,Implementor code of the designer of the subarchitecture" textline " " hexmask.long.byte 0x00 12.--19. 1. " SAMAJ ,The subarchitecture code" bitfld.long 0x00 8.--11. " SAMIN ,The subarchitecture minor code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6. " TRTBFR ,Format of the Jazelle Configurable Opcode Translation Table Register" "0,1" bitfld.long 0x00 0.--5. " TRTBSZ ,Size of the Jazelle Configurable Opcode Translation Table Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long c14:0x7001++0x0 line.long 0x00 "JOSCR,Jazelle OS Control Register" bitfld.long 0x00 1. " CV ,Configuration Valid" "Not valid,Valid" bitfld.long 0x00 0. " CD ,Configuration Disabled" "No,Yes" group.long c14:0x7002++0x0 line.long 0x00 "JMCR,Jazelle Main Configuration Register" bitfld.long 0x00 31. " nAR ,Not Array Operations" "Disabled,Enabled" bitfld.long 0x00 30. " FP ,Floating-point opcodes handler" "VM implementation,VFP instructions" bitfld.long 0x00 29. " AP ,Array Pointer" "Handler,Pointer" textline " " bitfld.long 0x00 28. " OP ,Object Pointer" "Handler,Pointer" bitfld.long 0x00 27. " IS ,Index Size" "8 bits,16 bits" bitfld.long 0x00 26. " SP ,Static Pointer" "Handler,Pointer" textline " " bitfld.long 0x00 0. " JE ,Jazelle Enable" "Disabled,Enabled" group.long c14:0x7003++0x0 line.long 0x00 "JPR,Jazelle Parameters Register" bitfld.long 0x00 17.--21. " BSH ,Bounds SHift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12.--16. " sADO ,Signed Array Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--11. " ARO ,Array Reference Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " STO ,STatic Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ODO ,Object Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.long c14:0x7004++0x0 line.long 0x00 "JCOTTRR,Jazelle Configurable Opcode Translation Table Register" bitfld.long 0x00 10.--15. " OPCODE ,Bottom bits of the configurable opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--3. " OPERATION ,Code for the operation" "0,1,2,3,4,5,6,7,8,9,?..." tree.end width 11. tree "Processor Identifier Registers" rgroup c14:0x340--0x340 line.long 0x00 "CPUID,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup c14:0x341--0x341 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DMinLine ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." textline " " bitfld.long 0x00 14.--15. " L1_Ipolicy ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " IMinLine ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup c14:0x343--0x343 line.long 0x00 "TLBTYPE,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILsize ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLsize ,Specifies the number of unified or data TLB lockable entries" textline " " bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128" bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate" rgroup c14:0x348--0x348 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..." rgroup c14:0x349--0x349 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..." rgroup c14:0x34a--0x34a line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..." rgroup c14:0x34c--0x34c line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..." textline " " bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored" textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..." rgroup c14:0x34d--0x34d line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup c14:0x34e--0x34e line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..." rgroup c14:0x34f--0x34f line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup c14:0x350--0x350 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..." rgroup c14:0x351--0x351 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..." rgroup c14:0x352--0x352 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..." rgroup c14:0x353--0x353 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..." rgroup c14:0x354--0x354 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..." tree.end tree "Coresight Management Registers" width 0xC textline " " group c14:0x3c0--0x3c0 line.long 0x0 "ITCTRL,Integration Mode Control Register" bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group c14:0x3e8--0x3e8 line.long 0x0 "CLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set" group c14:0x3e9--0x3e9 line.long 0x0 "CLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared" wgroup c14:0x3ec--0x3ec line.long 0x0 "LAR,Lock Access Register" hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key" rgroup c14:0x3ed--0x3ed line.long 0x0 "LSR,Lock Status Register" bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed" bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored" textline " " bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required" width 0xc rgroup c14:0x3ee--0x3ee line.long 0x0 "AUTHSTATUS,Authentication Status Register" bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented" bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented" bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented" bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented" bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled" width 0xc rgroup c14:0x3f2--0x3f2 line.long 0x0 "DEVID,Device Identifier" bitfld.long 0x00 0.--3. " PCSAMPLE ,Level of Program Counter sampling support (DBGPCSR and DBGCIDSR)" "Not implemented,DBGPCSR,Both,?..." rgroup c14:0x3f3--0x3f3 line.long 0x0 "DEVTYPE,Device Type" hexmask.long.byte 0x0 4.--7. 1. " STPC ,Sub Type: Processor Core" hexmask.long.byte 0x0 0.--3. 1. " MCDL ,Main Class: Debug Logic" rgroup c14:0x3f8--0x3f8 line.long 0x0 "PID0,Peripherial ID0" hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]" rgroup c14:0x3f9--0x3f9 line.long 0x0 "PID1,Peripherial ID1" hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]" hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]" rgroup c14:0x3fa--0x3fa line.long 0x0 "PID2,Peripherial ID2" hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " JEPCD ,JEP 106 ID code" "Not used,Used" textline " " hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]" rgroup c14:0x3fb--0x3fb line.long 0x0 "PID3,Peripherial ID3" hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd" hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified" rgroup c14:0x3f4--0x3f4 line.long 0x0 "PID4,Peripherial ID4" bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" rgroup c14:0x3fc--0x3fc line.long 0x0 "COMPONENTID0,Component ID0" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3fd--0x3fd line.long 0x0 "COMPONENTID1,Component ID1" hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)" hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble" rgroup c14:0x3fe--0x3fe line.long 0x0 "COMPONENTID2,Component ID2" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3ff--0x3ff line.long 0x0 "COMPONENTID3,Component ID3" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" tree.end textline " " width 0x7 rgroup c14:0x000--0x000 line.long 0x0 "DIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x0 16.--19. " Version ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,ARMv7 no ext.,?..." textline " " bitfld.long 0x0 15. " DEVID_IMP ,Debug Device ID Register DBGDEVID implemented" "Not implemented,Implemented" bitfld.long 0x0 14. " NSUHD_IMP ,Secure User halting debug implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 13. " PCSR_IMP ,Program Counter Sampling Register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " SE_IMP ,Security Extensions implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 4.--7. " Variant ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " Revision ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x7 group c14:0x22--0x22 line.long 0x0 "DSCR,Debug Status and Control Register" bitfld.long 0x0 30. " DTRRXfull ,The DTRRX Full Flag" "Empty,Full" bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full" textline " " bitfld.long 0x00 27. " DTRRXfull_l ,The DTRRX Full Flag 1" "Empty,Full" bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full" textline " " bitfld.long 0x0 25. " PIPEADV ,Sticky Pipeline Advance" "No effect,Instruction retired" bitfld.long 0x0 24. " INSTRCOMPL_L ,Latched Instruction Complete" "Executing,Not executing" textline " " bitfld.long 0x0 20.--21. " EXTDCCMODE ,External DCC access mode" "Non-blocking,Stall,Fast,?..." bitfld.long 0x0 19. " ADADISCARD ,Asynchronous Data Aborts Discarded" "Not discarded,Discarded" textline " " bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured" bitfld.long 0x0 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disabled" "No,Yes" textline " " bitfld.long 0x0 16. " SPIDDIS ,Secure Privileged Invasive Debug Disabled" "No,Yes" bitfld.long 0x0 15. " MDBGEN ,Monitor Debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled" bitfld.long 0x0 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " UDCCDIS ,User mode access to Comms Channel disable" "No,Yes" bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "No,Yes" textline " " bitfld.long 0x0 10. " DbgAck ,Force Debug Acknowledge" "Not forced,Forced" bitfld.long 0x0 8. " UND_l ,Sticky Undefined Instruction" "No exception,Exception" textline " " bitfld.long 0x0 7. " ADABORT_l ,Sticky Asynchronous Data Abort" "Not aborted,Aborted" bitfld.long 0x0 6. " SDABORT_l ,Sticky Synchronous Data Abort" "Not aborted,Aborted" textline " " bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Halt request,Breakpoint,Asynchronous Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited" textline " " bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state" width 0x7 if (((data.long(c14:0x00))&0x01000)==0x00000) group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled" bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" else group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled" bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled" bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" endif ;rgroup c14:0x1++0x1 ; line.long 0x0 "DRAR,Debug ROM Address Register" ; hexmask.long 0x0 12.--31. 0x1000 " DBROMPA ,Debug bus ROM physical address" ; bitfld.long 0x0 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid" ; line.long 0x4 "DSAR,Debug Self Address Offset Register" ; hexmask.long 0x4 12.--31. 0x1000 " DBSAOV ,Debug bus self-address offset value" ; bitfld.long 0x4 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid" ;hgroup c14:0x50++0x0 ; hide.long 0x0 "DTR,Data Transfer Register" ; in width 0x7 hgroup c14:0x020--0x020 hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register" in group c14:0x023--0x023 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" wgroup c14:0x21++0x00 line.long 0x00 "ITR,Instruction Transfer Register" hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute" wgroup c14:0x24++0x00 line.long 0x00 "DRCR,Debug Run Control Register" bitfld.long 0x00 4. " CBIUR , Cancel Bus Interface Unit Requests" "Not canceled,Canceled" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared" bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested" rgroup c14:0xc4++0x00 line.long 0x00 "PRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 2. " HNDLR ,Hold non-debug logic reset" "No reset,Reset" bitfld.long 0x00 1. " WRR ,Warm reset request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high" hgroup c14:0xc5++0x00 hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register" in tree.end width 6. tree "Breakpoint Registers" group c14:0x40++0x00 line.long 0x00 "BVR0,Breakpoint Value Register 0" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group c14:0x50++0x00 line.long 0x00 "BCR0,Breakpoint Control Register 0" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x41++0x00 line.long 0x00 "BVR1,Breakpoint Value Register 1" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group c14:0x51++0x00 line.long 0x00 "BCR1,Breakpoint Control Register 1" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x42++0x00 line.long 0x00 "BVR2,Breakpoint Value Register 2" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group c14:0x52++0x00 line.long 0x00 "BCR2,Breakpoint Control Register 2" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x43++0x00 line.long 0x00 "BVR3,Breakpoint Value Register 3" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group c14:0x53++0x00 line.long 0x00 "BCR3,Breakpoint Control Register 3" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x44++0x00 line.long 0x00 "BVR4,Breakpoint Value Register 4" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group c14:0x54++0x00 line.long 0x00 "BCR4,Breakpoint Control Register 4" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x45++0x00 line.long 0x00 "BVR5,Breakpoint Value Register 5" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group c14:0x55++0x00 line.long 0x00 "BCR5,Breakpoint Control Register 5" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end width 6. tree "Watchpoint Control Registers" group c14:0x60++0x00 line.long 0x00 "WVR0,Watchpoint Value Register 0" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group c14:0x70--0x70 line.long 0x0 "WCR0,Watchpoint Control Register 0" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x61++0x00 line.long 0x00 "WVR1,Watchpoint Value Register 1" hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1" group c14:0x71--0x71 line.long 0x0 "WCR1,Watchpoint Control Register 1" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x62++0x00 line.long 0x00 "WVR2,Watchpoint Value Register 2" hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2" group c14:0x72--0x72 line.long 0x0 "WCR2,Watchpoint Control Register 2" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x63++0x00 line.long 0x00 "WVR3,Watchpoint Value Register 3" hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3" group c14:0x73--0x73 line.long 0x0 "WCR3,Watchpoint Control Register 3" bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x006--0x006 line.long 0x0 "WFAR,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction" tree.end width 0xb width 9. base ad:(d.l(c15:0x400f)) tree "Snoop Control Unit (SCU)" group.long 0x00++0x03 line.long 0x00 "SCUCR,SCU Control Register" bitfld.long 0x00 6. " ICSE ,IC standby enable" "Disabled,Enabled" bitfld.long 0x00 5. " SCUSE ,SCU standby enable" "Disabled,Enabled" bitfld.long 0x00 4. " FADTP0E ,Force all Device to port0 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SCUSLE ,SCU Speculative linefills enable" "Disabled,Enabled" bitfld.long 0x00 2. " SCURPE ,SCU RAMs Parity enable" "Disabled,Enabled" bitfld.long 0x00 1. " AFE ,Address filtering enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SCUE ,SCU enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SCUCON,SCU Configuration Register" bitfld.long 0x00 14.--15. " RAM3 ,Cortex-A9 CPU3 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 12.--13. " RAM2 ,Cortex-A9 CPU2 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 10.--11. " RAM1 ,Cortex-A9 CPU1 Tag RAM Size" "16KB,32KB,64KB,?..." textline " " bitfld.long 0x00 8.--9. " RAM0 ,Cortex-A9 CPU0 Tag RAM Size" "16KB,32KB,64KB,?..." bitfld.long 0x00 7. " MOD3 ,CPU3 Mode" "AMP,SMP" bitfld.long 0x00 6. " MOD2 ,CPU2 Mode" "AMP,SMP" textline " " bitfld.long 0x00 5. " MOD1 ,CPU1 Mode" "AMP,SMP" bitfld.long 0x00 4. " MOD0 ,CPU0 Mode" "AMP,SMP" bitfld.long 0x00 0.--1. " NUM ,CPU Number" "CPU0,CPU0-CPU1,CPU0-CPU2,CPU0-CPU3" group.long 0x08++0x03 line.long 0x00 "SCUSTAT,SCU CPU Power Status Register" bitfld.long 0x00 24.--25. " STAT3 ,CPU3 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 16.--17. " STAT2 ,CPU2 Status" "Normal,Reserved,Dormant,Powered-off" textline " " bitfld.long 0x00 8.--9. " STAT1 ,CPU1 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 0.--1. " STAT0 ,CPU0 Status" "Normal,Reserved,Dormant,Powered-off" wgroup.long 0x0c++0x03 line.long 0x00 "INV,SCU Invalidate All Register" bitfld.long 0x00 12.--15. " WAY3 ,Cortex-A9 CPU3 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " WAY2 ,Cortex-A9 CPU2 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " WAY1 ,Cortex-A9 CPU1 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " WAY0 ,Cortex-A9 CPU0 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x03 line.long 0x00 "FSAR,Filtering Start Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FSA ,Filtering start address" group.long 0x44++0x03 line.long 0x00 "FEAR,Filtering End Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FEA ,Filtering end address" group.long 0x50++0x03 line.long 0x00 "SAC,SCU Access Control Register" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" group.long 0x54++0x03 line.long 0x00 "SSAC,SCU Secure Access Control Register" bitfld.long 0x00 11. " GCPU3 ,Global timer for CPU3" "Secure only,Secure/Non-secure" bitfld.long 0x00 10. " GCPU2 ,Global timer for CPU2" "Secure only,Secure/Non-secure" bitfld.long 0x00 9. " GCPU1 ,Global timer for CPU1" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 8. " GCPU0 ,Global timer for CPU0" "Secure only,Secure/Non-secure" bitfld.long 0x00 7. " TCPU3 ,Private timer for CPU3 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 6. " TCPU2 ,Private timer for CPU2 Access" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 5. " TCPU1 ,Private timer for CPU1 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 4. " TCPU0 ,Private timer for CPU0 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" tree.end width 0xb width 8. tree "Timer and Watchdog Blocks" base ad:(d.l(c15:0x400f))+0x600 group.long 0x00++0xb "Timer" line.long 0x00 "TLR,Timer Load Register" line.long 0x04 "TCR,Timer Counter Register" line.long 0x08 "TCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " AREL ,Auto reload" "Single shot,Auto-reload" bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "TISR,Timer Interrupt Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x20++0x13 "Watchdog" line.long 0x00 "WLR,Watchdog Load Register" line.long 0x04 "WCR,Watchdog Counter Register" line.long 0x08 "WCONR,Watchdog Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " WDM ,WD Mode" "Timer,Watchdog" bitfld.long 0x08 2. " ITEN ,IT Enable" "Disabled,Enabled" bitfld.long 0x08 1. " AREL ,Auto-Reload" "Single shot,Auto-reload" textline " " bitfld.long 0x08 0. " WEN ,Watchdog Enable" "Disabled,Enabled" line.long 0x0c "WISR,Watchdog Interrupt Status Register" eventfld.long 0x0C 0. " EFLAG ,Event Flag" "0,1" line.long 0x10 "WRSR,Watchdog Reset Sent Register" eventfld.long 0x10 0. " RFLAG ,Reset Flag" "No effect,Reset" wgroup.long 0x34++0x3 line.long 0x00 "WDR,Watchdog Disable Register" base ad:(d.l(c15:0x400f))+0x200 group.long 0x00++0xb "Global Timer" line.long 0x00 "GTLCR,Lower 32-bit Timer Counter Register" line.long 0x04 "GTUCR,Upper 32-bit Timer Counter Register" line.long 0x08 "GTCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "GTSR,Timer Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x10++0xb line.long 0x00 "GTLCOMR,Lower 32-bit Comparator Register" line.long 0x04 "GTUCOMR,Upper 32-bit Comparator Register" line.long 0x08 "GTINCR,Auto-increment Register for Comparator" tree.end width 11. tree.open "Interrupt Controller (PL-390)" width 17. base AD:0x48241000 tree "Distributor Interface" if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" else rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" endif rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..." hexmask.long.word 0x00 12.--23. 1. " REV_NUM ,Returns the revision number of the GIC" textline " " hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure) width 17. tree "Group/Security Registers" group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else hgroup.long 0x0084++0x03 hide.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else hgroup.long 0x0088++0x03 hide.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else hgroup.long 0x008C++0x03 hide.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else hgroup.long 0x0090++0x03 hide.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else hgroup.long 0x0094++0x03 hide.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else hgroup.long 0x0098++0x03 hide.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else hgroup.long 0x009C++0x03 hide.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else hgroup.long 0x00A0++0x03 hide.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else hgroup.long 0x00A4++0x03 hide.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else hgroup.long 0x00A8++0x03 hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else hgroup.long 0x00AC++0x03 hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else hgroup.long 0x00B0++0x03 hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else hgroup.long 0x00B4++0x03 hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else hgroup.long 0x00B8++0x03 hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else hgroup.long 0x00BC++0x03 hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else hgroup.long 0x00C0++0x03 hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else hgroup.long 0x00C4++0x03 hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else hgroup.long 0x00C8++0x03 hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else hgroup.long 0x00CC++0x03 hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else hgroup.long 0x00D0++0x03 hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else hgroup.long 0x00D4++0x03 hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else hgroup.long 0x00D8++0x03 hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else hgroup.long 0x00DC++0x03 hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else hgroup.long 0x0E0++0x03 hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else hgroup.long 0x00E4++0x03 hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else hgroup.long 0x00E8++0x03 hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else hgroup.long 0x00EC++0x03 hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else hgroup.long 0x0F0++0x03 hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else hgroup.long 0x00F4++0x03 hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else hgroup.long 0x00F8++0x03 hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)==0x1F) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1" else hgroup.long 0x00FC++0x03 hide.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end endif width 24. tree "Set/Clear Enable Registers" group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else hgroup.long 0x0104++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else hgroup.long 0x0108++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else hgroup.long 0x010C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else hgroup.long 0x0110++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else hgroup.long 0x0114++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else hgroup.long 0x0118++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else hgroup.long 0x011C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else hgroup.long 0x0120++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else hgroup.long 0x0124++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else hgroup.long 0x0128++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else hgroup.long 0x012C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else hgroup.long 0x0130++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else hgroup.long 0x0134++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else hgroup.long 0x0138++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else hgroup.long 0x013C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else hgroup.long 0x0140++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else hgroup.long 0x0144++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else hgroup.long 0x0148++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else hgroup.long 0x014C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else hgroup.long 0x0150++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else hgroup.long 0x0154++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else hgroup.long 0x0158++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else hgroup.long 0x015C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else hgroup.long 0x0160++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else hgroup.long 0x0164++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else hgroup.long 0x0168++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else hgroup.long 0x016C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else hgroup.long 0x0170++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else hgroup.long 0x0174++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else hgroup.long 0x0178++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)==0x1F) group.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled" else hgroup.long 0x017C++0x03 hide.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 22. tree "Set/Clear Pending Registers" group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Disabled,Enabled" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Disabled,Enabled" else hgroup.long 0x0204++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Disabled,Enabled" else hgroup.long 0x0208++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Disabled,Enabled" else hgroup.long 0x020C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Disabled,Enabled" else hgroup.long 0x0210++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Disabled,Enabled" else hgroup.long 0x0214++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Disabled,Enabled" else hgroup.long 0x0218++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Disabled,Enabled" else hgroup.long 0x021C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Disabled,Enabled" else hgroup.long 0x0220++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Disabled,Enabled" else hgroup.long 0x0224++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Disabled,Enabled" else hgroup.long 0x0228++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Disabled,Enabled" else hgroup.long 0x022C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Disabled,Enabled" else hgroup.long 0x0230++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Disabled,Enabled" else hgroup.long 0x0234++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Disabled,Enabled" else hgroup.long 0x0238++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Disabled,Enabled" else hgroup.long 0x023C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Disabled,Enabled" else hgroup.long 0x0240++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Disabled,Enabled" else hgroup.long 0x0244++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Disabled,Enabled" else hgroup.long 0x0248++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Disabled,Enabled" else hgroup.long 0x024C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Disabled,Enabled" else hgroup.long 0x0250++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Disabled,Enabled" else hgroup.long 0x0254++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Disabled,Enabled" else hgroup.long 0x0258++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Disabled,Enabled" else hgroup.long 0x025C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Disabled,Enabled" else hgroup.long 0x0260++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Disabled,Enabled" else hgroup.long 0x0264++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Disabled,Enabled" else hgroup.long 0x0268++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Disabled,Enabled" else hgroup.long 0x026C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Disabled,Enabled" else hgroup.long 0x0270++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Disabled,Enabled" else hgroup.long 0x0274++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Disabled,Enabled" else hgroup.long 0x0278++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)==0x1F) group.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Disabled,Enabled" else hgroup.long 0x027C++0x03 hide.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 24. tree "Set/Clear Active Registers" rgroup.long 0x0300++0x03 line.long 0x0 "GICD_ICDABR0,Active Status Register 0" bitfld.long 0x00 31. " ASB31 ,Active Status Bit 31" "Not active,Active" bitfld.long 0x00 30. " ASB30 ,Active Status Bit 30" "Not active,Active" bitfld.long 0x00 29. " ASB29 ,Active Status Bit 29" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB28 ,Active Status Bit 28" "Not active,Active" bitfld.long 0x00 27. " ASB27 ,Active Status Bit 27" "Not active,Active" bitfld.long 0x00 26. " ASB26 ,Active Status Bit 26" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB25 ,Active Status Bit 25" "Not active,Active" bitfld.long 0x00 24. " ASB24 ,Active Status Bit 24" "Not active,Active" bitfld.long 0x00 23. " ASB23 ,Active Status Bit 23" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB22 ,Active Status Bit 22" "Not active,Active" bitfld.long 0x00 21. " ASB21 ,Active Status Bit 21" "Not active,Active" bitfld.long 0x00 20. " ASB20 ,Active Status Bit 20" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB19 ,Active Status Bit 19" "Not active,Active" bitfld.long 0x00 18. " ASB18 ,Active Status Bit 18" "Not active,Active" bitfld.long 0x00 17. " ASB17 ,Active Status Bit 17" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB16 ,Active Status Bit 16" "Not active,Active" bitfld.long 0x00 15. " ASB15 ,Active Status Bit 15" "Not active,Active" bitfld.long 0x00 14. " ASB14 ,Active Status Bit 14" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB13 ,Active Status Bit 13" "Not active,Active" bitfld.long 0x00 12. " ASB12 ,Active Status Bit 12" "Not active,Active" bitfld.long 0x00 11. " ASB11 ,Active Status Bit 11" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB10 ,Active Status Bit 10" "Not active,Active" bitfld.long 0x00 9. " ASB9 ,Active Status Bit 9" "Not active,Active" bitfld.long 0x00 8. " ASB8 ,Active Status Bit 8" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB7 ,Active Status Bit 7" "Not active,Active" bitfld.long 0x00 6. " ASB6 ,Active Status Bit 6" "Not active,Active" bitfld.long 0x00 5. " ASB5 ,Active Status Bit 5" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB4 ,Active Status Bit 4" "Not active,Active" bitfld.long 0x00 3. " ASB3 ,Active Status Bit 3" "Not active,Active" bitfld.long 0x00 2. " ASB2 ,Active Status Bit 2" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB1 ,Active Status Bit 1" "Not active,Active" bitfld.long 0x00 0. " ASB0 ,Active Status Bit 0" "Not active,Active" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" bitfld.long 0x00 31. " ASB63 ,Active Status Bit 63" "Not active,Active" bitfld.long 0x00 30. " ASB62 ,Active Status Bit 62" "Not active,Active" bitfld.long 0x00 29. " ASB61 ,Active Status Bit 61" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB60 ,Active Status Bit 60" "Not active,Active" bitfld.long 0x00 27. " ASB59 ,Active Status Bit 59" "Not active,Active" bitfld.long 0x00 26. " ASB58 ,Active Status Bit 58" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB57 ,Active Status Bit 57" "Not active,Active" bitfld.long 0x00 24. " ASB56 ,Active Status Bit 56" "Not active,Active" bitfld.long 0x00 23. " ASB55 ,Active Status Bit 55" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB54 ,Active Status Bit 54" "Not active,Active" bitfld.long 0x00 21. " ASB53 ,Active Status Bit 53" "Not active,Active" bitfld.long 0x00 20. " ASB52 ,Active Status Bit 52" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB51 ,Active Status Bit 51" "Not active,Active" bitfld.long 0x00 18. " ASB50 ,Active Status Bit 50" "Not active,Active" bitfld.long 0x00 17. " ASB49 ,Active Status Bit 49" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB48 ,Active Status Bit 48" "Not active,Active" bitfld.long 0x00 15. " ASB47 ,Active Status Bit 47" "Not active,Active" bitfld.long 0x00 14. " ASB46 ,Active Status Bit 46" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB45 ,Active Status Bit 45" "Not active,Active" bitfld.long 0x00 12. " ASB44 ,Active Status Bit 44" "Not active,Active" bitfld.long 0x00 11. " ASB43 ,Active Status Bit 43" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB42 ,Active Status Bit 42" "Not active,Active" bitfld.long 0x00 9. " ASB41 ,Active Status Bit 41" "Not active,Active" bitfld.long 0x00 8. " ASB40 ,Active Status Bit 40" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB39 ,Active Status Bit 39" "Not active,Active" bitfld.long 0x00 6. " ASB38 ,Active Status Bit 38" "Not active,Active" bitfld.long 0x00 5. " ASB37 ,Active Status Bit 37" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB36 ,Active Status Bit 36" "Not active,Active" bitfld.long 0x00 3. " ASB35 ,Active Status Bit 35" "Not active,Active" bitfld.long 0x00 2. " ASB34 ,Active Status Bit 34" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB33 ,Active Status Bit 33" "Not active,Active" bitfld.long 0x00 0. " ASB32 ,Active Status Bit 32" "Not active,Active" else hgroup.long 0x0304++0x03 hide.long 0x0 "GICD_ICDABR1,Active Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" bitfld.long 0x00 31. " ASB95 ,Active Status Bit 95" "Not active,Active" bitfld.long 0x00 30. " ASB94 ,Active Status Bit 94" "Not active,Active" bitfld.long 0x00 29. " ASB93 ,Active Status Bit 93" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB92 ,Active Status Bit 92" "Not active,Active" bitfld.long 0x00 27. " ASB91 ,Active Status Bit 91" "Not active,Active" bitfld.long 0x00 26. " ASB90 ,Active Status Bit 90" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB89 ,Active Status Bit 89" "Not active,Active" bitfld.long 0x00 24. " ASB88 ,Active Status Bit 88" "Not active,Active" bitfld.long 0x00 23. " ASB87 ,Active Status Bit 87" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB86 ,Active Status Bit 86" "Not active,Active" bitfld.long 0x00 21. " ASB85 ,Active Status Bit 85" "Not active,Active" bitfld.long 0x00 20. " ASB84 ,Active Status Bit 84" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB83 ,Active Status Bit 83" "Not active,Active" bitfld.long 0x00 18. " ASB82 ,Active Status Bit 82" "Not active,Active" bitfld.long 0x00 17. " ASB81 ,Active Status Bit 81" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB80 ,Active Status Bit 80" "Not active,Active" bitfld.long 0x00 15. " ASB79 ,Active Status Bit 79" "Not active,Active" bitfld.long 0x00 14. " ASB78 ,Active Status Bit 78" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB77 ,Active Status Bit 77" "Not active,Active" bitfld.long 0x00 12. " ASB76 ,Active Status Bit 76" "Not active,Active" bitfld.long 0x00 11. " ASB75 ,Active Status Bit 75" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB74 ,Active Status Bit 74" "Not active,Active" bitfld.long 0x00 9. " ASB73 ,Active Status Bit 73" "Not active,Active" bitfld.long 0x00 8. " ASB72 ,Active Status Bit 72" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB71 ,Active Status Bit 71" "Not active,Active" bitfld.long 0x00 6. " ASB70 ,Active Status Bit 70" "Not active,Active" bitfld.long 0x00 5. " ASB69 ,Active Status Bit 69" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB68 ,Active Status Bit 68" "Not active,Active" bitfld.long 0x00 3. " ASB67 ,Active Status Bit 67" "Not active,Active" bitfld.long 0x00 2. " ASB66 ,Active Status Bit 66" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB65 ,Active Status Bit 65" "Not active,Active" bitfld.long 0x00 0. " ASB64 ,Active Status Bit 64" "Not active,Active" else hgroup.long 0x0308++0x03 hide.long 0x0 "GICD_ICDABR2,Active Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" bitfld.long 0x00 31. " ASB127 ,Active Status Bit 127" "Not active,Active" bitfld.long 0x00 30. " ASB126 ,Active Status Bit 126" "Not active,Active" bitfld.long 0x00 29. " ASB125 ,Active Status Bit 125" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB124 ,Active Status Bit 124" "Not active,Active" bitfld.long 0x00 27. " ASB123 ,Active Status Bit 123" "Not active,Active" bitfld.long 0x00 26. " ASB122 ,Active Status Bit 122" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB121 ,Active Status Bit 121" "Not active,Active" bitfld.long 0x00 24. " ASB120 ,Active Status Bit 120" "Not active,Active" bitfld.long 0x00 23. " ASB119 ,Active Status Bit 119" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB118 ,Active Status Bit 118" "Not active,Active" bitfld.long 0x00 21. " ASB117 ,Active Status Bit 117" "Not active,Active" bitfld.long 0x00 20. " ASB116 ,Active Status Bit 116" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB115 ,Active Status Bit 115" "Not active,Active" bitfld.long 0x00 18. " ASB114 ,Active Status Bit 114" "Not active,Active" bitfld.long 0x00 17. " ASB113 ,Active Status Bit 113" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB112 ,Active Status Bit 112" "Not active,Active" bitfld.long 0x00 15. " ASB111 ,Active Status Bit 111" "Not active,Active" bitfld.long 0x00 14. " ASB110 ,Active Status Bit 110" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB109 ,Active Status Bit 109" "Not active,Active" bitfld.long 0x00 12. " ASB108 ,Active Status Bit 108" "Not active,Active" bitfld.long 0x00 11. " ASB107 ,Active Status Bit 107" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB106 ,Active Status Bit 106" "Not active,Active" bitfld.long 0x00 9. " ASB105 ,Active Status Bit 105" "Not active,Active" bitfld.long 0x00 8. " ASB104 ,Active Status Bit 104" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB103 ,Active Status Bit 103" "Not active,Active" bitfld.long 0x00 6. " ASB102 ,Active Status Bit 102" "Not active,Active" bitfld.long 0x00 5. " ASB101 ,Active Status Bit 101" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB100 ,Active Status Bit 100" "Not active,Active" bitfld.long 0x00 3. " ASB99 ,Active Status Bit 99" "Not active,Active" bitfld.long 0x00 2. " ASB98 ,Active Status Bit 98" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB97 ,Active Status Bit 97" "Not active,Active" bitfld.long 0x00 0. " ASB96 ,Active Status Bit 96" "Not active,Active" else hgroup.long 0x030C++0x03 hide.long 0x0 "GICD_ICDABR3,Active Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" bitfld.long 0x00 31. " ASB159 ,Active Status Bit 159" "Not active,Active" bitfld.long 0x00 30. " ASB158 ,Active Status Bit 158" "Not active,Active" bitfld.long 0x00 29. " ASB157 ,Active Status Bit 157" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB156 ,Active Status Bit 156" "Not active,Active" bitfld.long 0x00 27. " ASB155 ,Active Status Bit 155" "Not active,Active" bitfld.long 0x00 26. " ASB154 ,Active Status Bit 154" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB153 ,Active Status Bit 153" "Not active,Active" bitfld.long 0x00 24. " ASB152 ,Active Status Bit 152" "Not active,Active" bitfld.long 0x00 23. " ASB151 ,Active Status Bit 151" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB150 ,Active Status Bit 150" "Not active,Active" bitfld.long 0x00 21. " ASB149 ,Active Status Bit 149" "Not active,Active" bitfld.long 0x00 20. " ASB148 ,Active Status Bit 148" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB147 ,Active Status Bit 147" "Not active,Active" bitfld.long 0x00 18. " ASB146 ,Active Status Bit 146" "Not active,Active" bitfld.long 0x00 17. " ASB145 ,Active Status Bit 145" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB144 ,Active Status Bit 144" "Not active,Active" bitfld.long 0x00 15. " ASB143 ,Active Status Bit 143" "Not active,Active" bitfld.long 0x00 14. " ASB142 ,Active Status Bit 142" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB141 ,Active Status Bit 141" "Not active,Active" bitfld.long 0x00 12. " ASB140 ,Active Status Bit 140" "Not active,Active" bitfld.long 0x00 11. " ASB139 ,Active Status Bit 139" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB138 ,Active Status Bit 138" "Not active,Active" bitfld.long 0x00 9. " ASB137 ,Active Status Bit 137" "Not active,Active" bitfld.long 0x00 8. " ASB136 ,Active Status Bit 136" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB135 ,Active Status Bit 135" "Not active,Active" bitfld.long 0x00 6. " ASB134 ,Active Status Bit 134" "Not active,Active" bitfld.long 0x00 5. " ASB133 ,Active Status Bit 133" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB132 ,Active Status Bit 132" "Not active,Active" bitfld.long 0x00 3. " ASB131 ,Active Status Bit 131" "Not active,Active" bitfld.long 0x00 2. " ASB130 ,Active Status Bit 130" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB129 ,Active Status Bit 129" "Not active,Active" bitfld.long 0x00 0. " ASB128 ,Active Status Bit 128" "Not active,Active" else hgroup.long 0x0310++0x03 hide.long 0x0 "GICD_ICDABR4,Active Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" bitfld.long 0x00 31. " ASB191 ,Active Status Bit 191" "Not active,Active" bitfld.long 0x00 30. " ASB190 ,Active Status Bit 190" "Not active,Active" bitfld.long 0x00 29. " ASB189 ,Active Status Bit 189" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB188 ,Active Status Bit 188" "Not active,Active" bitfld.long 0x00 27. " ASB187 ,Active Status Bit 187" "Not active,Active" bitfld.long 0x00 26. " ASB186 ,Active Status Bit 186" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB185 ,Active Status Bit 185" "Not active,Active" bitfld.long 0x00 24. " ASB184 ,Active Status Bit 184" "Not active,Active" bitfld.long 0x00 23. " ASB183 ,Active Status Bit 183" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB182 ,Active Status Bit 182" "Not active,Active" bitfld.long 0x00 21. " ASB181 ,Active Status Bit 181" "Not active,Active" bitfld.long 0x00 20. " ASB180 ,Active Status Bit 180" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB179 ,Active Status Bit 179" "Not active,Active" bitfld.long 0x00 18. " ASB178 ,Active Status Bit 178" "Not active,Active" bitfld.long 0x00 17. " ASB177 ,Active Status Bit 177" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB176 ,Active Status Bit 176" "Not active,Active" bitfld.long 0x00 15. " ASB175 ,Active Status Bit 175" "Not active,Active" bitfld.long 0x00 14. " ASB174 ,Active Status Bit 174" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB173 ,Active Status Bit 173" "Not active,Active" bitfld.long 0x00 12. " ASB172 ,Active Status Bit 172" "Not active,Active" bitfld.long 0x00 11. " ASB171 ,Active Status Bit 171" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB170 ,Active Status Bit 170" "Not active,Active" bitfld.long 0x00 9. " ASB169 ,Active Status Bit 169" "Not active,Active" bitfld.long 0x00 8. " ASB168 ,Active Status Bit 168" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB167 ,Active Status Bit 167" "Not active,Active" bitfld.long 0x00 6. " ASB166 ,Active Status Bit 166" "Not active,Active" bitfld.long 0x00 5. " ASB165 ,Active Status Bit 165" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB164 ,Active Status Bit 164" "Not active,Active" bitfld.long 0x00 3. " ASB163 ,Active Status Bit 163" "Not active,Active" bitfld.long 0x00 2. " ASB162 ,Active Status Bit 162" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB161 ,Active Status Bit 161" "Not active,Active" bitfld.long 0x00 0. " ASB160 ,Active Status Bit 160" "Not active,Active" else hgroup.long 0x0314++0x03 hide.long 0x0 "GICD_ICDABR5,Active Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" bitfld.long 0x00 31. " ASB223 ,Active Status Bit 223" "Not active,Active" bitfld.long 0x00 30. " ASB222 ,Active Status Bit 222" "Not active,Active" bitfld.long 0x00 29. " ASB221 ,Active Status Bit 221" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB220 ,Active Status Bit 220" "Not active,Active" bitfld.long 0x00 27. " ASB219 ,Active Status Bit 219" "Not active,Active" bitfld.long 0x00 26. " ASB218 ,Active Status Bit 218" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB217 ,Active Status Bit 217" "Not active,Active" bitfld.long 0x00 24. " ASB216 ,Active Status Bit 216" "Not active,Active" bitfld.long 0x00 23. " ASB215 ,Active Status Bit 215" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB214 ,Active Status Bit 214" "Not active,Active" bitfld.long 0x00 21. " ASB213 ,Active Status Bit 213" "Not active,Active" bitfld.long 0x00 20. " ASB212 ,Active Status Bit 212" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB211 ,Active Status Bit 211" "Not active,Active" bitfld.long 0x00 18. " ASB210 ,Active Status Bit 210" "Not active,Active" bitfld.long 0x00 17. " ASB209 ,Active Status Bit 209" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB208 ,Active Status Bit 208" "Not active,Active" bitfld.long 0x00 15. " ASB207 ,Active Status Bit 207" "Not active,Active" bitfld.long 0x00 14. " ASB206 ,Active Status Bit 206" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB205 ,Active Status Bit 205" "Not active,Active" bitfld.long 0x00 12. " ASB204 ,Active Status Bit 204" "Not active,Active" bitfld.long 0x00 11. " ASB203 ,Active Status Bit 203" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB202 ,Active Status Bit 202" "Not active,Active" bitfld.long 0x00 9. " ASB201 ,Active Status Bit 201" "Not active,Active" bitfld.long 0x00 8. " ASB200 ,Active Status Bit 200" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB199 ,Active Status Bit 199" "Not active,Active" bitfld.long 0x00 6. " ASB198 ,Active Status Bit 198" "Not active,Active" bitfld.long 0x00 5. " ASB197 ,Active Status Bit 197" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB196 ,Active Status Bit 196" "Not active,Active" bitfld.long 0x00 3. " ASB195 ,Active Status Bit 195" "Not active,Active" bitfld.long 0x00 2. " ASB194 ,Active Status Bit 194" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB193 ,Active Status Bit 193" "Not active,Active" bitfld.long 0x00 0. " ASB192 ,Active Status Bit 192" "Not active,Active" else hgroup.long 0x0318++0x03 hide.long 0x0 "GICD_ICDABR6,Active Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" bitfld.long 0x00 31. " ASB255 ,Active Status Bit 255" "Not active,Active" bitfld.long 0x00 30. " ASB254 ,Active Status Bit 254" "Not active,Active" bitfld.long 0x00 29. " ASB253 ,Active Status Bit 253" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB252 ,Active Status Bit 252" "Not active,Active" bitfld.long 0x00 27. " ASB251 ,Active Status Bit 251" "Not active,Active" bitfld.long 0x00 26. " ASB250 ,Active Status Bit 250" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB249 ,Active Status Bit 249" "Not active,Active" bitfld.long 0x00 24. " ASB248 ,Active Status Bit 248" "Not active,Active" bitfld.long 0x00 23. " ASB247 ,Active Status Bit 247" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB246 ,Active Status Bit 246" "Not active,Active" bitfld.long 0x00 21. " ASB245 ,Active Status Bit 245" "Not active,Active" bitfld.long 0x00 20. " ASB244 ,Active Status Bit 244" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB243 ,Active Status Bit 243" "Not active,Active" bitfld.long 0x00 18. " ASB242 ,Active Status Bit 242" "Not active,Active" bitfld.long 0x00 17. " ASB241 ,Active Status Bit 241" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB240 ,Active Status Bit 240" "Not active,Active" bitfld.long 0x00 15. " ASB239 ,Active Status Bit 239" "Not active,Active" bitfld.long 0x00 14. " ASB238 ,Active Status Bit 238" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB237 ,Active Status Bit 237" "Not active,Active" bitfld.long 0x00 12. " ASB236 ,Active Status Bit 236" "Not active,Active" bitfld.long 0x00 11. " ASB235 ,Active Status Bit 235" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB234 ,Active Status Bit 234" "Not active,Active" bitfld.long 0x00 9. " ASB233 ,Active Status Bit 233" "Not active,Active" bitfld.long 0x00 8. " ASB232 ,Active Status Bit 232" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB231 ,Active Status Bit 231" "Not active,Active" bitfld.long 0x00 6. " ASB230 ,Active Status Bit 230" "Not active,Active" bitfld.long 0x00 5. " ASB229 ,Active Status Bit 229" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB228 ,Active Status Bit 228" "Not active,Active" bitfld.long 0x00 3. " ASB227 ,Active Status Bit 227" "Not active,Active" bitfld.long 0x00 2. " ASB226 ,Active Status Bit 226" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB225 ,Active Status Bit 225" "Not active,Active" bitfld.long 0x00 0. " ASB224 ,Active Status Bit 224" "Not active,Active" else hgroup.long 0x031C++0x03 hide.long 0x0 "GICD_ICDABR7,Active Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" bitfld.long 0x00 31. " ASB287 ,Active Status Bit 287" "Not active,Active" bitfld.long 0x00 30. " ASB286 ,Active Status Bit 286" "Not active,Active" bitfld.long 0x00 29. " ASB285 ,Active Status Bit 285" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB284 ,Active Status Bit 284" "Not active,Active" bitfld.long 0x00 27. " ASB283 ,Active Status Bit 283" "Not active,Active" bitfld.long 0x00 26. " ASB282 ,Active Status Bit 282" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB281 ,Active Status Bit 281" "Not active,Active" bitfld.long 0x00 24. " ASB280 ,Active Status Bit 280" "Not active,Active" bitfld.long 0x00 23. " ASB279 ,Active Status Bit 279" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB278 ,Active Status Bit 278" "Not active,Active" bitfld.long 0x00 21. " ASB277 ,Active Status Bit 277" "Not active,Active" bitfld.long 0x00 20. " ASB276 ,Active Status Bit 276" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB275 ,Active Status Bit 275" "Not active,Active" bitfld.long 0x00 18. " ASB274 ,Active Status Bit 274" "Not active,Active" bitfld.long 0x00 17. " ASB273 ,Active Status Bit 273" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB272 ,Active Status Bit 272" "Not active,Active" bitfld.long 0x00 15. " ASB271 ,Active Status Bit 271" "Not active,Active" bitfld.long 0x00 14. " ASB270 ,Active Status Bit 270" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB269 ,Active Status Bit 269" "Not active,Active" bitfld.long 0x00 12. " ASB268 ,Active Status Bit 268" "Not active,Active" bitfld.long 0x00 11. " ASB267 ,Active Status Bit 267" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB266 ,Active Status Bit 266" "Not active,Active" bitfld.long 0x00 9. " ASB265 ,Active Status Bit 265" "Not active,Active" bitfld.long 0x00 8. " ASB264 ,Active Status Bit 264" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB263 ,Active Status Bit 263" "Not active,Active" bitfld.long 0x00 6. " ASB262 ,Active Status Bit 262" "Not active,Active" bitfld.long 0x00 5. " ASB261 ,Active Status Bit 261" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB260 ,Active Status Bit 260" "Not active,Active" bitfld.long 0x00 3. " ASB259 ,Active Status Bit 259" "Not active,Active" bitfld.long 0x00 2. " ASB258 ,Active Status Bit 258" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB257 ,Active Status Bit 257" "Not active,Active" bitfld.long 0x00 0. " ASB256 ,Active Status Bit 256" "Not active,Active" else hgroup.long 0x0320++0x03 hide.long 0x0 "GICD_ICDABR8,Active Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" bitfld.long 0x00 31. " ASB319 ,Active Status Bit 319" "Not active,Active" bitfld.long 0x00 30. " ASB318 ,Active Status Bit 318" "Not active,Active" bitfld.long 0x00 29. " ASB317 ,Active Status Bit 317" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB316 ,Active Status Bit 316" "Not active,Active" bitfld.long 0x00 27. " ASB315 ,Active Status Bit 315" "Not active,Active" bitfld.long 0x00 26. " ASB314 ,Active Status Bit 314" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB313 ,Active Status Bit 313" "Not active,Active" bitfld.long 0x00 24. " ASB312 ,Active Status Bit 312" "Not active,Active" bitfld.long 0x00 23. " ASB311 ,Active Status Bit 311" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB310 ,Active Status Bit 310" "Not active,Active" bitfld.long 0x00 21. " ASB309 ,Active Status Bit 309" "Not active,Active" bitfld.long 0x00 20. " ASB308 ,Active Status Bit 308" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB307 ,Active Status Bit 307" "Not active,Active" bitfld.long 0x00 18. " ASB306 ,Active Status Bit 306" "Not active,Active" bitfld.long 0x00 17. " ASB305 ,Active Status Bit 305" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB304 ,Active Status Bit 304" "Not active,Active" bitfld.long 0x00 15. " ASB303 ,Active Status Bit 303" "Not active,Active" bitfld.long 0x00 14. " ASB302 ,Active Status Bit 302" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB301 ,Active Status Bit 301" "Not active,Active" bitfld.long 0x00 12. " ASB300 ,Active Status Bit 300" "Not active,Active" bitfld.long 0x00 11. " ASB299 ,Active Status Bit 299" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB298 ,Active Status Bit 298" "Not active,Active" bitfld.long 0x00 9. " ASB297 ,Active Status Bit 297" "Not active,Active" bitfld.long 0x00 8. " ASB296 ,Active Status Bit 296" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB295 ,Active Status Bit 295" "Not active,Active" bitfld.long 0x00 6. " ASB294 ,Active Status Bit 294" "Not active,Active" bitfld.long 0x00 5. " ASB293 ,Active Status Bit 293" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB292 ,Active Status Bit 292" "Not active,Active" bitfld.long 0x00 3. " ASB291 ,Active Status Bit 291" "Not active,Active" bitfld.long 0x00 2. " ASB290 ,Active Status Bit 290" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB289 ,Active Status Bit 289" "Not active,Active" bitfld.long 0x00 0. " ASB288 ,Active Status Bit 288" "Not active,Active" else hgroup.long 0x0324++0x03 hide.long 0x0 "GICD_ICDABR9,Active Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" bitfld.long 0x00 31. " ASB351 ,Active Status Bit 351" "Not active,Active" bitfld.long 0x00 30. " ASB350 ,Active Status Bit 350" "Not active,Active" bitfld.long 0x00 29. " ASB349 ,Active Status Bit 349" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB348 ,Active Status Bit 348" "Not active,Active" bitfld.long 0x00 27. " ASB347 ,Active Status Bit 347" "Not active,Active" bitfld.long 0x00 26. " ASB346 ,Active Status Bit 346" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB345 ,Active Status Bit 345" "Not active,Active" bitfld.long 0x00 24. " ASB344 ,Active Status Bit 344" "Not active,Active" bitfld.long 0x00 23. " ASB343 ,Active Status Bit 343" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB342 ,Active Status Bit 342" "Not active,Active" bitfld.long 0x00 21. " ASB341 ,Active Status Bit 341" "Not active,Active" bitfld.long 0x00 20. " ASB340 ,Active Status Bit 340" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB339 ,Active Status Bit 339" "Not active,Active" bitfld.long 0x00 18. " ASB338 ,Active Status Bit 338" "Not active,Active" bitfld.long 0x00 17. " ASB337 ,Active Status Bit 337" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB336 ,Active Status Bit 336" "Not active,Active" bitfld.long 0x00 15. " ASB335 ,Active Status Bit 335" "Not active,Active" bitfld.long 0x00 14. " ASB334 ,Active Status Bit 334" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB333 ,Active Status Bit 333" "Not active,Active" bitfld.long 0x00 12. " ASB332 ,Active Status Bit 332" "Not active,Active" bitfld.long 0x00 11. " ASB331 ,Active Status Bit 331" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB330 ,Active Status Bit 330" "Not active,Active" bitfld.long 0x00 9. " ASB329 ,Active Status Bit 329" "Not active,Active" bitfld.long 0x00 8. " ASB328 ,Active Status Bit 328" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB327 ,Active Status Bit 327" "Not active,Active" bitfld.long 0x00 6. " ASB326 ,Active Status Bit 326" "Not active,Active" bitfld.long 0x00 5. " ASB325 ,Active Status Bit 325" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB324 ,Active Status Bit 324" "Not active,Active" bitfld.long 0x00 3. " ASB323 ,Active Status Bit 323" "Not active,Active" bitfld.long 0x00 2. " ASB322 ,Active Status Bit 322" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB321 ,Active Status Bit 321" "Not active,Active" bitfld.long 0x00 0. " ASB320 ,Active Status Bit 320" "Not active,Active" else hgroup.long 0x0328++0x03 hide.long 0x0 "GICD_ICDABR10,Active Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" bitfld.long 0x00 31. " ASB383 ,Active Status Bit 383" "Not active,Active" bitfld.long 0x00 30. " ASB382 ,Active Status Bit 382" "Not active,Active" bitfld.long 0x00 29. " ASB381 ,Active Status Bit 381" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB380 ,Active Status Bit 380" "Not active,Active" bitfld.long 0x00 27. " ASB379 ,Active Status Bit 379" "Not active,Active" bitfld.long 0x00 26. " ASB378 ,Active Status Bit 378" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB377 ,Active Status Bit 377" "Not active,Active" bitfld.long 0x00 24. " ASB376 ,Active Status Bit 376" "Not active,Active" bitfld.long 0x00 23. " ASB375 ,Active Status Bit 375" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB374 ,Active Status Bit 374" "Not active,Active" bitfld.long 0x00 21. " ASB373 ,Active Status Bit 373" "Not active,Active" bitfld.long 0x00 20. " ASB372 ,Active Status Bit 372" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB371 ,Active Status Bit 371" "Not active,Active" bitfld.long 0x00 18. " ASB370 ,Active Status Bit 370" "Not active,Active" bitfld.long 0x00 17. " ASB369 ,Active Status Bit 369" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB368 ,Active Status Bit 368" "Not active,Active" bitfld.long 0x00 15. " ASB367 ,Active Status Bit 367" "Not active,Active" bitfld.long 0x00 14. " ASB366 ,Active Status Bit 366" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB365 ,Active Status Bit 365" "Not active,Active" bitfld.long 0x00 12. " ASB364 ,Active Status Bit 364" "Not active,Active" bitfld.long 0x00 11. " ASB363 ,Active Status Bit 363" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB362 ,Active Status Bit 362" "Not active,Active" bitfld.long 0x00 9. " ASB361 ,Active Status Bit 361" "Not active,Active" bitfld.long 0x00 8. " ASB360 ,Active Status Bit 360" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB359 ,Active Status Bit 359" "Not active,Active" bitfld.long 0x00 6. " ASB358 ,Active Status Bit 358" "Not active,Active" bitfld.long 0x00 5. " ASB357 ,Active Status Bit 357" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB356 ,Active Status Bit 356" "Not active,Active" bitfld.long 0x00 3. " ASB355 ,Active Status Bit 355" "Not active,Active" bitfld.long 0x00 2. " ASB354 ,Active Status Bit 354" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB353 ,Active Status Bit 353" "Not active,Active" bitfld.long 0x00 0. " ASB352 ,Active Status Bit 352" "Not active,Active" else hgroup.long 0x032C++0x03 hide.long 0x0 "GICD_ICDABR11,Active Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" bitfld.long 0x00 31. " ASB415 ,Active Status Bit 415" "Not active,Active" bitfld.long 0x00 30. " ASB414 ,Active Status Bit 414" "Not active,Active" bitfld.long 0x00 29. " ASB413 ,Active Status Bit 413" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB412 ,Active Status Bit 412" "Not active,Active" bitfld.long 0x00 27. " ASB411 ,Active Status Bit 411" "Not active,Active" bitfld.long 0x00 26. " ASB410 ,Active Status Bit 410" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB409 ,Active Status Bit 409" "Not active,Active" bitfld.long 0x00 24. " ASB408 ,Active Status Bit 408" "Not active,Active" bitfld.long 0x00 23. " ASB407 ,Active Status Bit 407" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB406 ,Active Status Bit 406" "Not active,Active" bitfld.long 0x00 21. " ASB405 ,Active Status Bit 405" "Not active,Active" bitfld.long 0x00 20. " ASB404 ,Active Status Bit 404" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB403 ,Active Status Bit 403" "Not active,Active" bitfld.long 0x00 18. " ASB402 ,Active Status Bit 402" "Not active,Active" bitfld.long 0x00 17. " ASB401 ,Active Status Bit 401" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB400 ,Active Status Bit 400" "Not active,Active" bitfld.long 0x00 15. " ASB399 ,Active Status Bit 399" "Not active,Active" bitfld.long 0x00 14. " ASB398 ,Active Status Bit 398" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB397 ,Active Status Bit 397" "Not active,Active" bitfld.long 0x00 12. " ASB396 ,Active Status Bit 396" "Not active,Active" bitfld.long 0x00 11. " ASB395 ,Active Status Bit 395" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB394 ,Active Status Bit 394" "Not active,Active" bitfld.long 0x00 9. " ASB393 ,Active Status Bit 393" "Not active,Active" bitfld.long 0x00 8. " ASB392 ,Active Status Bit 392" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB391 ,Active Status Bit 391" "Not active,Active" bitfld.long 0x00 6. " ASB390 ,Active Status Bit 390" "Not active,Active" bitfld.long 0x00 5. " ASB389 ,Active Status Bit 389" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB388 ,Active Status Bit 388" "Not active,Active" bitfld.long 0x00 3. " ASB387 ,Active Status Bit 387" "Not active,Active" bitfld.long 0x00 2. " ASB386 ,Active Status Bit 386" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB385 ,Active Status Bit 385" "Not active,Active" bitfld.long 0x00 0. " ASB384 ,Active Status Bit 384" "Not active,Active" else hgroup.long 0x0330++0x03 hide.long 0x0 "GICD_ICDABR12,Active Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" bitfld.long 0x00 31. " ASB447 ,Active Status Bit 447" "Not active,Active" bitfld.long 0x00 30. " ASB446 ,Active Status Bit 446" "Not active,Active" bitfld.long 0x00 29. " ASB445 ,Active Status Bit 445" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB444 ,Active Status Bit 444" "Not active,Active" bitfld.long 0x00 27. " ASB443 ,Active Status Bit 443" "Not active,Active" bitfld.long 0x00 26. " ASB442 ,Active Status Bit 442" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB441 ,Active Status Bit 441" "Not active,Active" bitfld.long 0x00 24. " ASB440 ,Active Status Bit 440" "Not active,Active" bitfld.long 0x00 23. " ASB439 ,Active Status Bit 439" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB438 ,Active Status Bit 438" "Not active,Active" bitfld.long 0x00 21. " ASB437 ,Active Status Bit 437" "Not active,Active" bitfld.long 0x00 20. " ASB436 ,Active Status Bit 436" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB435 ,Active Status Bit 435" "Not active,Active" bitfld.long 0x00 18. " ASB434 ,Active Status Bit 434" "Not active,Active" bitfld.long 0x00 17. " ASB433 ,Active Status Bit 433" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB432 ,Active Status Bit 432" "Not active,Active" bitfld.long 0x00 15. " ASB431 ,Active Status Bit 431" "Not active,Active" bitfld.long 0x00 14. " ASB430 ,Active Status Bit 430" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB429 ,Active Status Bit 429" "Not active,Active" bitfld.long 0x00 12. " ASB428 ,Active Status Bit 428" "Not active,Active" bitfld.long 0x00 11. " ASB427 ,Active Status Bit 427" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB426 ,Active Status Bit 426" "Not active,Active" bitfld.long 0x00 9. " ASB425 ,Active Status Bit 425" "Not active,Active" bitfld.long 0x00 8. " ASB424 ,Active Status Bit 424" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB423 ,Active Status Bit 423" "Not active,Active" bitfld.long 0x00 6. " ASB422 ,Active Status Bit 422" "Not active,Active" bitfld.long 0x00 5. " ASB421 ,Active Status Bit 421" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB420 ,Active Status Bit 420" "Not active,Active" bitfld.long 0x00 3. " ASB419 ,Active Status Bit 419" "Not active,Active" bitfld.long 0x00 2. " ASB418 ,Active Status Bit 418" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB417 ,Active Status Bit 417" "Not active,Active" bitfld.long 0x00 0. " ASB416 ,Active Status Bit 416" "Not active,Active" else hgroup.long 0x0334++0x03 hide.long 0x0 "GICD_ICDABR13,Active Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" bitfld.long 0x00 31. " ASB479 ,Active Status Bit 479" "Not active,Active" bitfld.long 0x00 30. " ASB478 ,Active Status Bit 478" "Not active,Active" bitfld.long 0x00 29. " ASB477 ,Active Status Bit 477" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB476 ,Active Status Bit 476" "Not active,Active" bitfld.long 0x00 27. " ASB475 ,Active Status Bit 475" "Not active,Active" bitfld.long 0x00 26. " ASB474 ,Active Status Bit 474" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB473 ,Active Status Bit 473" "Not active,Active" bitfld.long 0x00 24. " ASB472 ,Active Status Bit 472" "Not active,Active" bitfld.long 0x00 23. " ASB471 ,Active Status Bit 471" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB470 ,Active Status Bit 470" "Not active,Active" bitfld.long 0x00 21. " ASB469 ,Active Status Bit 469" "Not active,Active" bitfld.long 0x00 20. " ASB468 ,Active Status Bit 468" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB467 ,Active Status Bit 467" "Not active,Active" bitfld.long 0x00 18. " ASB466 ,Active Status Bit 466" "Not active,Active" bitfld.long 0x00 17. " ASB465 ,Active Status Bit 465" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB464 ,Active Status Bit 464" "Not active,Active" bitfld.long 0x00 15. " ASB463 ,Active Status Bit 463" "Not active,Active" bitfld.long 0x00 14. " ASB462 ,Active Status Bit 462" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB461 ,Active Status Bit 461" "Not active,Active" bitfld.long 0x00 12. " ASB460 ,Active Status Bit 460" "Not active,Active" bitfld.long 0x00 11. " ASB459 ,Active Status Bit 459" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB458 ,Active Status Bit 458" "Not active,Active" bitfld.long 0x00 9. " ASB457 ,Active Status Bit 457" "Not active,Active" bitfld.long 0x00 8. " ASB456 ,Active Status Bit 456" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB455 ,Active Status Bit 455" "Not active,Active" bitfld.long 0x00 6. " ASB454 ,Active Status Bit 454" "Not active,Active" bitfld.long 0x00 5. " ASB453 ,Active Status Bit 453" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB452 ,Active Status Bit 452" "Not active,Active" bitfld.long 0x00 3. " ASB451 ,Active Status Bit 451" "Not active,Active" bitfld.long 0x00 2. " ASB450 ,Active Status Bit 450" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB449 ,Active Status Bit 449" "Not active,Active" bitfld.long 0x00 0. " ASB448 ,Active Status Bit 448" "Not active,Active" else hgroup.long 0x0338++0x03 hide.long 0x0 "GICD_ICDABR14,Active Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" bitfld.long 0x00 31. " ASB511 ,Active Status Bit 511" "Not active,Active" bitfld.long 0x00 30. " ASB510 ,Active Status Bit 510" "Not active,Active" bitfld.long 0x00 29. " ASB509 ,Active Status Bit 509" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB508 ,Active Status Bit 508" "Not active,Active" bitfld.long 0x00 27. " ASB507 ,Active Status Bit 507" "Not active,Active" bitfld.long 0x00 26. " ASB506 ,Active Status Bit 506" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB505 ,Active Status Bit 505" "Not active,Active" bitfld.long 0x00 24. " ASB504 ,Active Status Bit 504" "Not active,Active" bitfld.long 0x00 23. " ASB503 ,Active Status Bit 503" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB502 ,Active Status Bit 502" "Not active,Active" bitfld.long 0x00 21. " ASB501 ,Active Status Bit 501" "Not active,Active" bitfld.long 0x00 20. " ASB500 ,Active Status Bit 500" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB499 ,Active Status Bit 499" "Not active,Active" bitfld.long 0x00 18. " ASB498 ,Active Status Bit 498" "Not active,Active" bitfld.long 0x00 17. " ASB497 ,Active Status Bit 497" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB496 ,Active Status Bit 496" "Not active,Active" bitfld.long 0x00 15. " ASB495 ,Active Status Bit 495" "Not active,Active" bitfld.long 0x00 14. " ASB494 ,Active Status Bit 494" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB493 ,Active Status Bit 493" "Not active,Active" bitfld.long 0x00 12. " ASB492 ,Active Status Bit 492" "Not active,Active" bitfld.long 0x00 11. " ASB491 ,Active Status Bit 491" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB490 ,Active Status Bit 490" "Not active,Active" bitfld.long 0x00 9. " ASB489 ,Active Status Bit 489" "Not active,Active" bitfld.long 0x00 8. " ASB488 ,Active Status Bit 488" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB487 ,Active Status Bit 487" "Not active,Active" bitfld.long 0x00 6. " ASB486 ,Active Status Bit 486" "Not active,Active" bitfld.long 0x00 5. " ASB485 ,Active Status Bit 485" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB484 ,Active Status Bit 484" "Not active,Active" bitfld.long 0x00 3. " ASB483 ,Active Status Bit 483" "Not active,Active" bitfld.long 0x00 2. " ASB482 ,Active Status Bit 482" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB481 ,Active Status Bit 481" "Not active,Active" bitfld.long 0x00 0. " ASB480 ,Active Status Bit 480" "Not active,Active" else hgroup.long 0x033C++0x03 hide.long 0x0 "GICD_ICDABR15,Active Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" bitfld.long 0x00 31. " ASB543 ,Active Status Bit 543" "Not active,Active" bitfld.long 0x00 30. " ASB542 ,Active Status Bit 542" "Not active,Active" bitfld.long 0x00 29. " ASB541 ,Active Status Bit 541" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB540 ,Active Status Bit 540" "Not active,Active" bitfld.long 0x00 27. " ASB539 ,Active Status Bit 539" "Not active,Active" bitfld.long 0x00 26. " ASB538 ,Active Status Bit 538" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB537 ,Active Status Bit 537" "Not active,Active" bitfld.long 0x00 24. " ASB536 ,Active Status Bit 536" "Not active,Active" bitfld.long 0x00 23. " ASB535 ,Active Status Bit 535" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB534 ,Active Status Bit 534" "Not active,Active" bitfld.long 0x00 21. " ASB533 ,Active Status Bit 533" "Not active,Active" bitfld.long 0x00 20. " ASB532 ,Active Status Bit 532" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB531 ,Active Status Bit 531" "Not active,Active" bitfld.long 0x00 18. " ASB530 ,Active Status Bit 530" "Not active,Active" bitfld.long 0x00 17. " ASB529 ,Active Status Bit 529" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB528 ,Active Status Bit 528" "Not active,Active" bitfld.long 0x00 15. " ASB527 ,Active Status Bit 527" "Not active,Active" bitfld.long 0x00 14. " ASB526 ,Active Status Bit 526" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB525 ,Active Status Bit 525" "Not active,Active" bitfld.long 0x00 12. " ASB524 ,Active Status Bit 524" "Not active,Active" bitfld.long 0x00 11. " ASB523 ,Active Status Bit 523" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB522 ,Active Status Bit 522" "Not active,Active" bitfld.long 0x00 9. " ASB521 ,Active Status Bit 521" "Not active,Active" bitfld.long 0x00 8. " ASB520 ,Active Status Bit 520" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB519 ,Active Status Bit 519" "Not active,Active" bitfld.long 0x00 6. " ASB518 ,Active Status Bit 518" "Not active,Active" bitfld.long 0x00 5. " ASB517 ,Active Status Bit 517" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB516 ,Active Status Bit 516" "Not active,Active" bitfld.long 0x00 3. " ASB515 ,Active Status Bit 515" "Not active,Active" bitfld.long 0x00 2. " ASB514 ,Active Status Bit 514" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB513 ,Active Status Bit 513" "Not active,Active" bitfld.long 0x00 0. " ASB512 ,Active Status Bit 512" "Not active,Active" else hgroup.long 0x0340++0x03 hide.long 0x0 "GICD_ICDABR16,Active Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" bitfld.long 0x00 31. " ASB575 ,Active Status Bit 575" "Not active,Active" bitfld.long 0x00 30. " ASB574 ,Active Status Bit 574" "Not active,Active" bitfld.long 0x00 29. " ASB573 ,Active Status Bit 573" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB572 ,Active Status Bit 572" "Not active,Active" bitfld.long 0x00 27. " ASB571 ,Active Status Bit 571" "Not active,Active" bitfld.long 0x00 26. " ASB570 ,Active Status Bit 570" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB569 ,Active Status Bit 569" "Not active,Active" bitfld.long 0x00 24. " ASB568 ,Active Status Bit 568" "Not active,Active" bitfld.long 0x00 23. " ASB567 ,Active Status Bit 567" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB566 ,Active Status Bit 566" "Not active,Active" bitfld.long 0x00 21. " ASB565 ,Active Status Bit 565" "Not active,Active" bitfld.long 0x00 20. " ASB564 ,Active Status Bit 564" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB563 ,Active Status Bit 563" "Not active,Active" bitfld.long 0x00 18. " ASB562 ,Active Status Bit 562" "Not active,Active" bitfld.long 0x00 17. " ASB561 ,Active Status Bit 561" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB560 ,Active Status Bit 560" "Not active,Active" bitfld.long 0x00 15. " ASB559 ,Active Status Bit 559" "Not active,Active" bitfld.long 0x00 14. " ASB558 ,Active Status Bit 558" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB557 ,Active Status Bit 557" "Not active,Active" bitfld.long 0x00 12. " ASB556 ,Active Status Bit 556" "Not active,Active" bitfld.long 0x00 11. " ASB555 ,Active Status Bit 555" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB554 ,Active Status Bit 554" "Not active,Active" bitfld.long 0x00 9. " ASB553 ,Active Status Bit 553" "Not active,Active" bitfld.long 0x00 8. " ASB552 ,Active Status Bit 552" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB551 ,Active Status Bit 551" "Not active,Active" bitfld.long 0x00 6. " ASB550 ,Active Status Bit 550" "Not active,Active" bitfld.long 0x00 5. " ASB549 ,Active Status Bit 549" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB548 ,Active Status Bit 548" "Not active,Active" bitfld.long 0x00 3. " ASB547 ,Active Status Bit 547" "Not active,Active" bitfld.long 0x00 2. " ASB546 ,Active Status Bit 546" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB545 ,Active Status Bit 545" "Not active,Active" bitfld.long 0x00 0. " ASB544 ,Active Status Bit 544" "Not active,Active" else hgroup.long 0x0344++0x03 hide.long 0x0 "GICD_ICDABR17,Active Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" bitfld.long 0x00 31. " ASB607 ,Active Status Bit 607" "Not active,Active" bitfld.long 0x00 30. " ASB606 ,Active Status Bit 606" "Not active,Active" bitfld.long 0x00 29. " ASB605 ,Active Status Bit 605" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB604 ,Active Status Bit 604" "Not active,Active" bitfld.long 0x00 27. " ASB603 ,Active Status Bit 603" "Not active,Active" bitfld.long 0x00 26. " ASB602 ,Active Status Bit 602" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB601 ,Active Status Bit 601" "Not active,Active" bitfld.long 0x00 24. " ASB600 ,Active Status Bit 600" "Not active,Active" bitfld.long 0x00 23. " ASB599 ,Active Status Bit 599" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB598 ,Active Status Bit 598" "Not active,Active" bitfld.long 0x00 21. " ASB597 ,Active Status Bit 597" "Not active,Active" bitfld.long 0x00 20. " ASB596 ,Active Status Bit 596" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB595 ,Active Status Bit 595" "Not active,Active" bitfld.long 0x00 18. " ASB594 ,Active Status Bit 594" "Not active,Active" bitfld.long 0x00 17. " ASB593 ,Active Status Bit 593" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB592 ,Active Status Bit 592" "Not active,Active" bitfld.long 0x00 15. " ASB591 ,Active Status Bit 591" "Not active,Active" bitfld.long 0x00 14. " ASB590 ,Active Status Bit 590" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB589 ,Active Status Bit 589" "Not active,Active" bitfld.long 0x00 12. " ASB588 ,Active Status Bit 588" "Not active,Active" bitfld.long 0x00 11. " ASB587 ,Active Status Bit 587" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB586 ,Active Status Bit 586" "Not active,Active" bitfld.long 0x00 9. " ASB585 ,Active Status Bit 585" "Not active,Active" bitfld.long 0x00 8. " ASB584 ,Active Status Bit 584" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB583 ,Active Status Bit 583" "Not active,Active" bitfld.long 0x00 6. " ASB582 ,Active Status Bit 582" "Not active,Active" bitfld.long 0x00 5. " ASB581 ,Active Status Bit 581" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB580 ,Active Status Bit 580" "Not active,Active" bitfld.long 0x00 3. " ASB579 ,Active Status Bit 579" "Not active,Active" bitfld.long 0x00 2. " ASB578 ,Active Status Bit 578" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB577 ,Active Status Bit 577" "Not active,Active" bitfld.long 0x00 0. " ASB576 ,Active Status Bit 576" "Not active,Active" else hgroup.long 0x0348++0x03 hide.long 0x0 "GICD_ICDABR18,Active Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" bitfld.long 0x00 31. " ASB639 ,Active Status Bit 639" "Not active,Active" bitfld.long 0x00 30. " ASB638 ,Active Status Bit 638" "Not active,Active" bitfld.long 0x00 29. " ASB637 ,Active Status Bit 637" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB636 ,Active Status Bit 636" "Not active,Active" bitfld.long 0x00 27. " ASB635 ,Active Status Bit 635" "Not active,Active" bitfld.long 0x00 26. " ASB634 ,Active Status Bit 634" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB633 ,Active Status Bit 633" "Not active,Active" bitfld.long 0x00 24. " ASB632 ,Active Status Bit 632" "Not active,Active" bitfld.long 0x00 23. " ASB631 ,Active Status Bit 631" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB630 ,Active Status Bit 630" "Not active,Active" bitfld.long 0x00 21. " ASB629 ,Active Status Bit 629" "Not active,Active" bitfld.long 0x00 20. " ASB628 ,Active Status Bit 628" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB627 ,Active Status Bit 627" "Not active,Active" bitfld.long 0x00 18. " ASB626 ,Active Status Bit 626" "Not active,Active" bitfld.long 0x00 17. " ASB625 ,Active Status Bit 625" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB624 ,Active Status Bit 624" "Not active,Active" bitfld.long 0x00 15. " ASB623 ,Active Status Bit 623" "Not active,Active" bitfld.long 0x00 14. " ASB622 ,Active Status Bit 622" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB621 ,Active Status Bit 621" "Not active,Active" bitfld.long 0x00 12. " ASB620 ,Active Status Bit 620" "Not active,Active" bitfld.long 0x00 11. " ASB619 ,Active Status Bit 619" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB618 ,Active Status Bit 618" "Not active,Active" bitfld.long 0x00 9. " ASB617 ,Active Status Bit 617" "Not active,Active" bitfld.long 0x00 8. " ASB616 ,Active Status Bit 616" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB615 ,Active Status Bit 615" "Not active,Active" bitfld.long 0x00 6. " ASB614 ,Active Status Bit 614" "Not active,Active" bitfld.long 0x00 5. " ASB613 ,Active Status Bit 613" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB612 ,Active Status Bit 612" "Not active,Active" bitfld.long 0x00 3. " ASB611 ,Active Status Bit 611" "Not active,Active" bitfld.long 0x00 2. " ASB610 ,Active Status Bit 610" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB609 ,Active Status Bit 609" "Not active,Active" bitfld.long 0x00 0. " ASB608 ,Active Status Bit 608" "Not active,Active" else hgroup.long 0x034C++0x03 hide.long 0x0 "GICD_ICDABR19,Active Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" bitfld.long 0x00 31. " ASB671 ,Active Status Bit 671" "Not active,Active" bitfld.long 0x00 30. " ASB670 ,Active Status Bit 670" "Not active,Active" bitfld.long 0x00 29. " ASB669 ,Active Status Bit 669" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB668 ,Active Status Bit 668" "Not active,Active" bitfld.long 0x00 27. " ASB667 ,Active Status Bit 667" "Not active,Active" bitfld.long 0x00 26. " ASB666 ,Active Status Bit 666" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB665 ,Active Status Bit 665" "Not active,Active" bitfld.long 0x00 24. " ASB664 ,Active Status Bit 664" "Not active,Active" bitfld.long 0x00 23. " ASB663 ,Active Status Bit 663" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB662 ,Active Status Bit 662" "Not active,Active" bitfld.long 0x00 21. " ASB661 ,Active Status Bit 661" "Not active,Active" bitfld.long 0x00 20. " ASB660 ,Active Status Bit 660" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB659 ,Active Status Bit 659" "Not active,Active" bitfld.long 0x00 18. " ASB658 ,Active Status Bit 658" "Not active,Active" bitfld.long 0x00 17. " ASB657 ,Active Status Bit 657" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB656 ,Active Status Bit 656" "Not active,Active" bitfld.long 0x00 15. " ASB655 ,Active Status Bit 655" "Not active,Active" bitfld.long 0x00 14. " ASB654 ,Active Status Bit 654" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB653 ,Active Status Bit 653" "Not active,Active" bitfld.long 0x00 12. " ASB652 ,Active Status Bit 652" "Not active,Active" bitfld.long 0x00 11. " ASB651 ,Active Status Bit 651" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB650 ,Active Status Bit 650" "Not active,Active" bitfld.long 0x00 9. " ASB649 ,Active Status Bit 649" "Not active,Active" bitfld.long 0x00 8. " ASB648 ,Active Status Bit 648" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB647 ,Active Status Bit 647" "Not active,Active" bitfld.long 0x00 6. " ASB646 ,Active Status Bit 646" "Not active,Active" bitfld.long 0x00 5. " ASB645 ,Active Status Bit 645" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB644 ,Active Status Bit 644" "Not active,Active" bitfld.long 0x00 3. " ASB643 ,Active Status Bit 643" "Not active,Active" bitfld.long 0x00 2. " ASB642 ,Active Status Bit 642" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB641 ,Active Status Bit 641" "Not active,Active" bitfld.long 0x00 0. " ASB640 ,Active Status Bit 640" "Not active,Active" else hgroup.long 0x0350++0x03 hide.long 0x0 "GICD_ICDABR20,Active Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" bitfld.long 0x00 31. " ASB703 ,Active Status Bit 703" "Not active,Active" bitfld.long 0x00 30. " ASB702 ,Active Status Bit 702" "Not active,Active" bitfld.long 0x00 29. " ASB701 ,Active Status Bit 701" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB700 ,Active Status Bit 700" "Not active,Active" bitfld.long 0x00 27. " ASB699 ,Active Status Bit 699" "Not active,Active" bitfld.long 0x00 26. " ASB698 ,Active Status Bit 698" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB697 ,Active Status Bit 697" "Not active,Active" bitfld.long 0x00 24. " ASB696 ,Active Status Bit 696" "Not active,Active" bitfld.long 0x00 23. " ASB695 ,Active Status Bit 695" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB694 ,Active Status Bit 694" "Not active,Active" bitfld.long 0x00 21. " ASB693 ,Active Status Bit 693" "Not active,Active" bitfld.long 0x00 20. " ASB692 ,Active Status Bit 692" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB691 ,Active Status Bit 691" "Not active,Active" bitfld.long 0x00 18. " ASB690 ,Active Status Bit 690" "Not active,Active" bitfld.long 0x00 17. " ASB689 ,Active Status Bit 689" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB688 ,Active Status Bit 688" "Not active,Active" bitfld.long 0x00 15. " ASB687 ,Active Status Bit 687" "Not active,Active" bitfld.long 0x00 14. " ASB686 ,Active Status Bit 686" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB685 ,Active Status Bit 685" "Not active,Active" bitfld.long 0x00 12. " ASB684 ,Active Status Bit 684" "Not active,Active" bitfld.long 0x00 11. " ASB683 ,Active Status Bit 683" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB682 ,Active Status Bit 682" "Not active,Active" bitfld.long 0x00 9. " ASB681 ,Active Status Bit 681" "Not active,Active" bitfld.long 0x00 8. " ASB680 ,Active Status Bit 680" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB679 ,Active Status Bit 679" "Not active,Active" bitfld.long 0x00 6. " ASB678 ,Active Status Bit 678" "Not active,Active" bitfld.long 0x00 5. " ASB677 ,Active Status Bit 677" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB676 ,Active Status Bit 676" "Not active,Active" bitfld.long 0x00 3. " ASB675 ,Active Status Bit 675" "Not active,Active" bitfld.long 0x00 2. " ASB674 ,Active Status Bit 674" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB673 ,Active Status Bit 673" "Not active,Active" bitfld.long 0x00 0. " ASB672 ,Active Status Bit 672" "Not active,Active" else hgroup.long 0x0354++0x03 hide.long 0x0 "GICD_ICDABR21,Active Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" bitfld.long 0x00 31. " ASB735 ,Active Status Bit 735" "Not active,Active" bitfld.long 0x00 30. " ASB734 ,Active Status Bit 734" "Not active,Active" bitfld.long 0x00 29. " ASB733 ,Active Status Bit 733" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB732 ,Active Status Bit 732" "Not active,Active" bitfld.long 0x00 27. " ASB731 ,Active Status Bit 731" "Not active,Active" bitfld.long 0x00 26. " ASB730 ,Active Status Bit 730" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB729 ,Active Status Bit 729" "Not active,Active" bitfld.long 0x00 24. " ASB728 ,Active Status Bit 728" "Not active,Active" bitfld.long 0x00 23. " ASB727 ,Active Status Bit 727" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB726 ,Active Status Bit 726" "Not active,Active" bitfld.long 0x00 21. " ASB725 ,Active Status Bit 725" "Not active,Active" bitfld.long 0x00 20. " ASB724 ,Active Status Bit 724" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB723 ,Active Status Bit 723" "Not active,Active" bitfld.long 0x00 18. " ASB722 ,Active Status Bit 722" "Not active,Active" bitfld.long 0x00 17. " ASB721 ,Active Status Bit 721" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB720 ,Active Status Bit 720" "Not active,Active" bitfld.long 0x00 15. " ASB719 ,Active Status Bit 719" "Not active,Active" bitfld.long 0x00 14. " ASB718 ,Active Status Bit 718" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB717 ,Active Status Bit 717" "Not active,Active" bitfld.long 0x00 12. " ASB716 ,Active Status Bit 716" "Not active,Active" bitfld.long 0x00 11. " ASB715 ,Active Status Bit 715" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB714 ,Active Status Bit 714" "Not active,Active" bitfld.long 0x00 9. " ASB713 ,Active Status Bit 713" "Not active,Active" bitfld.long 0x00 8. " ASB712 ,Active Status Bit 712" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB711 ,Active Status Bit 711" "Not active,Active" bitfld.long 0x00 6. " ASB710 ,Active Status Bit 710" "Not active,Active" bitfld.long 0x00 5. " ASB709 ,Active Status Bit 709" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB708 ,Active Status Bit 708" "Not active,Active" bitfld.long 0x00 3. " ASB707 ,Active Status Bit 707" "Not active,Active" bitfld.long 0x00 2. " ASB706 ,Active Status Bit 706" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB705 ,Active Status Bit 705" "Not active,Active" bitfld.long 0x00 0. " ASB704 ,Active Status Bit 704" "Not active,Active" else hgroup.long 0x0358++0x03 hide.long 0x0 "GICD_ICDABR22,Active Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" bitfld.long 0x00 31. " ASB767 ,Active Status Bit 767" "Not active,Active" bitfld.long 0x00 30. " ASB766 ,Active Status Bit 766" "Not active,Active" bitfld.long 0x00 29. " ASB765 ,Active Status Bit 765" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB764 ,Active Status Bit 764" "Not active,Active" bitfld.long 0x00 27. " ASB763 ,Active Status Bit 763" "Not active,Active" bitfld.long 0x00 26. " ASB762 ,Active Status Bit 762" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB761 ,Active Status Bit 761" "Not active,Active" bitfld.long 0x00 24. " ASB760 ,Active Status Bit 760" "Not active,Active" bitfld.long 0x00 23. " ASB759 ,Active Status Bit 759" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB758 ,Active Status Bit 758" "Not active,Active" bitfld.long 0x00 21. " ASB757 ,Active Status Bit 757" "Not active,Active" bitfld.long 0x00 20. " ASB756 ,Active Status Bit 756" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB755 ,Active Status Bit 755" "Not active,Active" bitfld.long 0x00 18. " ASB754 ,Active Status Bit 754" "Not active,Active" bitfld.long 0x00 17. " ASB753 ,Active Status Bit 753" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB752 ,Active Status Bit 752" "Not active,Active" bitfld.long 0x00 15. " ASB751 ,Active Status Bit 751" "Not active,Active" bitfld.long 0x00 14. " ASB750 ,Active Status Bit 750" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB749 ,Active Status Bit 749" "Not active,Active" bitfld.long 0x00 12. " ASB748 ,Active Status Bit 748" "Not active,Active" bitfld.long 0x00 11. " ASB747 ,Active Status Bit 747" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB746 ,Active Status Bit 746" "Not active,Active" bitfld.long 0x00 9. " ASB745 ,Active Status Bit 745" "Not active,Active" bitfld.long 0x00 8. " ASB744 ,Active Status Bit 744" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB743 ,Active Status Bit 743" "Not active,Active" bitfld.long 0x00 6. " ASB742 ,Active Status Bit 742" "Not active,Active" bitfld.long 0x00 5. " ASB741 ,Active Status Bit 741" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB740 ,Active Status Bit 740" "Not active,Active" bitfld.long 0x00 3. " ASB739 ,Active Status Bit 739" "Not active,Active" bitfld.long 0x00 2. " ASB738 ,Active Status Bit 738" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB737 ,Active Status Bit 737" "Not active,Active" bitfld.long 0x00 0. " ASB736 ,Active Status Bit 736" "Not active,Active" else hgroup.long 0x035C++0x03 hide.long 0x0 "GICD_ICDABR23,Active Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" bitfld.long 0x00 31. " ASB799 ,Active Status Bit 799" "Not active,Active" bitfld.long 0x00 30. " ASB798 ,Active Status Bit 798" "Not active,Active" bitfld.long 0x00 29. " ASB797 ,Active Status Bit 797" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB796 ,Active Status Bit 796" "Not active,Active" bitfld.long 0x00 27. " ASB795 ,Active Status Bit 795" "Not active,Active" bitfld.long 0x00 26. " ASB794 ,Active Status Bit 794" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB793 ,Active Status Bit 793" "Not active,Active" bitfld.long 0x00 24. " ASB792 ,Active Status Bit 792" "Not active,Active" bitfld.long 0x00 23. " ASB791 ,Active Status Bit 791" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB790 ,Active Status Bit 790" "Not active,Active" bitfld.long 0x00 21. " ASB789 ,Active Status Bit 789" "Not active,Active" bitfld.long 0x00 20. " ASB788 ,Active Status Bit 788" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB787 ,Active Status Bit 787" "Not active,Active" bitfld.long 0x00 18. " ASB786 ,Active Status Bit 786" "Not active,Active" bitfld.long 0x00 17. " ASB785 ,Active Status Bit 785" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB784 ,Active Status Bit 784" "Not active,Active" bitfld.long 0x00 15. " ASB783 ,Active Status Bit 783" "Not active,Active" bitfld.long 0x00 14. " ASB782 ,Active Status Bit 782" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB781 ,Active Status Bit 781" "Not active,Active" bitfld.long 0x00 12. " ASB780 ,Active Status Bit 780" "Not active,Active" bitfld.long 0x00 11. " ASB779 ,Active Status Bit 779" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB778 ,Active Status Bit 778" "Not active,Active" bitfld.long 0x00 9. " ASB777 ,Active Status Bit 777" "Not active,Active" bitfld.long 0x00 8. " ASB776 ,Active Status Bit 776" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB775 ,Active Status Bit 775" "Not active,Active" bitfld.long 0x00 6. " ASB774 ,Active Status Bit 774" "Not active,Active" bitfld.long 0x00 5. " ASB773 ,Active Status Bit 773" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB772 ,Active Status Bit 772" "Not active,Active" bitfld.long 0x00 3. " ASB771 ,Active Status Bit 771" "Not active,Active" bitfld.long 0x00 2. " ASB770 ,Active Status Bit 770" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB769 ,Active Status Bit 769" "Not active,Active" bitfld.long 0x00 0. " ASB768 ,Active Status Bit 768" "Not active,Active" else hgroup.long 0x0360++0x03 hide.long 0x0 "GICD_ICDABR24,Active Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" bitfld.long 0x00 31. " ASB831 ,Active Status Bit 831" "Not active,Active" bitfld.long 0x00 30. " ASB830 ,Active Status Bit 830" "Not active,Active" bitfld.long 0x00 29. " ASB829 ,Active Status Bit 829" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB828 ,Active Status Bit 828" "Not active,Active" bitfld.long 0x00 27. " ASB827 ,Active Status Bit 827" "Not active,Active" bitfld.long 0x00 26. " ASB826 ,Active Status Bit 826" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB825 ,Active Status Bit 825" "Not active,Active" bitfld.long 0x00 24. " ASB824 ,Active Status Bit 824" "Not active,Active" bitfld.long 0x00 23. " ASB823 ,Active Status Bit 823" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB822 ,Active Status Bit 822" "Not active,Active" bitfld.long 0x00 21. " ASB821 ,Active Status Bit 821" "Not active,Active" bitfld.long 0x00 20. " ASB820 ,Active Status Bit 820" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB819 ,Active Status Bit 819" "Not active,Active" bitfld.long 0x00 18. " ASB818 ,Active Status Bit 818" "Not active,Active" bitfld.long 0x00 17. " ASB817 ,Active Status Bit 817" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB816 ,Active Status Bit 816" "Not active,Active" bitfld.long 0x00 15. " ASB815 ,Active Status Bit 815" "Not active,Active" bitfld.long 0x00 14. " ASB814 ,Active Status Bit 814" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB813 ,Active Status Bit 813" "Not active,Active" bitfld.long 0x00 12. " ASB812 ,Active Status Bit 812" "Not active,Active" bitfld.long 0x00 11. " ASB811 ,Active Status Bit 811" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB810 ,Active Status Bit 810" "Not active,Active" bitfld.long 0x00 9. " ASB809 ,Active Status Bit 809" "Not active,Active" bitfld.long 0x00 8. " ASB808 ,Active Status Bit 808" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB807 ,Active Status Bit 807" "Not active,Active" bitfld.long 0x00 6. " ASB806 ,Active Status Bit 806" "Not active,Active" bitfld.long 0x00 5. " ASB805 ,Active Status Bit 805" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB804 ,Active Status Bit 804" "Not active,Active" bitfld.long 0x00 3. " ASB803 ,Active Status Bit 803" "Not active,Active" bitfld.long 0x00 2. " ASB802 ,Active Status Bit 802" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB801 ,Active Status Bit 801" "Not active,Active" bitfld.long 0x00 0. " ASB800 ,Active Status Bit 800" "Not active,Active" else hgroup.long 0x0364++0x03 hide.long 0x0 "GICD_ICDABR25,Active Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" bitfld.long 0x00 31. " ASB863 ,Active Status Bit 863" "Not active,Active" bitfld.long 0x00 30. " ASB862 ,Active Status Bit 862" "Not active,Active" bitfld.long 0x00 29. " ASB861 ,Active Status Bit 861" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB860 ,Active Status Bit 860" "Not active,Active" bitfld.long 0x00 27. " ASB859 ,Active Status Bit 859" "Not active,Active" bitfld.long 0x00 26. " ASB858 ,Active Status Bit 858" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB857 ,Active Status Bit 857" "Not active,Active" bitfld.long 0x00 24. " ASB856 ,Active Status Bit 856" "Not active,Active" bitfld.long 0x00 23. " ASB855 ,Active Status Bit 855" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB854 ,Active Status Bit 854" "Not active,Active" bitfld.long 0x00 21. " ASB853 ,Active Status Bit 853" "Not active,Active" bitfld.long 0x00 20. " ASB852 ,Active Status Bit 852" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB851 ,Active Status Bit 851" "Not active,Active" bitfld.long 0x00 18. " ASB850 ,Active Status Bit 850" "Not active,Active" bitfld.long 0x00 17. " ASB849 ,Active Status Bit 849" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB848 ,Active Status Bit 848" "Not active,Active" bitfld.long 0x00 15. " ASB847 ,Active Status Bit 847" "Not active,Active" bitfld.long 0x00 14. " ASB846 ,Active Status Bit 846" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB845 ,Active Status Bit 845" "Not active,Active" bitfld.long 0x00 12. " ASB844 ,Active Status Bit 844" "Not active,Active" bitfld.long 0x00 11. " ASB843 ,Active Status Bit 843" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB842 ,Active Status Bit 842" "Not active,Active" bitfld.long 0x00 9. " ASB841 ,Active Status Bit 841" "Not active,Active" bitfld.long 0x00 8. " ASB840 ,Active Status Bit 840" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB839 ,Active Status Bit 839" "Not active,Active" bitfld.long 0x00 6. " ASB838 ,Active Status Bit 838" "Not active,Active" bitfld.long 0x00 5. " ASB837 ,Active Status Bit 837" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB836 ,Active Status Bit 836" "Not active,Active" bitfld.long 0x00 3. " ASB835 ,Active Status Bit 835" "Not active,Active" bitfld.long 0x00 2. " ASB834 ,Active Status Bit 834" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB833 ,Active Status Bit 833" "Not active,Active" bitfld.long 0x00 0. " ASB832 ,Active Status Bit 832" "Not active,Active" else hgroup.long 0x0368++0x03 hide.long 0x0 "GICD_ICDABR26,Active Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" bitfld.long 0x00 31. " ASB895 ,Active Status Bit 895" "Not active,Active" bitfld.long 0x00 30. " ASB894 ,Active Status Bit 894" "Not active,Active" bitfld.long 0x00 29. " ASB893 ,Active Status Bit 893" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB892 ,Active Status Bit 892" "Not active,Active" bitfld.long 0x00 27. " ASB891 ,Active Status Bit 891" "Not active,Active" bitfld.long 0x00 26. " ASB890 ,Active Status Bit 890" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB889 ,Active Status Bit 889" "Not active,Active" bitfld.long 0x00 24. " ASB888 ,Active Status Bit 888" "Not active,Active" bitfld.long 0x00 23. " ASB887 ,Active Status Bit 887" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB886 ,Active Status Bit 886" "Not active,Active" bitfld.long 0x00 21. " ASB885 ,Active Status Bit 885" "Not active,Active" bitfld.long 0x00 20. " ASB884 ,Active Status Bit 884" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB883 ,Active Status Bit 883" "Not active,Active" bitfld.long 0x00 18. " ASB882 ,Active Status Bit 882" "Not active,Active" bitfld.long 0x00 17. " ASB881 ,Active Status Bit 881" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB880 ,Active Status Bit 880" "Not active,Active" bitfld.long 0x00 15. " ASB879 ,Active Status Bit 879" "Not active,Active" bitfld.long 0x00 14. " ASB878 ,Active Status Bit 878" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB877 ,Active Status Bit 877" "Not active,Active" bitfld.long 0x00 12. " ASB876 ,Active Status Bit 876" "Not active,Active" bitfld.long 0x00 11. " ASB875 ,Active Status Bit 875" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB874 ,Active Status Bit 874" "Not active,Active" bitfld.long 0x00 9. " ASB873 ,Active Status Bit 873" "Not active,Active" bitfld.long 0x00 8. " ASB872 ,Active Status Bit 872" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB871 ,Active Status Bit 871" "Not active,Active" bitfld.long 0x00 6. " ASB870 ,Active Status Bit 870" "Not active,Active" bitfld.long 0x00 5. " ASB869 ,Active Status Bit 869" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB868 ,Active Status Bit 868" "Not active,Active" bitfld.long 0x00 3. " ASB867 ,Active Status Bit 867" "Not active,Active" bitfld.long 0x00 2. " ASB866 ,Active Status Bit 866" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB865 ,Active Status Bit 865" "Not active,Active" bitfld.long 0x00 0. " ASB864 ,Active Status Bit 864" "Not active,Active" else hgroup.long 0x036C++0x03 hide.long 0x0 "GICD_ICDABR27,Active Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" bitfld.long 0x00 31. " ASB927 ,Active Status Bit 927" "Not active,Active" bitfld.long 0x00 30. " ASB926 ,Active Status Bit 926" "Not active,Active" bitfld.long 0x00 29. " ASB925 ,Active Status Bit 925" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB924 ,Active Status Bit 924" "Not active,Active" bitfld.long 0x00 27. " ASB923 ,Active Status Bit 923" "Not active,Active" bitfld.long 0x00 26. " ASB922 ,Active Status Bit 922" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB921 ,Active Status Bit 921" "Not active,Active" bitfld.long 0x00 24. " ASB920 ,Active Status Bit 920" "Not active,Active" bitfld.long 0x00 23. " ASB919 ,Active Status Bit 919" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB918 ,Active Status Bit 918" "Not active,Active" bitfld.long 0x00 21. " ASB917 ,Active Status Bit 917" "Not active,Active" bitfld.long 0x00 20. " ASB916 ,Active Status Bit 916" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB915 ,Active Status Bit 915" "Not active,Active" bitfld.long 0x00 18. " ASB914 ,Active Status Bit 914" "Not active,Active" bitfld.long 0x00 17. " ASB913 ,Active Status Bit 913" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB912 ,Active Status Bit 912" "Not active,Active" bitfld.long 0x00 15. " ASB911 ,Active Status Bit 911" "Not active,Active" bitfld.long 0x00 14. " ASB910 ,Active Status Bit 910" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB909 ,Active Status Bit 909" "Not active,Active" bitfld.long 0x00 12. " ASB908 ,Active Status Bit 908" "Not active,Active" bitfld.long 0x00 11. " ASB907 ,Active Status Bit 907" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB906 ,Active Status Bit 906" "Not active,Active" bitfld.long 0x00 9. " ASB905 ,Active Status Bit 905" "Not active,Active" bitfld.long 0x00 8. " ASB904 ,Active Status Bit 904" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB903 ,Active Status Bit 903" "Not active,Active" bitfld.long 0x00 6. " ASB902 ,Active Status Bit 902" "Not active,Active" bitfld.long 0x00 5. " ASB901 ,Active Status Bit 901" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB900 ,Active Status Bit 900" "Not active,Active" bitfld.long 0x00 3. " ASB899 ,Active Status Bit 899" "Not active,Active" bitfld.long 0x00 2. " ASB898 ,Active Status Bit 898" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB897 ,Active Status Bit 897" "Not active,Active" bitfld.long 0x00 0. " ASB896 ,Active Status Bit 896" "Not active,Active" else hgroup.long 0x0370++0x03 hide.long 0x0 "GICD_ICDABR28,Active Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" bitfld.long 0x00 31. " ASB959 ,Active Status Bit 959" "Not active,Active" bitfld.long 0x00 30. " ASB958 ,Active Status Bit 958" "Not active,Active" bitfld.long 0x00 29. " ASB957 ,Active Status Bit 957" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB956 ,Active Status Bit 956" "Not active,Active" bitfld.long 0x00 27. " ASB955 ,Active Status Bit 955" "Not active,Active" bitfld.long 0x00 26. " ASB954 ,Active Status Bit 954" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB953 ,Active Status Bit 953" "Not active,Active" bitfld.long 0x00 24. " ASB952 ,Active Status Bit 952" "Not active,Active" bitfld.long 0x00 23. " ASB951 ,Active Status Bit 951" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB950 ,Active Status Bit 950" "Not active,Active" bitfld.long 0x00 21. " ASB949 ,Active Status Bit 949" "Not active,Active" bitfld.long 0x00 20. " ASB948 ,Active Status Bit 948" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB947 ,Active Status Bit 947" "Not active,Active" bitfld.long 0x00 18. " ASB946 ,Active Status Bit 946" "Not active,Active" bitfld.long 0x00 17. " ASB945 ,Active Status Bit 945" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB944 ,Active Status Bit 944" "Not active,Active" bitfld.long 0x00 15. " ASB943 ,Active Status Bit 943" "Not active,Active" bitfld.long 0x00 14. " ASB942 ,Active Status Bit 942" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB941 ,Active Status Bit 941" "Not active,Active" bitfld.long 0x00 12. " ASB940 ,Active Status Bit 940" "Not active,Active" bitfld.long 0x00 11. " ASB939 ,Active Status Bit 939" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB938 ,Active Status Bit 938" "Not active,Active" bitfld.long 0x00 9. " ASB937 ,Active Status Bit 937" "Not active,Active" bitfld.long 0x00 8. " ASB936 ,Active Status Bit 936" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB935 ,Active Status Bit 935" "Not active,Active" bitfld.long 0x00 6. " ASB934 ,Active Status Bit 934" "Not active,Active" bitfld.long 0x00 5. " ASB933 ,Active Status Bit 933" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB932 ,Active Status Bit 932" "Not active,Active" bitfld.long 0x00 3. " ASB931 ,Active Status Bit 931" "Not active,Active" bitfld.long 0x00 2. " ASB930 ,Active Status Bit 930" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB929 ,Active Status Bit 929" "Not active,Active" bitfld.long 0x00 0. " ASB928 ,Active Status Bit 928" "Not active,Active" else hgroup.long 0x0374++0x03 hide.long 0x0 "GICD_ICDABR29,Active Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" bitfld.long 0x00 31. " ASB991 ,Active Status Bit 991" "Not active,Active" bitfld.long 0x00 30. " ASB990 ,Active Status Bit 990" "Not active,Active" bitfld.long 0x00 29. " ASB989 ,Active Status Bit 989" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB988 ,Active Status Bit 988" "Not active,Active" bitfld.long 0x00 27. " ASB987 ,Active Status Bit 987" "Not active,Active" bitfld.long 0x00 26. " ASB986 ,Active Status Bit 986" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB985 ,Active Status Bit 985" "Not active,Active" bitfld.long 0x00 24. " ASB984 ,Active Status Bit 984" "Not active,Active" bitfld.long 0x00 23. " ASB983 ,Active Status Bit 983" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB982 ,Active Status Bit 982" "Not active,Active" bitfld.long 0x00 21. " ASB981 ,Active Status Bit 981" "Not active,Active" bitfld.long 0x00 20. " ASB980 ,Active Status Bit 980" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB979 ,Active Status Bit 979" "Not active,Active" bitfld.long 0x00 18. " ASB978 ,Active Status Bit 978" "Not active,Active" bitfld.long 0x00 17. " ASB977 ,Active Status Bit 977" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB976 ,Active Status Bit 976" "Not active,Active" bitfld.long 0x00 15. " ASB975 ,Active Status Bit 975" "Not active,Active" bitfld.long 0x00 14. " ASB974 ,Active Status Bit 974" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB973 ,Active Status Bit 973" "Not active,Active" bitfld.long 0x00 12. " ASB972 ,Active Status Bit 972" "Not active,Active" bitfld.long 0x00 11. " ASB971 ,Active Status Bit 971" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB970 ,Active Status Bit 970" "Not active,Active" bitfld.long 0x00 9. " ASB969 ,Active Status Bit 969" "Not active,Active" bitfld.long 0x00 8. " ASB968 ,Active Status Bit 968" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB967 ,Active Status Bit 967" "Not active,Active" bitfld.long 0x00 6. " ASB966 ,Active Status Bit 966" "Not active,Active" bitfld.long 0x00 5. " ASB965 ,Active Status Bit 965" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB964 ,Active Status Bit 964" "Not active,Active" bitfld.long 0x00 3. " ASB963 ,Active Status Bit 963" "Not active,Active" bitfld.long 0x00 2. " ASB962 ,Active Status Bit 962" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB961 ,Active Status Bit 961" "Not active,Active" bitfld.long 0x00 0. " ASB960 ,Active Status Bit 960" "Not active,Active" else hgroup.long 0x0378++0x03 hide.long 0x0 "GICD_ICDABR30,Active Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)==0x1F) rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active" bitfld.long 0x00 26. " ASB1018 ,Active Status Bit 1018" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active" bitfld.long 0x00 24. " ASB1016 ,Active Status Bit 1016" "Not active,Active" bitfld.long 0x00 23. " ASB1015 ,Active Status Bit 1015" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active" bitfld.long 0x00 21. " ASB1013 ,Active Status Bit 1013" "Not active,Active" bitfld.long 0x00 20. " ASB1012 ,Active Status Bit 1012" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active" bitfld.long 0x00 18. " ASB1010 ,Active Status Bit 1010" "Not active,Active" bitfld.long 0x00 17. " ASB1009 ,Active Status Bit 1009" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active" bitfld.long 0x00 15. " ASB1007 ,Active Status Bit 1007" "Not active,Active" bitfld.long 0x00 14. " ASB1006 ,Active Status Bit 1006" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active" bitfld.long 0x00 12. " ASB1004 ,Active Status Bit 1004" "Not active,Active" bitfld.long 0x00 11. " ASB1003 ,Active Status Bit 1003" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active" bitfld.long 0x00 9. " ASB1001 ,Active Status Bit 1001" "Not active,Active" bitfld.long 0x00 8. " ASB1000 ,Active Status Bit 1000" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB999 ,Active Status Bit 999" "Not active,Active" bitfld.long 0x00 6. " ASB998 ,Active Status Bit 998" "Not active,Active" bitfld.long 0x00 5. " ASB997 ,Active Status Bit 997" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB996 ,Active Status Bit 996" "Not active,Active" bitfld.long 0x00 3. " ASB995 ,Active Status Bit 995" "Not active,Active" bitfld.long 0x00 2. " ASB994 ,Active Status Bit 994" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB993 ,Active Status Bit 993" "Not active,Active" bitfld.long 0x00 0. " ASB992 ,Active Status Bit 992" "Not active,Active" else hgroup.long 0x037C++0x03 hide.long 0x0 "GICD_ICDABR31,Active Status Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 20. tree "Priority Registers" group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else hgroup.long 0x420++0x03 hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hgroup.long 0x424++0x03 hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hgroup.long 0x428++0x03 hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hgroup.long 0x42C++0x03 hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hgroup.long 0x430++0x03 hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hgroup.long 0x434++0x03 hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hgroup.long 0x438++0x03 hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hgroup.long 0x43C++0x03 hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else hgroup.long 0x440++0x03 hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hgroup.long 0x444++0x03 hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hgroup.long 0x448++0x03 hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hgroup.long 0x44C++0x03 hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hgroup.long 0x450++0x03 hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hgroup.long 0x454++0x03 hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hgroup.long 0x458++0x03 hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hgroup.long 0x45C++0x03 hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else hgroup.long 0x460++0x03 hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hgroup.long 0x464++0x03 hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hgroup.long 0x468++0x03 hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hgroup.long 0x46C++0x03 hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hgroup.long 0x470++0x03 hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hgroup.long 0x474++0x03 hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hgroup.long 0x478++0x03 hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hgroup.long 0x47C++0x03 hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else hgroup.long 0x480++0x03 hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hgroup.long 0x484++0x03 hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hgroup.long 0x488++0x03 hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hgroup.long 0x48C++0x03 hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hgroup.long 0x490++0x03 hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hgroup.long 0x494++0x03 hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hgroup.long 0x498++0x03 hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hgroup.long 0x49C++0x03 hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else hgroup.long 0x4A0++0x03 hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hgroup.long 0x4A4++0x03 hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hgroup.long 0x4A8++0x03 hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hgroup.long 0x4AC++0x03 hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hgroup.long 0x4B0++0x03 hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hgroup.long 0x4B4++0x03 hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hgroup.long 0x4B8++0x03 hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hgroup.long 0x4BC++0x03 hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else hgroup.long 0x4C0++0x03 hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hgroup.long 0x4C4++0x03 hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hgroup.long 0x4C8++0x03 hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hgroup.long 0x4CC++0x03 hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hgroup.long 0x4D0++0x03 hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hgroup.long 0x4D4++0x03 hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hgroup.long 0x4D8++0x03 hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hgroup.long 0x4DC++0x03 hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else hgroup.long 0x4E0++0x03 hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hgroup.long 0x4E4++0x03 hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hgroup.long 0x4E8++0x03 hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hgroup.long 0x4EC++0x03 hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hgroup.long 0x4F0++0x03 hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hgroup.long 0x4F4++0x03 hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hgroup.long 0x4F8++0x03 hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hgroup.long 0x4FC++0x03 hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else hgroup.long 0x500++0x03 hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hgroup.long 0x504++0x03 hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hgroup.long 0x508++0x03 hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hgroup.long 0x50C++0x03 hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hgroup.long 0x510++0x03 hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hgroup.long 0x514++0x03 hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hgroup.long 0x518++0x03 hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hgroup.long 0x51C++0x03 hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else hgroup.long 0x520++0x03 hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hgroup.long 0x524++0x03 hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hgroup.long 0x528++0x03 hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hgroup.long 0x52C++0x03 hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hgroup.long 0x530++0x03 hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hgroup.long 0x534++0x03 hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hgroup.long 0x538++0x03 hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hgroup.long 0x53C++0x03 hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else hgroup.long 0x540++0x03 hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hgroup.long 0x544++0x03 hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hgroup.long 0x548++0x03 hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hgroup.long 0x54C++0x03 hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hgroup.long 0x550++0x03 hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hgroup.long 0x554++0x03 hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hgroup.long 0x558++0x03 hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hgroup.long 0x55C++0x03 hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else hgroup.long 0x560++0x03 hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hgroup.long 0x564++0x03 hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hgroup.long 0x568++0x03 hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hgroup.long 0x56C++0x03 hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hgroup.long 0x570++0x03 hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hgroup.long 0x574++0x03 hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hgroup.long 0x578++0x03 hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hgroup.long 0x57C++0x03 hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else hgroup.long 0x580++0x03 hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hgroup.long 0x584++0x03 hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hgroup.long 0x588++0x03 hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hgroup.long 0x58C++0x03 hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hgroup.long 0x590++0x03 hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hgroup.long 0x594++0x03 hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hgroup.long 0x598++0x03 hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hgroup.long 0x59C++0x03 hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else hgroup.long 0x5A0++0x03 hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hgroup.long 0x5A4++0x03 hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hgroup.long 0x5A8++0x03 hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hgroup.long 0x5AC++0x03 hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hgroup.long 0x5B0++0x03 hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hgroup.long 0x5B4++0x03 hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hgroup.long 0x5B8++0x03 hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hgroup.long 0x5BC++0x03 hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else hgroup.long 0x5C0++0x03 hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hgroup.long 0x5C4++0x03 hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hgroup.long 0x5C8++0x03 hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hgroup.long 0x5CC++0x03 hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hgroup.long 0x5D0++0x03 hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hgroup.long 0x5D4++0x03 hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hgroup.long 0x5D8++0x03 hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hgroup.long 0x5DC++0x03 hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else hgroup.long 0x5E0++0x03 hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hgroup.long 0x5E4++0x03 hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hgroup.long 0x5E8++0x03 hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hgroup.long 0x5EC++0x03 hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hgroup.long 0x5F0++0x03 hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hgroup.long 0x5F4++0x03 hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hgroup.long 0x5F8++0x03 hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hgroup.long 0x5FC++0x03 hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else hgroup.long 0x600++0x03 hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hgroup.long 0x604++0x03 hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hgroup.long 0x608++0x03 hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hgroup.long 0x60C++0x03 hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hgroup.long 0x610++0x03 hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hgroup.long 0x614++0x03 hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hgroup.long 0x618++0x03 hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hgroup.long 0x61C++0x03 hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else hgroup.long 0x620++0x03 hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hgroup.long 0x624++0x03 hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hgroup.long 0x628++0x03 hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hgroup.long 0x62C++0x03 hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hgroup.long 0x630++0x03 hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hgroup.long 0x634++0x03 hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hgroup.long 0x638++0x03 hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hgroup.long 0x63C++0x03 hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else hgroup.long 0x640++0x03 hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hgroup.long 0x644++0x03 hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hgroup.long 0x648++0x03 hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hgroup.long 0x64C++0x03 hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hgroup.long 0x650++0x03 hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hgroup.long 0x654++0x03 hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hgroup.long 0x658++0x03 hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hgroup.long 0x65C++0x03 hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else hgroup.long 0x660++0x03 hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hgroup.long 0x664++0x03 hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hgroup.long 0x668++0x03 hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hgroup.long 0x66C++0x03 hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hgroup.long 0x670++0x03 hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hgroup.long 0x674++0x03 hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hgroup.long 0x678++0x03 hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hgroup.long 0x67C++0x03 hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else hgroup.long 0x680++0x03 hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hgroup.long 0x684++0x03 hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hgroup.long 0x688++0x03 hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hgroup.long 0x68C++0x03 hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hgroup.long 0x690++0x03 hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hgroup.long 0x694++0x03 hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hgroup.long 0x698++0x03 hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hgroup.long 0x69C++0x03 hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else hgroup.long 0x6A0++0x03 hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hgroup.long 0x6A4++0x03 hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hgroup.long 0x6A8++0x03 hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hgroup.long 0x6AC++0x03 hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hgroup.long 0x6B0++0x03 hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hgroup.long 0x6B4++0x03 hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hgroup.long 0x6B8++0x03 hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hgroup.long 0x6BC++0x03 hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else hgroup.long 0x6C0++0x03 hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hgroup.long 0x6C4++0x03 hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hgroup.long 0x6C8++0x03 hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hgroup.long 0x6CC++0x03 hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hgroup.long 0x6D0++0x03 hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hgroup.long 0x6D4++0x03 hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hgroup.long 0x6D8++0x03 hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hgroup.long 0x6DC++0x03 hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else hgroup.long 0x6E0++0x03 hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hgroup.long 0x6E4++0x03 hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hgroup.long 0x6E8++0x03 hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hgroup.long 0x6EC++0x03 hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hgroup.long 0x6F0++0x03 hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hgroup.long 0x6F4++0x03 hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hgroup.long 0x6F8++0x03 hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hgroup.long 0x6FC++0x03 hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else hgroup.long 0x700++0x03 hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hgroup.long 0x704++0x03 hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hgroup.long 0x708++0x03 hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hgroup.long 0x70C++0x03 hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hgroup.long 0x710++0x03 hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hgroup.long 0x714++0x03 hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hgroup.long 0x718++0x03 hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hgroup.long 0x71C++0x03 hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else hgroup.long 0x720++0x03 hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hgroup.long 0x724++0x03 hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hgroup.long 0x728++0x03 hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hgroup.long 0x72C++0x03 hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hgroup.long 0x730++0x03 hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hgroup.long 0x734++0x03 hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hgroup.long 0x738++0x03 hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hgroup.long 0x73C++0x03 hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else hgroup.long 0x740++0x03 hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hgroup.long 0x744++0x03 hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hgroup.long 0x748++0x03 hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hgroup.long 0x74C++0x03 hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hgroup.long 0x750++0x03 hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hgroup.long 0x754++0x03 hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hgroup.long 0x758++0x03 hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hgroup.long 0x75C++0x03 hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else hgroup.long 0x760++0x03 hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hgroup.long 0x764++0x03 hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hgroup.long 0x768++0x03 hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hgroup.long 0x76C++0x03 hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hgroup.long 0x770++0x03 hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hgroup.long 0x774++0x03 hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hgroup.long 0x778++0x03 hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hgroup.long 0x77C++0x03 hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else hgroup.long 0x780++0x03 hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hgroup.long 0x784++0x03 hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hgroup.long 0x788++0x03 hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hgroup.long 0x78C++0x03 hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hgroup.long 0x790++0x03 hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hgroup.long 0x794++0x03 hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hgroup.long 0x798++0x03 hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hgroup.long 0x79C++0x03 hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else hgroup.long 0x7A0++0x03 hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hgroup.long 0x7A4++0x03 hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hgroup.long 0x7A8++0x03 hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hgroup.long 0x7AC++0x03 hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hgroup.long 0x7B0++0x03 hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hgroup.long 0x7B4++0x03 hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hgroup.long 0x7B8++0x03 hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hgroup.long 0x7BC++0x03 hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else hgroup.long 0x7C0++0x03 hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hgroup.long 0x7C4++0x03 hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hgroup.long 0x7C8++0x03 hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hgroup.long 0x7CC++0x03 hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hgroup.long 0x7D0++0x03 hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hgroup.long 0x7D4++0x03 hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hgroup.long 0x7D8++0x03 hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hgroup.long 0x7DC++0x03 hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1F) group.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 " group.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 " group.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000" group.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004" group.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008" group.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012" group.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016" else hgroup.long 0x7E0++0x03 hide.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hgroup.long 0x7E4++0x03 hide.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hgroup.long 0x7E8++0x03 hide.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hgroup.long 0x7EC++0x03 hide.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hgroup.long 0x7F0++0x03 hide.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hgroup.long 0x7F4++0x03 hide.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hgroup.long 0x7F8++0x03 hide.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" endif tree.end width 19. tree "Processor Targets Registers" if (((d.l(AD:0x48241000+0x04))&0x000000E0)>0x1) rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 " if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1F) group.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 " group.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 " group.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000" group.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004" group.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008" group.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012" group.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016" else hgroup.long 0xBE0++0x03 hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hgroup.long 0xBE4++0x03 hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hgroup.long 0xBE8++0x03 hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hgroup.long 0xBEC++0x03 hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hgroup.long 0xBF0++0x03 hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hgroup.long 0xBF4++0x03 hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hgroup.long 0xBF8++0x03 hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif else hgroup.long 0x800++0x03 hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " hgroup.long 0x804++0x03 hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " hgroup.long 0x808++0x03 hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " hgroup.long 0x80C++0x03 hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " hgroup.long 0x810++0x03 hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " hgroup.long 0x814++0x03 hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " hgroup.long 0x818++0x03 hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " hgroup.long 0x81C++0x03 hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " hgroup.long 0x820++0x03 hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " hgroup.long 0x824++0x03 hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " hgroup.long 0x828++0x03 hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " hgroup.long 0x82C++0x03 hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " hgroup.long 0x830++0x03 hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " hgroup.long 0x834++0x03 hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " hgroup.long 0x838++0x03 hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " hgroup.long 0x83C++0x03 hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " hgroup.long 0x840++0x03 hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " hgroup.long 0x844++0x03 hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " hgroup.long 0x848++0x03 hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " hgroup.long 0x84C++0x03 hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " hgroup.long 0x850++0x03 hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " hgroup.long 0x854++0x03 hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " hgroup.long 0x858++0x03 hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " hgroup.long 0x85C++0x03 hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " hgroup.long 0x860++0x03 hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " hgroup.long 0x864++0x03 hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " hgroup.long 0x868++0x03 hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " hgroup.long 0x86C++0x03 hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " hgroup.long 0x870++0x03 hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " hgroup.long 0x874++0x03 hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " hgroup.long 0x878++0x03 hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " hgroup.long 0x87C++0x03 hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " hgroup.long 0x880++0x03 hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " hgroup.long 0x884++0x03 hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " hgroup.long 0x888++0x03 hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " hgroup.long 0x88C++0x03 hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " hgroup.long 0x890++0x03 hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " hgroup.long 0x894++0x03 hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " hgroup.long 0x898++0x03 hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " hgroup.long 0x89C++0x03 hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " hgroup.long 0x8A0++0x03 hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " hgroup.long 0x8A4++0x03 hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " hgroup.long 0x8A8++0x03 hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " hgroup.long 0x8AC++0x03 hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " hgroup.long 0x8B0++0x03 hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " hgroup.long 0x8B4++0x03 hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " hgroup.long 0x8B8++0x03 hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " hgroup.long 0x8BC++0x03 hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " hgroup.long 0x8C0++0x03 hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " hgroup.long 0x8C4++0x03 hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " hgroup.long 0x8C8++0x03 hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " hgroup.long 0x8CC++0x03 hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " hgroup.long 0x8D0++0x03 hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " hgroup.long 0x8D4++0x03 hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " hgroup.long 0x8D8++0x03 hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " hgroup.long 0x8DC++0x03 hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " hgroup.long 0x8E0++0x03 hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " hgroup.long 0x8E4++0x03 hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " hgroup.long 0x8E8++0x03 hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " hgroup.long 0x8EC++0x03 hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " hgroup.long 0x8F0++0x03 hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " hgroup.long 0x8F4++0x03 hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " hgroup.long 0x8F8++0x03 hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " hgroup.long 0x8FC++0x03 hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " hgroup.long 0x900++0x03 hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " hgroup.long 0x904++0x03 hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " hgroup.long 0x908++0x03 hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " hgroup.long 0x90C++0x03 hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " hgroup.long 0x910++0x03 hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " hgroup.long 0x914++0x03 hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " hgroup.long 0x918++0x03 hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " hgroup.long 0x91C++0x03 hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " hgroup.long 0x920++0x03 hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " hgroup.long 0x924++0x03 hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " hgroup.long 0x928++0x03 hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " hgroup.long 0x92C++0x03 hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " hgroup.long 0x930++0x03 hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " hgroup.long 0x934++0x03 hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " hgroup.long 0x938++0x03 hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " hgroup.long 0x93C++0x03 hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " hgroup.long 0x940++0x03 hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " hgroup.long 0x944++0x03 hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " hgroup.long 0x948++0x03 hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " hgroup.long 0x94C++0x03 hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " hgroup.long 0x950++0x03 hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " hgroup.long 0x954++0x03 hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " hgroup.long 0x958++0x03 hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " hgroup.long 0x95C++0x03 hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " hgroup.long 0x960++0x03 hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " hgroup.long 0x964++0x03 hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " hgroup.long 0x968++0x03 hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " hgroup.long 0x96C++0x03 hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " hgroup.long 0x970++0x03 hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " hgroup.long 0x974++0x03 hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " hgroup.long 0x978++0x03 hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " hgroup.long 0x97C++0x03 hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " hgroup.long 0x980++0x03 hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " hgroup.long 0x984++0x03 hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " hgroup.long 0x988++0x03 hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " hgroup.long 0x98C++0x03 hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " hgroup.long 0x990++0x03 hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hgroup.long 0x994++0x03 hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hgroup.long 0x998++0x03 hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hgroup.long 0x99C++0x03 hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hgroup.long 0x9A0++0x03 hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hgroup.long 0x9A4++0x03 hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hgroup.long 0x9A8++0x03 hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hgroup.long 0x9AC++0x03 hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hgroup.long 0x9B0++0x03 hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hgroup.long 0x9B4++0x03 hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hgroup.long 0x9B8++0x03 hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hgroup.long 0x9BC++0x03 hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hgroup.long 0x9C0++0x03 hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hgroup.long 0x9C4++0x03 hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hgroup.long 0x9C8++0x03 hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hgroup.long 0x9CC++0x03 hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hgroup.long 0x9D0++0x03 hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hgroup.long 0x9D4++0x03 hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hgroup.long 0x9D8++0x03 hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hgroup.long 0x9DC++0x03 hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hgroup.long 0x9E0++0x03 hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hgroup.long 0x9E4++0x03 hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hgroup.long 0x9E8++0x03 hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hgroup.long 0x9EC++0x03 hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hgroup.long 0x9F0++0x03 hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hgroup.long 0x9F4++0x03 hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hgroup.long 0x9F8++0x03 hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hgroup.long 0x9FC++0x03 hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hgroup.long 0xA00++0x03 hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hgroup.long 0xA04++0x03 hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hgroup.long 0xA08++0x03 hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hgroup.long 0xA0C++0x03 hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hgroup.long 0xA10++0x03 hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hgroup.long 0xA14++0x03 hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hgroup.long 0xA18++0x03 hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hgroup.long 0xA1C++0x03 hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hgroup.long 0xA20++0x03 hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hgroup.long 0xA24++0x03 hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hgroup.long 0xA28++0x03 hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hgroup.long 0xA2C++0x03 hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hgroup.long 0xA30++0x03 hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hgroup.long 0xA34++0x03 hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hgroup.long 0xA38++0x03 hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hgroup.long 0xA3C++0x03 hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hgroup.long 0xA40++0x03 hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hgroup.long 0xA44++0x03 hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hgroup.long 0xA48++0x03 hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hgroup.long 0xA4C++0x03 hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hgroup.long 0xA50++0x03 hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hgroup.long 0xA54++0x03 hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hgroup.long 0xA58++0x03 hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hgroup.long 0xA5C++0x03 hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hgroup.long 0xA60++0x03 hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hgroup.long 0xA64++0x03 hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hgroup.long 0xA68++0x03 hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hgroup.long 0xA6C++0x03 hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hgroup.long 0xA70++0x03 hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hgroup.long 0xA74++0x03 hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hgroup.long 0xA78++0x03 hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hgroup.long 0xA7C++0x03 hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hgroup.long 0xA80++0x03 hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hgroup.long 0xA84++0x03 hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hgroup.long 0xA88++0x03 hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hgroup.long 0xA8C++0x03 hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hgroup.long 0xA90++0x03 hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hgroup.long 0xA94++0x03 hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hgroup.long 0xA98++0x03 hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hgroup.long 0xA9C++0x03 hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hgroup.long 0xAA0++0x03 hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hgroup.long 0xAA4++0x03 hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hgroup.long 0xAA8++0x03 hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hgroup.long 0xAAC++0x03 hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hgroup.long 0xAB0++0x03 hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hgroup.long 0xAB4++0x03 hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hgroup.long 0xAB8++0x03 hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hgroup.long 0xABC++0x03 hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hgroup.long 0xAC0++0x03 hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hgroup.long 0xAC4++0x03 hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hgroup.long 0xAC8++0x03 hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hgroup.long 0xACC++0x03 hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hgroup.long 0xAD0++0x03 hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hgroup.long 0xAD4++0x03 hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hgroup.long 0xAD8++0x03 hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hgroup.long 0xADC++0x03 hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hgroup.long 0xAE0++0x03 hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hgroup.long 0xAE4++0x03 hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hgroup.long 0xAE8++0x03 hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hgroup.long 0xAEC++0x03 hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hgroup.long 0xAF0++0x03 hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hgroup.long 0xAF4++0x03 hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hgroup.long 0xAF8++0x03 hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hgroup.long 0xAFC++0x03 hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hgroup.long 0xB00++0x03 hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hgroup.long 0xB04++0x03 hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hgroup.long 0xB08++0x03 hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hgroup.long 0xB0C++0x03 hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hgroup.long 0xB10++0x03 hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hgroup.long 0xB14++0x03 hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hgroup.long 0xB18++0x03 hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hgroup.long 0xB1C++0x03 hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hgroup.long 0xB20++0x03 hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hgroup.long 0xB24++0x03 hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hgroup.long 0xB28++0x03 hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hgroup.long 0xB2C++0x03 hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hgroup.long 0xB30++0x03 hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hgroup.long 0xB34++0x03 hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hgroup.long 0xB38++0x03 hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hgroup.long 0xB3C++0x03 hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hgroup.long 0xB40++0x03 hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hgroup.long 0xB44++0x03 hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hgroup.long 0xB48++0x03 hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hgroup.long 0xB4C++0x03 hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hgroup.long 0xB50++0x03 hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hgroup.long 0xB54++0x03 hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hgroup.long 0xB58++0x03 hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hgroup.long 0xB5C++0x03 hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hgroup.long 0xB60++0x03 hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hgroup.long 0xB64++0x03 hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hgroup.long 0xB68++0x03 hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hgroup.long 0xB6C++0x03 hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hgroup.long 0xB70++0x03 hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hgroup.long 0xB74++0x03 hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hgroup.long 0xB78++0x03 hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hgroup.long 0xB7C++0x03 hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hgroup.long 0xB80++0x03 hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hgroup.long 0xB84++0x03 hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hgroup.long 0xB88++0x03 hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hgroup.long 0xB8C++0x03 hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hgroup.long 0xB90++0x03 hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hgroup.long 0xB94++0x03 hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hgroup.long 0xB98++0x03 hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hgroup.long 0xB9C++0x03 hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hgroup.long 0xBA0++0x03 hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hgroup.long 0xBA4++0x03 hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hgroup.long 0xBA8++0x03 hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hgroup.long 0xBAC++0x03 hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hgroup.long 0xBB0++0x03 hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hgroup.long 0xBB4++0x03 hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hgroup.long 0xBB8++0x03 hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hgroup.long 0xBBC++0x03 hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hgroup.long 0xBC0++0x03 hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hgroup.long 0xBC4++0x03 hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hgroup.long 0xBC8++0x03 hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hgroup.long 0xBCC++0x03 hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hgroup.long 0xBD0++0x03 hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hgroup.long 0xBD4++0x03 hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hgroup.long 0xBD8++0x03 hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hgroup.long 0xBDC++0x03 hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hgroup.long 0xBE0++0x03 hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hgroup.long 0xBE4++0x03 hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hgroup.long 0xBE8++0x03 hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hgroup.long 0xBEC++0x03 hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hgroup.long 0xBF0++0x03 hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hgroup.long 0xBF4++0x03 hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hgroup.long 0xBF8++0x03 hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif tree.end width 14. tree "Configuration Registers" hgroup.long 0xC00++0x03 hide.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" textline " " rgroup.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC08++0x03 hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" hgroup.long 0xC0C++0x03 hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC10++0x03 hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" hgroup.long 0xC14++0x03 hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC18++0x03 hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" hgroup.long 0xC1C++0x03 hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC20++0x03 hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" hgroup.long 0xC24++0x03 hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC28++0x03 hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" hgroup.long 0xC2C++0x03 hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC30++0x03 hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" hgroup.long 0xC34++0x03 hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC38++0x03 hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" hgroup.long 0xC3C++0x03 hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC40++0x03 hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" hgroup.long 0xC44++0x03 hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC48++0x03 hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" hgroup.long 0xC4C++0x03 hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC50++0x03 hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" hgroup.long 0xC54++0x03 hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC58++0x03 hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" hgroup.long 0xC5C++0x03 hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC60++0x03 hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" hgroup.long 0xC64++0x03 hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC68++0x03 hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" hgroup.long 0xC6C++0x03 hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC70++0x03 hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" hgroup.long 0xC74++0x03 hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC78++0x03 hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" hgroup.long 0xC7C++0x03 hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC80++0x03 hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" hgroup.long 0xC84++0x03 hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC88++0x03 hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" hgroup.long 0xC8C++0x03 hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC90++0x03 hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" hgroup.long 0xC94++0x03 hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xC98++0x03 hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" hgroup.long 0xC9C++0x03 hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCA0++0x03 hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" hgroup.long 0xCA4++0x03 hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCA8++0x03 hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" hgroup.long 0xCAC++0x03 hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCB0++0x03 hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" hgroup.long 0xCB4++0x03 hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCB8++0x03 hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" hgroup.long 0xCBC++0x03 hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCC0++0x03 hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" hgroup.long 0xCC4++0x03 hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCC8++0x03 hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" hgroup.long 0xCCC++0x03 hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCD0++0x03 hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" hgroup.long 0xCD4++0x03 hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCD8++0x03 hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" hgroup.long 0xCDC++0x03 hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCE0++0x03 hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" hgroup.long 0xCE4++0x03 hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCE8++0x03 hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" hgroup.long 0xCEC++0x03 hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCF0++0x03 hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" hgroup.long 0xCF4++0x03 hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1F) group.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else hgroup.long 0xCF8++0x03 hide.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" hgroup.long 0xCFC++0x03 hide.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" endif tree.end width 12. tree "Peripheral Interrupt Status Registers" rgroup.long 0x0D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI_C[15] ,Returns the status of the ppi_c[15] inputs on the Distributor" "Low,High" bitfld.long 0x00 14. " PPI_C[14] ,Returns the status of the ppi_c[14] inputs on the Distributor" "Low,High" bitfld.long 0x00 13. " PPI_C[13] ,Returns the status of the ppi_c[13] inputs on the Distributor" "Low,High" bitfld.long 0x00 12. " PPI_C[12] ,Returns the status of the ppi_c[12] inputs on the Distributor" "Low,High" textline " " bitfld.long 0x00 11. " PPI_C[11] ,Returns the status of the ppi_c[11] inputs on the Distributor" "Low,High" bitfld.long 0x00 10. " PPI_C[10] ,Returns the status of the ppi_c[10] inputs on the Distributor" "Low,High" bitfld.long 0x00 9. " PPI_C[9] ,Returns the status of the ppi_c[9] inputs on the Distributor" "Low,High" bitfld.long 0x00 8. " PPI_C[8] ,Returns the status of the ppi_c[8] inputs on the Distributor" "Low,High" textline " " bitfld.long 0x00 7. " PPI_C[7] ,Returns the status of the ppi_c[7] inputs on the Distributor" "Low,High" bitfld.long 0x00 6. " PPI_C[6] ,Returns the status of the ppi_c[6] inputs on the Distributor" "Low,High" bitfld.long 0x00 5. " PPI_C[5] ,Returns the status of the ppi_c[5] inputs on the Distributor" "Low,High" bitfld.long 0x00 4. " PPI_C[4] ,Returns the status of the ppi_c[4] inputs on the Distributor" "Low,High" textline " " bitfld.long 0x00 3. " PPI_C[3] ,Returns the status of the ppi_c[3] inputs on the Distributor" "Low,High" bitfld.long 0x00 2. " PPI_C[2] ,Returns the status of the ppi_c[2] inputs on the Distributor" "Low,High" bitfld.long 0x00 1. " PPI_C[1] ,Returns the status of the ppi_c[1] inputs on the Distributor" "Low,High" bitfld.long 0x00 0. " PPI_C[0] ,Returns the status of the ppi_c[0] inputs on the Distributor" "Low,High" textline " " width 22. if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x01) rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High" bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High" bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High" textline " " bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High" bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High" bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High" textline " " bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High" bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High" bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High" textline " " bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High" bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High" bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High" textline " " bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High" bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High" bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High" textline " " bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High" bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High" bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High" textline " " bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High" bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High" bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High" textline " " bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High" bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High" bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High" textline " " bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High" bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High" bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High" textline " " bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High" bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High" bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High" textline " " bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High" bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High" else hgroup.long 0x0D04++0x03 hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x02) rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High" bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High" bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High" bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High" bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High" bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High" bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High" bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High" bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High" bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High" bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High" bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High" bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High" bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High" bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High" bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High" bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High" bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High" bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High" bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High" bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High" bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High" else hgroup.long 0x0D08++0x03 hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x03) rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High" bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High" bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High" bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High" bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High" bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High" bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High" bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High" bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High" bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High" bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High" bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High" bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High" bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High" bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High" bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High" bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High" bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High" bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High" bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High" bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High" bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High" else hgroup.long 0x0D0C++0x03 hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x04) rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High" bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High" bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High" bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High" bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High" bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High" bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High" bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High" bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High" bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High" bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High" bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High" bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High" bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High" bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High" bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High" bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High" bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High" bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High" bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High" bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High" bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High" else hgroup.long 0x0D10++0x03 hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x05) rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High" bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High" bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High" bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High" bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High" bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High" bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High" bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High" bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High" bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High" bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High" bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High" bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High" bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High" bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High" bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High" bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High" bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High" bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High" bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High" bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High" bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High" else hgroup.long 0x0D14++0x03 hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x06) rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High" bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High" bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High" bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High" bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High" bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High" bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High" bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High" bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High" bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High" bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High" bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High" bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High" bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High" bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High" bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High" bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High" bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High" bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High" bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High" bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High" bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High" else hgroup.long 0x0D18++0x03 hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x07) rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High" bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High" bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High" bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High" bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High" bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High" bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High" bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High" bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High" bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High" bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High" bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High" bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High" bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High" bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High" bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High" bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High" bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High" bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High" bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High" bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High" bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High" else hgroup.long 0x0D1C++0x03 hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x08) rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High" bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High" bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High" bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High" bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High" bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High" bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High" bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High" bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High" bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High" bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High" bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High" bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High" bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High" bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High" bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High" bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High" bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High" bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High" bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High" bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High" bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High" else hgroup.long 0x0D20++0x03 hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x09) rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High" bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High" bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High" bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High" bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High" bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High" bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High" bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High" bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High" bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High" bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High" bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High" bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High" bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High" bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High" bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High" bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High" bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High" bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High" bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High" bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High" bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High" else hgroup.long 0x0D24++0x03 hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High" bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High" bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High" bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High" bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High" bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High" bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High" bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High" bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High" bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High" bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High" bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High" bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High" bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High" bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High" bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High" bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High" bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High" bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High" bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High" bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High" bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High" else hgroup.long 0x0D28++0x03 hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0B) rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High" bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High" bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High" bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High" bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High" bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High" bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High" bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High" bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High" bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High" bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High" bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High" bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High" bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High" bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High" bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High" bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High" bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High" bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High" bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High" bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High" bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High" else hgroup.long 0x0D2C++0x03 hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High" bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High" bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High" bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High" bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High" bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High" bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High" bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High" bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High" bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High" bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High" bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High" bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High" bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High" bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High" bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High" bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High" bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High" bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High" bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High" bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High" bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High" else hgroup.long 0x0D30++0x03 hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High" bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High" bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High" bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High" bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High" bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High" bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High" bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High" bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High" bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High" bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High" bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High" bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High" bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High" bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High" bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High" bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High" bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High" bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High" bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High" bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High" bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High" else hgroup.long 0x0D34++0x03 hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High" bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High" bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High" bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High" bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High" bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High" bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High" bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High" bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High" bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High" bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High" bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High" bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High" bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High" bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High" bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High" bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High" bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High" bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High" bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High" bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High" bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High" else hgroup.long 0x0D38++0x03 hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x0F) rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High" bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High" bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High" bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High" bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High" bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High" bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High" bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High" bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High" bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High" bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High" bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High" bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High" bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High" bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High" bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High" bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High" bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High" bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High" bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High" bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High" bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High" else hgroup.long 0x0D3C++0x03 hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x10) rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High" bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High" bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High" bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High" bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High" bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High" bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High" bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High" bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High" bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High" bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High" bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High" bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High" bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High" bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High" bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High" bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High" bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High" bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High" bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High" bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High" bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High" else hgroup.long 0x0D40++0x03 hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x11) rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High" bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High" bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High" bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High" bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High" bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High" bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High" bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High" bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High" bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High" bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High" bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High" bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High" bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High" bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High" bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High" bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High" bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High" bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High" bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High" bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High" bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High" else hgroup.long 0x0D44++0x03 hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x12) rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High" bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High" bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High" bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High" bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High" bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High" bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High" bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High" bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High" bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High" bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High" bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High" bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High" bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High" bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High" bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High" bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High" bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High" bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High" bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High" bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High" bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High" else hgroup.long 0x0D48++0x03 hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x13) rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High" bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High" bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High" bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High" bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High" bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High" bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High" bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High" bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High" bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High" bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High" bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High" bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High" bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High" bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High" bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High" bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High" bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High" bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High" bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High" bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High" bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High" else hgroup.long 0x0D4C++0x03 hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x14) rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High" bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High" bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High" bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High" bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High" bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High" bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High" bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High" bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High" bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High" bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High" bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High" bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High" bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High" bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High" bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High" bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High" bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High" bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High" bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High" bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High" bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High" else hgroup.long 0x0D50++0x03 hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x15) rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High" bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High" bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High" bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High" bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High" bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High" bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High" bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High" bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High" bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High" bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High" bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High" bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High" bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High" bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High" bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High" bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High" bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High" bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High" bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High" bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High" bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High" else hgroup.long 0x0D54++0x03 hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x16) rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High" bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High" bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High" bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High" bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High" bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High" bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High" bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High" bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High" bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High" bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High" bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High" bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High" bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High" bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High" bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High" bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High" bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High" bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High" bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High" bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High" bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High" else hgroup.long 0x0D58++0x03 hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x17) rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High" bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High" bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High" bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High" bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High" bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High" bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High" bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High" bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High" bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High" bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High" bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High" bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High" bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High" bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High" bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High" bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High" bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High" bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High" bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High" bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High" bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High" else hgroup.long 0x0D5C++0x03 hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x18) rgroup.long 0x060++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High" bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High" bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High" bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High" bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High" bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High" bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High" bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High" bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High" bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High" bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High" bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High" bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High" bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High" bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High" bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High" bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High" bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High" bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High" bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High" bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High" bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High" else hgroup.long 0x0D60++0x03 hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x19) rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High" bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High" bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High" bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High" bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High" bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High" bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High" bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High" bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High" bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High" bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High" bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High" bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High" bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High" bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High" bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High" bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High" bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High" bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High" bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High" bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High" bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High" else hgroup.long 0x0D64++0x03 hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High" bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High" bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High" bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High" bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High" bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High" bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High" bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High" bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High" bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High" bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High" bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High" bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High" bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High" bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High" bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High" bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High" bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High" bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High" bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High" bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High" bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High" else hgroup.long 0x0D68++0x03 hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1B) rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High" bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High" bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High" bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High" bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High" bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High" bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High" bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High" bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High" bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High" bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High" bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High" bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High" bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High" bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High" bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High" bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High" bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High" bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High" bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High" bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High" bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High" else hgroup.long 0x0D6C++0x03 hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High" bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High" bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High" bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High" bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High" bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High" bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High" bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High" bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High" bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High" bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High" bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High" bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High" bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High" bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High" bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High" bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High" bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High" bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High" bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High" bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High" bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High" else hgroup.long 0x0D70++0x03 hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High" bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High" bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High" bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High" bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High" bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High" bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High" bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High" bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High" bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High" bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High" bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High" bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High" bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High" bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High" bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High" bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High" bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High" bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High" bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High" bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High" bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High" else hgroup.long 0x0D74++0x03 hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High" bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High" bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High" bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High" bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High" bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High" bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High" bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High" bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High" bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High" bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High" bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High" bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High" bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High" bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High" bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High" bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High" bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High" bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High" bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High" bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High" bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High" else hgroup.long 0x0D78++0x03 hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((d.l(AD:0x48241000+0x04))&0x0000001F)>=0x1F) rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High" bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High" bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High" bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High" bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High" bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High" bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High" bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High" bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High" bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High" bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High" bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High" bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High" bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High" bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High" bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High" bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High" bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High" bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High" else hgroup.long 0x0D7C++0x03 hide.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 25. tree "Software Generated Interrupt" if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.byte 0x0FE0++0x00 line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.byte 0x00 0.--7. 1. " PART_NUMBER_0 ,Returns 0x90" rgroup.byte 0x0FE4++0x00 line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.byte 0x00 4.--7. " JEP106_ID_3_0 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PART_NUMBER_1 ,Returns 0x3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FE8++0x00 line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.byte 0x00 4.--7. " ARCHITECTURE ,Identifies the architecture version of the GIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 3. " JEDEC_USED ,This indicates that the GIC uses a manufacturers identity code that was allocated by JEDEC according to JEP106" "Low,High" bitfld.byte 0x00 0.--2. " JEP106_ID_CODE ,JEP106 identity code field" "0,1,2,3,4,5,6,7" rgroup.byte 0x0FEC++0x00 line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.byte 0x00 4.--7. " REVAND ,The top-level RTL provides four AND gates that are tied-off to provide an output value of 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " MOD_NUMBER ,The customer can update this field if they modify the RTL of the GIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD0++0x00 line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.byte 0x00 4.--7. " 4KB_COUNT ,The number of 4KB address blocks you require to access the registers expressed in powers of 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " JEP106_C_CODE ,The JEP106 continuation code value represents how many 0x7F continuation characters occur in the manufacturers identity code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD4++0x00 line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register" bitfld.byte 0x00 5.--7. " PPI_NUMBER_0 ,The LSBs of the number of PPIs that the GIC provides" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--4. " SGI_NUMBER ,The number of SGIs that the GIC provides" "None,INTID0,INTID[1:0],INTID[2:0],INTID[3:0],INTID[4:0],INTID[5:0],INTID[6:0],INTID[7:0],INTID[8:0],INTID[9:0],INTID[10:0],INTID[11:0],INTID[12:0],INTID[13:0],INTID[14:0],INTID[15:0],?..." rgroup.byte 0x0FD8++0x00 line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register" bitfld.byte 0x00 2.--7. " SPI_NUMBER_0 ,The LSBs of the number of SPIs that the GIC provides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.byte 0x00 0.--1. " PPI_NUMBER_1 ,The MSBs of the number of PPIs that the GIC provides" "0,1,2,3" rgroup.byte 0x0FDC++0x00 line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register" bitfld.byte 0x00 7. " TZ ,Identifies the number of security states that the GIC supports" "S,NS&S" bitfld.byte 0x00 4.--6. " PRIORITY ,The number of priority levels that the GIC provides" "16,32,64,128,256,?..." bitfld.byte 0x00 0.--3. " SPI_NUMBER_1 ,The MSBs of the number of SPIs that the GIC provides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FC0++0x00 line.byte 0x00 "GICD_PIDR8,Peripheral ID8 Register" bitfld.byte 0x00 7. " IDENTIFIER ,Identifies the AMBA interface that this register belongs to" "Distributor,CPU Interface" bitfld.byte 0x00 5.--6. " IF_TYPE ,Identifies the AMBA protocol that the GIC supports" "AXI,AHB-Lite,?..." bitfld.byte 0x00 2.--4. " CPU_IF ,Identifies the number of CPU Interfaces that the GIC contains" "1,2,3,4,5,6,7,8" textline " " bitfld.byte 0x00 1. " FIQ_LEGACY ,Identifies if the GIC provides a legacy FIQ input signal for each CPU Interface" "Not supported,Supported" bitfld.byte 0x00 0. " IRQ_LEGACY ,Identifies if the GIC provides a legacy IRQ input signal for each CPU Interface" "Not supported,Supported" tree.end tree.end base AD:0x48240100 width 17. tree "CPU Interface" if (((d.l(AD:0x48241000+0x04))&0x400)==0x0) group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register" bitfld.long 0x00 0. " ENABLE ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " textline " " else group.long 0x0000++0x03 line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)" bitfld.long 0x00 0. " ENABLE ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled" textline " " textline " " textline " " endif group.long 0x0004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else group.long 0x0008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" endif hgroup.long 0x000C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x0010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access" rgroup.long 0x0014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface" rgroup.long 0x0018++0x03 line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt" if (((d.l(AD:0x48241000+0x04))&0x400)==0x400) group.long 0x001C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" else hgroup.long 0x001C++0x03 hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register" endif rgroup.long 0x00FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..." textline " " bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" tree.end width 0x0B tree.end tree.end tree.open "PRCM(Power, Reset, and Clock Management)" tree "Power Managment Registers" tree "PRCM_PRM_CEFUSE" base ad:0x44DF0700 width 11. group.long 0x00++0x03 line.long 0x00 "PWRSTCTRL,This register controls the CEFUSE power state to reach upon a domain sleep transition" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Not request,Request" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,,,On" group.long 0x04++0x03 line.long 0x00 "PWRSTST,This register provides a status on the current CEFUSE power domain state" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered" "Off,,,On" rbitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "Disabled,In progress" rbitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "On,Off" rbitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,,,On" group.long 0x24++0x03 line.long 0x00 "CONTEXT,This register contains dedicated CEFUSE module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" width 11. tree.end tree "PRCM_PRM_DEVICE" base ad:0x44DF4000 width 21. group.long 0x00++0x03 line.long 0x00 "RSTCTRL,Global software cold and warm reset control" eventfld.long 0x00 1. " RST_GLOBAL_COLD_SW ,Global COLD software reset control" "No reset,Reset" eventfld.long 0x00 0. " RST_GLOBAL_WARM_SW ,Global WARM software reset control" "No reset,Reset" group.long 0x04++0x03 line.long 0x00 "RSTST,This register logs the global reset sources" eventfld.long 0x00 9. " ICEPICK_RST ,IcePick reset event" "No reset,Reset" eventfld.long 0x00 5. " EXTERNAL_WARM_RST ,External warm reset event" "No reset,Reset" eventfld.long 0x00 4. " WDT1_RST ,Watchdog1 timer reset event" "No reset,Reset" textline " " eventfld.long 0x00 1. " GLOBAL_WARM_SW_RST ,Global warm software reset event" "No reset,Reset" eventfld.long 0x00 0. " GLOBAL_COLD_RST ,Power-on (cold) reset event" "No reset,Reset" group.long 0x08++0x03 line.long 0x00 "RSTTIME,Reset duration control" bitfld.long 0x00 10.--14. " RSTTIME2 , (Power domain) reset duration 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--9. 1. " RSTTIME1 , (Global) reset duration 1" group.long 0x0C++0x03 line.long 0x00 "SRAM_COUNT,Common setup for SRAM LDO transition counters" hexmask.long.byte 0x00 24.--31. 1. " STARTUP_COUNT , Determines the start-up duration of SRAM and ABB LDO" hexmask.long.byte 0x00 16.--23. 1. " SLPCNT_VALUE , Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high" hexmask.long.byte 0x00 8.--15. 1. " VSETUPCNT_VALUE , SRAM LDO rampup time from retention to active mode" hexmask.long.byte 0x00 0.--5. 1. " PCHARGECNT_VALUE ,Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good" group.long 0x10++0x03 line.long 0x00 "LDO_SRAM_CORE_SETUP,Setup of the SRAM LDO for CORE voltage domain" bitfld.long 0x00 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO" "Not overriden,Overriden" bitfld.long 0x00 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO" "One,Two" bitfld.long 0x00 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO" "One,Not supplied" textline " " bitfld.long 0x00 5. " ENFUNC3_EXPORT ,ENFUNC3 input of SRAM LDO" "Disabled,Enabled" bitfld.long 0x00 4. " ENFUNC2_EXPORT ,ENFUNC2 input of SRAM LDO" "Used,Not used" bitfld.long 0x00 3. " ENFUNC1_EXPORT ,ENFUNC1 input of SRAM LDO" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ABBOFF_SLEEP_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "VDDS,VDDAR" bitfld.long 0x00 1. " ABBOFF_ACT_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "VDDS,VDDAR" group.long 0x14++0x03 line.long 0x00 "LDO_SRAM_CORE_CTRL,Control and status of the SRAM LDO for CORE voltage domain" rbitfld.long 0x00 9. " SRAM_IN_TRANSITION ,SRAM LDO state machine is in transition state" "Stable,Transition state" rbitfld.long 0x00 8. " SRAMLDO_STS ,SRAMLDO status" "ACTIVE mode,RETENTION mode" bitfld.long 0x00 0. " RETMODE_EN ,Control if the SRAM LDO retention mode is used or not" "Mode off,Mode on" group.long 0x18++0x03 line.long 0x00 "LDO_SRAM_MPU_SETUP,Setup of the SRAM LDO for MPU voltage domain" bitfld.long 0x00 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO" "Not overriden,Overriden" bitfld.long 0x00 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO" "One,Two" bitfld.long 0x00 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO" "One,Not supplied" textline " " bitfld.long 0x00 5. " ENFUNC3_EXPORT ,ENFUNC3 input of SRAM LDO" "Disabled,Enabled" bitfld.long 0x00 4. " ENFUNC2_EXPORT ,ENFUNC2 input of SRAM LDO" "Used,Not used" bitfld.long 0x00 3. " ENFUNC1_EXPORT ,ENFUNC1 input of SRAM LDO" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ABBOFF_SLEEP_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "VDDS,VDDAR" bitfld.long 0x00 1. " ABBOFF_ACT_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "VDDS,VDDAR" bitfld.long 0x00 0. " DISABLE_RTA_EXPORT ,Control for HD memory RTA feature" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "LDO_SRAM_MPU_CTRL,Control and status of the SRAM LDO for MPU voltage domain" rbitfld.long 0x00 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state" "Stable,Transition state" rbitfld.long 0x00 8. " SRAMLDO_STS ,SRAMLDO status" "ACTIVE mode,RETENTION mode" bitfld.long 0x00 0. " RETMODE_EN ,Control if the SRAM LDO retention mode is used or not" "Mode off,Mode on" group.long 0x20++0x03 line.long 0x00 "IO_COUNT,This register allows controlling EMIF IO isolation removal setup" hexmask.long.byte 0x00 0.--7. 1. " ISO_2_ON_TIME ,Determines the setup time of the DDR IOs going out of isolation" group.long 0x24++0x03 line.long 0x00 "IO_PMCTRL,This register allows controlling power management features of the IOs." rbitfld.long 0x00 25. " IO_ISO_STS ,IO ISO Status" "Not active,Active" bitfld.long 0x00 24. " IO_ISO_CTRL ,IO ISO control" "Off,On" bitfld.long 0x00 16. " GLOBAL_WUEN ,Global IO wakeup enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " WUCLK_STS , Gives value of WUCLKOUT signal coming back from IO pad ring." "0,1" bitfld.long 0x00 8. " WUCLK_CTRL ,Direct control on WUCLKIN signal to IO pad ring" "Functional,Reset" rbitfld.long 0x00 5. " IO_ON_STS ,Gives the functional status of the IO ring" "Not all,All" textline " " bitfld.long 0x00 4. " ISOOVR_EXTEND ,Control non-EMIF IO isolation extension" "Not extended,Extended" rbitfld.long 0x00 1. " ISOCLK_STS , Gives value of ISOCLKOUT signal coming back from IO pad ring." "0,1" bitfld.long 0x00 0. " ISOCLK_OVERRIDE ,Override control on ISOCLKIN signal to IO pad ring" "Not overriden,Overriden" rgroup.long 0x28++0x03 line.long 0x00 "VC_VAL_BYPASS,This MMR has flag to indicate OPP change to EMIF to allow read/write leveling." bitfld.long 0x00 25. " OPP_CHANGE_EMIF_LVL , This bit controls read-write leveling of EMIF memories (DDR3)" "Enabled,Disabled" group.long 0x30++0x03 line.long 0x00 "EMIF_CTRL,This register controls EMIF controller low power configurations." bitfld.long 0x00 0. " EMIF_DEVOFF ,EMIF Controller DeepSleep Mode Enable" "Disabled,Enabled" width 11. tree.end tree "PRCM_PRM_GFX" base ad:0x44DF0400 width 18. group.long 0x00++0x03 line.long 0x00 "PM_GFX_PWRSTCTRL,This register controls the GFX power state to reach upon a domain sleep transition" rbitfld.long 0x00 16.--17. " GFX_MEM_ONSTATE ,GFX memory state when domain is ON" ",,,On" bitfld.long 0x00 8. " GFX_MEM_RETSTATE ,GFX_MEM bank state when domain is retention" "Off,Retained" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Not request,Request" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,,,On" group.long 0x04++0x03 line.long 0x00 "PM_GFX_PWRSTST,This register provides a status on the current GFX power domain state" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered" "OFF,RETENTION,ON-INACTIVE,ON-ACTIVE" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "Disabled,In progress" bitfld.long 0x00 4.--5. " GFX_MEM_STATEST ,GFX memory state status" "OFF,RETENTION,,ON" textline " " bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "Off,On" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "Off,,,On" group.long 0x10++0x03 line.long 0x00 "RM_GFX_RSTCTRL,This register controls the release of the GFX Domain resets." bitfld.long 0x00 0. " GFX_RST ,GFX domain local reset control" "Cleared,Asserted" group.long 0x14++0x03 line.long 0x00 "RM_GFX_RSTST,This register logs the different reset sources of the GFX domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x00 0. " GFX_RST ,GFX Domain Logic Reset" "No reset,Reset" group.long 0x24++0x03 line.long 0x00 "RM_GFX_CONTEXT,This register contains dedicated GFX context statuses. [warm reset insensitive]" eventfld.long 0x00 8. " LOSTMEM_GFX_MEM ,Specify if memory-based context in GFX_MEM memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" width 11. tree.end tree "PRM_MPU" base ad:0x44DF0300 width 15. group.long 0x00++0x03 line.long 0x00 "MPU_PWRSTCTRL,This register controls the MPU power state to reach upon mpu domain sleep transition" rbitfld.long 0x00 20.--21. " MPU_L2_ONSTATE ,Default power domain memory state when domain is ON" ",,,On" rbitfld.long 0x00 18.--19. " MPU_L1_ONSTATE ,Default power domain memory state when domain is ON" ",,,On" rbitfld.long 0x00 16.--17. " MPU_RAM_ONSTATE ,Default power domain memory state when domain is ON" ",,,On" textline " " bitfld.long 0x00 10. " MPU_L2_RETSTATE ,L2 bank state when domain is retention" "Off,Retained" bitfld.long 0x00 9. " MPU_L1_RETSTATE ,L1 bank state when domain is retention" "Off,Retained" bitfld.long 0x00 8. " MPU_RAM_RETSTATE ,MPU RAM bank state when domain is retention" "Off,Retained" textline " " bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Not request,Request" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "RETENTION state,Whole logic" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,RETENTION,,ON" group.long 0x04++0x03 line.long 0x00 "MPU_PWRSTST,This register provides a status on the current MPU power domain state0" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered" "OFF,RETENTION,ON-INACTIVE,ON-ACTIVE" rbitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "Disabled,In progress" rbitfld.long 0x00 8.--9. " MPU_L2_STATEST ,MPU L2 memory state status" "OFF,RETENTION,,ON" rbitfld.long 0x00 6.--7. " MPU_L1_STATEST ,MPU L1 memory state status" "OFF,RETENTION,,ON" textline " " rbitfld.long 0x00 4.--5. " MPU_RAM_STATEST ,MPU_RAM memory state status" "OFF,RETENTION,,ON" rbitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "Off,On" rbitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,RETENTION,,ON" group.long 0x14++0x03 line.long 0x00 "MPU_RSTST,This register logs the different reset sources of the ALWON domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" eventfld.long 0x00 6. " ICECRUSHER_MPU_RST ,MPU Processor has been reset due to MPU ICECRUSHER1 reset event" "No reset,Reset" eventfld.long 0x00 5. " EMULATION_MPU_RST , MPU Processor has been reset due to emulation reset source" "No reset,Reset" group.long 0x24++0x03 line.long 0x00 "MPU_CONTEXT,This register contains dedicated MPU context statuses. [warm reset insensitive]" eventfld.long 0x00 10. " LOSTMEM_MPU_L2 ,Specify if memory-based context in MPU_L2 memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 9. " LOSTMEM_MPU_L1 ,Specify if memory-based context in MPU_L1 memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 8. " LOSTMEM_MPU_RAM ,Specify if memory-based context in MPU_RAM memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" width 11. tree.end tree "PRM_PER" base ad:0x44DF0800 width 28. group.long 0x000++0x03 line.long 0x00 "PER_PWRSTCTRL,Controls the power state of PER power domain" rbitfld.long 0x00 22.--23. " RAM2_MEM_ONSTATE ,OCMC RAM Group 2 (Last 192KB) memory on state" ",,,ON" rbitfld.long 0x00 20.--21. " RAM1_MEM_ONSTATE ,OCMC RAM Group 1 (First 64KB) memory on state" ",,,ON" textline " " rbitfld.long 0x00 18.--19. " PER_MEM_ONSTATE ,Other memories in PER Domain ON state" ",,,ON" rbitfld.long 0x00 16.--17. " PRU_ICSS_MEM_ONSTATE ,PRU-ICSS memory ON state" ",,,ON" bitfld.long 0x00 11. " RAM2_MEM_RETSTATE ,RAM2_MEM[OCMC RAM Group 2 (Last 192KB)] bank state when domain is retention" "Off,Retained" textline " " bitfld.long 0x00 10. " RAM1_MEM_RETSTATE ,RAM1_MEM[OCMC RAM Group 1 (First 64KB)] bank state when domain is retention" "Off,Retained" bitfld.long 0x00 9. " PER_MEM_RETSTATE ,PER_MEM bank state when domain is retention" "Off,Retained" bitfld.long 0x00 8. " PRU_ICSS_MEM_RETSTATE ,PRU-ICSS bank state when domain is retention" "Off,Retained" textline " " bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Not requested,Requested" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "Retention registers,Whole" bitfld.long 0x00 0.--1. " POWERSTATE ,PER domain power state control" "OFF,RETENTION,,ON" group.long 0x004++0x03 line.long 0x00 "PER_PWRSTST,This register provides a status on the current PER power domain state" bitfld.long 0x00 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered" "OFF,RETENTION,ON-INACTIVE,ON-ACTIVE" rbitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "Inactive,Active" textline " " rbitfld.long 0x00 10.--11. " RAM2_MEM_STATEST ,OCMC RAM Group 1 (Last 192KB) memory state status" "OFF,RETENTION,,ON" rbitfld.long 0x00 8.--9. " RAM1_MEM_STATEST ,OCMC RAM Group 1 (First 64KB) memory state status" "OFF,RETENTION,,ON" rbitfld.long 0x00 6.--7. " PER_MEM_STATEST ,PER domain memory state status" "OFF,RETENTION,,ON" textline " " rbitfld.long 0x00 4.--5. " PRU_ICSS_MEM_STATEST ,PRU-ICSS memory state status" "OFF,RETENTION,,ON" rbitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "Off,On" rbitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,RETENTION,,ON" group.long 0x010++0x03 line.long 0x00 "PER_RSTCTRL,This register controls the release of the PER Domain resets" rbitfld.long 0x00 2. " ASSERT ,ASSERT" "0,1" bitfld.long 0x00 1. " PRU_ICSS_LRST ,PER domain PRU-ICSS local reset control" "No reset,Reset" group.long 0x014++0x03 line.long 0x00 "PER_RSTST,This register logs the different reset sources of the PER domain" eventfld.long 0x00 0. " PRU_ICSS_LRST ,PRU-ICSS Processor software reset status" "No reset,Reset" group.long 0x024++0x03 line.long 0x00 "PER_L3_CONTEXT,This register contains dedicated L3 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x044++0x03 line.long 0x00 "PER_L3_INSTR_CONTEXT,This register contains dedicated L3_INSTR module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x054++0x03 line.long 0x00 "PER_OCMCRAM_CONTEXT,This register contains dedicated OCMCRAM module context statuses" eventfld.long 0x00 9. " LOSTMEM_RAM2_MEM ,Specify if memory-based context in RAM2_MEM memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 8. " LOSTMEM_RAM1_MEM ,Context has been lost" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x06C++0x03 line.long 0x00 "PER_VPFE0_CONTEXT,This register contains dedicated VPFE0 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x074++0x03 line.long 0x00 "PER_VPFE1_CONTEXT,This register contains dedicated VPFE1 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x07C++0x03 line.long 0x00 "PER_TPCC_CONTEXT,This register contains dedicated TPCC module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x084++0x03 line.long 0x00 "PER_TPTC0_CONTEXT,This register contains dedicated TPTC0 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x08C++0x03 line.long 0x00 "PER_TPTC1_CONTEXT,This register contains dedicated TPTC1 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x094++0x03 line.long 0x00 "PER_TPTC2_CONTEXT,This register contains dedicated TPTC2 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x09C++0x03 line.long 0x00 "PER_DLL_AGING_CONTEXT,This register contains dedicated DLL_AGING module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x0A4++0x03 line.long 0x00 "PER_L4HS_CONTEXT,This register contains dedicated L4HS module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x224++0x03 line.long 0x00 "PER_GPMC_CONTEXT,This register contains dedicated GPMC module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x234++0x03 line.long 0x00 "PER_ADC1_CONTEXT,This register contains dedicated ADC1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x23C++0x03 line.long 0x00 "PER_MCASP0_CONTEXT,This register contains dedicated MCASP0 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x244++0x03 line.long 0x00 "PER_MCASP1_CONTEXT,This register contains dedicated MCASP1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x24C++0x03 line.long 0x00 "PER_MMC2_CONTEXT,This register contains dedicated MMC2 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x25C++0x03 line.long 0x00 "PER_QSPI_CONTEXT,This register contains dedicated QSPI module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x264++0x03 line.long 0x00 "PER_USB_OTG_SS0_CONTEXT,This register contains dedicated USB_OTG0 context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in _BANK1 memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x26C++0x03 line.long 0x00 "PER_USB_OTG_SS1_CONTEXT,This register contains dedicated USB_OTG0 context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in _BANK1 memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x324++0x03 line.long 0x00 "PER_PRU_ICSS_CONTEXT,This register contains dedicated ICSS module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x424++0x03 line.long 0x00 "PER_L4LS_CONTEXT,This register contains dedicated L4LS module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x42C++0x03 line.long 0x00 "PER_DCAN0_CONTEXT,This register contains dedicated DCAN0 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x434++0x03 line.long 0x00 "PER_DCAN1_CONTEXT,This register contains dedicated DCAN1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x43C++0x03 line.long 0x00 "PER_PWMSS0_CONTEXT,This register contains dedicated PWMSS0 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x444++0x03 line.long 0x00 "PER_PWMSS1_CONTEXT,This register contains dedicated PWMSS1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x44C++0x03 line.long 0x00 "PER_PWMSS2_CONTEXT,This register contains dedicated PWMSS2 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x454++0x03 line.long 0x00 "PER_PWMSS3_CONTEXT,This register contains dedicated PWMSS3 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x45C++0x03 line.long 0x00 "PER_PWMSS4_CONTEXT,This register contains dedicated PWMSS4 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x464++0x03 line.long 0x00 "PER_PWMSS5_CONTEXT,This register contains dedicated PWMSS5 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x46C++0x03 line.long 0x00 "PER_ELM_CONTEXT,This register contains dedicated ELM module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x47C++0x03 line.long 0x00 "PER_GPIO1_CONTEXT,This register contains dedicated GPIO1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x484++0x03 line.long 0x00 "PER_GPIO2_CONTEXT,This register contains dedicated GPIO2 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x48C++0x03 line.long 0x00 "PER_GPIO3_CONTEXT,This register contains dedicated GPIO3 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x494++0x03 line.long 0x00 "PER_GPIO4_CONTEXT,This register contains dedicated GPIO4 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x49C++0x03 line.long 0x00 "PER_GPIO5_CONTEXT,This register contains dedicated GPIO5 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x4A4++0x03 line.long 0x00 "PER_HDQ1W_CONTEXT,This register contains dedicated HDQ1W module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x4AC++0x03 line.long 0x00 "PER_I2C1_CONTEXT,This register contains dedicated I2C1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x4B4++0x03 line.long 0x00 "PER_I2C2_CONTEXT,This register contains dedicated I2C2 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x4BC++0x03 line.long 0x00 "PER_MAILBOX0_CONTEXT,This register contains dedicated MAILBOX0 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x4C4++0x03 line.long 0x00 "PER_MMC0_CONTEXT,This register contains dedicated MMC0 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x4CC++0x03 line.long 0x00 "PER_MMC1_CONTEXT,This register contains dedicated MMC1 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x504++0x03 line.long 0x00 "PER_SPI0_CONTEXT,This register contains dedicated SPI0 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x50C++0x03 line.long 0x00 "PER_SPI1_CONTEXT,This register contains dedicated SPI1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x514++0x03 line.long 0x00 "PER_SPI2_CONTEXT,This register contains dedicated SPI2 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x51C++0x03 line.long 0x00 "PER_SPI3_CONTEXT,This register contains dedicated SPI3 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x524++0x03 line.long 0x00 "PER_SPI4_CONTEXT,This register contains dedicated SPI4 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x52C++0x03 line.long 0x00 "PER_SPINLOCK_CONTEXT,This register contains dedicated SPINLOCK module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x534++0x03 line.long 0x00 "PER_TIMER2_CONTEXT,This register contains dedicated TIMER2 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x53C++0x03 line.long 0x00 "PER_TIMER3_CONTEXT,This register contains dedicated TIMER3 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x544++0x03 line.long 0x00 "PER_TIMER4_CONTEXT,This register contains dedicated TIMER4 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x54C++0x03 line.long 0x00 "PER_TIMER5_CONTEXT,This register contains dedicated TIMER5 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x554++0x03 line.long 0x00 "PER_TIMER6_CONTEXT,This register contains dedicated TIMER6 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x55C++0x03 line.long 0x00 "PER_TIMER7_CONTEXT,This register contains dedicated TIMER7 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x564++0x03 line.long 0x00 "PER_TIMER8_CONTEXT,This register contains dedicated TIMER8 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x56C++0x03 line.long 0x00 "PER_TIMER9_CONTEXT,This register contains dedicated TIMER9 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x574++0x03 line.long 0x00 "PER_TIMER10_CONTEXT,This register contains dedicated TIMER10 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x57C++0x03 line.long 0x00 "PER_TIMER11_CONTEXT,This register contains dedicated TIMER11 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x584++0x03 line.long 0x00 "PER_UART1_CONTEXT,This register contains dedicated UART1 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x58C++0x03 line.long 0x00 "PER_UART2_CONTEXT,This register contains dedicated UART2 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x594++0x03 line.long 0x00 "PER_UART3_CONTEXT,This register contains dedicated UART3 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x59C++0x03 line.long 0x00 "PER_UART4_CONTEXT,This register contains dedicated UART4 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x5A4++0x03 line.long 0x00 "PER_UART5_CONTEXT,This register contains dedicated UART5 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x5BC++0x03 line.long 0x00 "PER_USBPHYOCP2SCP0_CONTEXT,This register contains dedicated USBPHYOCP2SCP0 context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x5C4++0x03 line.long 0x00 "PER_USBPHYOCP2SCP1_CONTEXT,This register contains dedicated USBPHYOCP2SCP0 context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x724++0x03 line.long 0x00 "PER_EMIF_CONTEXT,This register contains dedicated EMIF module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x72C++0x03 line.long 0x00 "PER_DLL_CONTEXT,This register contains dedicated DLL module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0xA24++0x03 line.long 0x00 "PER_DSS_CONTEXT,This register contains dedicated DSS module context statuses" eventfld.long 0x00 8. " LOSTMEM_DSS_MEM ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0xB24++0x03 line.long 0x00 "PER_CPGMAC0_CONTEXT,This register contains dedicated CPGMAC0 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0xC24++0x03 line.long 0x00 "PER_OCPWP_CONTEXT,This register contains dedicated OCPWP module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" width 11. tree.end tree "PRM_RTC" base ad:0x44DF0524 width 13. group.long 0x24++0x03 line.long 0x00 "RTC_CONTEXT,This register contains dedicated RTC module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" width 11. tree.end tree "PRM_WKUP" base ad:0x44DF2000 width 27. group.long 0x010++0x03 line.long 0x00 "WKUP_RSTCTRL,This register controls the release of the ALWAYS ON Domain resets." bitfld.long 0x00 3. " WKUP_PROC_LRST ,Assert Reset to WKUP_PROC" "No reset,Reset" group.long 0x014++0x03 line.long 0x00 "WKUP_RSTST,This register logs the different reset sources of the ALWON domain" eventfld.long 0x00 7. " ICECRUSHER_WKUP_PROC_RST ,Wakeup Processor has been reset due to Wakeup Processor ICECRUSHER1 reset event" "No reset,Reset" eventfld.long 0x00 6. " EMULATION_WKUP_PROC_RST ,Wakeup Processor has been reset due to emulation reset source" "No reset,Reset" eventfld.long 0x00 5. " WKUP_PROC_LRST ,Wakeup Processor has been reset" "No reset,Reset" group.long 0x024++0x03 line.long 0x00 "WKUP_DBGSS_CONTEXT,This register contains dedicated DEBUGSS module context statuses" eventfld.long 0x00 8. " LOSTMEM_DBGSS_MEM ,Specify if memory-based context in DEBUGSS_MEM memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x124++0x03 line.long 0x00 "WKUP_ADC0_CONTEXT,This register contains dedicated ADC0 module context statuses." eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x224++0x03 line.long 0x00 "WKUP_L4WKUP_CONTEXT,This register contains dedicated L4WKUP module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x22C++0x03 line.long 0x00 "WKUP_PROC_CONTEXT,This register contains dedicated WKUP_M3 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x234++0x03 line.long 0x00 "WKUP_SYNCTIMER_CONTEXT,This register contains dedicated SYNCTIMER module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x324++0x03 line.long 0x00 "WKUP_TIMER0_CONTEXT,This register contains dedicated TIMER0 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x32C++0x03 line.long 0x00 "WKUP_TIMER1_CONTEXT,This register contains dedicated TIMER1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x33C++0x03 line.long 0x00 "WKUP_WDT1_CONTEXT,This register contains dedicated WDT1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x344++0x03 line.long 0x00 "WKUP_I2C0_CONTEXT,This register contains dedicated I2C0 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x34C++0x03 line.long 0x00 "WKUP_UART0_CONTEXT,This register contains dedicated UART0 module context statuses" eventfld.long 0x00 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in RETAINED_BANK memory bank has been lost due to a previous power transition or other reset source" "Maintained,Lost" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x354++0x03 line.long 0x00 "WKUP_SMARTREFLEX0_CONTEXT,This register contains dedicated SMARTREFLEX0 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x35C++0x03 line.long 0x00 "WKUP_SMARTREFLEX1_CONTEXT,This register contains dedicated SMARTREFLEX1 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" group.long 0x36C++0x03 line.long 0x00 "WKUP_GPIO0_CONTEXT,This register contains dedicated GPIO0 module context statuses" eventfld.long 0x00 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source" "Maintained,Lost" width 11. tree.end tree "PRM_IRQ" base ad:0x44DF0000 width 27. rgroup.long 0x00++0x03 line.long 0x00 "PRCM_REVISION,This register contains the IP revision code for the PRCM" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family." textline " " bitfld.long 0x00 11.--15. " R_RTL , RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" ",,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "Standard,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision (Y)" "ES1.0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "PRCM_PRM_IRQSTS_MPU,This register provides status on MPU interrupt events" eventfld.long 0x00 16. " DPLL_EXTDEV_RECAL_ST ,ENAbles dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 15. " DPLL_PER_RECAL_ST ,Interrupt status for usb dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 14. " DPLL_DDR_RECAL_ST ,Interrupt status for ddr dpll recaliberation" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " DPLL_DISP_RECAL_ST ,ENAbles dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 12. " DPLL_CORE_RECAL_ST ,Interrupt status for core dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 11. " DPLL_MPU_RECAL_ST ,interrupt status for mpu dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 10. " FORCEWKUP_ST ,Software supervised wakeup completed event interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " IO_ST ,IO pad event interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 8. " TRANSITION_ST ,Software supervised transition completed event interrupt status (any domain)" "No interrupt,Interrupt" eventfld.long 0x00 0. " FREQ_UPDATE_ST ,Frequency Update interrupt status" "No interrupt,Interrupt" group.long 0x08++0x03 line.long 0x00 "PRCM_PRM_IRQEN_MPU,This register is used to enable and disable events used to trigger MPU interrupt activation." bitfld.long 0x00 16. " DPLL_EXTDEV_RECAL_EN ,Interrupt enable for extdev dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 15. " DPLL_DISP_RECAL_EN ,Interrupt enable for disp dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 14. " DPLL_DDR_RECAL_EN ,Interrupt enable for ddr dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 13. " DPLL_PER_RECAL_EN ,Interrupt enable for usb dpll recaliberation" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DPLL_CORE_RECAL_EN ,Interrupt enable for core dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 11. " DPLL_MPU_RECAL_EN ,Interrupt enable for mpu dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 10. " FORCEWKUP_EN ,Software supervised Froce Wakeup completed event interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IO_EN ,IO pad event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " TRANSITION_EN ,Software supervised transition completed event interrupt enable (any domain)" "Disabled,Enabled" bitfld.long 0x00 0. " FREQ_UPDATE_EN ,Frequency Update interrupt enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "PRCM_PRM_IRQSTS_WKUP_PROC,This register provides status on Wakeup Processor interrupt events" eventfld.long 0x00 16. " DPLL_EXTDEV_RECAL_ST ,Interrupt status for extdev dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 15. " DPLL_PER_RECAL_ST ,Interrupt status for usb dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 14. " DPLL_DDR_RECAL_ST ,Interrupt status for ddr dpll recaliberation" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " DPLL_DISP_RECAL_ST ,Interrupt status for disp dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 12. " DPLL_CORE_RECAL_ST ,Interrupt status for core dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 11. " DPLL_MPU_RECAL_ST ,Interrupt status for mpu dpll recaliberation" "Disabled,Enabled" eventfld.long 0x00 10. " FORCEWKUP_ST ,Software supervised wakeup completed event interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " IO_ST ,IO pad event interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 8. " TRANSITION_ST ,Software supervised transition completed event interrupt status (any domain)" "No interrupt,Interrupt" eventfld.long 0x00 0. " FREQ_UPDATE_ST ,Frequency Update interrupt status" "No interrupt,Interrupt" group.long 0x10++0x03 line.long 0x00 "PRCM_PRM_IRQEN_WKUP_PROC,This register is used to enable and disable events used to trigger Wakeup Processor interrupt activation." bitfld.long 0x00 16. " DPLL_EXTDEV_RECAL_EN ,Interrupt enable for extdev dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 15. " DPLL_DISP_RECAL_EN ,Interrupt enable for disp dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 14. " DPLL_DDR_RECAL_EN ,Interrupt enable for ddr dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 13. " DPLL_PER_RECAL_EN ,Interrupt enable for usb dpll recaliberation" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DPLL_CORE_RECAL_EN ,Interrupt enable for core dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 11. " DPLL_MPU_RECAL_EN ,Interrupt enable for mpu dpll recaliberation" "Disabled,Enabled" bitfld.long 0x00 10. " FORCEWKUP_EN ,Software supervised Froce Wakeup completed event interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " IO_EN ,IO pad event interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TRANSITION_EN ,Software supervised transition completed event interrupt enable (any domain)" "Disabled,Enabled" bitfld.long 0x00 0. " FREQ_UPDATE_EN ,Frequency Update interrupt enable" "Disabled,Enabled" width 11. tree.end tree.end tree "Clock module" tree "CM_CEFUSE" base ad:0x44DF8700 width 24. group.long 0x00++0x03 line.long 0x00 "CM_CEFUSE_CLKSTCTRL,CEFUSE Clock State Control Register" rbitfld.long 0x00 9. " CLKACTIVITY_CUST_EFUSE_SYS_CLK ,State of the Cust_Efuse_SYSCLK clock input of the domain" "Gated,Active" rbitfld.long 0x00 8. " CLKACTIVITY_L4_CEFUSE_GICLK ,State of the L4_CEFUSE_GCLK clock input of the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the clock domain in customer efuse power domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x20++0x03 line.long 0x00 "PRCM_CM_CEFUSE_CLKCTRL,This register manages the CEFUSE clocks" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," width 11. tree.end tree "CM_DEVICE" base ad:0x44DF4100 width 22. group.long 0x00++0x03 line.long 0x00 "PRCM_CM_CLKOUT1_CTRL,This register provides the control over CLKOUT1 output" bitfld.long 0x00 24. " CLKOUT_32KSEL ,32KHz clock source selection for CLKOUT1 and CLKOUT2" "32KHz,32KHz" bitfld.long 0x00 23. " CLKOUT1EN ,External clock CLKOUT1 activity" "Disabled,Enabled" bitfld.long 0x00 20.--21. " CLKOUT1SEL0DIV ,External clock CLKOUT1 when CLKOUT1SOURCE=SEL0" "1,2,3,4" bitfld.long 0x00 16.--17. " CLKOUT1SOURCE ,External output CLKOUT1 clock source" "32Khz,32Khz,Based on CLKOUT,DPLL_EXTDEV" textline " " bitfld.long 0x00 8.--10. " CLKOUT1SEL2DIV2 ,External clock CLKOUT1 first divison factor" "1,2,4,8,16,32,," bitfld.long 0x00 4.--6. " CLKOUT1SEL2DIV1 ,External clock CLKOUT1 first divison factor" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--2. " CLKOUT1SEL2SOURCE ,CLKOUT1" "32KHz,32KHz,DDR_PHY_Clk,192Mhz,LCD,MPU_PLL_CLKOUT,," group.long 0x04++0x03 line.long 0x00 "PRCM_CM_DLL_CTRL,Special register for DLL control" rbitfld.long 0x00 2. " DLL_READYST , Gives the DLL ready status" "Not ready,Ready" bitfld.long 0x00 1. " DLL_RESET ,DLL Reset" "No reset,Reset" bitfld.long 0x00 0. " DLL_OVERRIDE ,Control if DLL lock and code outputs are overriden or not" "Not overriden,Overriden" group.long 0x08++0x03 line.long 0x00 "PRCM_CM_CLKOUT2_CTRL,Control over CLKOUT2 output" bitfld.long 0x00 16. " CLKOUT2EN ,Controls the external clock activity" "Disabled,Enabled" bitfld.long 0x00 8.--10. " CLKOUT2POSTDIV ,External clock CLKOUT2 first divison factor" "1,2,4,8,16,32,," bitfld.long 0x00 4.--6. " CLKOUT2DIV ,External clock CLKOUT2 divison factor" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--2. " CLKOUT2SOURCE ,Rxternal output CLKOUT2 clock source" "32KHz,L3F_CLK,DDR_PHY_Clk,192Mhz,LCD,MPU_PLL_CLKOUT,DPLL_EXTDEV," width 11. tree.end tree "CM_DPLL" base ad:0x44DF4200 width 30. group.long 0x00++0x03 line.long 0x00 "DPLL_DPLL_CLKSEL_TIMER1_CLK,Selects the Mux select line for TIMER1 clock" bitfld.long 0x00 0.--2. " CLKSEL ,Selects the Mux select line for DMTIMER_1MS clock" "CLK_M_OSC,CLK_32KHZ from PER_PLL,TCLKIN,CLK_RC32K,32KHz from RTC,5,6,7" group.long 0x04++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER2_CLK,Selects the Mux select line for TIMER2 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER2 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x08++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER3_CLK,Selects the Mux select line for TIMER3 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER3 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x0C++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER4_CLK,Selects the Mux select line for TIMER4 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER4 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x10++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER5_CLK,Selects the Mux select line for TIMER5 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER5 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x14++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER6_CLK,Selects the Mux select line for TIMER6 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER6 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x18++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER7_CLK,Selects the Mux select line for TIMER7 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER6 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x1C++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER8_CLK,Selects the Mux select line for TIMER8 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER6 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x20++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER9_CLK,Selects the Mux select line for TIMER9 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER6 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x24++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER10_CLK,Selects the Mux select line for TIMER10 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER6 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x28++0x03 line.long 0x00 "DPLL_CLKSEL_TIMER11_CLK,Selects the Mux select line for TIMER11 clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER6 clock" "TCLKIN,CLK_M_OSC,CLK_32KHZ," group.long 0x2C++0x03 line.long 0x00 "DPLL_CLKSEL_WDT1_CLK,Selects the Mux select line for Watchdog1 clock" bitfld.long 0x00 0. " CLKSEL ,Selects the Mux select line for WDT1 clock" "32KHZ from RC,32KHZ from 32K Clock" group.long 0x30++0x03 line.long 0x00 "DPLL_CLKSEL_SYNCTIMER_CLK,Selects the Mux select line for SYNCTIMER clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for SYNCTIMER clock" "RTC 32K,,PER PLL 32KHz," group.long 0x34++0x03 line.long 0x00 "DPLL_CLKSEL_MAC_CLK,Selects the clock divide ration for MII clock" bitfld.long 0x00 2. " MII_CLK_SEL ,MII Clock Divider Selection" "1/2,1/5" group.long 0x38++0x03 line.long 0x00 "DPLL_CLKSEL_CPTS_RFT_CLK,Selects the Mux select line for CPTS RFT clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for cpgmac rft clock" "HSDIVIDER_CORE M4,HSDIVIDE_CORE M5,DISP PLL clock as CPTS RFT," group.long 0x3C++0x03 line.long 0x00 "DPLL_CLKSEL_GFX_FCLK,Selects the divider value for GFX clock" bitfld.long 0x00 1. " CLKSEL_GFX_FCLK ,Selects the clock on gfx fclk" "CORE PLL,PER PLL" bitfld.long 0x00 0. " CLKDIV_SEL_GFX_FCLK ,Selects the divider value on gfx fclk " "L3 or 192MHz,L3 clock/2 or 192Mhz/2" group.long 0x40++0x03 line.long 0x00 "DPLL_CLKSEL_GPIO0_DBCLK,Selects the Mux select line for GPIO0 debounce clock" bitfld.long 0x00 0.--2. " CLKSEL ,Selects the Mux select line for GPIO0 debounce clock" "RC Oscillator,32K Crystal Oscillator,PER_PLL,SYS_CLK,,,," group.long 0x48++0x03 line.long 0x00 "CLKSEL_PRU_ICSS_OCP_CLK,Controls Mux Select of PRU-ICSS OCP clock mux" bitfld.long 0x00 0. " CLKSEL ,Controls Mux Select of PRU-ICSS OCP clock mux" "L3F clock as OCP,DISP DPLL clock as OCP" group.long 0x4C++0x03 line.long 0x00 "CLKSEL_ADC1_CLK,Selects the Mux select line for ADC1 clock [warm reset insensitive]" bitfld.long 0x00 0. " CLKSEL ,Selects the Mux select line for ADC1 clock" "Main Crystal clock,192MHz PER PLL clock output" group.long 0x50++0x03 line.long 0x00 "DPLL_CLKSEL_DLL_AGING_CLK,Selects the clock divider for DLL_AGING module clock" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the divider value for generating the DLL_AGING clock" "/8,/16,/32," group.long 0x60++0x03 line.long 0x00 "DPLL_CLKSEL_USBPHY32KHZ_GCLK,Selects the Mux select line for USBPHY 32KHZ clock" bitfld.long 0x00 0. " CLKSEL ,Selects the Mux select line for USBPHY 32KHZ clock" "RTC 32K," width 11. tree.end tree "CM_GFX" base ad:0x44DF8400 width 26. group.long 0x00++0x03 line.long 0x00 "PRCM_CM_GFX_L3_CLKSTCTRL,Enables the domain power state transition" rbitfld.long 0x00 9. " CLKACTIVITY_GFX_FCLK ,State of the GFX_GCLK" "Gated,Active" rbitfld.long 0x00 8. " CLKACTIVITY_GFX_L3_GCLK ,State of the GFX_L3_GCLK clock" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the GFX clock domain in GFX power domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x20++0x03 line.long 0x00 "PRCM_CM_GFX_CLKCTRL,This register manages the GFX clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," width 11. tree.end tree "CM_MPU" base ad:0x44DF8300 width 23. group.long 0x00++0x03 line.long 0x00 "PRCM_CM_MPU_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. " CLKACTIVITY_MPU_CLK ,State of the MPU Clock" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the MPU clock domains" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x20++0x03 line.long 0x00 "PRCM_CM_MPU_CLKCTRL,This register manages the MPU clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Automatically,Enabled," width 11. tree.end tree "CM_PER" base ad:0x44DF8800 width 36. group.long 0x00++0x03 line.long 0x00 "PRCM_CM_PER_L3_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 10. " CLKACTIVITY_L3_GCLK ,L3_GCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 8. " CLKACTIVITY_DLL_AGING_GCLK ,DLL_AGING_GCLK clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3 clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x20++0x03 line.long 0x00 "PRCM_CM_PER_L3_CLKCTRL,This register manages the L3 Interconnect clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x40++0x03 line.long 0x00 "PRCM_CM_PER_L3_INSTR_CLKCTRL,This register manages the L3 INSTR clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x50++0x03 line.long 0x00 "PRCM_CM_PER_OCMCRAM_CLKCTRL,This register manages the OCMC clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x68++0x03 line.long 0x00 "PRCM_CM_PER_VPFE0_CLKCTRL,This register manages the VPFE0 clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x70++0x03 line.long 0x00 "PRCM_CM_PER_VPFE1_CLKCTRL,This register manages the VPFE1 clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x78++0x03 line.long 0x00 "PRCM_CM_PER_TPCC_CLKCTRL,This register manages the TPCC clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x78++0x03 line.long 0x00 "PRCM_CM_PER_TPTC0_CLKCTRL,This register manages the TPTC clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x88++0x03 line.long 0x00 "PRCM_CM_PER_TPTC0_CLKCTRL,This register manages the TPTC clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x90++0x03 line.long 0x00 "PRCM_CM_PER_TPTC2_CLKCTRL,This register manages the TPTC2 clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x98++0x03 line.long 0x00 "PRCM_CM_PER_DLL_AGING_CLKCTRL,This register manages the DLL_AGING clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0xA0++0x03 line.long 0x00 "PRCM_CM_PER_DLL_AGING_CLKCTRL,This register manages the DLL_AGING clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x200++0x03 line.long 0x00 "PRCM_CM_PER_L3S_CLKSTCTRL, register enables the domain power state transition" rbitfld.long 0x00 12. " CLKACTIVITY_USB_OTG_SS_REFCLK ,USB_OTG_SS_REFCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 11. " CLKACTIVITY_MMC_FCLK ,MMC_GCLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 10. " CLKACTIVITY_MCASP_GCLK ,MCASP_GCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 9. " CLKACTIVITY_ADC1_FGCLK ,This register manages the ADC1 clocks" "Gated,Active" textline " " rbitfld.long 0x00 8. " CLKACTIVITY_L3S_GCLK ,L3S_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3 clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x220++0x03 line.long 0x00 "PRCM_CM_PER_GPMC_CLKCTRL,This register manages the GPMC clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x230++0x03 line.long 0x00 "PRCM_CM_PER_ADC1_CLKCTRL,This register manages the ADC1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x238++0x03 line.long 0x00 "PRCM_CM_PER_MCASP0_CLKCTRL,This register manages the MCASP0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x240++0x03 line.long 0x00 "PRCM_CM_PER_MCASP1_CLKCTRL,This register manages the MCASP1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x248++0x03 line.long 0x00 "PRCM_CM_PER_MMC2_CLKCTRL,This register manages the MMC2 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x258++0x03 line.long 0x00 "PRCM_CM_PER_QSPI_CLKCTRL,This register manages the QSPI clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x260++0x03 line.long 0x00 "PRCM_CM_PER_USB_OTG_SS0_CLKCTRL,This register manages the USB_OTG_SS0 clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 8. " OPTFCLKEN_REFCLK960M ,USB_OTG optional clock control" "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x268++0x03 line.long 0x00 "PRCM_CM_PER_USB_OTG_SS1_CLKCTRL,This register manages the USB_OTG_SS1 clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 8. " OPTFCLKEN_REFCLK960M ,USB_OTG optional clock control" "Disabled,Enabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x300++0x03 line.long 0x00 "PRCM_CM_PER_PRU_ICSS_CLKSTCTRL,This register enables the clock domain state transition" rbitfld.long 0x00 10. " CLKACTIVITY_PRU_ICSS_UART_GCLK ,PRU-ICSS UART clock in the domain" "Gated,Active" rbitfld.long 0x00 9. " CLKACTIVITY_PRU_ICSS_IEP_GCLK ,PRU-ICSS IEP clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 8. " CLKACTIVITY_PRU_ICSS_OCP_GCLK ,PRU-ICSS OCP clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the PRU-ICSS OCP clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x320++0x03 line.long 0x00 "PRCM_CM_PER_PRU_ICSS_CLKCTRL,This register manages the ICSS clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x400++0x03 line.long 0x00 "PRCM_CM_PER_L4LS_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 27. " CLKACTIVITY_I2C_FCLK ,I2C_FCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 26. " CLKACTIVITY_GPIO_5_GDBCLK ,GPIO5_GDBCLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 25. " CLKACTIVITY_GPIO_4_GDBCLK ,GPIO4_GDBCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 24. " CLKACTIVITY_GPIO_3_GDBCLK ,GPIO3_GDBCLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 23. " CLKACTIVITY_GPIO_2_GDBCLK ,GPIO2_GDBCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 22. " CLKACTIVITY_GPIO_1_GDBCLK ,GPIO1_GDBCLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 21. " CLKACTIVITY_TIMER11_GCLK ,TIMER11 CLKTIMER clock in the domain" "Gated,Active" rbitfld.long 0x00 20. " CLKACTIVITY_TIMER10_GCLK ,TIMER10 CLKTIMER clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 19. " CLKACTIVITY_TIMER9_GCLK ,TIMER9 CLKTIMER clock in the domain" "Gated,Active" rbitfld.long 0x00 18. " CLKACTIVITY_TIMER8_GCLK ,TIMER8 CLKTIMER clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 17. " CLKACTIVITY_TIMER7_GCLK ,TIMER7 CLKTIMER clock in the domain" "Gated,Active" rbitfld.long 0x00 16. " CLKACTIVITY_TIMER6_GCLK ,TIMER6 CLKTIMER clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 15. " CLKACTIVITY_TIMER5_GCLK ,TIMER5 CLKTIMER clock in the domain" "Gated,Active" rbitfld.long 0x00 14. " CLKACTIVITY_TIMER4_GCLK ,TIMER4 CLKTIMER clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 13. " CLKACTIVITY_TIMER3_GCLK ,TIMER3 CLKTIMER clock in the domain" "Gated,Active" rbitfld.long 0x00 12. " CLKACTIVITY_TIMER2_GCLK ,TIMER2 CLKTIMER clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 11. " CLKACTIVITY_CAN_CLK ,CAN_CLK clock in the domain" "Gated,Active" rbitfld.long 0x00 10. " CLKACTIVITY_UART_GFCLK ,UART_GFCLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 9. " CLKACTIVITY_SPI_GCLK ,SPI_GCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 8. " CLKACTIVITY_L4LS_GCLK ,L4LS_GCLK clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL , Controls the clock state transition of the L4 SLOW clock domain in PER power domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x420++0x03 line.long 0x00 "PRCM_CM_PER_L4LS_CLKCTRL,This register manages the L4LS clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x428++0x03 line.long 0x00 "PRCM_CM_PER_DCAN0_CLKCTRL,This register manages the DCAN0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x430++0x03 line.long 0x00 "PRCM_CM_PER_DCAN1_CLKCTRL,This register manages the DCAN1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x438++0x03 line.long 0x00 "PRCM_CM_PER_PWMSS0_CLKCTRL,This register manages the PWMSS0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x440++0x03 line.long 0x00 "PRCM_CM_PER_PWMSS1_CLKCTRL,This register manages the PWMSS1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x448++0x03 line.long 0x00 "PRCM_CM_PER_PWMSS2_CLKCTRL,This register manages the PWMSS2 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x450++0x03 line.long 0x00 "PRCM_CM_PER_PWMSS3_CLKCTRL,This register manages the PWMSS3 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x458++0x03 line.long 0x00 "PRCM_CM_PER_PWMSS4_CLKCTRL,This register manages the PWMSS4 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x460++0x03 line.long 0x00 "PRCM_CM_PER_PWMSS5_CLKCTRL,This register manages the PWMSS5 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x468++0x03 line.long 0x00 "PRCM_CM_PER_ELM_CLKCTRL,This register manages the ELM clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x470++0x03 line.long 0x00 "PRCM_CM_PER_ERMC_CLKCTRL,This register manages the ERMC clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x478++0x03 line.long 0x00 "PRCM_CM_PER_GPIO1_CLKCTRL,This register manages the GPIO1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_GPIO_1_GDBCLK ,Optional functional clock control" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x480++0x03 line.long 0x00 "PRCM_CM_PER_GPIO2_CLKCTRL,This register manages the GPIO2 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_GPIO_2_GDBCLK ,Optional functional clock control" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x488++0x03 line.long 0x00 "PRCM_CM_PER_GPIO3_CLKCTRL,This register manages the GPIO3 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_GPIO_3_GDBCLK ,Optional functional clock control" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x490++0x03 line.long 0x00 "PRCM_CM_PER_GPIO4_CLKCTRL,This register manages the GPIO4 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_GPIO_4_GDBCLK ,Optional functional clock control" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x498++0x03 line.long 0x00 "PRCM_CM_PER_GPIO5_CLKCTRL,This register manages the GPIO5 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_GPIO_5_GDBCLK ,Optional functional clock control" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x4A0++0x03 line.long 0x00 "PRCM_CM_PER_HDQ1W_CLKCTRL,This register manages the HDQ1W clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x4A8++0x03 line.long 0x00 "PRCM_CM_PER_I2C1_CLKCTRL,This register manages the I2C1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x4B0++0x03 line.long 0x00 "PRCM_CM_PER_I2C2_CLKCTRL,This register manages the I2C2 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x4B8++0x03 line.long 0x00 "PRCM_CM_PER_MAILBOX0_CLKCTRL,This register manages the MAILBOX0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x4C0++0x03 line.long 0x00 "PRCM_CM_PER_MMC0_CLKCTRL,This register manages the MMC0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x4C8++0x03 line.long 0x00 "PRCM_CM_PER_MMC1_CLKCTRL,This register manages the MMC1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x500++0x03 line.long 0x00 "PRCM_CM_PER_SPI0_CLKCTRL,This register manages the SPI0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x508++0x03 line.long 0x00 "PRCM_CM_PER_SPI1_CLKCTRL,This register manages the SPI1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x510++0x03 line.long 0x00 "PRCM_CM_PER_SPI2_CLKCTRL,This register manages the SPI2 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x518++0x03 line.long 0x00 "PRCM_CM_PER_SPI3_CLKCTRL,This register manages the SPI3 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x520++0x03 line.long 0x00 "PRCM_CM_PER_SPI4_CLKCTRL,This register manages the SPI4 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x528++0x03 line.long 0x00 "PRCM_CM_PER_SPINLOCK_CLKCTRL,This register manages the SPINLOCK clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x530++0x03 line.long 0x00 "PRCM_CM_PER_TIMER2_CLKCTRL,This register manages the TIMER2 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x538++0x03 line.long 0x00 "PRCM_CM_PER_TIMER3_CLKCTRL,This register manages the TIMER3 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x540++0x03 line.long 0x00 "PRCM_CM_PER_TIMER4_CLKCTRL,This register manages the TIMER4 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x548++0x03 line.long 0x00 "PRCM_CM_PER_TIMER5_CLKCTRL,This register manages the TIMER5 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x550++0x03 line.long 0x00 "PRCM_CM_PER_TIMER6_CLKCTRL,This register manages the TIMER6 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x558++0x03 line.long 0x00 "PRCM_CM_PER_TIMER7_CLKCTRL,This register manages the TIMER7 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x560++0x03 line.long 0x00 "PRCM_CM_PER_TIMER8_CLKCTRL,This register manages the TIMER8 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x568++0x03 line.long 0x00 "PRCM_CM_PER_TIMER9_CLKCTRL,This register manages the TIMER9 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x570++0x03 line.long 0x00 "PRCM_CM_PER_TIMER10_CLKCTRL,This register manages the TIMER10 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x578++0x03 line.long 0x00 "PRCM_CM_PER_TIMER11_CLKCTRL,This register manages the TIMER11 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x580++0x03 line.long 0x00 "PRCM_CM_PER_UART1_CLKCTRL,This register manages the UART1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x588++0x03 line.long 0x00 "PRCM_CM_PER_UART2_CLKCTRL,This register manages the UART2 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x590++0x03 line.long 0x00 "PRCM_CM_PER_UART3_CLKCTRL,This register manages the UART3 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x598++0x03 line.long 0x00 "PRCM_CM_PER_UART4_CLKCTRL,This register manages the UART4 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x5A0++0x03 line.long 0x00 "PRCM_CM_PER_UART5_CLKCTRL,This register manages the UART5 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x5B8++0x03 line.long 0x00 "PRCM_CM_PER_USBPHYOCP2SCP0_CLKCTRL,This register manages the USBPHYOCP2SCP0 clocks and the optional clock of USB PHY" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x5C0++0x03 line.long 0x00 "PRCM_CM_PER_USBPHYOCP2SCP1_CLKCTRL,This register manages the USBPHYOCP2SCP1 clocks and the optional clock of USB PHY" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x700++0x03 line.long 0x00 "PRCM_CM_PER_EMIF_CLKSTCTRL,This register enables the clock domain state transition" rbitfld.long 0x00 10. " CLKACTIVITY_EMIF_PHY_GCLK ,EMIF PHY clock in the domain" "Gated,Active" rbitfld.long 0x00 9. " CLKACTIVITY_DLL_GCLK ,DLL clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 8. " CLKACTIVITY_EMIF_L3_GCLK ,EMIF L3 clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the ICSS OCP clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x720++0x03 line.long 0x00 "PRCM_CM_PER_EMIF_CLKCTRL,This register manages the EMIF clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x728++0x03 line.long 0x00 "PRCM_CM_PER_DLL_CLKCTRL,This register manages the DLL clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_DLL_CLK ,Optional functional clock control" "Disabled,Enabled" group.long 0x800++0x03 line.long 0x00 "PRCM_CM_PER_LCDC_CLKSTCTRL,This register enables the clock domain state transition" rbitfld.long 0x00 10. " CLKACTIVITY_LCDC_GCLK ,LCD clock in the domain" "Gated,Active" rbitfld.long 0x00 8. " CLKACTIVITY_LCDC_L3_OCP_GCLK ,LCDC L3 OCP clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the LCDC OCP clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0xA00++0x03 line.long 0x00 "PRCM_CM_PER_DSS_CLKSTCTRL,This register enables the clock domain state transition" rbitfld.long 0x00 11. " CLKACTIVITY_DSS_L3_OCP_GCLK ,DSS L3 OCP clock in the domain" "Gated,Active" rbitfld.long 0x00 10. " CLKACTIVITY_DSS_SYSCLK ,DSS SYSCLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 9. " CLKACTIVITY_DSS_CLK ,DSS CLK clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSS OCP clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0xA20++0x03 line.long 0x00 "PRCM_CM_PER_DSS_CLKCTRL,This register manages the DSS clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0xB00++0x03 line.long 0x00 "PRCM_CM_PER_CPSW_CLKSTCTRL,This register enables the clock domain state transition" rbitfld.long 0x00 12. " CLKACTIVITY_CPSW_5MHZ_GCLK ,CPSW_5MHZ_GCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 11. " CLKACTIVITY_CPSW_50MHZ_GCLK ,CPSW_50MHZ_GCLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 10. " CLKACTIVITY_CPSW_250MHZ_GCLK ,CPSW_250MHZ_GCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 9. " CLKACTIVITY_CPTS_RFT_GCLK ,CLKACTIVITY_CPTS_RFT_GCLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 8. " CLKACTIVITY_CPSW_125MHZ_GCLK ,CPSW 125 MHz OCP clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the CPSW OCP clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0xB20++0x03 line.long 0x00 "PRCM_CM_PER_CPGMAC0_CLKCTRL,This register manages the CPSW clocks" rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0xC00++0x03 line.long 0x00 "PRCM_CM_PER_OCPWP_L3_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 8. " CLKACTIVITY_OCPWP_L3_GCLK ,OCPWP L3 clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the OCPWP clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0xC20++0x03 line.long 0x00 "PRCM_CM_PER_OCPWP_CLKCTRL,This register manages the OCPWP clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," width 11. tree.end tree "CM_RTC" base ad:0x44DF8500 width 23. group.long 0x00++0x03 line.long 0x00 "PRCM_CM_RTC_CLKSTCTRL,This register enables the domain power state transition" bitfld.long 0x00 9. " CLKACTIVITY_RTC_32KCLK ,32K RTC clock in the domain" "Gated,Active" bitfld.long 0x00 8. " CLKACTIVITY_L4_RTC_GCLK ,L4 RTC clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,RTC clock domains" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x20++0x03 line.long 0x00 "PRCM_CM_RTC_CLKCTRL,This register manages the RTC clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," width 11. tree.end tree "CM_TAMPER" base ad:0x00 width 26. group.long 0x00++0x03 line.long 0x00 "PRCM_CM_TAMPER_CLKSTCTRL,This register enables the domain power state transition" bitfld.long 0x00 9. " CLKACTIVITY_RTC_32KCLK ,32K RTC clock in the domain" "Gated,Active" bitfld.long 0x00 8. " CLKACTIVITY_TAMPER_L4_GCLK , TAMPER_L4 clock in the domain" "Gated,Active" width 11. tree.end tree "CM_WKUP" base ad:0x44DF2800 width 35. group.long 0x00++0x03 line.long 0x00 "PRCM_CM_L3_AON_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 12. " CLKACTIVITY_DBG_CLKC ,CLKC clock in the domain" "Gated,Active" rbitfld.long 0x00 11. " CLKACTIVITY_DBG_CLKB ,CLKB clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 10. " CLKACTIVITY_DBG_CLKA ,CLKA clock in the domain" "Gated,Active" rbitfld.long 0x00 9. " CLKACTIVITY_L3_AON_GCLK ,L3_AON clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 8. " CLKACTIVITY_DBGSYSCLK ,Debugss sysclk clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the l3 AON clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x20++0x03 line.long 0x00 "PRCM_CM_WKUP_DBGSS_CLKCTRL,This register manages the DEBUGSS clocks" bitfld.long 0x00 27.--29. " STM_PMD_CLKDIVSEL ,STM Trace clock divider control" "1,,2,3,4,..." bitfld.long 0x00 24.--26. " TRC_PMD_CLKDIVSEL ,TPIU trace clock divider control" "1,,2,3,4,..." textline " " bitfld.long 0x00 22.--23. " TRC_PMD_CLKSEL ,TPIU Trace clock select" "DGBSYSCLK,CLKA,CLKB,CLKC" bitfld.long 0x00 20.--21. " STM_PMD_CLKSEL ,STM trace clock select" "DGBSYSCLK,CLKA,CLKB,CLKC" textline " " rbitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" textline " " bitfld.long 0x00 11. " OPTCLK_DBG_CLKC ,Controls Optional Functional Clock CLKC" "Disabled,Enabled" bitfld.long 0x00 10. " OPTCLK_DBG_CLKB ,Controls Optional Functional Clock CLKB" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " OPTCLK_DBG_CLKA ,Optional functional clock control" "Disabled,Enabled" bitfld.long 0x00 8. " OPTFCLKEN_DBGSYSCLK ,Optional functional clock control" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x100++0x03 line.long 0x00 "PRCM_CM_L3S_ADC0_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 9. " CLKACTIVITY_ADC0_FCLK ,ADC0 FCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 8. " CLKACTIVITY_L3S_ADC0_GCLK ,L3S_ADC0 clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the always on clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x120++0x03 line.long 0x00 "PRCM_CM_WKUP_ADC0_CLKCTRL,This register manages the ADC0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," rgroup.long 0x200++0x03 line.long 0x00 "PRCM_CM_L4_WKUP_AON_CLKSTCTRL,This register enables the domain power state transition" bitfld.long 0x00 10. " CLKACTIVITY_USBPHY_32KHZ_GCLK ,USBPHY 32KHZ clock in the domain" "Gated,Active" bitfld.long 0x00 9. " CLKACTIVITY_SYNCTIMER32K_GFCLK ,SYNCTIMER clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 8. " CLKACTIVITY_L4_WKUP_AON_GCLK ,L4_WKUP clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the always on L4 clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," rgroup.long 0x220++0x03 line.long 0x00 "PRCM_CM_WKUP_L4WKUP_CLKCTRL,This register manages the L4WKUP clocks" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," rgroup.long 0x228++0x03 line.long 0x00 "PRCM_CM_WKUP_PROC_CLKCTRL,This register manages the WKUP M3 clocks" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x230++0x03 line.long 0x00 "PRCM_CM_WKUP_SYNCTIMER_CLKCTRL,This register manages the SYNCTIMER clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_FCLK32 ,Optional functional clock control" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x238++0x03 line.long 0x00 "PRCM_CM_WKUP_CLKDIV32K_CLKCTRL,This register manages the CLKDIV32K clocks" bitfld.long 0x00 8. " OPTFCLKEN_FCLK ,Optional functional clock control" "Disabled,Enabled" group.long 0x240++0x03 line.long 0x00 "PRCM_CM_WKUP_USBPHY0_CLKCTRL,This register manages the USBPHY0 32KHz clocks" bitfld.long 0x00 8. " OPTFCLKEN_CLK32K ,Optional functional clock control" "Disabled,Enabled" group.long 0x248++0x03 line.long 0x00 "PRCM_CM_WKUP_USBPHY1_CLKCTRL,This register manages the USBPHY1 32KHz clocks" bitfld.long 0x00 8. " OPTFCLKEN_CLK32K ,Optional functional clock control" "Disabled,Enabled" group.long 0x300++0x03 line.long 0x00 "PRCM_CM_WKUP_CLKSTCTRL,This register enables the domain power state transition" rbitfld.long 0x00 16. " CLKACTIVITY_TIMER1_GCLK ,TIMER1 clock in the domain" "Gated,Active" rbitfld.long 0x00 15. " CLKACTIVITY_UART0_GFCLK ,UART0 clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 14. " CLKACTIVITY_I2C0_GFCLK ,I2C0 clock in the domain" "Gated,Active" rbitfld.long 0x00 11. " CLKACTIVITY_GPIO0_GDBCLK ,WKUPGPIO_DBGICLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 10. " CLKACTIVITY_WDT1_GCLK ,WDT1_GCLK clock in the domain" "Gated,Active" rbitfld.long 0x00 9. " CLKACTIVITY_SR_SYSCLK ,SMARTREFLEX SYSCLK clock in the domain" "Gated,Active" textline " " rbitfld.long 0x00 8. " CLKACTIVITY_L4_WKUP_GCLK ,L4_WKUP clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the always on clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP," group.long 0x320++0x03 line.long 0x00 "PRCM_CM_WKUP_TIMER0_CLKCTRL,This register manages the TIMER0clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x328++0x03 line.long 0x00 "PRCM_CM_WKUP_TIMER1_CLKCTRL,This register manages the TIMER1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x338++0x03 line.long 0x00 "PRCM_CM_WKUP_WDT1_CLKCTRL,This register manages the WDT1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x340++0x03 line.long 0x00 "PRCM_CM_WKUP_I2C0_CLKCTRL,This register manages the I2C0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x348++0x03 line.long 0x00 "PRCM_CM_WKUP_UART0_CLKCTRL,This register manages the UART0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x350++0x03 line.long 0x00 "PRCM_CM_WKUP_SMARTREFLEX0_CLKCTRL,This register manages the SmartReflex0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x358++0x03 line.long 0x00 "PRCM_CM_WKUP_SMARTREFLEX1_CLKCTRL,This register manages the SmartReflex1 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x360++0x03 line.long 0x00 "PRCM_CM_WKUP_CTRL_CLKCTRL,This register manages the Control Module clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x368++0x03 line.long 0x00 "PRCM_CM_WKUP_GPIO0_CLKCTRL,This register manages the GPIO0 clocks" rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 8. " OPTFCLKEN_GPIO0_GDBCLK ,Optional functional clock control" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,,Enabled," group.long 0x520++0x03 line.long 0x00 "PRCM_CM_CLKMODE_DPLL_CORE,This register manages the DPLL clocks" bitfld.long 0x00 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square Wave" bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "Both sides,Lower side" textline " " rbitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL" "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL" "Disabled,Enabled" bitfld.long 0x00 10. " DPLL_LPMODE_EN , Set the DPLL in Low Power mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " DPLL_RELOCK_RAMP_EN ,Clock ramping enable" "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,Enable/disable the automatic recalibration feature of the DPLL" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--7. " DPLL_RAMP_RATE ,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "2,4,8,16,32,64,128,512" bitfld.long 0x00 3.--4. " DPLL_RAMP_LEVEL ,Clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "No ramping,/8 /4 /2=>2/8 2/4 2/2,/4 /2 /1.5=> 2/4 2/2 2/1.5," textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control" ",,,,MN Bypass,Bypass Low,Bypass Fast,Lock" rgroup.long 0x524++0x03 line.long 0x00 "PRCM_CM_IDLEST_DPLL_CORE,This register allows monitoring the master clock activity" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "No,MN_Bypass" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "Bypass/Stop,Locked" group.long 0x52C++0x03 line.long 0x00 "PRCM_CM_CLKSEL_DPLL_CORE,This register provides controls over the DPLL" hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor" hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor" group.long 0x538++0x03 line.long 0x00 "PRCM_CM_DIV_M4_DPLL_CORE,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER" bitfld.long 0x00 12. " HSDIVIDER_CLKOUT1_PWDN ,Power down for HSDIVIDER M4 divider and hence CLKOUT1 output" "Active,Powered down" rbitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT1 ,HSDIVIDER CLKOUT1 status" "Gated,Enabled" textline " " bitfld.long 0x00 8. " HSDIVIDER_CLKOUT1_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT1" "Gated,Enabled" rbitfld.long 0x00 5. " HSDIVIDER_CLKOUT1_DIVCHACK ,Divider value status" "No effect,Effect" textline " " bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT1_DIV ,DPLL post-divider factor M4 for internal clock generation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x53C++0x03 line.long 0x00 "PRCM_CM_DIV_M5_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER" bitfld.long 0x00 12. " HSDIVIDER_CLKOUT2_PWDN ,Power down for HSDIVIDER M5 divider and hence CLKOUT2 output" "Active,Powered down" rbitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT2 ,HSDIVIDER CLKOUT2 status" "Gated,Enabled" textline " " bitfld.long 0x00 8. " HSDIVIDER_CLKOUT2_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT2" "Gated,Enabled" rbitfld.long 0x00 5. " HSDIVIDER_CLKOUT2_DIVCHACK ,Divider value status" "No effect,Effect" textline " " bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT2_DIV ,DPLL post-divider factor M5 for internal clock generation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x540++0x03 line.long 0x00 "PRCM_CM_DIV_M6_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER" bitfld.long 0x00 12. " HSDIVIDER_CLKOUT3_PWDN ,Power down for HSDIVIDER M6 divider and hence CLKOUT3 output" "Active,Powered down" rbitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT3 ,HSDIVIDER CLKOUT3 status" "Gated,Enabled" textline " " bitfld.long 0x00 8. " HSDIVIDER_CLKOUT3_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT3" "Gated,Enabled" rbitfld.long 0x00 5. " HSDIVIDER_CLKOUT3_DIVCHACK ,Divider value status" "No effect,Effect" textline " " bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT3_DIV ,DPLL post-divider factor M6 for internal clock generation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x548++0x03 line.long 0x00 "PRCM_CM_SSC_DELTAMSTEP_DPLL_CORE,Control the DeltaMStep parameter" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" group.long 0x54C++0x03 line.long 0x00 "PRCM_CM_SSC_MODFREQDIV_DPLL_CORE,Control the Modulation Frequency" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x560++0x03 line.long 0x00 "PRCM_CM_CLKMODE_DPLL_MPU,This register allows controlling the DPLL modes" bitfld.long 0x00 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square Wave" bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "Both sides,Lower side" textline " " rbitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL" "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL" "Disabled,Enabled" bitfld.long 0x00 10. " DPLL_LPMODE_EN , Set the DPLL in Low Power mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " DPLL_RELOCK_RAMP_EN ,Clock ramping enable" "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,Enable/disable the automatic recalibration feature of the DPLL" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--7. " DPLL_RAMP_RATE ,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "2,4,8,16,32,64,128,512" bitfld.long 0x00 3.--4. " DPLL_RAMP_LEVEL ,Clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "No ramping,/8 /4 /2=>2/8 2/4 2/2,/4 /2 /1.5=> 2/4 2/2 2/1.5," textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control" ",,,,MN Bypass,Bypass Low,Bypass Fast,Lock" rgroup.long 0x564++0x03 line.long 0x00 "PRCM_CM_IDLEST_DPLL_MPU,This register allows monitoring the master clock activity" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "No,MN_Bypass" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "Bypass/Stop,Locked" if (((d.l(ad:0x44DF2800+0x56C))&0x400000)==0x400000) //this.DCC_EN== "ENABLED" group.long 0x56C++0x03 line.long 0x00 "PRCM_CM_CLKSEL_DPLL_MPU,This register provides controls over the DPLL" hexmask.long.byte 0x00 24.--31. 1. " DCC_COUNT_MAX ,The value 'NbCycles' set in this field" bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Selects CLKINP or CLKINPULOW as Bypass Clock" "CLKINP,CLKINPULOW" textline " " bitfld.long 0x00 22. " DCC_EN ,Enable or disable Duty Cycle Correction" "Disabled,Enabled" hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor" textline " " hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor" else group.long 0x56C++0x03 line.long 0x00 "PRCM_CM_CLKSEL_DPLL_MPU,This register provides controls over the DPLL" bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Selects CLKINP or CLKINPULOW as Bypass Clock" "CLKINP,CLKINPULOW" bitfld.long 0x00 22. " DCC_EN ,Enable or disable Duty Cycle Correction" "Disabled,Enabled" textline " " hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor" hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor" endif group.long 0x570++0x03 line.long 0x00 "PRCM_CM_DIV_M2_DPLL_MPU,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status" "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT" "Gated,Enabled" textline " " rbitfld.long 0x00 5. " DPLL_CLKOUT_DIVCHACK ,Divider value status" "No effect,Effect" bitfld.long 0x00 0.--4. " DPLL_CLKOUT_DIV ,DPLL M2 post-divider factor" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x588++0x03 line.long 0x00 "PRCM_CM_SSC_DELTAMSTEP_DPLL_MPU,Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" group.long 0x58C++0x03 line.long 0x00 "PRCM_CM_SSC_MODFREQDIV_DPLL_MPU,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x5A0++0x03 line.long 0x00 "PRCM_CM_CLKMODE_DPLL_DDR,This register allows controlling the DPLL modes" bitfld.long 0x00 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square Wave" bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "Both sides,Lower side" textline " " rbitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL" "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL" "Disabled,Enabled" bitfld.long 0x00 10. " DPLL_LPMODE_EN , Set the DPLL in Low Power mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " DPLL_RELOCK_RAMP_EN ,Clock ramping enable" "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,Enable/disable the automatic recalibration feature of the DPLL" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--7. " DPLL_RAMP_RATE ,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "2,4,8,16,32,64,128,512" bitfld.long 0x00 3.--4. " DPLL_RAMP_LEVEL ,Clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "No ramping,/8 /4 /2=>2/8 2/4 2/2,/4 /2 /1.5=> 2/4 2/2 2/1.5," textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control" ",,,,MN Bypass,Bypass Low,Bypass Fast,Lock" rgroup.long 0x5A4++0x03 line.long 0x00 "PRCM_CM_IDLEST_DPLL_DDR,This register allows monitoring the master clock activity" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "No,MN_Bypass" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "Bypass/Stop,Locked" group.long 0x5AC++0x03 line.long 0x00 "PRCM_CM_CLKSEL_DPLL_DDR,This register provides controls over the DPLL" bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Selects CLKINP or CLKINPULOW as Bypass Clock" "CLKINP,CLKINPULOW" bitfld.long 0x00 22. " DCC_EN ,Enable or disable Duty Cycle Correction" "Disabled,Enabled" textline " " hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor" hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor" group.long 0x5B0++0x03 line.long 0x00 "PRCM_CM_DIV_M2_DPLL_DDR,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status" "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT" "Gated,Enabled" textline " " rbitfld.long 0x00 5. " DPLL_CLKOUT_DIVCHACK ,Divider value status" "No effect,Effect" bitfld.long 0x00 0.--4. " DPLL_CLKOUT_DIV ,DPLL M2 post-divider factor" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5B8++0x03 line.long 0x00 "PRCM_CM_DIV_M4_DPLL_DDR,This register provides controls over the CLKOUT1 o/p of the DDR PLL HSDIVIDER" bitfld.long 0x00 12. " HSDIVIDER_CLKOUT1_PWDN ,Power down for HSDIVIDER M4 divider and hence CLKOUT1 output" "Active,Powered down" rbitfld.long 0x00 9. " ST_HSDIVIDER_CLKOUT1 ,HSDIVIDER CLKOUT1 status" "Gated,Enabled" textline " " bitfld.long 0x00 8. " HSDIVIDER_CLKOUT1_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT1" "Gated,Enabled" rbitfld.long 0x00 5. " HSDIVIDER_CLKOUT1_DIVCHACK ,Divider value status" "No effect,Effect" textline " " bitfld.long 0x00 0.--4. " HSDIVIDER_CLKOUT1_DIV ,DPLL post-divider factor M4 for internal clock generation" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x5C8++0x03 line.long 0x00 "PRCM_CM_SSC_DELTAMSTEP_DPLL_DDR,Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" group.long 0x5CC++0x03 line.long 0x00 "PRCM_CM_SSC_MODFREQDIV_DPLL_DDR,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x5E0++0x03 line.long 0x00 "PRCM_CM_CLKMODE_DPLL_PER,This register allows controlling the DPLL modes" bitfld.long 0x00 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square Wave" bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "Both sides,Lower side" textline " " rbitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL" "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control" ",,,,MN Bypass,Bypass Low,,Lock" rgroup.long 0x5E4++0x03 line.long 0x00 "PRCM_CM_IDLEST_DPLL_PER,This register allows monitoring the master clock activity" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "No,MN_Bypass" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "Bypass/Stop,Locked" group.long 0x5EC++0x03 line.long 0x00 "PRCM_CM_CLKSEL_DPLL_PER,This register provides controls over the DPLL" hexmask.long.byte 0x00 24.--31. 1. " DPLL_SD_DIV ,Sigma-Delta divider select" hexmask.long.word 0x00 8.--19. 1. " DPLL_MULT ,DPLL multiplier factor" textline " " hexmask.long.byte 0x00 0.--7. 1. " DPLL_DIV ,DPLL divider factor" group.long 0x5F0++0x03 line.long 0x00 "PRCM_CM_DIV_M2_DPLL_PER,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status" "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT" "Gated,Enabled" textline " " rbitfld.long 0x00 7. " DPLL_CLKOUT_DIVCHACK ,Divider value status" "No effect,Effect" hexmask.long.byte 0x00 0.--6. 1. " DPLL_CLKOUT_DIV ,DPLL M2 post-divider factor" group.long 0x604++0x03 line.long 0x00 "PRCM_CM_CLKSEL2_DPLL_PER,This register provides DPLL fractional multiplier factor control and BandWidth Control for PER DPLL" hexmask.long.tbyte 0x00 0.--17. 1. " DPLL_MULT_FRAC ,DPLL fractional multiplier factor" group.long 0x608++0x03 line.long 0x00 "PRCM_CM_SSC_DELTAMSTEP_DPLL_PER,Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" group.long 0x60C++0x03 line.long 0x00 "PRCM_CM_SSC_MODFREQDIV_DPLL_PER,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x614++0x03 line.long 0x00 "PRCM_CM_CLKDCOLDO_DPLL_PER,This register provides controls over the CLKDCOLDO output of the DPLL" rbitfld.long 0x00 12. " DPLL_CLKDCOLDO_PWDN , Software control for PWRDN on DCOLDO O/P" "ACTIVE,PWRDN" rbitfld.long 0x00 9. " ST_DPLL_CLKDCOLDO ,DPLL CLKDCOLDO status" "Gated,Enabled" textline " " bitfld.long 0x00 8. " DPLL_CLKDCOLDO_GATE_CTRL ,Control gating of DPLL CLKDCOLDO" "Gated,Enabled" group.long 0x620++0x03 line.long 0x00 "PRCM_CM_CLKMODE_DPLL_DISP,This register allows controlling the DPLL modes" bitfld.long 0x00 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square Wave" bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "Both sides,Lower side" textline " " rbitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL" "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" textline " " rbitfld.long 0x00 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL" "Disabled,Enabled" bitfld.long 0x00 10. " DPLL_LPMODE_EN , Set the DPLL in Low Power mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " DPLL_RELOCK_RAMP_EN ,Clock ramping enable" "Disabled,Enabled" bitfld.long 0x00 8. " DPLL_DRIFTGUARD_EN ,Enable/disable the automatic recalibration feature of the DPLL" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--7. " DPLL_RAMP_RATE ,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "2,4,8,16,32,64,128,512" bitfld.long 0x00 3.--4. " DPLL_RAMP_LEVEL ,Clock frequency ramping feature when switching from bypass clock to normal clock during lock and re-lock" "No ramping,/8 /4 /2=>2/8 2/4 2/2,/4 /2 /1.5=> 2/4 2/2 2/1.5," textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control" ",,,,MN Bypass,Bypass Low,Bypass Fast,Lock" rgroup.long 0x624++0x03 line.long 0x00 "PRCM_CM_IDLEST_DPLL_DISP,This register allows monitoring the master clock activity" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "No,MN_Bypass" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "Bypass/Stop,Locked" group.long 0x62C++0x03 line.long 0x00 "PRCM_CM_CLKSEL_DPLL_DISP,This register provides controls over the DPLL" bitfld.long 0x00 23. " DPLL_BYP_CLKSEL ,Select CLKINP or CLKINPULOW as bypass clock" "CLKINP,CLKINPULOW" hexmask.long.word 0x00 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor" textline " " hexmask.long.byte 0x00 0.--6. 1. " DPLL_DIV ,DPLL divider factor" group.long 0x630++0x03 line.long 0x00 "PRCM_CM_DIV_M2_DPLL_DISP,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status" "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT" "Gated,Enabled" textline " " rbitfld.long 0x00 5. " DPLL_CLKOUT_DIVCHACK ,Divider value status" "No effect,Effect" bitfld.long 0x00 0.--4. " DPLL_CLKOUT_DIV ,DPLL M2 post-divider factor" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x648++0x03 line.long 0x00 "PRCM_CM_SSC_DELTAMSTEP_DPLL_DISP,Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" group.long 0x64C++0x03 line.long 0x00 "PRCM_CM_SSC_MODFREQDIV_DPLL_DISP,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x660++0x03 line.long 0x00 "PRCM_CM_CLKMODE_DPLL_EXTDEV,This register allows controlling the DPLL modes" bitfld.long 0x00 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square Wave" bitfld.long 0x00 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "Both sides,Lower side" textline " " rbitfld.long 0x00 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL" "Off,On" bitfld.long 0x00 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--2. " DPLL_EN ,DPLL control" ",,,,MN Bypass,Bypass Low,,Lock" rgroup.long 0x664++0x03 line.long 0x00 "PRCM_CM_IDLEST_DPLL_EXTDEV,This register allows monitoring the master clock activity" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "No,MN_Bypass" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "Bypass/Stop,Locked" group.long 0x66C++0x03 line.long 0x00 "PRCM_CM_CLKSEL_DPLL_EXTDEV,This register provides controls over the DPLL" hexmask.long.byte 0x00 24.--31. 1. " DPLL_SD_DIV ,Sigma-Delta divider select" textline " " hexmask.long.word 0x00 8.--19. 1. " DPLL_MULT ,DPLL multiplier factor" hexmask.long.byte 0x00 0.--7. 1. " DPLL_DIV ,DPLL divider factor" group.long 0x670++0x03 line.long 0x00 "PRCM_CM_DIV_M2_DPLL_EXTDEV,This register provides controls over the M2 divider of the DPLL" rbitfld.long 0x00 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status" "Gated,Enabled" bitfld.long 0x00 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT" "Gated,Enabled" textline " " rbitfld.long 0x00 7. " DPLL_CLKOUT_DIVCHACK ,Divider value status" "No effect,Effect" hexmask.long.byte 0x00 0.--6. 1. " DPLL_CLKOUT_DIV ,DPLL M2 post-divider factor" group.long 0x684++0x03 line.long 0x00 "PRCM_CLKSEL2_DPLL_EXTDEV,This register provides DPLL fractional multiplier factor control and BandWidth Control for EXTDEV DPLL" bitfld.long 0x00 18.--20. " FREQSELDCO ,Control the input 'freqseldco' for the DPLL_EXTDEV" ",,500-1000 MHz,,1000-2000 MHz,,," hexmask.long.tbyte 0x00 0.--17. 1. " DPLL_MULT_FRAC ,DPLL fractional multiplier factor" group.long 0x688++0x03 line.long 0x00 "PRCM_CM_SSC_DELTAMSTEP_DPLL_EXTDEV,Control the DeltaMStep parameter for Spread Spectrum Clocking technique DeltaMStep is split into fractional and integer part" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" rgroup.long 0x68C++0x03 line.long 0x00 "PRCM_CM_SSC_MODFREQDIV_DPLL_EXTDEV,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking technique" bitfld.long 0x00 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" group.long 0x7A0++0x03 line.long 0x00 "PRCM_CM_SHADOW_FREQ_CONFIG1,Shadow register to program new DPLL configuration affecting EMIF and GPMC" bitfld.long 0x00 11.--15. " DPLL_DDR_M2_DIV ,Shadow register for CM_DIV_M2_DPLL_DDR.DPLL_CLKOUT_DIV" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " DPLL_DDR_EN ,Shadow register for CM_CLKMODE_DPLL_DDR.DPLL_EN" ",,,,MN Bypass,Bypass Low,Bypass Fast,Lock" textline " " bitfld.long 0x00 3. " DLL_RESET ,Specify if DLL should be reset or not during the frequency change hardware sequence" "Not reset,Reset" bitfld.long 0x00 2. " DLL_OVERRIDE ,Shadow register for CM_DLL_CTRL.DLL_OVERRIDE" "Not overriden,Overriden" textline " " bitfld.long 0x00 0. " FREQ_UPDATE ,Writing '1' indicates that a new configuration is available" "No,Yes" group.long 0x7A4++0x03 line.long 0x00 "PRCM_CM_SHADOW_FREQ_CONFIG2,Shadow register to program new DPLL configuration affecting GPMC" bitfld.long 0x00 8.--10. " DPLL_CORE_EN ,Shadow register for CM_CLKMODE_DPLL_CORE.DPLL_EN" ",,,,MN Bypass,Bypass Low,Bypass Fast,Lock" bitfld.long 0x00 2.--6. " DPLL_CORE_M4_DIV ,Shadow register for CM_DIV_M4_DPLL_CORE.DIV" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0. " GPMC_FREQ_UPDATE ,Controls whether or not GPMC has to be put automatically into idle during the frequency change operation" "No,Yes" width 11. tree.end tree.end tree.end tree "CM(Control Module)" base ad:0x44E10000 width 24. rgroup.long 0x00++0x03 line.long 0x00 "CTRL_REVISION,CTRL_REVISION" bitfld.long 0x00 30.--31. " SCHEME ,Scheme value" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNCTION ,Function value" bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor version" rgroup.long 0x04++0x03 line.long 0x00 "CTRL_HWINFO,IP Module dependent" rgroup.long 0x10++0x03 line.long 0x00 "CTRL_SYSCONFIG,CTRL_SYSCONFIG" rbitfld.long 0x00 4.--5. " STANDBY ,Configure local initiator state management" "Force Standby,No Standby,Smart Standby,Smart Standby wakeup capable" bitfld.long 0x00 2.--3. " IDLEMODE , Configure local target state management" "Force Idle,No Idle,Smart Idle,Smart Idle wakeup capable" rbitfld.long 0x00 1. " FREEEMU ,Sensitivity to Emulation suspend input" "Sensitive,Not sensitive" textline " " if (((d.l(ad:0x44E10000+0x40))&0x80000000)==0x80000000) //this.CRYSTAL_FREQ_SOURCE== "YES" group.long 0x40++0x03 line.long 0x00 "CTRL_STS,CTRL_STS" rbitfld.long 0x00 31. " CRYSTAL_FREQ_SOURCE ,Use SYSBOOT15_14 and crystal_freq_selection" "No,Yes" rbitfld.long 0x00 29.--30. " CRYSTAL_FREQ_SELECTION ,CRYSTAL_FREQ_SELECTION" "19.2MHz,24MHz,25MHz,26MHz" bitfld.long 0x00 25. " SYSBOOT17 ,Used by Control Module to determine whether CLKOUT1 pin is selected" "Pinmux Mode0,CLKOUT1" textline " " bitfld.long 0x00 24. " SYSBOOT16 ,Used by boot ROM" "Not swapped,Swapped" bitfld.long 0x00 18.--19. " ADMUX ,GPMC CS0 Default Address Muxing" "No Addr/Data Muxing,Addr/Addr/Data Muxing,Addr/Data Muxing," bitfld.long 0x00 17. " WAITEN ,GPMC CS0 Default Wait Enable" "Diabled,Enabled" textline " " bitfld.long 0x00 16. " BW ,GPMC CS0 Default Bus Width" "8 bit data,16 bit data" rbitfld.long 0x00 8.--10. " DEVTYPE ,DEVTYPE" ",,,General Purpose Device,,,," hexmask.long.byte 0x00 0.--7. " SYSBOOT0 ,ROM Boot Selection" else group.long 0x40++0x03 line.long 0x00 "CTRL_STS,CTRL_STS" rbitfld.long 0x00 31. " CRYSTAL_FREQ_SOURCE ,Use SYSBOOT15_14 and crystal_freq_selection" "No,Yes" bitfld.long 0x00 25. " SYSBOOT17 ,Used by Control Module to determine whether CLKOUT1 pin is selected" "Pinmux Mode0,CLKOUT1" bitfld.long 0x00 24. " SYSBOOT16 ,Used by boot ROM" "Not swapped,Swapped" textline " " bitfld.long 0x00 22.--23. " SYSBOOT15_14 ,Used to select crystal clock frequency" "19.2MHz,24MHz,25MHz,26MHz" bitfld.long 0x00 18.--19. " ADMUX ,GPMC CS0 Default Address Muxing" "No Addr/Data Muxing,Addr/Addr/Data Muxing,Addr/Data Muxing," bitfld.long 0x00 17. " WAITEN ,GPMC CS0 Default Wait Enable" "Diabled,Enabled" textline " " bitfld.long 0x00 16. " BW ,GPMC CS0 Default Bus Width" "8 bit data,16 bit data" rbitfld.long 0x00 8.--10. " DEVTYPE ,DEVTYPE" ",,,General Purpose Device,,,," hexmask.long.byte 0x00 0.--7. 1. " SYSBOOT0 ,ROM Boot Selection" endif group.long 0x1E0++0x03 line.long 0x00 "CTRL_MPU_L2,CTRL_MPU_L2" bitfld.long 0x00 16. " PIUSEL2SRAM ,Enables MPUSS L2 Cache as SRAM" "L2 cache,L3 OCMC" group.long 0x428++0x03 line.long 0x00 "CTRL_CORE_SLDO,CTRL_CORE_SLDO" hexmask.long.word 0x00 16.--25. 1. " VSET ,Trims VDDAR" group.long 0x42C++0x03 line.long 0x00 "CTRL_MPU_SLDO,CTRL_MPU_SLDO" hexmask.long.word 0x00 16.--25. 1. " VSET ,Trims VDDAR" group.long 0x444++0x03 line.long 0x00 "CTRL_CLK32KDIVRATIO,CTRL_CLK32KDIVRATIO" bitfld.long 0x00 0. " CLKDIVOPP50_EN ,CLKDIVOPP50_EN" "OPP100,OPP50" if (((d.l(ad:0x44E10000+0x448))&0x2)==0x00) //this.ECOZ== "Valid" group.long 0x448++0x03 line.long 0x00 "CTRL_BANDGAP,CTRL_BANDGAP" hexmask.long.byte 0x00 8.--15. 1. " DTEMP ,Temperature data from ADC" bitfld.long 0x00 7. " CBIASSEL ,When set uses resister divider as reference rather than bandgap" "Not set,Set" bitfld.long 0x00 6. " BGROFF ,Turns off bandgap" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TMPSOFF ,Turn off temperature sensor" "Disabled,Enabled" bitfld.long 0x00 4. " SOC ,Transition starts new ADC conversion cycle" "Stopped,Started" bitfld.long 0x00 3. " CLRZ ,Resets the digital outputs" "Reset,Not reset" textline " " bitfld.long 0x00 2. " CONTCONV ,Conversion mode" "Single,Continuous" rbitfld.long 0x00 1. " ECOZ ,When low DTEMP is valid" "Valid,Not valid" rbitfld.long 0x00 0. " TSHUT ,Goes high during thermal shutdown event (147C)" "Low,High" else group.long 0x448++0x03 line.long 0x00 "CTRL_BANDGAP,CTRL_BANDGAP" bitfld.long 0x00 7. " CBIASSEL ,When set uses resister divider as reference rather than bandgap" "Not set,Set" bitfld.long 0x00 6. " BGROFF ,Turns off bandgap" "Disabled,Enabled" bitfld.long 0x00 5. " TMPSOFF ,Turn off temperature sensor" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SOC ,Transition starts new ADC conversion cycle" "Stopped,Started" bitfld.long 0x00 3. " CLRZ ,Resets the digital outputs" "Reset,Not reset" bitfld.long 0x00 2. " CONTCONV ,Conversion mode" "Single,Continuous" textline " " rbitfld.long 0x00 1. " ECOZ ,When low DTEMP is valid" "Valid,Not valid" rbitfld.long 0x00 0. " TSHUT ,Goes high during thermal shutdown event (147C)" "Low,High" endif group.long 0x44C++0x03 line.long 0x00 "CTRL_BANDGAP_TRIM,CTRL_BANDGAP_TRIM" hexmask.long.byte 0x00 24.--31. 1. " DTRBGAPC ,Trim the output voltage of bandgap" hexmask.long.byte 0x00 16.--23. 1. " DTRBGAPV ,Trim the output voltage of bandgap" textline " " hexmask.long.byte 0x00 8.--15. 1. " DTRTEMPS ,Trim the temperature sensor" hexmask.long.byte 0x00 0.--7. 1. " DTRTEMPSC ,Trim the temperature sensor" group.long 0x458++0x03 line.long 0x00 "CTRL_PLL_CLKINPULOW,CTRL_PLL_CLKINPULOW" bitfld.long 0x00 2. " DDR_PLL_CLKINPULOW_SEL ,DDR_PLL_CLKINPULOW_SEL" "CORE_CLKOUT_M6,PER_CLKOUT_M2" bitfld.long 0x00 1. " DISP_PLL_CLKINPULOW_SEL ,DISP_PLL_CLKINPULOW_SEL" "CORE_CLKOUT_M6,PER_CLKOUT_M2" bitfld.long 0x00 0. " MPU_DPLL_CLKINPULOW_SEL ,MPU_DPLL_CLKINPULOW_SEL" "CORE_CLKOUT_M6,PER_CLKOUT_M2" group.long 0x468++0x03 line.long 0x00 "CTRL_MOSC,CTRL_MOSC" bitfld.long 0x00 0. " RESSELECT ,Resistor connected between padxi and padxo" "Connected,Disconnected" group.long 0x470++0x03 line.long 0x00 "CTRL_DEEPSLEEP,CTRL_DEEPSLEEP" bitfld.long 0x00 18. " FORCE_DSPADCONF_EN ,Forces the DSPADCONF by overriding control from PRCM" "Not forced,Forced" bitfld.long 0x00 17. " DSEN ,Deep Sleep Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " DSCOUNT ,Programmable count of how many OSC clocks needs to be seen before exiting deep sleep mode" rgroup.long 0x50C++0x03 line.long 0x00 "CTRL_DPLL_PWR_SW_STS,CTRL_DPLL_PWR_SW_STS" bitfld.long 0x00 25. " PGOODOUT_DDR ,PGOODOUT signals from DDR DPLL" "0,1" bitfld.long 0x00 24. " PONOUT_DDR ,PONOUT signal from DDR DPLL" "0,1" bitfld.long 0x00 17. " PGOODOUT_DISP ,PGOODOUT signal from DISP DPLL" "0,1" textline " " bitfld.long 0x00 16. " PONOUT_DISP ,PONOUT signal from DISP DPLL" "0,1" bitfld.long 0x00 9. " PGOODOUT_PER ,PGOODOUT signal from PER DPLL" "0,1" bitfld.long 0x00 8. " PONOUT_PER ,PONOUT signal from PER DPLL" "0,1" textline " " bitfld.long 0x00 1. " PGOODOUT_MPU ,PGOODOUT signal from MPU DPLL" "0,1" bitfld.long 0x00 0. " PONOUT_MPU ,PONOUT signal from MPU DPLL" "0,1" group.long 0x534++0x03 line.long 0x00 "CTRL_DISPLAY_PLL_SEL,CTRL_DISPLAY_PLL_SEL" bitfld.long 0x00 0. " SELECT ,Display control" "PRCM,DISPPLL" rgroup.long 0x600++0x03 line.long 0x00 "CTRL_DEVICE_ID,CTRL_DEVICE_ID" bitfld.long 0x00 28.--31. " DEVREV ,Device revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 12.--27. 1. " PARTNUM ,Device part number (unique JTAG ID)" hexmask.long.word 0x00 1.--11. 1. " MFGR ,Manufacturer's JTAG ID" rgroup.long 0x604++0x03 line.long 0x00 "CTRL_DEV_FEATURE,CTRL_DEV_FEATURE" bitfld.long 0x00 29. " SGX ,When set indicates 3D Graphics (SGX) is Enabled" "Disabled,Enabled" bitfld.long 0x00 25. " DSS ,When set indicates DSS is Enabled" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " PRU_ICSS_FEA ,Individual bits being enabled indicate certain PRU-ICSS Features are enabled" textline " " bitfld.long 0x00 7. " DCAN ,When set indicates DCAN is enabled (DCAN0 and DCAN1)" "Disabled,Enabled" bitfld.long 0x00 1. " CPSW ,When set indicates that CPSW is enabled" "Disabled,Enabled" bitfld.long 0x00 0. " PRU_ICSS ,When set indicates PRU-ICSS module is enabled" "Disabled,Enabled" group.long 0x608++0x03 line.long 0x00 "CTRL_INIT_PRIORITY_0,CTRL_INIT_PRIORITY_0" bitfld.long 0x00 26.--27. " TCWR2 ,TPTC 2 Write Port initiator priority" "0,1,2,3" bitfld.long 0x00 24.--25. " TCRD2 ,TPTC 2 Read Port initiator priority" "0,1,2,3" bitfld.long 0x00 22.--23. " TCWR1 ,TPTC 1 Write Port initiator priority" "0,1,2,3" textline " " bitfld.long 0x00 20.--21. " TCRD1 ,TPTC 1 Read Port initiator priority" "0,1,2,3" bitfld.long 0x00 18.--19. " TCWR0 ,TPTC 0 Write Port initiator priority" "0,1,2,3" bitfld.long 0x00 16.--17. " TCRD0 ,TPTC 0 Read Port initiator priority" "0,1,2,3" textline " " bitfld.long 0x00 14.--15. " P1500 ,P1500 Port Initiator priority" "0,1,2,3" bitfld.long 0x00 4.--5. " PRU_ICSS1 ,PRU-ICSS1 initiator priority" "0,1,2,3" bitfld.long 0x00 0.--1. " HOST_ARM ,Host ARM MPU initiator priority" "0,1,2,3" group.long 0x60C++0x03 line.long 0x00 "CTRL_INIT_PRIORITY_1,CTRL_INIT_PRIORITY_1" bitfld.long 0x00 24.--25. " DBG ,Debug Subsystem initiator priority" "0,1,2,3" bitfld.long 0x00 20.--21. " SGX ,SGX initiator priority" "0,1,2,3" bitfld.long 0x00 10.--11. " VPFE1 ,VPFE1 initiator priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " VPFE0 ,VPFE0 initiator priority" "0,1,2,3" bitfld.long 0x00 2.--3. " DSS ,DSS DMA port initiator priority" "0,1,2,3" bitfld.long 0x00 0.--1. " CPSW ,CPSW initiator priority" "0,1,2,3" rgroup.long 0x610++0x03 line.long 0x00 "CTRL_DEV_ATTR,CTRL_DEV_ATTR" bitfld.long 0x00 13.--14. " PACKAGE_TYPE ,PACKAGE_TYPE" "ZDN,,," hexmask.long.word 0x00 0.--11. 1. " MPU_MAX_FREQ ,MPU_MAX_FREQ" group.long 0x614++0x03 line.long 0x00 "CTRL_TPTC_CFG,CTRL_TPTC_CFG" bitfld.long 0x00 4.--5. " TC2DBS ,TC2 Default Burst Size" "16 byte,32 byte,64 byte,128 byte" bitfld.long 0x00 2.--3. " TC1DBS ,TC1 Default Burst Size" "16 byte,32 byte,64 byte,128 byte" bitfld.long 0x00 0.--1. " TC0DBS ,TC0 Default Burst Size" "16 byte,32 byte,64 byte,128 byte" group.long 0x620++0x03 line.long 0x00 "CTRL_USB_CTRL0,CTRL_USB_CTRL0" bitfld.long 0x00 23. " DATAPOLARITY_INV ,Data Polarity Invert" "DP/DM,DM/DP" bitfld.long 0x00 21. " USB_WUEN ,USB Wakeup Enable" "Disabled,Enabled" bitfld.long 0x00 20. " OTGSESSENDEN ,Session End Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " OTGVDET_EN ,VBUS Detect Enable" "Disabled,Enabled" bitfld.long 0x00 18. " DMGPIO_PD ,Pull-down on DM in GPIO Mode" "Enabled,Disabled" bitfld.long 0x00 17. " DPGPIO_PD ,Pull-down on DP in GPIO Mode" "Enabled,Disabled" textline " " bitfld.long 0x00 14. " GPIO_SIG_CROSS ,GPIO_SIG_CROSS" "UART TX -> DM,UART RX -> DP" bitfld.long 0x00 13. " GPIO_SIG_INV ,GPIO_SIG_INV" "UART TX -> DP,UART RX -> DM" bitfld.long 0x00 12. " GPIOMODE ,GPIO Mode" "USB,GPIO" textline " " bitfld.long 0x00 10. " CDET_EXTCTL ,Bypass the charger detection state machine" "On,Bypassed" bitfld.long 0x00 9. " DPPULLUP ,Pull-up on DP line" "No effect,Enabled" bitfld.long 0x00 8. " DMPULLDN ,Pull-down on DM line" "No effect,Enabled" textline " " bitfld.long 0x00 7. " CHGVSRC_EN ,Enable VSRC on DP line (Host Charger case)" "Disabled,Enabled" bitfld.long 0x00 6. " CHGISINK_EN ,Enable ISINK on DM line (Host Charger case)" "Disabled,Enabled" bitfld.long 0x00 5. " SINKONDP ,Sink on DP" "DM,DP" textline " " bitfld.long 0x00 4. " SRCONDM ,Source on DM" "DP,DM" bitfld.long 0x00 3. " CHGDET_RSTRT ,Restart Charger Detect" "No,Restart" bitfld.long 0x00 2. " CHGDET_DIS ,Charger Detect Disable " "No,Yes" textline " " bitfld.long 0x00 1. " OTG_PWRDN ,Power down the USB OTG PHY" "Normal mode,Powered down" bitfld.long 0x00 0. " CM_PWRDN ,Power down the USB CM PHY" "Normal mode,Powered down" rgroup.long 0x624++0x03 line.long 0x00 "CTRL_USB_STS0,CTRL_USB_STS0" bitfld.long 0x00 8. " WUEVT ,Wakeup Event" "0,1" bitfld.long 0x00 5.--7. " CHGDETSTS ,Charge Detection Status" "Wait State,No Contact,PS/2,Unknown error,Dedicated charger,HOST charger,PC,Interrupt" bitfld.long 0x00 4. " CDET_DMDET ,DM Comparator Output" "0,1" textline " " bitfld.long 0x00 3. " CDET_DPDET ,DP Comparator Output" "0,1" bitfld.long 0x00 2. " CDET_DATADET ,Charger Comparator Output" "0,1" bitfld.long 0x00 1. " CHGDETECT ,Charger Detection Status" "Not detected,Detected" textline " " bitfld.long 0x00 0. " CHGDETDONE ,Charger Detection Protocol Done" "Not detected,Detected" group.long 0x628++0x03 line.long 0x00 "CTRL_USB_CTRL1,CTRL_USB_CTRL1" bitfld.long 0x00 23. " DATAPOLARITY_INV ,Data Polarity Invert" "DP/DM,DM/DP" bitfld.long 0x00 21. " USB_WUEN ,USB Wakeup Enable" "Disabled,Enabled" bitfld.long 0x00 20. " OTGSESSENDEN ,Session End Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " OTGVDET_EN ,VBUS Detect Enable" "Disabled,Enabled" bitfld.long 0x00 18. " DMGPIO_PD ,Pull-down on DM in GPIO Mode" "Enabled,Disabled" bitfld.long 0x00 17. " DPGPIO_PD ,Pull-down on DP in GPIO Mode" "Enabled,Disabled" textline " " bitfld.long 0x00 14. " GPIO_SIG_CROSS ,GPIO_SIG_CROSS" "UART TX -> DM,UART RX -> DP" bitfld.long 0x00 13. " GPIO_SIG_INV ,GPIO_SIG_INV" "UART TX -> DP,UART RX -> DM" bitfld.long 0x00 12. " GPIOMODE ,GPIO Mode" "USB,GPIO" textline " " bitfld.long 0x00 10. " CDET_EXTCTL ,Bypass the charger detection state machine" "On,Bypassed" bitfld.long 0x00 9. " DPPULLUP ,Pull-up on DP line" "No effect,Enabled" bitfld.long 0x00 8. " DMPULLDN ,Pull-down on DM line" "No effect,Enabled" textline " " bitfld.long 0x00 7. " CHGVSRC_EN ,Enable VSRC on DP line (Host Charger case)" "Disabled,Enabled" bitfld.long 0x00 6. " CHGISINK_EN ,Enable ISINK on DM line (Host Charger case)" "Disabled,Enabled" bitfld.long 0x00 5. " SINKONDP ,Sink on DP" "DM,DP" textline " " bitfld.long 0x00 4. " SRCONDM ,Source on DM" "DP,DM" bitfld.long 0x00 3. " CHGDET_RSTRT ,Restart Charger Detect" "No,Restart" bitfld.long 0x00 2. " CHGDET_DIS ,Charger Detect Disable " "No,Yes" textline " " bitfld.long 0x00 1. " OTG_PWRDN ,Power down the USB OTG PHY" "Normal mode,Powered down" bitfld.long 0x00 0. " CM_PWRDN ,Power down the USB CM PHY" "Normal mode,Powered down" rgroup.long 0x62C++0x03 line.long 0x00 "CTRL_USB_STS1,CTRL_USB_STS1" bitfld.long 0x00 8. " WUEVT ,Wakeup Event" "0,1" bitfld.long 0x00 5.--7. " CHGDETSTS ,Charge Detection Status" "Wait State,No Contact,PS/2,Unknown error,Dedicated charger,HOST charger,PC,Interrupt" bitfld.long 0x00 4. " CDET_DMDET ,DM Comparator Output" "0,1" textline " " bitfld.long 0x00 3. " CDET_DPDET ,DP Comparator Output" "0,1" bitfld.long 0x00 2. " CDET_DATADET ,Charger Comparator Output" "0,1" bitfld.long 0x00 1. " CHGDETECT ,Charger Detection Status" "Not detected,Detected" textline " " bitfld.long 0x00 0. " CHGDETDONE ,Charger Detection Protocol Done" "Not detected,Detected" rgroup.long 0x630++0x03 line.long 0x00 "CTRL_MAC_ID0_LO,CTRL_MAC_ID0_LO" hexmask.long.byte 0x00 8.--15. 1. " MACADDR_7_0 ,MAC0 Address - Byte 0" hexmask.long.byte 0x00 0.--7. 1. " MACADDR_15_8 ,MAC0 Address - Byte 1" rgroup.long 0x634++0x03 line.long 0x00 "CTRL_MAC_ID0_HI,CTRL_MAC_ID0_HI" hexmask.long.byte 0x00 24.--31. 1. " MACADDR_23_16 ,MAC0 Address - Byte 2" hexmask.long.byte 0x00 16.--23. 1. " MACADDR_31_24 ,MAC0 Address - Byte 3" textline " " hexmask.long.byte 0x00 8.--15. 1. " MACADDR_39_32 ,MAC0 Address - Byte 4" hexmask.long.byte 0x00 0.--7. 1. " MACADDR_47_40 ,MAC0 Address - Byte 5" rgroup.long 0x638++0x03 line.long 0x00 "CTRL_MAC_ID1_LO,CTRL_MAC_ID1_LO" hexmask.long.byte 0x00 8.--15. 1. " MACADDR_7_0 ,MAC1 Address - Byte 0" hexmask.long.byte 0x00 0.--7. 1. " MACADDR_15_8 ,MAC1 Address - Byte 1" rgroup.long 0x63C++0x03 line.long 0x00 "CTRL_MAC_ID1_HI,CTRL_MAC_ID1_HI" hexmask.long.byte 0x00 24.--31. 1. " MACADDR_23_16 ,MAC1 Address - Byte 2" hexmask.long.byte 0x00 16.--23. 1. " MACADDR_31_24 ,MAC1 Address - Byte 3" textline " " hexmask.long.byte 0x00 8.--15. 1. " MACADDR_39_32 ,MAC1 Address - Byte 4" hexmask.long.byte 0x00 0.--7. 1. " MACADDR_47_40 ,MAC1 Address - Byte 5" group.long 0x644++0x03 line.long 0x00 "CTRL_DCAN_RAMINIT,CTRL_DCAN_RAMINIT" eventfld.long 0x00 9. " DCAN1_RAMINIT_DONE ,DCAN0_RAMINIT_DONE" "Not completed,Completed" eventfld.long 0x00 8. " DCAN0_RAMINIT_DONE ,DCAN0_RAMINIT_DONE" "Not completed,Completed" textline " " bitfld.long 0x00 1. " DCAN1_RAMINIT_START ,Start DCAN1 RAM initialization sequence" "Stopped,Started" bitfld.long 0x00 0. " DCAN0_RAMINIT_START ,Start DCAN0 RAM initialization sequence" "Stopped,Started" group.long 0x64C++0x03 line.long 0x00 "CTRL_USB_CTRL2,CTRL_USB_CTRL2" bitfld.long 0x00 25.--26. " PHY1_FILTER_THR_VBUSVALID ,PHY1_FILTER_THR_VBUSVALID" "1us,100us,5ms,500ms" bitfld.long 0x00 23.--24. " PHY1_FILTER_THR_AVALID ,PHY1_FILTER_THR_AVALID" "1us,100us,5ms,500ms" bitfld.long 0x00 21.--22. " PHY1_FILTER_THR_BVALID ,PHY1_FILTER_THR_BVALID" "1us,100us,5ms,500ms" textline " " bitfld.long 0x00 19.--20. " PHY1_FILTER_THR_SESSEND ,PHY1_FILTER_THR_SESSEND" "1us,100us,5ms,500ms" bitfld.long 0x00 17.--18. " PHY1_FILTER_THR_IDDIG ,PHY1_FILTER_THR_IDDIG" "1us,100us,5ms,500ms" bitfld.long 0x00 16. " PHY1_FILTER_BYPASS ,PHY1_FILTER_BYPASS" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 9.--10. " PHY0_FILTER_THR_VBUSVALID ,PHY0_FILTER_THR_VBUSVALID" "1us,100us,5ms,500ms" bitfld.long 0x00 7.--8. " PHY0_FILTER_THR_AVALID ,PHY0_FILTER_THR_AVALID" "1us,100us,5ms,500ms" bitfld.long 0x00 5.--6. " PHY0_FILTER_THR_BVALID ,PHY0_FILTER_THR_BVALID" "1us,100us,5ms,500ms" textline " " bitfld.long 0x00 3.--4. " PHY0_FILTER_THR_SESSEND ,PHY0_FILTER_THR_SESSEND" "1us,100us,5ms,500ms" bitfld.long 0x00 1.--2. " PHY0_FILTER_THR_IDDIG ,PHY0_FILTER_THR_IDDIG" "1us,100us,5ms,500ms" bitfld.long 0x00 0. " PHY0_FILTER_BYPASS ,PHY0_FILTER_BYPASS" "Not bypassed,Bypassed" group.long 0x650++0x03 line.long 0x00 "CTRL_GMII_SEL,CTRL_GMII_SEL" bitfld.long 0x00 7. " RMII2_IO_CLK_EN ,RMII2_IO_CLK_EN" "PLL,Chip pin" bitfld.long 0x00 6. " RMII1_IO_CLK_EN ,RMII1_IO_CLK_EN" "PLL,Chip pin" bitfld.long 0x00 5. " RGMII2_IDMODE ,RGMII2 Internal Delay Mode" "Delay,No Delay" textline " " bitfld.long 0x00 4. " RGMII1_IDMODE ,RGMII1 Internal Delay Mode" "Delay,No Delay" bitfld.long 0x00 2.--3. " GMII2_SEL ,GMII2_SEL" "GMII/MII,RMII,RGMII," bitfld.long 0x00 0.--1. " GMII1_SEL ,GMII1_SEL" "GMII/MII,RMII,RGMII," group.long 0x654++0x03 line.long 0x00 "CTRL_MPUSS,CTRL_MPUSS" bitfld.long 0x00 7.--10. " HSDCC_DATA ,HSDCC_DATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--6. " HSDCC_ADDR ,HSDCC_ADDR" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3. " HSDCC_CLK ,HSDCC_CLK" "0,1" bitfld.long 0x00 1.--2. " PIL2SRAMCLKDIV ,PIL2SRAMCLKDIV" "MPU_CLK/2,MPU_CLK/3,MPU_CLK/4,MPU_CLK/6" group.long 0x658++0x03 line.long 0x00 "CTRL_TIMER_CASCADE,CTRL_TIMER_CASCADE" bitfld.long 0x00 1. " TIMER45CASCADE_EN ,Enables cascading of timer4 & timer5" "Disabled,Enabled" bitfld.long 0x00 0. " TIMER23CASCADE_EN ,Enables cascading of timer2 & timer3" "Disabled,Enabled" group.long 0x664++0x03 line.long 0x00 "CTRL_PWMSS,CTRL_PWMSS" bitfld.long 0x00 6. " PWMSS5_TBCLKEN ,Timebase clock enable for PWMSS5" "Disabled,Enabled" bitfld.long 0x00 5. " PWMSS4_TBCLKEN ,Timebase clock enable for PWMSS4" "Disabled,Enabled" bitfld.long 0x00 4. " PWMSS3_TBCLKEN ,Timebase clock enable for PWMSS3" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PWM_SYNCSEL ,PWM 3 sync select" "PWM2,PIN" bitfld.long 0x00 2. " PWMSS2_TBCLKEN ,Timebase clock enable for PWMSS2" "Disabled,Enabled" bitfld.long 0x00 1. " PWMSS1_TBCLKEN ,Timebase clock enable for PWMSS1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PWMSS0_TBCLKEN ,Timebase clock enable for PWMSS0" "Disabled,Enabled" group.long 0x670++0x03 line.long 0x00 "CTRL_MREQPRIO_0,CTRL_MREQPRIO_0" bitfld.long 0x00 28.--30. " SGX ,MReqPriority for SGX Initiator OCP Interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " CPSW ,MReqPriority for CPSW Initiator OCP Interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " PRU_ICSS1_PRU1 ,MReqPriority for PRU-ICSS1 PRU1Initiator OCP Interface" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--10. " PRU_ICSS1_PRU0 ,MReqPriority for PRU-ICSS1 PRU0 Initiator OCP Interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " SAB_INIT1 ,MReqPriority for MPUSS Initiator 1 OCP Interface" "0,1,2,3,4,5,6,7" group.long 0x674++0x03 line.long 0x00 "CTRL_MREQPRIO_1,CTRL_MREQPRIO_1" bitfld.long 0x00 12.--14. " VPFE1 ,MReqPriority for VPFE1 OCP Interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " VPFE0 ,MReqPriority for VPFE0 OCP Interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " DSS ,MReqPriority for DSS OCP Interface" "0,1,2,3,4,5,6,7" group.long 0x690++0x03 line.long 0x00 "CTRL_HW_EVT_SEL_GRP1,CTRL_HW_EVT_SEL_GRP1" hexmask.long.byte 0x00 24.--31. 1. " EVT4 ,Select 4th trace event from group 1" hexmask.long.byte 0x00 16.--23. 1. " EVT3 ,Select 3rd trace event from group 1" textline " " hexmask.long.byte 0x00 8.--15. 1. " EVT2 ,Select 2nd trace event from group 1" hexmask.long.byte 0x00 0.--7. 1. " EVT1 ,Select 1st trace event from group 1" group.long 0x694++0x03 line.long 0x00 "CTRL_HW_EVT_SEL_GRP2,CTRL_HW_EVT_SEL_GRP2" hexmask.long.byte 0x00 24.--31. 1. " EVT8 ,Select 8th trace event from group 2" hexmask.long.byte 0x00 16.--23. 1. " EVT7 ,Select 7th trace event from group 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " EVT6 ,Select 6th trace event from group 2" hexmask.long.byte 0x00 0.--7. 1. " EVT5 ,Select 5th trace event from group 2" group.long 0x698++0x03 line.long 0x00 "CTRL_HW_EVT_SEL_GRP3,CTRL_HW_EVT_SEL_GRP3" hexmask.long.byte 0x00 24.--31. 1. " EVT12 ,Select 12th trace event from group 3" hexmask.long.byte 0x00 16.--23. 1. " EVT11 ,Select 11th trace event from group 3" textline " " hexmask.long.byte 0x00 8.--15. 1. " EVT10 ,Select 10th trace event from group 3" hexmask.long.byte 0x00 0.--7. 1. " EVT9 ,Select 9th trace event from group 3" group.long 0x69C++0x03 line.long 0x00 "CTRL_HW_EVT_SEL_GRP4,CTRL_HW_EVT_SEL_GRP4" hexmask.long.byte 0x00 24.--31. 1. " EVT16 ,Select 16th trace event from group 4" hexmask.long.byte 0x00 16.--23. 1. " EVT15 ,Select 15th trace event from group 4" textline " " hexmask.long.byte 0x00 8.--15. 1. " EVT14 ,Select 14th trace event from group 4" hexmask.long.byte 0x00 0.--7. 1. " EVT13 ,Select 13th trace event from group 4" group.long 0x6A0++0x03 line.long 0x00 "CTRL_SMRT,CTRL_SMRT" bitfld.long 0x00 0. " SR1_SLEEP ,SR1_SLEEP" "Disabled,Enabled" bitfld.long 0x00 0. " SR0_SLEEP ,SR0_SLEEP" "Disabled,Enabled" group.long 0x6A4++0x03 line.long 0x00 "CTRL_MPUSS_HW_DBG_SEL,CTRL_MPUSS_HW_DBG_SEL" bitfld.long 0x00 9. " HW_DBG_GATE_EN ,Save powet input" "Gated,Not gated" bitfld.long 0x00 0.--3. " HW_DBG_SEL ,Selects which Group of signals are sent out to the MODENA_HW_DBG_INFO register" "Group 0,Group 1,Group 2,Group 3,Group 4,Group 5,Group 6,Group 7,,,,,,,," rgroup.long 0x6A8++0x03 line.long 0x00 "CTRL_MPUSS_HW_DBG_INFO,Hardware Debug Info from MPUSS" rgroup.long 0x770++0x03 line.long 0x00 "CTRL_VDD_MPU_OPP_050,CTRL_VDD_MPU_OPP_050" hexmask.long.tbyte 0x00 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domain OPP50" rgroup.long 0x774++0x03 line.long 0x00 "CTRL_VDD_MPU_OPP_100,CTRL_VDD_MPU_OPP_100" hexmask.long.tbyte 0x00 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domain OPP100" rgroup.long 0x778++0x03 line.long 0x00 "CTRL_VDD_MPU_OPP_120,CTRL_VDD_MPU_OPP_120" hexmask.long.tbyte 0x00 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domain OPP120" rgroup.long 0x77C++0x03 line.long 0x00 "CTRL_VDD_MPU_OPP_TURBO,CTRL_VDD_MPU_OPP_TURBO" hexmask.long.tbyte 0x00 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domain OPPTURBO" rgroup.long 0x780++0x03 line.long 0x00 "CTRL_VDD_MPU_OPP_NITRO,CTRL_VDD_MPU_OPP_NITRO" hexmask.long.tbyte 0x00 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domain OPPNITRO" rgroup.long 0x7B8++0x03 line.long 0x00 "CTRL_VDD_CORE_OPP_050,CTRL_VDD_CORE_OPP_050" hexmask.long.tbyte 0x00 0.--23. 1. " NTARGET ,Ntarget value for CORE Voltage domain OPP50" rgroup.long 0x7BC++0x03 line.long 0x00 "CTRL_VDD_CORE_OPP_100,CTRL_VDD_CORE_OPP_100" hexmask.long.tbyte 0x00 0.--23. 1. " NTARGET ,Ntarget value for CORE Voltage domain OPP100" rgroup.long 0x7D0++0x03 line.long 0x00 "CTRL_BB_SCALE,CTRL_BB_SCALE" bitfld.long 0x00 8.--11. " SCALE ,Dynamic Core Voltage Scaling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " BBIAS ,BBIAS value from Efuse" "0,1,2,3" rgroup.long 0x7F4++0x03 line.long 0x00 "CTRL_USB_VID_PID,CTRL_USB_VID_PID" hexmask.long.word 0x00 16.--31. 1. " USB_VID ,USB Vendor ID" hexmask.long.word 0x00 0.--15. 1. " USB_PID ,USB Product ID" tree "CTRL_CONF_GPMC_AD 0.--15. " width 21. group.long 0x800++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD0,CTRL_CONF_GPMC_AD0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x804++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD1,CTRL_CONF_GPMC_AD1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x808++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD2,CTRL_CONF_GPMC_AD2" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80C++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD3,CTRL_CONF_GPMC_AD3" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x810++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD4,CTRL_CONF_GPMC_AD4" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x814++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD5,CTRL_CONF_GPMC_AD5" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x818++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD6,CTRL_CONF_GPMC_AD6" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x81C++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD7,CTRL_CONF_GPMC_AD7" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x820++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD8,CTRL_CONF_GPMC_AD8" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x824++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD9,CTRL_CONF_GPMC_AD9" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x828++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD10,CTRL_CONF_GPMC_AD10" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x82C++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD11,CTRL_CONF_GPMC_AD11" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x830++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD12,CTRL_CONF_GPMC_AD12" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x834++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD13,CTRL_CONF_GPMC_AD13" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x838++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD14,CTRL_CONF_GPMC_AD14" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x83C++0x03 line.long 0x00 "CTRL_CONF_GPMC_AD15,CTRL_CONF_GPMC_AD15" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "CTRL_CONF_GPMC_A 0.--11. " width 20. group.long 0x840++0x03 line.long 0x00 "CTRL_CONF_GPMC_A0,CTRL_CONF_GPMC_A0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x844++0x03 line.long 0x00 "CTRL_CONF_GPMC_A1,CTRL_CONF_GPMC_A1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x848++0x03 line.long 0x00 "CTRL_CONF_GPMC_A2,CTRL_CONF_GPMC_A2" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x84C++0x03 line.long 0x00 "CTRL_CONF_GPMC_A3,CTRL_CONF_GPMC_A3" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x850++0x03 line.long 0x00 "CTRL_CONF_GPMC_A4,CTRL_CONF_GPMC_A4" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x854++0x03 line.long 0x00 "CTRL_CONF_GPMC_A5,CTRL_CONF_GPMC_A5" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x858++0x03 line.long 0x00 "CTRL_CONF_GPMC_A6,CTRL_CONF_GPMC_A6" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x85C++0x03 line.long 0x00 "CTRL_CONF_GPMC_A7,CTRL_CONF_GPMC_A7" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x860++0x03 line.long 0x00 "CTRL_CONF_GPMC_A8,CTRL_CONF_GPMC_A8" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x864++0x03 line.long 0x00 "CTRL_CONF_GPMC_A9,CTRL_CONF_GPMC_A9" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x868++0x03 line.long 0x00 "CTRL_CONF_GPMC_A10,CTRL_CONF_GPMC_A10" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x86C++0x03 line.long 0x00 "CTRL_CONF_GPMC_A11,CTRL_CONF_GPMC_A11" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-Down,Pull-Up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,DIsabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end width 25. group.long 0x870++0x03 line.long 0x00 "CTRL_CONF_GPMC_WAIT0,CTRL_CONF_GPMC_WAIT0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x874++0x03 line.long 0x00 "CTRL_CONF_GPMC_WPN,CTRL_CONF_GPMC_WPN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x878++0x03 line.long 0x00 "CTRL_CONF_GPMC_BE1N,CTRL_CONF_GPMC_BE1N" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x87C++0x03 line.long 0x00 "CTRL_CONF_GPMC_CSN0,CTRL_CONF_GPMC_CSN0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x880++0x03 line.long 0x00 "CTRL_CONF_GPMC_CSN1,CTRL_CONF_GPMC_CSN1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x884++0x03 line.long 0x00 "CTRL_CONF_GPMC_CSN2,CTRL_CONF_GPMC_CSN2" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x888++0x03 line.long 0x00 "CTRL_CONF_GPMC_CSN3,CTRL_CONF_GPMC_CSN3" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x88C++0x03 line.long 0x00 "CTRL_CONF_GPMC_CLK,CTRL_CONF_GPMC_CLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x890++0x03 line.long 0x00 "CTRL_CONF_GPMC_ADVN_ALE,CTRL_CONF_GPMC_ADVN_ALE" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x894++0x03 line.long 0x00 "CTRL_CONF_GPMC_OEN_REN,CTRL_CONF_GPMC_OEN_REN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x898++0x03 line.long 0x00 "CTRL_CONF_GPMC_WEN,CTRL_CONF_GPMC_WEN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x89C++0x03 line.long 0x00 "CTRL_CONF_GPMC_BE0N_CLE,CTRL_CONF_GPMC_BE0N_CLE" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree "CTRL_CONF_DSS_DATA 0.--11. " width 22. group.long 0x8A0++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA0,CTRL_CONF_DSS_DATA0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8A4++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA1,CTRL_CONF_DSS_DATA1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8A8++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA2,CTRL_CONF_DSS_DATA2" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8AC++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA3,CTRL_CONF_DSS_DATA3" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8B0++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA4,CTRL_CONF_DSS_DATA4" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8B4++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA5,CTRL_CONF_DSS_DATA5" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8B8++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA6,CTRL_CONF_DSS_DATA6" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8BC++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA7,CTRL_CONF_DSS_DATA7" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8C0++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA8,CTRL_CONF_DSS_DATA8" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8C4++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA9,CTRL_CONF_DSS_DATA9" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8C8++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA10,CTRL_CONF_DSS_DATA10" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8CC++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA11,CTRL_CONF_DSS_DATA11" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8D0++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA12,CTRL_CONF_DSS_DATA12" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8D4++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA13,CTRL_CONF_DSS_DATA13" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8D8++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA14,CTRL_CONF_DSS_DATA14" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8DC++0x03 line.long 0x00 "CTRL_CONF_DSS_DATA15,CTRL_CONF_DSS_DATA15" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end width 29. group.long 0x8E0++0x03 line.long 0x00 "CTRL_CONF_DSS_VSYNC,CTRL_CONF_DSS_VSYNC" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8E4++0x03 line.long 0x00 "CTRL_CONF_DSS_HSYNC,CTRL_CONF_DSS_HSYNC" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8E8++0x03 line.long 0x00 "CTRL_CONF_DSS_PCLK,CTRL_CONF_DSS_PCLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8EC++0x03 line.long 0x00 "CTRL_CONF_DSS_AC_BIAS_EN,CTRL_CONF_DSS_AC_BIAS_EN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8F0++0x03 line.long 0x00 "CTRL_CONF_MMC0_DAT3,CTRL_CONF_MMC0_DAT3" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8F4++0x03 line.long 0x00 "CTRL_CONF_MMC0_DAT2,CTRL_CONF_MMC0_DAT2" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8F8++0x03 line.long 0x00 "CTRL_CONF_MMC0_DAT1,CTRL_CONF_MMC0_DAT1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8FC++0x03 line.long 0x00 "CTRL_CONF_MMC0_DAT0,CTRL_CONF_MMC0_DAT0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x900++0x03 line.long 0x00 "CTRL_CONF_MMC0_CLK,CTRL_CONF_MMC0_CLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x904++0x03 line.long 0x00 "CTRL_CONF_MMC0_CMD,CTRL_CONF_MMC0_CMD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x908++0x03 line.long 0x00 "CTRL_CONF_MII1_COL,CTRL_CONF_MII1_COL" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x90C++0x03 line.long 0x00 "CTRL_CONF_MII1_CRS,CTRL_CONF_MII1_CRS" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x910++0x03 line.long 0x00 "CTRL_CONF_MII1_RXERR,CTRL_CONF_MII1_RXERR" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x914++0x03 line.long 0x00 "CTRL_CONF_MII1_TXEN,CTRL_CONF_MII1_TXEN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x918++0x03 line.long 0x00 "CTRL_CONF_MII1_RXDV,CTRL_CONF_MII1_RXDV" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x91C++0x03 line.long 0x00 "CTRL_CONF_MII1_TXD3,CTRL_CONF_MII1_TXD3" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x920++0x03 line.long 0x00 "CTRL_CONF_MII1_TXD2,CTRL_CONF_MII1_TXD2" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x924++0x03 line.long 0x00 "CTRL_CONF_MII1_TXD1,CTRL_CONF_MII1_TXD1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x928++0x03 line.long 0x00 "CTRL_CONF_MII1_TXD0,CTRL_CONF_MII1_TXD0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x92C++0x03 line.long 0x00 "CTRL_CONF_MII1_TXCLK,CTRL_CONF_MII1_TXCLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x930++0x03 line.long 0x00 "CTRL_CONF_MII1_RXCLK,CTRL_CONF_MII1_RXCLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x934++0x03 line.long 0x00 "CTRL_CONF_MII1_RXD3,CTRL_CONF_MII1_RXD3" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x938++0x03 line.long 0x00 "CTRL_CONF_MII1_RXD2,CTRL_CONF_MII1_RXD2" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x93C++0x03 line.long 0x00 "CTRL_CONF_MII1_RXD1,CTRL_CONF_MII1_RXD1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x940++0x03 line.long 0x00 "CTRL_CONF_MII1_RXD0,CTRL_CONF_MII1_RXD0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x944++0x03 line.long 0x00 "CTRL_CONF_RMII1_REFCLK,CTRL_CONF_RMII1_REFCLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x948++0x03 line.long 0x00 "CTRL_CONF_MDIO_DATA,CTRL_CONF_MDIO_DATA" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x94C++0x03 line.long 0x00 "CTRL_CONF_MDIO_CLK,CTRL_CONF_MDIO_CLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x950++0x03 line.long 0x00 "CTRL_CONF_SPI0_SCLK,CTRL_CONF_SPI0_SCLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x954++0x03 line.long 0x00 "CTRL_CONF_SPI0_D0,CTRL_CONF_SPI0_D0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x958++0x03 line.long 0x00 "CTRL_CONF_SPI0_D1,CTRL_CONF_SPI0_D1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x95C++0x03 line.long 0x00 "CTRL_CONF_SPI0_CS0,CTRL_CONF_SPI0_CS0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x960++0x03 line.long 0x00 "CTRL_CONF_SPI0_CS1,CTRL_CONF_SPI0_CS1" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x964++0x03 line.long 0x00 "CTRL_CONF_ECAP0_IN_PWM0_OUT,CTRL_CONF_ECAP0_IN_PWM0_OUT" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x968++0x03 line.long 0x00 "CTRL_CONF_UART0_CTSN,CTRL_CONF_UART0_CTSN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x96C++0x03 line.long 0x00 "CTRL_CONF_UART0_RTSN,CTRL_CONF_UART0_RTSN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x970++0x03 line.long 0x00 "CTRL_CONF_UART0_RXD,CTRL_CONF_UART0_RXD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x974++0x03 line.long 0x00 "CTRL_CONF_UART0_TXD,CTRL_CONF_UART0_TXD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x978++0x03 line.long 0x00 "CTRL_CONF_UART1_CTSN,CTRL_CONF_UART1_CTSN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x97C++0x03 line.long 0x00 "CTRL_CONF_UART1_RTSN,CTRL_CONF_UART1_RTSN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x980++0x03 line.long 0x00 "CTRL_CONF_UART1_RXD,CTRL_CONF_UART1_RXD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x984++0x03 line.long 0x00 "CTRL_CONF_UART1_TXD,CTRL_CONF_UART1_TXD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x988++0x03 line.long 0x00 "CTRL_CONF_I2C0_SDA,CTRL_CONF_I2C0_SDA" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x98C++0x03 line.long 0x00 "CTRL_CONF_I2C0_SCL,CTRL_CONF_I2C0_SCL" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x990++0x03 line.long 0x00 "CTRL_CONF_MCASP0_ACLKX,CTRL_CONF_MCASP0_ACLKX" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x994++0x03 line.long 0x00 "CTRL_CONF_MCASP0_FSX,CTRL_CONF_MCASP0_FSX" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x998++0x03 line.long 0x00 "CTRL_CONF_MCASP0_AXR0,CTRL_CONF_MCASP0_AXR0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x99C++0x03 line.long 0x00 "CTRL_CONF_MCASP0_AHCLKR,CTRL_CONF_MCASP0_AHCLKR" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9A0++0x03 line.long 0x00 "CTRL_CONF_MCASP0_ACLKR,CTRL_CONF_MCASP0_ACLKR" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9A4++0x03 line.long 0x00 "CTRL_CONF_MCASP0_FSR,CTRL_CONF_MCASP0_FSR" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9A8++0x03 line.long 0x00 "CTRL_CONF_MCASP0_AXR1,CTRL_CONF_MCASP0_AXR1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9AC++0x03 line.long 0x00 "CTRL_CONF_MCASP0_AHCLKX,CTRL_CONF_MCASP0_AHCLKX" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9B0++0x03 line.long 0x00 "CTRL_CONF_CAM0_HD,CTRL_CONF_CAM0_HD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9B4++0x03 line.long 0x00 "CTRL_CONF_CAM0_VD,CTRL_CONF_CAM0_VD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9B8++0x03 line.long 0x00 "CTRL_CONF_CAM0_FIELD,CTRL_CONF_CAM0_FIELD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9BC++0x03 line.long 0x00 "CTRL_CONF_CAM0_WEN,CTRL_CONF_CAM0_WEN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9C0++0x03 line.long 0x00 "CTRL_CONF_CAM0_PCLK,CTRL_CONF_CAM0_PCLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9C4++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA8,CTRL_CONF_CAM0_DATA8" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9C8++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA9,CTRL_CONF_CAM0_DATA9" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9CC++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA9,CTRL_CONF_CAM1_DATA9" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9D0++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA8,CTRL_CONF_CAM1_DATA8" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9D4++0x03 line.long 0x00 "CTRL_CONF_CAM1_HD,CTRL_CONF_CAM1_HD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9D8++0x03 line.long 0x00 "CTRL_CONF_CAM1_VD,CTRL_CONF_CAM1_VD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9DC++0x03 line.long 0x00 "CTRL_CONF_CAM1_PCLK,CTRL_CONF_CAM1_PCLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9E0++0x03 line.long 0x00 "CTRL_CONF_CAM1_FIELD,CTRL_CONF_CAM1_FIELD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9E4++0x03 line.long 0x00 "CTRL_CONF_CAM1_WEN,CTRL_CONF_CAM1_WEN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9E8++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA0,CTRL_CONF_CAM1_DATA0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9EC++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA1,CTRL_CONF_CAM1_DATA1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9F0++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA2,CTRL_CONF_CAM1_DATA2" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9F4++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA3,CTRL_CONF_CAM1_DATA3" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9F8++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA4,CTRL_CONF_CAM1_DATA4" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9FC++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA5,CTRL_CONF_CAM1_DATA5" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA00++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA6,CTRL_CONF_CAM1_DATA6" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA04++0x03 line.long 0x00 "CTRL_CONF_CAM1_DATA7,CTRL_CONF_CAM1_DATA7" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA08++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA00,CTRL_CONF_CAM0_DATA00" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0C++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA01,CTRL_CONF_CAM0_DATA01" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA10++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA02,CTRL_CONF_CAM0_DATA02" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA14++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA03,CTRL_CONF_CAM0_DATA03" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA18++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA04,CTRL_CONF_CAM0_DATA04" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA1C++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA05,CTRL_CONF_CAM0_DATA05" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA20++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA06,CTRL_CONF_CAM0_DATA06" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA24++0x03 line.long 0x00 "CTRL_CONF_CAM0_DATA07,CTRL_CONF_CAM0_DATA07" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA28++0x03 line.long 0x00 "CTRL_CONF_UART3_RXD,CTRL_CONF_UART3_RXD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA2C++0x03 line.long 0x00 "CTRL_CONF_UART3_TXD,CTRL_CONF_UART3_TXD" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA30++0x03 line.long 0x00 "CTRL_CONF_UART3_CTSN,CTRL_CONF_UART3_CTSN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA34++0x03 line.long 0x00 "CTRL_CONF_UART3_RTSN,CTRL_CONF_UART3_RTSN" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA38++0x03 line.long 0x00 "CTRL_CONF_GPIO5_8,CTRL_CONF_GPIO5_8" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA3C++0x03 line.long 0x00 "CTRL_CONF_GPIO5_9,CTRL_CONF_GPIO5_9" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA40++0x03 line.long 0x00 "CTRL_CONF_GPIO5_10,CTRL_CONF_GPIO5_10" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA44++0x03 line.long 0x00 "CTRL_CONF_GPIO5_11,CTRL_CONF_GPIO5_11" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA48++0x03 line.long 0x00 "CTRL_CONF_GPIO5_12,CTRL_CONF_GPIO5_12" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA4C++0x03 line.long 0x00 "CTRL_CONF_GPIO5_13,CTRL_CONF_GPIO5_13" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA50++0x03 line.long 0x00 "CTRL_CONF_SPI4_SCLK,CTRL_CONF_SPI4_SCLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA54++0x03 line.long 0x00 "CTRL_CONF_SPI4_D0,CTRL_CONF_SPI4_D0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA58++0x03 line.long 0x00 "CTRL_CONF_SPI4_D1,CTRL_CONF_SPI4_D1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA5C++0x03 line.long 0x00 "CTRL_CONF_SPI4_CS0,CTRL_CONF_SPI4_CS0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA60++0x03 line.long 0x00 "CTRL_CONF_SPI2_SCLK,CTRL_CONF_SPI2_SCLK" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA64++0x03 line.long 0x00 "CTRL_CONF_SPI2_D0,CTRL_CONF_SPI2_D0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA68++0x03 line.long 0x00 "CTRL_CONF_SPI2_D1,CTRL_CONF_SPI2_D1" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA6C++0x03 line.long 0x00 "CTRL_CONF_SPI2_CS0,CTRL_CONF_SPI2_CS0" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA70++0x03 line.long 0x00 "CTRL_CONF_XDMA_EVT_INTR0,CTRL_CONF_XDMA_EVT_INTR0" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA74++0x03 line.long 0x00 "CTRL_CONF_XDMA_EVT_INTR1,CTRL_CONF_XDMA_EVT_INTR1" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA78++0x03 line.long 0x00 "CTRL_CONF_CLKREQ,CTRL_CONF_CLKREQ" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA7C++0x03 line.long 0x00 "CTRL_CONF_NRESETIN_OUT,CTRL_CONF_NRESETIN_OUT" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA84++0x03 line.long 0x00 "CTRL_CONF_NNMI,CTRL_CONF_NNMI" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA90++0x03 line.long 0x00 "CTRL_CONF_TMS,CTRL_CONF_TMS" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA94++0x03 line.long 0x00 "CTRL_CONF_TDI,CTRL_CONF_TDI" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA98++0x03 line.long 0x00 "CTRL_CONF_TDO,CTRL_CONF_TDO" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA9C++0x03 line.long 0x00 "CTRL_CONF_TCK,CTRL_CONF_TCK" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAA0++0x03 line.long 0x00 "CTRL_CONF_NTRST,CTRL_CONF_NTRST" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAA4++0x03 line.long 0x00 "CTRL_CONF_EMU0,CTRL_CONF_EMU0" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAA8++0x03 line.long 0x00 "CTRL_CONF_EMU1,CTRL_CONF_EMU1" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAAC++0x03 line.long 0x00 "CTRL_CONF_OSC1_IN,CTRL_CONF_OSC1_IN" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAB0++0x03 line.long 0x00 "CTRL_CONF_OSC1_OUT,CTRL_CONF_OSC1_OUT" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAB4++0x03 line.long 0x00 "CTRL_CONF_RTC_PORZ,CTRL_CONF_RTC_PORZ" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAB8++0x03 line.long 0x00 "CTRL_CONF_EXT_WAKEUP0,CTRL_CONF_EXT_WAKEUP0" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xABC++0x03 line.long 0x00 "CTRL_CONF_PMIC_POWER_EN0,CTRL_CONF_PMIC_POWER_EN0" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAC0++0x03 line.long 0x00 "CTRL_CONF_USB0_DRVVBUS,CTRL_CONF_USB0_DRVVBUS" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAC4++0x03 line.long 0x00 "CTRL_CONF_USB1_DRVVBUS,CTRL_CONF_USB1_DRVVBUS" rbitfld.long 0x00 30. " WUEVT ,Wakeup Event" "Not occurred,Occurred" bitfld.long 0x00 29. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.long 0x00 28. " DSPULLTYPESELECT ,DS0 mode Pull-Up/Down selection" "Pull-down,Pull-up" textline " " bitfld.long 0x00 27. " DSPULLUDEN ,DS0 mode Pull-Up/Down enable" "Enabled,Disabled" bitfld.long 0x00 26. " DS0OUTVALUE ,DS0 mode output value" "0,1" bitfld.long 0x00 25. " DS0OUTEN ,DS0 mode output enable" "Enabled,Disabled" textline " " bitfld.long 0x00 24. " DS0EN ,DS0 mode override control" "Keeps previous state,State is forced" bitfld.long 0x00 19. " SLEWCTRL ,Select between Faster or Slower Slew rate" "Fast,Slow" bitfld.long 0x00 18. " RXACTIVE ,Input Enable Value for the PAD" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " PUTYPESEL ,Pad Pullup / Pulldown Type Selection" "Pulldown,Pullup" bitfld.long 0x00 16. " PUDEN ,Pad Pullup / Pulldown Enable" "Enabled,Disabled" bitfld.long 0x00 0.--3. " MMODE ,Pad Functional Signal Mux Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE00++0x03 line.long 0x00 "CTRL_CQDETECT_STS,CTRL_CQDETECT_STS" bitfld.long 0x00 23. " CQMODE_CAMERA ,CQMODE_CAMERA" "1.8V mode,3.3V mode" bitfld.long 0x00 22. " CQMODE_LCDC ,CQMODE_LCDC" "1.8V mode,3.3V mode" bitfld.long 0x00 21. " CQMODE_GENERAL ,CQMODE_GENERAL" "1.8V mode,3.3V mode" textline " " bitfld.long 0x00 20. " CQMODE_GEMAC_B ,CQMODE_GEMAC_B" "1.8V mode,3.3V mode" bitfld.long 0x00 19. " CQMODE_GEMAC_A ,CQMODE_GEMAC_A" "1.8V mode,3.3V mode" bitfld.long 0x00 18. " CQMODE_MMCSD_B ,CQMODE_MMCSD_B" "1.8V mode,3.3V mode" textline " " bitfld.long 0x00 17. " CQMODE_MMCSD_A ,CQMODE_MMCSD_A" "1.8V mode,3.3V mode" bitfld.long 0x00 16. " CQMODE_GPMC ,CQMODE_GPMC" "1.8V mode,3.3V mode" rbitfld.long 0x00 15. " CQERR_CAMERA ,CQDetect Mode Error Status" "No error,Error" textline " " rbitfld.long 0x00 14. " CQERR_LCDC ,CQDetect Mode Error Status" "No error,Error" rbitfld.long 0x00 13. " CQERR_GENERAL ,CQDetect Mode Error Status" "No error,Error" rbitfld.long 0x00 12. " CQERR_GEMAC_B ,CQDetect Mode Error Status" "No error,Error" textline " " rbitfld.long 0x00 11. " CQERR_GEMAC_A ,CQDetect Mode Error Status" "No error,Error" rbitfld.long 0x00 10. " CQERR_MMCSD_B ,CQDetect Mode Error Status" "No error,Error" rbitfld.long 0x00 9. " CQERR_MMCSD_A ,CQDetect Mode Error Status" "No error,Error" textline " " rbitfld.long 0x00 8. " CQERR_GPMC ,CQDetect Mode Error Status" "No error,Error" rbitfld.long 0x00 7. " CQSTAT_CAMERA ,CQSTAT_CAMERA" "1.8V mode,3.3V mode" rbitfld.long 0x00 6. " CQSTAT_LCDC ,CQSTAT_LCDC" "1.8V mode,3.3V mode" textline " " rbitfld.long 0x00 5. " CQSTAT_GENERAL ,CQSTAT_GENERAL" "1.8V mode,3.3V mode" rbitfld.long 0x00 4. " CQSTAT_GEMAC_B ,CQSTAT_GEMAC_B" "1.8V mode,3.3V mode" rbitfld.long 0x00 3. " CQSTAT_GEMAC_A ,CQSTAT_GEMAC_A" "1.8V mode,3.3V mode" textline " " rbitfld.long 0x00 2. " CQSTAT_MMCSD_B ,CQSTAT_MMCSD_B" "1.8V mode,3.3V mode" rbitfld.long 0x00 1. " CQSTAT_MMCSD_A ,CQSTAT_MMCSD_A" "1.8V mode,3.3V mode" rbitfld.long 0x00 0. " CQSTAT_GPMC ,CQSTAT_GPMC" "1.8V mode,3.3V mode" group.long 0xE04++0x03 line.long 0x00 "CTRL_DDR_IO,CTRL_DDR_IO" bitfld.long 0x00 31. " DDR3_RST_DEF_VAL ,DDR3_RST_DEF_VAL" "DDR3 RESET,DDR RESET" group.long 0xE08++0x03 line.long 0x00 "CTRL_CQDETECT_STS2,CTRL_CQDETECT_STS2" bitfld.long 0x00 17. " CQMODE_MDIO ,CQMODE_MDIO" "1.8V mode,3.3V mode" bitfld.long 0x00 16. " CQMODE_CLKOUT ,CQMODE_CLKOUT" "1.8V mode,3.3V mode" rbitfld.long 0x00 9. " CQERR_MDIO ,CQDetect Mode Error Status" "No error,Error" textline " " rbitfld.long 0x00 8. " CQERR_CLKOUT ,CQDetect Mode Error Status" "No error,Error" rbitfld.long 0x00 1. " CQSTAT_MDIO ,CQSTAT_MDIO" "1.8V mode,3.3V mode" rbitfld.long 0x00 0. " CQSTAT_CLKOUT ,CQSTAT_CLKOUT" "1.8V mode,3.3V mode" group.long 0xE0C++0x03 line.long 0x00 "CTRL_VTP,CTRL_VTP" hexmask.long.byte 0x00 16.--22. 1. " PCIN ,Default/reset values of 'P' for the VTP controller" hexmask.long.byte 0x00 8.--14. 1. " NCIN ,Default/reset values of 'N' for the VTP controller" bitfld.long 0x00 6. " EN ,Active high enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 5. " READY ,READY" "Not completed,Completed" bitfld.long 0x00 4. " LOCK ,LOCK" "Normal,Freeze" bitfld.long 0x00 1.--3. " FILTER ,Digital filter bits" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0. " CLRZ ,Clears flops start count again after low going pulse" "Not clear,Clear" group.long 0xE14++0x03 line.long 0x00 "CTRL_VREF,CTRL_VREF" bitfld.long 0x00 3.--4. " DDR_VREF_CCAP ,Select for coupling cap for DDR" "No capacitor,BIAS2 and VSS,BIAS2 and VDDS,BIAS2 and VSS & BIAS2 and VDDS" bitfld.long 0x00 1.--2. " DDR_VREF_TAP ,Select for int ref for DDR" "2uA,4uA,6uA,8uA" bitfld.long 0x00 0. " DDR_VREF_EN ,Active high internal reference enable for DDR" "Disabled,Enabled" width 25. tree "CTRL_TPCC_EVT_MUX 0.--63." group.long 0xF90++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_0_3,CTRL_TPCC_EVT_MUX_0_3" bitfld.long 0x00 24.--29. " EVT_MUX_3 ,Selects 1 of 64 inputs for DMA event 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_2 ,Selects 1 of 64 inputs for DMA event 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_1 ,Selects 1 of 64 inputs for DMA event 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_0 ,Selects 1 of 64 inputs for DMA event 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF94++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_4_7,CTRL_TPCC_EVT_MUX_4_7" bitfld.long 0x00 24.--29. " EVT_MUX_7 ,Selects 1 of 64 inputs for DMA event 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_6 ,Selects 1 of 64 inputs for DMA event 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_5 ,Selects 1 of 64 inputs for DMA event 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_4 ,Selects 1 of 64 inputs for DMA event 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF98++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_8_11,CTRL_TPCC_EVT_MUX_8_11" bitfld.long 0x00 24.--29. " EVT_MUX_11 ,Selects 1 of 64 inputs for DMA event 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_10 ,Selects 1 of 64 inputs for DMA event 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_9 ,Selects 1 of 64 inputs for DMA event 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_8 ,Selects 1 of 64 inputs for DMA event 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF9C++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_12_15,CTRL_TPCC_EVT_MUX_12_15" bitfld.long 0x00 24.--29. " EVT_MUX_15 ,Selects 1 of 64 inputs for DMA event 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_14 ,Selects 1 of 64 inputs for DMA event 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_13 ,Selects 1 of 64 inputs for DMA event 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_12 ,Selects 1 of 64 inputs for DMA event 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFA0++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_16_19,CTRL_TPCC_EVT_MUX_16_19" bitfld.long 0x00 24.--29. " EVT_MUX_19 ,Selects 1 of 64 inputs for DMA event 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_18 ,Selects 1 of 64 inputs for DMA event 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_17 ,Selects 1 of 64 inputs for DMA event 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_16 ,Selects 1 of 64 inputs for DMA event 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFA4++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_20_23,CTRL_TPCC_EVT_MUX_20_23" bitfld.long 0x00 24.--29. " EVT_MUX_23 ,Selects 1 of 64 inputs for DMA event 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_22 ,Selects 1 of 64 inputs for DMA event 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_21 ,Selects 1 of 64 inputs for DMA event 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_20 ,Selects 1 of 64 inputs for DMA event 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFA8++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_24_27,CTRL_TPCC_EVT_MUX_24_27" bitfld.long 0x00 24.--29. " EVT_MUX_27 ,Selects 1 of 64 inputs for DMA event 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_26 ,Selects 1 of 64 inputs for DMA event 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_25 ,Selects 1 of 64 inputs for DMA event 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_24 ,Selects 1 of 64 inputs for DMA event 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFAC++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_28_31,CTRL_TPCC_EVT_MUX_28_31" bitfld.long 0x00 24.--29. " EVT_MUX_31 ,Selects 1 of 64 inputs for DMA event 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_30 ,Selects 1 of 64 inputs for DMA event 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_29 ,Selects 1 of 64 inputs for DMA event 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_28 ,Selects 1 of 64 inputs for DMA event 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFB0++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_32_35,CTRL_TPCC_EVT_MUX_32_35" bitfld.long 0x00 24.--29. " EVT_MUX_35 ,Selects 1 of 64 inputs for DMA event 35" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_34 ,Selects 1 of 64 inputs for DMA event 34" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_33 ,Selects 1 of 64 inputs for DMA event 33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_32 ,Selects 1 of 64 inputs for DMA event 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFB4++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_36_39,CTRL_TPCC_EVT_MUX_36_39" bitfld.long 0x00 24.--29. " EVT_MUX_39 ,Selects 1 of 64 inputs for DMA event 39" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_38 ,Selects 1 of 64 inputs for DMA event 38" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_37 ,Selects 1 of 64 inputs for DMA event 37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_36 ,Selects 1 of 64 inputs for DMA event 36" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFB8++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_40_43,CTRL_TPCC_EVT_MUX_40_43" bitfld.long 0x00 24.--29. " EVT_MUX_43 ,Selects 1 of 64 inputs for DMA event 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_42 ,Selects 1 of 64 inputs for DMA event 42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_41 ,Selects 1 of 64 inputs for DMA event 41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_40 ,Selects 1 of 64 inputs for DMA event 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFBC++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_44_47,CTRL_TPCC_EVT_MUX_44_47" bitfld.long 0x00 24.--29. " EVT_MUX_47 ,Selects 1 of 64 inputs for DMA event 47" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_46 ,Selects 1 of 64 inputs for DMA event 46" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_45 ,Selects 1 of 64 inputs for DMA event 45" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_44 ,Selects 1 of 64 inputs for DMA event 44" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFC0++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_48_51,CTRL_TPCC_EVT_MUX_48_51" bitfld.long 0x00 24.--29. " EVT_MUX_51 ,Selects 1 of 64 inputs for DMA event 51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_50 ,Selects 1 of 64 inputs for DMA event 50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_49 ,Selects 1 of 64 inputs for DMA event 49" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_48 ,Selects 1 of 64 inputs for DMA event 48" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFC4++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_52_55,CTRL_TPCC_EVT_MUX_52_55" bitfld.long 0x00 24.--29. " EVT_MUX_55 ,Selects 1 of 64 inputs for DMA event 55" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_54 ,Selects 1 of 64 inputs for DMA event 54" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_53 ,Selects 1 of 64 inputs for DMA event 53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_52 ,Selects 1 of 64 inputs for DMA event 52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFC8++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_56_59,CTRL_TPCC_EVT_MUX_56_59" bitfld.long 0x00 24.--29. " EVT_MUX_59 ,Selects 1 of 64 inputs for DMA event 59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_58 ,Selects 1 of 64 inputs for DMA event 58" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_57 ,Selects 1 of 64 inputs for DMA event 57" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_56 ,Selects 1 of 64 inputs for DMA event 56" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xFCC++0x03 line.long 0x00 "CTRL_TPCC_EVT_MUX_60_63,CTRL_TPCC_EVT_MUX_60_63" bitfld.long 0x00 24.--29. " EVT_MUX_63 ,Selects 1 of 64 inputs for DMA event 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " EVT_MUX_62 ,Selects 1 of 64 inputs for DMA event 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8.--13. " EVT_MUX_61 ,Selects 1 of 64 inputs for DMA event 61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " EVT_MUX_60 ,Selects 1 of 64 inputs for DMA event 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " tree.end width 24. group.long 0xFD0++0x03 line.long 0x00 "CTRL_TIMER_EVT_CAPT,CTRL_TIMER_EVT_CAPT" bitfld.long 0x00 16.--20. " TIMER7_EVTCAPT ,Timer 7 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TIMER6_EVTCAPT ,Timer 6 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TIMER5_EVTCAPT ,Timer 5 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xFD4++0x03 line.long 0x00 "CTRL_ECAP_EVT_CAPT,CTRL_ECAP_EVT_CAPT" bitfld.long 0x00 16.--20. " TIMER2_EVTCAPT ,Timer 2 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TIMER1_EVTCAPT ,Timer 1 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TIMER0_EVTCAPT ,Timer 0 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xFD8++0x03 line.long 0x00 "CTRL_ADC0_EVT_CAPT,CTRL_ADC0_EVT_CAPT" bitfld.long 0x00 0.--4. " ADC0_EVTCAPT ,ADC0 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xFDC++0x03 line.long 0x00 "CTRL_ADC1_EVT_CAPT,CTRL_ADC1_EVT_CAPT" bitfld.long 0x00 0.--4. " ADC1_EVTCAPT ,ADC0 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1000++0x03 line.long 0x00 "CTRL_RESET_ISO,CTRL_RESET_ISO" bitfld.long 0x00 1. " JTAG_ISO_CTRL ,JTAG IOs isolation status" "Not isolated,Isolated" bitfld.long 0x00 0. " CPSW_ISO_CTRL ,Ethernet switch isolation status" "Not isolated,Isolated" group.long 0x1318++0x03 line.long 0x00 "CTRL_DPLL_PWR_SW,CTRL_DPLL_PWR_SW" bitfld.long 0x00 31. " SW_CTRL_DDR_PLL ,Enable software control" "Disabled,Enabled" bitfld.long 0x00 29. " ISOSCAN_DDR ,Drives ISOSCAN of DDR PLL" "Not drive,Drive" bitfld.long 0x00 28. " RET_DDR ,Drives RET signal of DDR PLL" "Not drive,Drive" bitfld.long 0x00 27. " RESET_DDR ,Drives RESET of DDR DPLL" "Not drive,Drive" textline " " bitfld.long 0x00 26. " ISO_DDR ,Drives ISO of DDR DPLL" "Not drive,Drive" bitfld.long 0x00 25. " PGOODIN_DDR ,Drives PGOODIN of DDR DPLL" "Not drive,Drive" bitfld.long 0x00 24. " PONIN_DDR ,Drives PONIN of DDR DPLL" "Not drive,Drive" bitfld.long 0x00 23. " SW_CTRL_DISP_PLL ,Enable software control" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " ISOSCAN_DISP ,Drives ISOSCAN of DISP PLL" "Not drive,Drive" bitfld.long 0x00 20. " RET_DISP ,Drives RET of DISP DPLL" "Not drive,Drive" bitfld.long 0x00 19. " RESET_DISP ,Drives RESET of DISP DPLL" "Not drive,Drive" bitfld.long 0x00 18. " ISO_DISP ,Drives ISO of DISP DPLL" "Not drive,Drive" textline " " bitfld.long 0x00 17. " PGOODIN_DISP ,Drives PGOODIN of DISP DPLL" "Not drive,Drive" bitfld.long 0x00 16. " PONIN_DISP ,Drives PONIN of DISP DPLL" "Not drive,Drive" bitfld.long 0x00 15. " SW_CTRL_PER_PLL ,Enable software control" "Disabled,Enabled" bitfld.long 0x00 13. " ISOSCAN_PER ,Drives ISOSCAN of PER PLL" "Not drive,Drive" textline " " bitfld.long 0x00 12. " RET_PER ,Drives RET of PER DPLL" "Not drive,Drive" bitfld.long 0x00 11. " RESET_PER ,Drives RESET signal of PER DPLL" "Not drive,Drive" bitfld.long 0x00 10. " ISO_PER ,Drives ISO signal of PER DPLL" "Not drive,Drive" bitfld.long 0x00 9. " PGOODIN_PER ,Drives PGOODIN signal of PER DPLL" "Not drive,Drive" textline " " bitfld.long 0x00 8. " PONIN_PER ,Drives PONIN signal of PER DPLL" "Not drive,Drive" bitfld.long 0x00 7. " SW_CTRL_MPU_PLL ,Enable S/W control" "Disabled,Enabled" bitfld.long 0x00 5. " ISOSCAN_MPU ,Drives ISOSCAN of MPU PLL" "Not drive,Drive" bitfld.long 0x00 4. " RET_MPU ,Drives RET of MPU DPLL" "Not drive,Drive" textline " " bitfld.long 0x00 3. " RESET_MPU ,Drives RESET signal of MPU DPLL" "Not drive,Drive" bitfld.long 0x00 2. " ISO_MPU ,Drives ISO signal of MPU DPLL" "Not drive,Drive" bitfld.long 0x00 1. " PGOODIN_MPU ,Drives PGOODIN signal of MPU DPLL" "Not drive,Drive" bitfld.long 0x00 0. " PONIN_MPU ,Drives PONIN signal of MPU DPLL" "Not drive,Drive" group.long 0x131C++0x03 line.long 0x00 "CTRL_DDR_CKE,CTRL_DDR_CKE" rbitfld.long 0x00 3. " DDR_CKE1_ST ,CKE status bit" "0,1" rbitfld.long 0x00 2. " DDR_CKE0_ST ,CKE status bit" "0,1" bitfld.long 0x00 1. " DDR_CKE1_CTRL ,CKE from EMIF/DDRPHY is ANDed with this bit" "Gated,Normal" bitfld.long 0x00 0. " DDR_CKE0_CTRL ,CKE from EMIF/DDRPHY is ANDed with this bit" "Gated,Normal" group.long 0x1320++0x03 line.long 0x00 "CTRL_VSLDO,CTRL_VSLDO" hexmask.long 0x00 2.--30. 1. " CTRL_VSLDO ,Selectively Modifiable Attribute Bits (Spare Register)" bitfld.long 0x00 1. " VSLDO_CORE_AUTO_RAMP_EN ,VSLDO_CORE_AUTO_RAMP_EN" "PRCM controls VSLDO,Allows H/W to bring VSLDO" group.long 0x1324++0x03 line.long 0x00 "CTRL_WAKEPROC_TXEV_EOI,CTRL_WAKEPROC_TXEV_EOI" bitfld.long 0x00 0. " CTRL_WAKEPROC_TXEV_EOI ,CTRL_WAKEPROC_TXEV_EOI" "No event,Event" width 20. tree "CTRL_IPC_MSG_REG 0.--15." group.long 0x1328++0x03 line.long 0x00 "CTRL_IPC_MSG_REG0,Inter Processor Messaging Register" group.long 0x132C++0x03 line.long 0x00 "CTRL_IPC_MSG_REG1,Inter Processor Messaging Register" group.long 0x1330++0x03 line.long 0x00 "CTRL_IPC_MSG_REG2,Inter Processor Messaging Register" group.long 0x1334++0x03 line.long 0x00 "CTRL_IPC_MSG_REG3,Inter Processor Messaging Register" group.long 0x1338++0x03 line.long 0x00 "CTRL_IPC_MSG_REG4,Inter Processor Messaging Register" group.long 0x133C++0x03 line.long 0x00 "CTRL_IPC_MSG_REG5,Inter Processor Messaging Register" group.long 0x1340++0x03 line.long 0x00 "CTRL_IPC_MSG_REG6,Inter Processor Messaging Register" group.long 0x1344++0x03 line.long 0x00 "CTRL_IPC_MSG_REG7,Inter Processor Messaging Register" group.long 0x1348++0x03 line.long 0x00 "CTRL_IPC_MSG_REG8,Inter Processor Messaging Register" group.long 0x134C++0x03 line.long 0x00 "CTRL_IPC_MSG_REG9,Inter Processor Messaging Register" group.long 0x1350++0x03 line.long 0x00 "CTRL_IPC_MSG_REG10,Inter Processor Messaging Register" group.long 0x1354++0x03 line.long 0x00 "CTRL_IPC_MSG_REG11,Inter Processor Messaging Register" group.long 0x1358++0x03 line.long 0x00 "CTRL_IPC_MSG_REG12,Inter Processor Messaging Register" group.long 0x135C++0x03 line.long 0x00 "CTRL_IPC_MSG_REG13,Inter Processor Messaging Register" group.long 0x1360++0x03 line.long 0x00 "CTRL_IPC_MSG_REG14,Inter Processor Messaging Register" tree.end textline " " width 30. group.long 0x1364++0x03 line.long 0x00 "CTRL_IPC_INTR,CTRL_IPC_INTR" bitfld.long 0x00 31. " INTR2WAKEPROC ,Interrupt to M3" "No interrupt,Interrupt" hexmask.long 0x00 0.--30. 1. " IPC_MSG_REG15 ,Inter Processor Messaging Register" group.long 0x138C++0x03 line.long 0x00 "CTRL_DPLL_PWR_SW_CTRL2,CTRL_DPLL_PWR_SW_CTRL2" bitfld.long 0x00 7. " SW_CTRL_EXTCLK_PLL ,Enable S/W control" "Disabled,Enabled" bitfld.long 0x00 5. " ISOSCAN_EXTCLK ,Drives ISOSCAN of EXTCLK PLL" "No drive,Drive" bitfld.long 0x00 4. " RET_EXTCLK ,Drives RET of EXTCLK DPLL" "No drive,Drive" textline " " bitfld.long 0x00 3. " RESET_EXTCLK ,Drives RESET signal of EXTCLK DPLL" "No drive,Drive" bitfld.long 0x00 2. " ISO_EXTCLK ,Drives ISO signal of EXTCLK DPLL" "No drive,Drive" bitfld.long 0x00 1. " PGOODIN_EXTCLK ,Drives PGOODIN signal of EXTCLK DPLL" "No drive,Drive" textline " " bitfld.long 0x00 0. " PONIN_EXTCLK ,Drives PONIN signal of EXTCLK DPLL" "No drive,Drive" rgroup.long 0x1390++0x03 line.long 0x00 "CTRL_DPLL_PWR_SW_STS2,CTRL_DPLL_PWR_SW_STS2" bitfld.long 0x00 1. " PGOODOUT_EXTCLK ,PGOODOUT signal from EXTCLK DPLL" "0,1" bitfld.long 0x00 0. " PONOUT_EXTCLK ,PONOUT signal from EXTCLK DPLL" "0,1" group.long 0x1394++0x03 line.long 0x00 "CTRL_RESET_MISC,CTRL_RESET_MISC" hexmask.long 0x00 2.--31. 1. " CTRL_RESET_MISC ,Selectively Modifiable Attribute Bits (Spare Register)" bitfld.long 0x00 0. " NRESETIN_OUT_CTRL ,NRESETIN_OUT usable status" "Useable,Not useable" group.long 0x1404++0x03 line.long 0x00 "CTRL_DDR_ADDRCTRL_IOCTRL,CTRL_DDR_ADDRCTRL_IOCTRL" bitfld.long 0x00 8.--9. " IO_CONFIG_SR_CLK ,Program clock IO Pads (CK/CK#) output Slew Rate" "0,1,2,3" bitfld.long 0x00 5.--7. " IO_CONFIG_I_CLK ,Configuration input to program clock IO Pads (CK/CK#) output Impedance" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--4. " IO_CONFIG_SR ,Program addr/cmd IO Pads output Slew Rate" "0,1,2,3" bitfld.long 0x00 0.--2. " IO_CONFIG_I ,Configuration input to program addr/cmd IO Pad output Impedance" "0,1,2,3,4,5,6,7" group.long 0x1408++0x03 line.long 0x00 "CTRL_DDR_ADDRCTRL_WD0_IOCTRL,CTRL_DDR_ADDRCTRL_WD0_IOCTRL" bitfld.long 0x00 29. " Ddr_odt0 ,Ddr_odt0" "0,1" bitfld.long 0x00 28. " Ddr_odt1 ,Ddr_odt1" "0,1" bitfld.long 0x00 27. " Ddr_resetn ,Ddr_resetn" "0,1" bitfld.long 0x00 26. " Ddr_csn0 ,Ddr_csn0" "0,1" textline " " bitfld.long 0x00 25. " Ddr_csn1 ,Ddr_csn1" "0,1" bitfld.long 0x00 24. " Ddr_cke ,Ddr_cke" "0,1" bitfld.long 0x00 23. " Ddr_ck ,Ddr_ck" "0,1" bitfld.long 0x00 22. " Ddr_nck ,Ddr_nck" "0,1" textline " " bitfld.long 0x00 20. " Ddr_casn ,Ddr_casn" "0,1" bitfld.long 0x00 20. " Ddr_rasn ,Ddr_rasn" "0,1" bitfld.long 0x00 19. " Ddr_wen ,Ddr_wen" "0,1" bitfld.long 0x00 18. " Ddr_ba0 ,Ddr_ba0" "0,1" textline " " bitfld.long 0x00 17. " Ddr_ba1 ,Ddr_ba1" "0,1" bitfld.long 0x00 16. " Ddr_ba2 ,Ddr_ba2" "0,1" bitfld.long 0x00 15. " Addr_15 ,Addr_15" "0,1" bitfld.long 0x00 14. " Addr_14 ,Addr_14" "0,1" textline " " bitfld.long 0x00 13. " Addr_13 ,Addr_13" "0,1" bitfld.long 0x00 12. " Addr_12 ,Addr_12" "0,1" bitfld.long 0x00 11. " Addr_11 ,Addr_11" "0,1" bitfld.long 0x00 10. " Addr_10 ,Addr_10" "0,1" textline " " bitfld.long 0x00 9. " Addr_9 ,Addr_9" "0,1" bitfld.long 0x00 8. " Addr_8 ,Addr_8" "0,1" bitfld.long 0x00 7. " Addr_7 ,Addr_7" "0,1" bitfld.long 0x00 6. " Addr_6 ,Addr_6" "0,1" textline " " bitfld.long 0x00 5. " Addr_5 ,Addr_5" "0,1" bitfld.long 0x00 4. " Addr_4 ,Addr_4" "0,1" bitfld.long 0x00 3. " Addr_3 ,Addr_3" "0,1" bitfld.long 0x00 2. " Addr_2 ,Addr_2" "0,1" textline " " bitfld.long 0x00 1. " Addr_1 ,Addr_1" "0,1" bitfld.long 0x00 0. " Addr_0 ,Addr_0" "0,1" group.long 0x140C++0x03 line.long 0x00 "CTRL_DDR_ADDRCTRL_WD1_IOCTRL,CTRL_DDR_ADDRCTRL_WD1_IOCTRL" bitfld.long 0x00 29. " Ddr_odt0 ,Ddr_odt0" "0,1" bitfld.long 0x00 28. " Ddr_odt1 ,Ddr_odt1" "0,1" bitfld.long 0x00 27. " Ddr_resetn ,Ddr_resetn" "0,1" bitfld.long 0x00 26. " Ddr_csn0 ,Ddr_csn0" "0,1" textline " " bitfld.long 0x00 25. " Ddr_csn1 ,Ddr_csn1" "0,1" bitfld.long 0x00 24. " Ddr_cke ,Ddr_cke" "0,1" bitfld.long 0x00 23. " Ddr_ck ,Ddr_ck" "0,1" bitfld.long 0x00 22. " Ddr_nck ,Ddr_nck" "0,1" textline " " bitfld.long 0x00 20. " Ddr_casn ,Ddr_casn" "0,1" bitfld.long 0x00 20. " Ddr_rasn ,Ddr_rasn" "0,1" bitfld.long 0x00 19. " Ddr_wen ,Ddr_wen" "0,1" bitfld.long 0x00 18. " Ddr_ba0 ,Ddr_ba0" "0,1" textline " " bitfld.long 0x00 17. " Ddr_ba1 ,Ddr_ba1" "0,1" bitfld.long 0x00 16. " Ddr_ba2 ,Ddr_ba2" "0,1" bitfld.long 0x00 15. " Addr_15 ,Addr_15" "0,1" bitfld.long 0x00 14. " Addr_14 ,Addr_14" "0,1" textline " " bitfld.long 0x00 13. " Addr_13 ,Addr_13" "0,1" bitfld.long 0x00 12. " Addr_12 ,Addr_12" "0,1" bitfld.long 0x00 11. " Addr_11 ,Addr_11" "0,1" bitfld.long 0x00 10. " Addr_10 ,Addr_10" "0,1" textline " " bitfld.long 0x00 9. " Addr_9 ,Addr_9" "0,1" bitfld.long 0x00 8. " Addr_8 ,Addr_8" "0,1" bitfld.long 0x00 7. " Addr_7 ,Addr_7" "0,1" bitfld.long 0x00 6. " Addr_6 ,Addr_6" "0,1" textline " " bitfld.long 0x00 5. " Addr_5 ,Addr_5" "0,1" bitfld.long 0x00 4. " Addr_4 ,Addr_4" "0,1" bitfld.long 0x00 3. " Addr_3 ,Addr_3" "0,1" bitfld.long 0x00 2. " Addr_2 ,Addr_2" "0,1" textline " " bitfld.long 0x00 1. " Addr_1 ,Addr_1" "0,1" bitfld.long 0x00 0. " Addr_0 ,Addr_0" "0,1" group.long 0x1440++0x03 line.long 0x00 "CTRL_DDR_DATA0_IOCTRL,CTRL_DDR_DATA0_IOCTRL" bitfld.long 0x00 19. 29. " IO_CONFIG_WD_DQS_0 ,IO_CONFIG_WD_DQS_0" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 18. 28. " IO_CONFIG_WD_DM_0 ,IO_CONFIG_WD_DM_0" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 17. 27. " IO_CONFIG_7_DQ ,IO_CONFIG_7_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 16. 26. " IO_CONFIG_6_DQ ,IO_CONFIG_6_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 15. 25. " IO_CONFIG_5_DQ ,IO_CONFIG_5_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 14. 24. " IO_CONFIG_4_DQ ,IO_CONFIG_4_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 13. 23. " IO_CONFIG_3_DQ ,IO_CONFIG_3_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 12. 22. " IO_CONFIG_2_DQ ,IO_CONFIG_2_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 11. 21. " IO_CONFIG_1_DQ ,IO_CONFIG_1_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 10. 20. " IO_CONFIG_0_DQ ,IO_CONFIG_0_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 8.--9. " IO_CONFIG_SR_CLK ,Program clock IO Pads (DQS/DQS#) output Slew Rate" "0,1,2,3" bitfld.long 0x00 5.--7. " IO_CONFIG_I_CLK ,Configuration input to program clock IO Pads (DQS/DQS#) output Impedance" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--4. " IO_CONFIG_SR ,Program data IO Pads output Slew Rate for D(7 to 0)" "0,1,2,3" bitfld.long 0x00 0.--2. " IO_CONFIG_I ,Configuration input to program data IO Pad output Impedance for D(7 to 0)" "0,1,2,3,4,5,6,7" group.long 0x1444++0x03 line.long 0x00 "CTRL_DDR_DATA1_IOCTRL,CTRL_DDR_DATA1_IOCTRL" bitfld.long 0x00 19. 29. " IO_CONFIG_WD_DQS_1 ,IO_CONFIG_WD_DQS_1" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 18. 28. " IO_CONFIG_WD_DM_1 ,IO_CONFIG_WD_DM_1" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 17. 27. " IO_CONFIG_15_DQ ,IO_CONFIG_15_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 16. 26. " IO_CONFIG_14_DQ ,IO_CONFIG_14_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 15. 25. " IO_CONFIG_13_DQ ,IO_CONFIG_13_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 14. 24. " IO_CONFIG_12_DQ ,IO_CONFIG_12_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 13. 23. " IO_CONFIG_11_DQ ,IO_CONFIG_11_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 12. 22. " IO_CONFIG_10_DQ ,IO_CONFIG_10_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 11. 21. " IO_CONFIG_9_DQ ,IO_CONFIG_1_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 10. 20. " IO_CONFIG_8_DQ ,IO_CONFIG_0_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 8.--9. " IO_CONFIG_SR_CLK ,Program clock IO Pads (DQS1/DQS1#) output Slew Rate" "0,1,2,3" bitfld.long 0x00 5.--7. " IO_CONFIG_I_CLK ,Configuration input to program clock IO Pads (DQS1/DQS1#) output Impedance" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--4. " IO_CONFIG_SR ,Program data IO Pads output Slew Rate for D(15 to 8)" "0,1,2,3" bitfld.long 0x00 0.--2. " IO_CONFIG_I ,Configuration input to program data IO Pad output Impedance for D(15 to 8)" "0,1,2,3,4,5,6,7" group.long 0x1448++0x03 line.long 0x00 "CTRL_DDR_DATA2_IOCTRL,CTRL_DDR_DATA2_IOCTRL" bitfld.long 0x00 19. 29. " IO_CONFIG_WD_DQS_2 ,IO_CONFIG_WD_DQS_2" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 18. 28. " IO_CONFIG_WD_DM_2 ,IO_CONFIG_WD_DM_2" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 17. 27. " IO_CONFIG_23_DQ ,IO_CONFIG_23_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 16. 26. " IO_CONFIG_22_DQ ,IO_CONFIG_22_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 15. 25. " IO_CONFIG_21_DQ ,IO_CONFIG_21_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 14. 24. " IO_CONFIG_20_DQ ,IO_CONFIG_20_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 13. 23. " IO_CONFIG_19_DQ ,IO_CONFIG_19_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 12. 22. " IO_CONFIG_18_DQ ,IO_CONFIG_18_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 11. 21. " IO_CONFIG_17_DQ ,IO_CONFIG_17_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 10. 20. " IO_CONFIG_16_DQ ,IO_CONFIG_16_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 8.--9. " IO_CONFIG_SR_CLK ,Program clock IO Pads (DQS2/DQS2#) output Slew Rate" "0,1,2,3" bitfld.long 0x00 5.--7. " IO_CONFIG_I_CLK ,Configuration input to program clock IO Pads (DQS2/DQS2#) output Impedance" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--4. " IO_CONFIG_SR ,Program data IO Pads output Slew Rate for D(23 to 16)" "0,1,2,3" bitfld.long 0x00 0.--2. " IO_CONFIG_I ,Configuration input to program data IO Pad output Impedance for D(23 to 16)" "0,1,2,3,4,5,6,7" group.long 0x144C++0x03 line.long 0x00 "CTRL_DDR_DATA3_IOCTRL,CTRL_DDR_DATA3_IOCTRL" bitfld.long 0x00 19. 29. " IO_CONFIG_WD_DQS_3 ,IO_CONFIG_WD_DQS_3" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 18. 28. " IO_CONFIG_WD_DM_3 ,IO_CONFIG_WD_DM_3" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 17. 27. " IO_CONFIG_31_DQ ,IO_CONFIG_31_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 16. 26. " IO_CONFIG_30_DQ ,IO_CONFIG_30_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 15. 25. " IO_CONFIG_29_DQ ,IO_CONFIG_29_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 14. 24. " IO_CONFIG_28_DQ ,IO_CONFIG_28_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 13. 23. " IO_CONFIG_27_DQ ,IO_CONFIG_27_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 12. 22. " IO_CONFIG_26_DQ ,IO_CONFIG_26_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 11. 21. " IO_CONFIG_25_DQ ,IO_CONFIG_25_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" bitfld.long 0x00 10. 20. " IO_CONFIG_24_DQ ,IO_CONFIG_24_DQ" "Pullup/down disabled,Weak pulldown enabled,Weak pullup enabled,Weak keeper enabled" textline " " bitfld.long 0x00 8.--9. " IO_CONFIG_SR_CLK ,Program clock IO Pads (DQS3/DQS3#) output Slew Rate" "0,1,2,3" bitfld.long 0x00 5.--7. " IO_CONFIG_I_CLK ,Configuration input to program clock IO Pads (DQS3/DQS3#) output Impedance" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--4. " IO_CONFIG_SR ,Program data IO Pads output Slew Rate for D(31 to 24)" "0,1,2,3" bitfld.long 0x00 0.--2. " IO_CONFIG_I ,Configuration input to program data IO Pad output Impedance for D(31 to 24)" "0,1,2,3,4,5,6,7" group.long 0x1460++0x03 line.long 0x00 "CTRL_EMIF_SDRAM_CONFIG_EXT,CTRL_EMIF_SDRAM_CONFIG_EXT" bitfld.long 0x00 17. " NARROW_ONLY ,NARROW_ONLY" "No,Yes" bitfld.long 0x00 14.--15. " PHY_NUM_OF_SAMPLES ,Controls the number of samples used during read data eye training " "4,0x01,0x02,128" bitfld.long 0x00 13. " PHY_SEL_LOGIC ,Selects data read eye training algorithm" "0,#1" textline " " bitfld.long 0x00 12. " PHY_ALL_DQ_MPR_RD_RESP ,Controls the number of DQ pins used during read data eye training" "One,All" bitfld.long 0x00 9.--11. " PHY_OUTPUT_STS_SELECT ,Use to select the status to be observed on the spare_out pins through EMIF_SDRAM_STATUS_EXT" "Start_ratio(7 to 0),Start_ratio(15 to 8),End_ratio(7 to 0),End_ratio(15 to 8),,,," bitfld.long 0x00 8. " DYNAMIC_PWRDN_EN ,Enables dynamic PWRDN control in the IOs to reduce power consumption" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--6. " PHY_RD_LOCAL_ODT ,DDR IOs termination control value during reads" "0,1,2,3" bitfld.long 0x00 3. " DFI_CLOCK_PHASE_CTRL ,DFI clock division phase control in EMIF4D5SS" "0,1" bitfld.long 0x00 1. " EN_SLICE_1 ,Enable CMD PHY1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EN_SLICE_0 ,Enable CMD PHY0" "Disabled,Enabled" rgroup.long 0x1464++0x03 line.long 0x00 "CTRL_EMIF_SDRAM_STS_EXT,CTRL_EMIF_SDRAM_STS_EXT" if (((d.l(ad:0x44E10000+0x3000))&0x1)==0x01) //this.TINITZ== "Reset" group.long 0x3000++0x03 line.long 0x00 "CTRL_DISPPLL_CLKCTRL,CTRL_DISPPLL_CLKCTRL" bitfld.long 0x00 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK & FBCLK" "Disabled,Enabled" bitfld.long 0x00 30. " ENSSC ,Controls Clock Spreading" "Disabled,Enabled" bitfld.long 0x00 24. " NWELLTRIM ,Trim values for the PLL" "0,1" textline " " bitfld.long 0x00 23. " IDLE ,Sets PLL to Idle mode" "Active and Locked,Bypass low power" bitfld.long 0x00 22. " BYPASSACKZ ,Bypass status acknowledge signal" "Not bypassed,Bypassed" bitfld.long 0x00 21. " STBYRET ,Standby retention control" "Retention by gating,Relock" textline " " bitfld.long 0x00 20. " CLKOUTEN ,CLKOUT enable or disable" "Disabled,Enabled" bitfld.long 0x00 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW" bitfld.long 0x00 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO o/p." "Power down,Power up" textline " " bitfld.long 0x00 16. " M2PWDNZ ,M3PWDNZ" "Power down,M2" bitfld.long 0x00 15. " M3PWDNZ ,M3PWDNZ" "Power down,M3" bitfld.long 0x00 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp,Stopmode" textline " " bitfld.long 0x00 13. " LOWCURRSTDBY ,When in Lossclk/Stbyret/Idle" "Fast relock,Slow relock" bitfld.long 0x00 12. " LPMODE ,Set if CLPINP/(N+1)=1Mz and CLKINP*M/(N+1) = 100MHz" "Not set,Set" bitfld.long 0x00 11. " DRIFTGUARDEN ,Recalibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RELAXED_LOCK ,RELAXED_LOCK" "1%,2%" bitfld.long 0x00 0. " TINITZ ,PLL core soft reset" "No reset,Reset" else group.long 0x3000++0x03 line.long 0x00 "CTRL_DISPPLL_CLKCTRL,CTRL_DISPPLL_CLKCTRL" bitfld.long 0x00 31. " CYCLESLIPEN ,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK & FBCLK" "Disabled,Enabled" bitfld.long 0x00 30. " ENSSC ,Controls Clock Spreading" "Disabled,Enabled" bitfld.long 0x00 24. " NWELLTRIM ,Trim values for the PLL" "0,1" textline " " bitfld.long 0x00 22. " BYPASSACKZ ,Bypass status acknowledge signal" "Not bypassed,Bypassed" bitfld.long 0x00 21. " STBYRET ,Standby retention control" "Retention by gating,Relock" bitfld.long 0x00 20. " CLKOUTEN ,CLKOUT enable or disable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " ULOWCLKEN ,Select CLKOUT source in bypass" "CLKINP/(N2+1),CLKINPULOW" bitfld.long 0x00 17. " CLKDCOLDOPWDNZ ,Asynchronous power down for CLKDCOLDO o/p." "Power down,Power up" bitfld.long 0x00 16. " M2PWDNZ ,M3PWDNZ" "Power down,M2" textline " " bitfld.long 0x00 15. " M3PWDNZ ,M3PWDNZ" "Power down,M3" bitfld.long 0x00 14. " STOPMODE ,When in Lossclk/Stbyret" "Limp,Stopmode" bitfld.long 0x00 13. " LOWCURRSTDBY ,When in Lossclk/Stbyret/Idle" "Fast relock,Slow relock" textline " " bitfld.long 0x00 12. " LPMODE ,Set if CLPINP/(N+1)=1Mz and CLKINP*M/(N+1) = 100MHz" "Not set,Set" bitfld.long 0x00 11. " DRIFTGUARDEN ,Recalibration enable" "Disabled,Enabled" bitfld.long 0x00 8. " RELAXED_LOCK ,RELAXED_LOCK" "1%,2%" textline " " bitfld.long 0x00 0. " TINITZ ,PLL core soft reset" "No reset,Reset" endif group.long 0x3004++0x03 line.long 0x00 "CTRL_DISPPLL_TEN,CTRL_DISPPLL_TEN" bitfld.long 0x00 0. " TEN ,SD and SELFREQDCO latch" "Not active,Active" group.long 0x3008++0x03 line.long 0x00 "CTRL_DISPPLL_TENIV,CTRL_DISPPLL_TENIV" bitfld.long 0x00 0. " TENIV ,M2 and N2 latch" "Not active,Active" group.long 0x300C++0x03 line.long 0x00 "CTRL_DISPPLL_M2NDIV,CTRL_DISPPLL_M2NDIV" hexmask.long.byte 0x00 16.--22. 1. " M2 ,Post-divider is REGM2" hexmask.long.byte 0x00 0.--7. 1. " N ,Pre-divider is REGN+1" group.long 0x3010++0x03 line.long 0x00 "CTRL_DISPPLL_MN2DIV,CTRL_DISPPLL_MN2DIV" bitfld.long 0x00 16.--19. " N2 ,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " M ,Feedback multiplier is REGM" group.long 0x3014++0x03 line.long 0x00 "CTRL_DISPPLL_FRACDIV,CTRL_DISPPLL_FRACDIV" hexmask.long.byte 0x00 24.--31. 1. " REGSD ,Sigma-Delta Divider" hexmask.long.tbyte 0x00 0.--17. 1. " FRACTIONALM ,Fractional part of the M divide" group.long 0x3018++0x03 line.long 0x00 "CTRL_DISPPLL_BWCTRL,CTRL_DISPPLL_BWCTRL" bitfld.long 0x00 1.--2. " BWCTRL ,Change Loop Bandwidth" "0,1,2,3" group.long 0x301C++0x03 line.long 0x00 "CTRL_DISPPLL_FRACCTRL,CTRL_DISPPLL_FRACCTRL" bitfld.long 0x00 31. " DOWNSPREAD ,DOWNSPREAD" "Low frequency,Both side" bitfld.long 0x00 28.--30. " MODFREQDIVIDEREXPONENT ,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 21.--27. 1. " MODFREQDIVIDERMANTISSA ,Mantissa of the REFCLK divider to define the modulation frequency" textline " " bitfld.long 0x00 18.--20. " DELTAMSTEPINTEGER ,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x00 0.--17. 1. " DELTAMSTEPFRACTION ,The fraction part of Frequency Spread control" rgroup.long 0x3020++0x03 line.long 0x00 "CTRL_DISPPLL_STS,CTRL_DISPPLL_STS" bitfld.long 0x00 30. " SSACK ,Spread-spectrum Clocking on output clocks disable/enable" "Disabled,Enabled" bitfld.long 0x00 29. " LDOPWDN ,ADJLLLJ internal LDO power down status" "No,Yes" bitfld.long 0x00 28. " RECAL_BSTS3 ,Recalibration status flag" "Not required,Required" textline " " bitfld.long 0x00 27. " RECAL_PIN ,Recalibration status flag" "Not required,Required" bitfld.long 0x00 10. " PHASELOCK ,Status on PHASELOCK output pin" "0,1" bitfld.long 0x00 9. " FREQLOCK ,Status on FREQLOCK output pin" "0,1" textline " " bitfld.long 0x00 8. " BYPASSACK ,Status of BYPASSACK output pin" "0,1" bitfld.long 0x00 7. " STBYRETACK ,Internal clocks ADPLLLJ are gated/active" "Gated,Active" bitfld.long 0x00 6. " LOSSREF ,Reference input loss" "0,1" textline " " bitfld.long 0x00 5. " CLKOUTACK ,Enable/disable condition of CLKOUT" "Disabled,Enabled" bitfld.long 0x00 4. " LOCK2 ,ADPLL internal loop lock status" "Unlocked,Locked" bitfld.long 0x00 3. " M2CHANGEACK ,Acknowledge for M2 change" "0,1" textline " " bitfld.long 0x00 2. " LIMP ,Limp mode on/off" "Stop,LIMP" bitfld.long 0x00 1. " HIGHJITTER ,HIGHJITTER" "Disasbled,Enabled" bitfld.long 0x00 0. " BYPASS ,Bypass status signal" "Not bypassed,Bypassed" group.long 0x3024++0x03 line.long 0x00 "CTRL_DISPPLL_M3DIV,CTRL_DISPPLL_M3DIV" bitfld.long 0x00 0.--4. " M3 ,Post Divider Reg M3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x3028++0x03 line.long 0x00 "CTRL_DISPPLL_RAMPCTRL,CTRL_DISPPLL_RAMPCTRL" bitfld.long 0x00 19.--20. " CLKRAMPLEVEL ,Controls the ramp sequence" "No ramping,Bypass clk /Fout/8 / Fout/4 / Fout/2 / Fout,Bypass clk / Fout/4 / Fout/2 / Fout/1.5 /Fout," bitfld.long 0x00 16.--18. " CLKRAMPRATE ,Controls the time spent on each ramp step" "2,4,8,16,32,64,128,512" bitfld.long 0x00 0. " RELOCK_RAMP_EN ,RELOCK_RAMP_EN" "0,1" width 11. tree.end tree "MS(MEMORY SUBSYSTEM)" tree "GMPC" base ad:0x50000000 width 22. group.long 0x1C++0x03 line.long 0x00 "GPMC_IRQENABLE,Interrupt enable register" bitfld.long 0x00 9. " WAIT1EDGEDETECTIONENABLE ,Enables the Wait1 Edge Detection interrupt" "Disabled,Enabled" bitfld.long 0x00 8. " WAIT0EDGEDETECTIONENABLE ,Enables the Wait0 Edge Detection interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TERMINALCOUNTEVENTENABLE ,Enables TerminalCountEvent interrupt issuing in pre-fetch or write posting mode" "Masked,Not masked" bitfld.long 0x00 0. " FIFOEVENTENABLE ,Enables the FIFOEvent interrupt" "Masked,Not masked" group.long 0x48++0x03 line.long 0x00 "GPMC_ERR_TYPE,Stores the type of error when an error occurs." bitfld.long 0x00 8.--10. " ILLEGALMCMD ,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4. " ERRORNOTSUPPADD ,Not supported Address error" "No error,Error" bitfld.long 0x00 3. " ERRORTIMEOUT ,Not supported Command error" "No error,Error" textline " " bitfld.long 0x00 2. " ERRORTIMEOUT ,Time-out error" "No error,Error" eventfld.long 0x00 0. " ERRORVALID ,Error validity status" "Not detected,Detected" group.long 0x18++0x03 line.long 0x00 "GPMC_IRQSTATUS,Interrupt status register" bitfld.long 0x00 9. " WAIT1EDGEDETECTIONSTATUS ,Status of the Wait1 Edge Detection interrupt" "Not detected,Detected" bitfld.long 0x00 8. " WAIT0EDGEDETECTIONSTATUS ,Status of the Wait0 Edge Detection interrupt" "Not detected,Detected" textline " " bitfld.long 0x00 1. " TERMINALCOUNTSTATUS ,Status of the TerminalCountEvent interrupt" "Greater than 0,Equal to 0" bitfld.long 0x00 0. " FIFOEVENTSTATUS ,Status of the FIFOEvent interrupt" "Least,Less" rgroup.long 0x14++0x03 line.long 0x00 "GPMC_SYSSTATUS,Register provides status information about the module" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not reset,Reset" group.long 0x54++0x03 line.long 0x00 "GPMC_STATUS,The status register provides global status bits of the GPMC." bitfld.long 0x00 9. " WAIT1STATUS ,Is a copy of input pin WAIT1" "Asserted,De-asserted" bitfld.long 0x00 8. " WAIT0STATUS ,Is a copy of input pin WAIT0" "Asserted,De-asserted" bitfld.long 0x00 0. " EMPTYWRITEBUFFERSTATUS ,Stores the empty status of the write buffer" "Not empty,Empty" rgroup.long 0x00++0x03 line.long 0x00 "GPMC_REVISION,The GPMC_REVISION register contains the IP revision code." hexmask.long.byte 0x00 0.--7. 1. " REV ,IP revision" group.long 0x10++0x03 line.long 0x00 "GPMC_SYSCONFIG,Controls the various parameters of the OCP interface" bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle," bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Free-running,Gated" group.long 0x50++0x03 line.long 0x00 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC." bitfld.long 0x00 9. " WAIT1PINPOLARITY ,Selects the polarity of input pin WAIT1" "Active low,Active high" bitfld.long 0x00 8. " WAIT0PINPOLARITY ,Selects the polarity of input pin WAIT0" "Active low,Active high" bitfld.long 0x00 4. " WRITEPROTECT ,Controls the WP output pin level" "Low,High" textline " " bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support" "No effect,Not modified" bitfld.long 0x00 0. " NANDFORCEPOSTEDWRITE ,Enables Force Posted Write" "Disabled,Enabled" group.long 0x44++0x03 line.long 0x00 "GPMC_ERR_ADDRESS,Address of the illegal access when an error occurs." hexmask.long 0x00 0.--30. 1. " ILLEGALADD ,Address of illegal access" group.long 0x40++0x03 line.long 0x00 "GPMC_TIMEOUT_CONTROL,The GPMC_TIMEOUT_CONTROL register allows the user to set the start value of the timeout counter" hexmask.long.word 0x00 4.--12. 1. " TIMEOUTSTARTVALUE ,Start value of the time-out counter" bitfld.long 0x00 0. " TIMEOUTENABLE ,Enable bit of the TimeOut feature" "Disabled,Enabled" group.long 0x60++0x03 line.long 0x00 "GPMC_CONFIG1_0,The configuration 1 register sets signal control parameters per chip select." bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported" bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple" bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple" bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous" bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC.CLK activation time" "At start,One,Two," textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page length" "4 Words,8 Words,16 Words," bitfld.long 0x00 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses" "Not monitored,Monitored" bitfld.long 0x00 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "Valid,One,Two," bitfld.long 0x00 16.--17. " WAITPINSELECT ,Selects the input WAIT pin for this chip select." "WAIT0,WAIT1,," bitfld.long 0x00 12.--13. " DEVICESIZE ,Selects the device size attached" "8 bit,16 bit,2,3" textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR,,NAND," bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the Address and data multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Multiplexed," bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "Latencies x1,Latencies x2" textline " " bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC.FCLK clock" "GPMC_FCLK/1,GPMC_FCLK/2,GPMC_FCLK/3,GPMC_FCLK/4" group.long 0x64++0x03 line.long 0x00 "GPMC_CONFIG2_0,Chip-select signal timing parameter configuration." bitfld.long 0x00 16.--20. " CSWROFFTIME ,CS# de-assertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " CSRDOFFTIME ,CS# de-assertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " CSEXTRADELAY ,CS# Add Extra Half GPMC.FCLK cycle" "Not delayed,Delayed" bitfld.long 0x00 0.--3. " CSONTIME ,CS# assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x68++0x03 line.long 0x00 "GPMC_CONFIG3_0,ADV# signal timing parameter configuration." bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,ADV# de-assertion for first address phase when using the AAD-Mux protoco" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,ADV# assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " ADVWROFFTIME ,ADV# de-assertion time from start cycle time for write accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,ADV# de-assertion time from start cycle time for read accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " ADVEXTRADELAY ,ADV# Add Extra Half GPMC.FCLK cycle" "Not delayed,Delayed" bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,ADV# assertion for first address phase when using the AAD-Multiplexed protocol" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 0.--3. " ADVONTIME ,ADV# assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x6C++0x03 line.long 0x00 "GPMC_CONFIG4_0,WE# and OE# signals timing parameter configuration." bitfld.long 0x00 24.--28. " WEOFFTIME ,WE# de-assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " WEEXTRADELAY ,WE# Add Extra Half GPMC.FCLK cycle" "Not delayed,Delayed" bitfld.long 0x00 16.--19. " WEONTIME ,WE# assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,OE# de-assertion time for the first address phase in an AAD-Multiplexed access" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--12. " OEOFFTIME ,OE# de-assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 7. " OEEXTRADELAY ,OE# Add Extra Half GPMC.FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,OE# assertion time for the first address phase in an AAD-Multiplexed access" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " OEONTIME ,OE# assertion time from start cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x70++0x03 line.long 0x00 "GPMC_CONFIG5_0,RdAccessTime and CycleTime timing parameters configuration." bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x74++0x03 line.long 0x00 "GPMC_CONFIG6_0,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle, and BusTurnAround parameters configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from StartAccessTime to the GPMC.FCLK rising edge corresponding the the GPMC.CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC.FCLK rising edge the first data of the synchronous burst write is driven in the add/data multiplexed bus" "0,1,2,3,4,5,6,Reset,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay between two successive accesses to the same chip-selec" "No delay,Add delay" bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay between two successive accesses to a different chip-select" "No delay,Add delay" bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency between two successive accesses to the same chip-select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x78++0x03 line.long 0x00 "GPMC_CONFIG7_0,Chip-select address mapping configuration." bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 Mbytes,,,,,,,,128 Mbytes,,,,64 Mbytes,,32 Mbytes,16 Mbytes" bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address" wgroup.long 0x7C++0x03 line.long 0x00 "GPMC_NAND_COMMAND_0,Address location" wgroup.long 0x80++0x03 line.long 0x00 "GPMC_NAND_ADDRESS_0,Address location." wgroup.long 0x84++0x03 line.long 0x00 "GPMC_NAND_DATA_0,This register is not a true register, just an address location." width 23. group.long 0x1FC++0x03 line.long 0x00 "GPMC_ECC_SIZE_CONFIG,GPMC_ECC_SIZE_CONFIG" hexmask.long.byte 0x00 22.--29. 1. " ECCSIZE1 ,Defines ECC size 1" hexmask.long.byte 0x00 12.--19. 1. " ECCSIZE0 ,Defines ECC size 0" bitfld.long 0x00 8. " ECC9RESULTSIZE ,Selects ECC size for ECC 9" "ECCSIZE0,ECCSIZE1" textline " " bitfld.long 0x00 7. " ECC8RESULTSIZE ,Selects ECC size for ECC 8" "ECCSIZE0,ECCSIZE1" bitfld.long 0x00 6. " ECC7RESULTSIZE ,Selects ECC size for ECC 7" "ECCSIZE0,ECCSIZE1" bitfld.long 0x00 5. " ECC6RESULTSIZE ,Selects ECC size for ECC 6" "ECCSIZE0,ECCSIZE1" textline " " bitfld.long 0x00 4. " ECC5RESULTSIZE ,Selects ECC size for ECC 5" "ECCSIZE0,ECCSIZE1" bitfld.long 0x00 3. " ECC4RESULTSIZE ,Selects ECC size for ECC 4" "ECCSIZE0,ECCSIZE1" bitfld.long 0x00 2. " ECC3RESULTSIZE ,Selects ECC size for ECC 3" "ECCSIZE0,ECCSIZE1" textline " " bitfld.long 0x00 1. " ECC2RESULTSIZE ,Selects ECC size for ECC 2" "ECCSIZE0,ECCSIZE1" bitfld.long 0x00 0. " ECC1RESULTSIZE ,Selects ECC size for ECC 1" "ECCSIZE0,ECCSIZE1" group.long 0x1E4++0x03 line.long 0x00 "GPMC_PREFETCH_CONFIG2,GPMC_PREFETCH_CONFIG2" hexmask.long.word 0x00 0.--13. 1. " TRANSFERCOUNT ,Selects the number of bytes to be read or written by the engine to the selected CS (active low)" rgroup.long 0x1F0++0x03 line.long 0x00 "GPMC_PREFETCH_STATUS,GPMC_PREFETCH_STATUS" hexmask.long.byte 0x00 24.--30. 1. " FIFOPOINTER ,FIFOPOINTER" bitfld.long 0x00 16. " FIFOTHRESHOLDSTATUS ,Set when FIFOPointer exceeds FIFOThreshold value" "Smaller or equal,Greater" hexmask.long.word 0x00 0.--13. 1. " COUNTVALUE ,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value" group.long 0x1F8++0x03 line.long 0x00 "GPMC_ECC_CONTROL,GPMC_ECC_CONTROL" bitfld.long 0x00 8. " ECCCLEAR ,Clear all ECC result registers" "Ignored,Clears all ECC" bitfld.long 0x00 0.--3. " ECCPOINTER ,Selects ECC result register" "Disabeled,1,2,3,4,5,6,7,8,9,,,,,," group.long 0x1F4++0x03 line.long 0x00 "GPMC_ECC_CONFIG,GPMC_ECC_CONFIG" bitfld.long 0x00 16. " ECCALGORITHM ,ECC algorithm used" "Hamming,BCH" bitfld.long 0x00 12.--13. " ECCBCHTSEL ,Error correction capability used for BCH" "4 bits,8 bits,16 bits," bitfld.long 0x00 8.--11. " ECCWRAPMODE ,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " ECC16B ,Selects an ECC calculated on 16 columns" "8,16" bitfld.long 0x00 4.--6. " ECCTOPSECTOR ,Number of sectors to process with the BCH algorithm" "1 sector (512kB page),2 sectors,,4 sectors (2kB page),,,,8 sectors (4kB page)" bitfld.long 0x00 1.--3. " ECCCS ,Selects the Chip-select where ECC is computed" "0,1,2,3,4,5,," textline " " bitfld.long 0x00 0. " ECCENABLE ,Enables the ECC feature" "Disabled,Enabled" group.long 0x1EC++0x03 line.long 0x00 "GPMC_PREFETCH_CONTROL,GPMC_PREFETCH_CONTROL" bitfld.long 0x00 0. " STARTENGINE ,Resets the FIFO pointer and starts the engine" "Stopped,Running" group.long 0x1E0++0x03 line.long 0x00 "GPMC_PREFETCH_CONFIG1,GPMC_PREFETCH_CONFIG1" bitfld.long 0x00 28.--30. " CYCLEOPTIMIZATION ,Define the number of GPMC.FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " ENABLEOPTIMIZEDACCESS ,Enables access cycle optimization" "Disabled,Enabled" bitfld.long 0x00 24.--26. " ENGINECSSELECTOR ,Selects the CS" "CS0,CS1,CS2,CS3,CS4,CS5,CS6," textline " " bitfld.long 0x00 23. " PFPWENROUNDROBIN ,Prefetch Postwrite engine round robin arbitration enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PFPWWEIGHTEDPRIO ,PFPWWEIGHTEDPRIO" "Next accesses,Two accesses,,,,,,,,,,,,,,16 accesses" hexmask.long.byte 0x00 8.--14. 1. " FIFOTHRESHOLD ,Fifo threshold" textline " " bitfld.long 0x00 7. " ENABLEENGINE ,Enable engine" "Disabled,Enabled" bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Selects Wait Edge Detection" "Wait0,Wait1,," bitfld.long 0x00 3. " SYNCHROMODE ,SYNCHRO Mode" "STARTENGINE,STARTENGINE and wait" textline " " bitfld.long 0x00 2. " DMAMODE ,DMA Mode" "Request synchronization,Interrupt synchronization" bitfld.long 0x00 0. " ACCESSMODE ,Access Mode" "Prefetch read mode,Write-posting mode" width 20. group.long 0x360++0x03 line.long 0x00 "GPMC_BCH_RESULT4_6,Bits 128 to 159" group.long 0x244++0x03 line.long 0x00 "GPMC_BCH_RESULT1_0,Bits 32 to 63" group.long 0x340++0x03 line.long 0x00 "GPMC_BCH_RESULT4_4,Bits 128 to 159" group.long 0x308++0x03 line.long 0x00 "GPMC_BCH_RESULT6_0,Bits 192 to 207" group.long 0x250++0x03 line.long 0x00 "GPMC_BCH_RESULT0_1,Bits 0 to 31" rgroup.long 0x218++0x03 line.long 0x00 "GPMC_ECC7_RESULT," bitfld.long 0x00 27. " P2048O ,Odd Row Parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x00 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x00 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x00 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x00 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x00 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x00 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048E ,Even Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x00 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x00 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x00 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x00 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x00 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x00 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x00 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x00 0. " P1E ,Even Column Parity bit 1" "0,1" group.long 0x300++0x03 line.long 0x00 "GPMC_BCH_RESULT4_0,Bits 128 to 159" group.long 0x268++0x03 line.long 0x00 "GPMC_BCH_RESULT2_2,Bits 64 to 95" group.long 0x334++0x03 line.long 0x00 "GPMC_BCH_RESULT5_3,Bits 160 to 191" group.long 0x2D0++0x03 line.long 0x00 "GPMC_BCH_SWDATA,Directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface." hexmask.long.word 0x00 0.--15. 1. " BCH_DATA ,Data to be included in the BCH calculation" group.long 0x270++0x03 line.long 0x00 "GPMC_BCH_RESULT0_3,Bits 0 to 31" group.long 0x240++0x03 line.long 0x00 "GPMC_BCH_RESULT0_0, bits 0 to 31" group.long 0x364++0x03 line.long 0x00 "GPMC_BCH_RESULT5_6,Bits 160 to 191" rgroup.long 0x21C++0x03 line.long 0x00 "GPMC_ECC8_RESULT,GPMC_ECC8_RESULT" bitfld.long 0x00 27. " P2048O ,Odd Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x00 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x00 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x00 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x00 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x00 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x00 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048E ,Even Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x00 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x00 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x00 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x00 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x00 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x00 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x00 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x00 0. " P1E ,Even Column Parity bit 1" "0,1" group.long 0x290++0x03 line.long 0x00 "GPMC_BCH_RESULT0_5,Bits 0 to 31" group.long 0x220++0x03 line.long 0x00 "GPMC_ECC9_RESULT,GPMC_ECC9_RESULT" bitfld.long 0x00 27. " P2048O ,Odd Row Parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x00 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x00 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x00 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x00 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x00 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x00 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048E ,Even Row Parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x00 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x00 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x00 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x00 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x00 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x00 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x00 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x00 0. " P1E ,Even Column Parity bit 1" "0,1" group.long 0x320++0x03 line.long 0x00 "GPMC_BCH_RESULT4_2,Bits 128 to 159" group.long 0x25C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_1,Bits 96 to 127" group.long 0x304++0x03 line.long 0x00 "GPMC_BCH_RESULT5_0,Bits 160 to 191" group.long 0x358++0x03 line.long 0x00 "GPMC_BCH_RESULT6_5,Bits 192 to 207" group.long 0x29C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_5,Bits 96 to 127" rgroup.long 0x200++0x03 line.long 0x00 "GPMC_ECC1_RESULT,GPMC_ECC1_RESULT" bitfld.long 0x00 27. " P2048O ,Odd Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x00 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x00 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x00 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x00 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x00 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x00 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048E ,Even Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x00 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x00 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x00 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x00 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x00 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x00 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x00 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x00 0. " P1E ,Even Column Parity bit 1" "0,1" rgroup.long 0x208++0x03 line.long 0x00 "GPMC_ECC3_RESULT,GPMC_ECC3_RESULT" bitfld.long 0x00 27. " P2048O ,Odd Row Parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x00 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x00 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x00 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x00 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x00 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x00 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048E ,Even Row Parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x00 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x00 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x00 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x00 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x00 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x00 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x00 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x00 0. " P1E ,Even Column Parity bit 1" "0,1" group.long 0x2A0++0x03 line.long 0x00 "GPMC_BCH_RESULT0_6,Bits 0 to 31" group.long 0x368++0x03 line.long 0x00 "GPMC_BCH_RESULT6_6,Bits 192 to 207" rgroup.long 0x214++0x03 line.long 0x00 "GPMC_ECC6_RESULT,GPMC_ECC6_RESULT" bitfld.long 0x00 27. " P2048O ,Odd Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x00 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x00 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x00 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x00 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x00 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x00 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048E ,Even Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x00 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x00 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x00 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x00 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x00 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x00 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x00 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x00 0. " P1E ,Even Column Parity bit 1" "0,1" group.long 0x264++0x03 line.long 0x00 "GPMC_BCH_RESULT1_2,Bits 32 to 63" group.long 0x258++0x03 line.long 0x00 "GPMC_BCH_RESULT2_1,Bits 64 to 95" group.long 0x344++0x03 line.long 0x00 "GPMC_BCH_RESULT5_4,Bits 160 to 191" group.long 0x294++0x03 line.long 0x00 "GPMC_BCH_RESULT1_5,Bits 32 to 63" group.long 0x27C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_3,Bits 96 to 127" group.long 0x298++0x03 line.long 0x00 "GPMC_BCH_RESULT2_5,Bits 64 to 95" group.long 0x350++0x03 line.long 0x00 "GPMC_BCH_RESULT4_5,Bits 128 to 159" group.long 0x338++0x03 line.long 0x00 "GPMC_BCH_RESULT6_3,Bits 192 to 207" group.long 0x324++0x03 line.long 0x00 "GPMC_BCH_RESULT5_2,Bits 160 to 191" group.long 0x2AC++0x03 line.long 0x00 "GPMC_BCH_RESULT3_6,Bits 96 to 127" group.long 0x310++0x03 line.long 0x00 "GPMC_BCH_RESULT4_1,Bits 128 to 159" group.long 0x318++0x03 line.long 0x00 "GPMC_BCH_RESULT6_1,Bits 192 to 207" rgroup.long 0x204++0x03 line.long 0x00 "GPMC_ECC2_RESULT,GPMC_ECC2_RESULT" bitfld.long 0x00 27. " P2048O ,Odd Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x00 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x00 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x00 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x00 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x00 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x00 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048E ,Even Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x00 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x00 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x00 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x00 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x00 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x00 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x00 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x00 0. " P1E ,Even Column Parity bit 1" "0,1" group.long 0x348++0x03 line.long 0x00 "GPMC_BCH_RESULT6_4,Bits 192 to 207" group.long 0x280++0x03 line.long 0x00 "GPMC_BCH_RESULT0_4,Bits 0 to 31" group.long 0x2A4++0x03 line.long 0x00 "GPMC_BCH_RESULT1_6,Bits 32 to 63" group.long 0x0000024C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_0,Bits 96 to 127" group.long 0x00000260++0x03 line.long 0x00 "GPMC_BCH_RESULT0_2,Bits 0 to 31" rgroup.long 0x00000210++0x03 line.long 0x00 "GPMC_ECC5_RESULT," bitfld.long 0x00 27. " P2048O ,Odd Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x00 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x00 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x00 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x00 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x00 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x00 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048E ,Even Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x00 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x00 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x00 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x00 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x00 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x00 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x00 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x00 0. " P1E ,Even Column Parity bit 1" "0,1" group.long 0x0000026C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_2,Bits 96 to 127" group.long 0x00000330++0x03 line.long 0x00 "GPMC_BCH_RESULT4_3,Bits 128 to 159" group.long 0x00000284++0x03 line.long 0x00 "GPMC_BCH_RESULT1_4,Bits 32 to 63" group.long 0x00000288++0x03 line.long 0x00 "GPMC_BCH_RESULT2_4,Bits 64 to 95" group.long 0x0000028C++0x03 line.long 0x00 "GPMC_BCH_RESULT3_4,Bits 96 to 127" group.long 0x00000278++0x03 line.long 0x00 "GPMC_BCH_RESULT2_3,Bits 64 to 95" rgroup.long 0x0000020C++0x03 line.long 0x00 "GPMC_ECC4_RESULT," bitfld.long 0x00 27. " P2048O ,Odd Row Parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x00 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x00 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x00 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x00 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x00 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x00 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x00 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x00 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x00 11. " P2048E ,Even Row Parity bit 2048, only used for ECC computed on 512 Bytes" "0,1" bitfld.long 0x00 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x00 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x00 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x00 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x00 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x00 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x00 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x00 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x00 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x00 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x00 0. " P1E ,Even Column Parity bit 1" "0,1" group.long 0x000002A8++0x03 line.long 0x00 "GPMC_BCH_RESULT2_6,Bits 64 to 95" group.long 0x00000314++0x03 line.long 0x00 "GPMC_BCH_RESULT5_1,Bits 160 to 191" group.long 0x00000274++0x03 line.long 0x00 "GPMC_BCH_RESULT1_3,Bits 32 to 63" group.long 0x00000254++0x03 line.long 0x00 "GPMC_BCH_RESULT1_1,Bits 32 to 63" group.long 0x00000354++0x03 line.long 0x00 "GPMC_BCH_RESULT5_5,Bits 160 to 191" group.long 0x00000248++0x03 line.long 0x00 "GPMC_BCH_RESULT2_0,Bits 64 to 95" group.long 0x00000328++0x03 line.long 0x00 "GPMC_BCH_RESULT6_2,Bits 192 to 207" width 11. tree.end tree "EMIF" base ad:0x4C000000 width 16. rgroup.long 0x00++0x03 line.long 0x00 "MOD_ID_REV,MOD_ID_REV" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old and current schemes" "0,1,2,3" bitfld.long 0x00 28.--29. " BU ,Business Unit" "0,1,2,3" textline " " hexmask.long.word 0x00 16.--27. 1. " MODULE_ID ,EMIF module ID" hexmask.long.byte 0x00 11.--15. 1. " RTL_VERSION ,RTL Version" textline " " bitfld.long 0x00 8.--10. " MAJOR_REVISION ,Major Revision" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--5. 1. " MINOR_REVISION ,Minor Revision" rgroup.long 0x04++0x03 line.long 0x00 "STS,STS" bitfld.long 0x00 31. " BE ,Big Endian" "Little,Big" bitfld.long 0x00 30. " DUAL_CLK_MODE ,Dual Clock mode" "0,1" textline " " bitfld.long 0x00 29. " FAST_INIT ,Fast initialization mode" "Disabled,Enabled" bitfld.long 0x00 6. " RDLVLGATETO ,Read DQS Gate Training Timeout" "No timeout,Timeout" textline " " bitfld.long 0x00 5. " RDLVLTO ,Read Data Eye Training Timeout" "No timeout,Timeout" bitfld.long 0x00 4. " WRLVLTO ,Write Leveling Timeout" "No timeout,Timeout" textline " " bitfld.long 0x00 2. " PHY_DLL_READY ,DDR PHY Ready" "Not ready,Ready" if (((d.l(ad:0x4C000000+0x08))&0xE0000000)==0x60000000) //this.SDRAM_TYPE== "DDR3" group.long 0x08++0x03 line.long 0x00 "SDRAM_CONFIG,SDRAM_CONFIG" bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type selection" ",,,DDR3,LPDDR2,,," bitfld.long 0x00 27.--28. " IBANK_POS ,Internal bank position" "0,1,2,3" textline " " bitfld.long 0x00 24.--26. " DDR_TERM ,DDR3 termination resistor value" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,," bitfld.long 0x00 23. " LPDDR2_DDQS ,LPDDR2 differential DQS enable" "Single,Differential" textline " " bitfld.long 0x00 21.--22. " DYN_ODT ,DDR3 Dynamic ODT" "Off,RZQ/4,RZQ/2," bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL select" "No,Yes" textline " " bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM drive strength" "RZQ/6,RZQ/7,," bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write latency" "5,6,7,8" textline " " bitfld.long 0x00 14.--15. " NARROW_MODE ,SDRAM data bus width" "32bit,16bit,," bitfld.long 0x00 10.--13. " CL ,CAS Latency" ",,5,,6,,7,,8,,9,,10,,11," textline " " bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--6. " IBANK ,Internal Bank setup" "1,2,4,8,,,," textline " " bitfld.long 0x00 3. " EBANK ,External chip select setup" "Pad_cs_o_n[0],Pad_cs_o_n[1:0]" bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size" "256-word,512-word,1024-word,2048-word,,,," else group.long 0x08++0x03 line.long 0x00 "SDRAM_CONFIG,SDRAM_CONFIG" bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type selection" ",,,DDR3,LPDDR2,,," bitfld.long 0x00 27.--28. " IBANK_POS ,Internal bank position" "0,1,2,3" textline " " bitfld.long 0x00 24.--26. " DDR_TERM ,DDR3 termination resistor value" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,," bitfld.long 0x00 23. " LPDDR2_DDQS ,LPDDR2 differential DQS enable" "Single,Differential" textline " " bitfld.long 0x00 21.--22. " DYN_ODT ,DDR3 Dynamic ODT" "Off,RZQ/4,RZQ/2," bitfld.long 0x00 20. " DDR_DISABLE_DLL ,Disable DLL select" "No,Yes" textline " " bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM drive strength" "RZQ/6,RZQ/7,," bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write latency" "5,6,7,8" textline " " bitfld.long 0x00 14.--15. " NARROW_MODE ,SDRAM data bus width" "32bit,16bit,," bitfld.long 0x00 10.--13. " CL ,CAS Latency" ",,,3,4,5,6,7,8,,,,,,," textline " " bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--6. " IBANK ,Internal Bank setup" "1,2,4,8,,,," textline " " bitfld.long 0x00 3. " EBANK ,External chip select setup" "Pad_cs_o_n[0],Pad_cs_o_n[1:0]" bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size" "256-word,512-word,1024-word,2048-word,,,," endif group.long 0x0C++0x03 line.long 0x00 "SDRAM_CONFIG_2,SDRAM_CONFIG_2" bitfld.long 0x00 30. " CS1NVMEN ,CS1 LPDDR2 NVM enable" "Disabled,Enabled" bitfld.long 0x00 27. " EBANK_POS ,External bank position" "Lower,Higher" textline " " bitfld.long 0x00 4.--5. " RDBNUM ,Row Buffer setup" "1,2,2,8" bitfld.long 0x00 0.--2. " RDBSIZE ,Row Data Buffer Size" "32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes" textline " " width 30. group.long 0x10++0x03 line.long 0x00 "SDRAM_REFRESH_CTRL,SDRAM_REFRESH_CTRL" bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh disable" "No,Yes" bitfld.long 0x00 29. " SRT ,DDR3 Self Refresh temperature range" "Normal operating,Extended operating" textline " " bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Full array,1/2 array,1/4 array,1/8 array,3/4 array,1/2 array,1/4 array,1/8 array" textline " " hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE ,Refresh Rate" group.long 0x14++0x03 line.long 0x00 "SDRAM_REFRESH_CTRL_SHADOW,SDRAM_REFRESH_CTRL_SHADOW" hexmask.long.word 0x00 0.--15. 1. " REFRESH_RATE_SHDW ,Shadow field for reg_refresh_rate" group.long 0x18++0x03 line.long 0x00 "SDRAM_TIMING_1,SDRAM_TIMING_1" bitfld.long 0x00 29.--31. " T_RTW ,Minimum number of DDR clock cycles between Read to Write data phases" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--28. " T_RP ,Minimum number of DDR clock cycles from Precharge to Activate or Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21.--24. " T_RCD ,Minimum number of DDR clock cycles from Activate to Read or Write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " T_WR ,Minimum number of DDR clock cycles from last Write transfer to Pre-charge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--16. " T_RAS ,Minimum number of DDR clock cycles from Activate to Pre-charge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--11. " T_RC ,Minimum number of DDR clock cycles from Activate to Activate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 3.--5. " T_RRD ,Minimum number of DDR clock cycles from Activate to Activate for a different bank" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " T_WTR ,Minimum number of DDR clock cycles from last Write to Read" "0,1,2,3,4,5,6,7" group.long 0x1C++0x03 line.long 0x00 "SDRAM_TIMING_1_SHADOW,SDRAM_TIMING_1_SHADOW" bitfld.long 0x00 29.--31. " T_RTW_SHDW ,Shadow field for reg_t_rtw" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--28. " T_RP_SHDW ,Shadow field for reg_t_rp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21.--24. " T_RCD_SHDW ,Shadow field for reg_t_rcd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " T_WR_SHDW ,Shadow field for reg_t_wr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--16. " T_RAS_SHDW ,Shadow field for reg_t_ras" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--11. " T_RC_SHDW ,Shadow field for reg_t_rc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 3.--5. " T_RRD_SHDW ,Shadow field for reg_t_rrd" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " T_WTR_SHDW ,Shadow field for reg_t_wtr" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "SDRAM_TIMING_2,SDRAM_TIMING_2" bitfld.long 0x00 28.--30. " T_XP ,Minimum number of DDR clock cycles from Powerdown exit to any command other than a Read command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--27. " T_XP ,Minimum number of DDR clock cycles from ODT enable to write data driven for and DDR3" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 16.--24. 1. " T_XSNR ,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command" hexmask.long.word 0x00 6.--15. 1. " T_XSRD ,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command" textline " " bitfld.long 0x00 3.--5. " T_RTP ,Minimum number of DDR clock cycles from the last Read command to a Pre-charge command for DDR3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " T_CKE ,Minimum number of DDR clock cycles between pad_cke_o changes" "0,1,2,3,4,5,6,7" group.long 0x24++0x03 line.long 0x00 "SDRAM_TIMING_2_SHADOW,SDRAM_TIMING_2_SHADOW" bitfld.long 0x00 28.--30. " T_XP_SHDW ,Shadow field for reg_t_xp" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--27. " T_ODSHDW ,Shadow field for reg_t_odt" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 16.--24. 1. " T_XSNR_SHDW ,Shadow field for reg_t_xsnr" hexmask.long.word 0x00 6.--15. 1. " T_XSRD_SHDW ,Shadow field for reg_t_xsrd" textline " " bitfld.long 0x00 3.--5. " T_RTP_SHDW ,Shadow field for reg_t_rtp" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " T_CKE_SHDW ,Shadow field for reg_t_cke" "0,1,2,3,4,5,6,7" group.long 0x28++0x03 line.long 0x00 "SDRAM_TIMING_3,SDRAM_TIMING_3" bitfld.long 0x00 28.--31. " T_PDLL_UL ,Minimum number of DDR clock cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " T_CSTA ,Minimum number of DDR clock cycles between write-to-write or read-to-read data phases to different chip selects" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21.--23. " T_CKESR ,Minimum number of DDR clock cycles for which LPDDR2 must remain in Self Refresh" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--20. " ZQ_ZQCS ,Number of DDR clock cycles for a ZQCS command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 13.--14. " T_TDQSCKMAX ,Number of DDR clock cycles that satisfies tDQSCKmax for LPDDR2" "0,1,2,3" hexmask.long.word 0x00 4.--12. 1. " T_RFC ,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate" textline " " bitfld.long 0x00 0.--3. " T_RAS_MAX ,Maximum number of reg_refresh_rate intervals from Activate to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x03 line.long 0x00 "SDRAM_TIMING_3_SHADOW,SDRAM_TIMING_3_SHADOW" bitfld.long 0x00 28.--31. " T_PDLL_UL_SHDW ,Shadow field for reg_t_pdll_ul" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " T_CSTA_SHDW ,Shadow field for reg_t_csta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21.--23. " T_CKESR_SHDW ,Shadow field for reg_t_ckesr" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--20. " ZQ_ZQCS_SHDW ,Shadow field for reg_zq_zqcs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 13.--14. " T_TDQSCKMAX_SHDW ,Shadow field for reg_t_tdqsckmax" "0,1,2,3" hexmask.long.word 0x00 4.--12. 1. " T_RFC_SHDW ,Shadow field for reg_t_rfc" textline " " bitfld.long 0x00 0.--3. " T_RAS_MAX_SHDW ,Shadow field for reg_t_ras_max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x03 line.long 0x00 "LPDDR2_NVM_TIMING,LPDDR2_NVM_TIMING" bitfld.long 0x00 28.--30. " NVM_T_XP ,Minimum number of DDR clock cycles from Powerdown exit to any command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " NVM_T_WTR ,Minimum number of DDR clock cycles from last Write to Read" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20.--23. " NVM_T_RP ,Minimum number of DDR clock cycles from Preactive to Activate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " NVM_T_WRA ,Minimum number of DDR clock cycles from last Write transfer to Activate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " NVM_T_RRD ,Minimum number of DDR clock cycles from Activate to Activate for a different bank" hexmask.long.byte 0x00 0.--7. 1. " NVM_T_RCDMIN ,Minimum number of DDR clock cycles from Activate to Read or Write" group.long 0x34++0x03 line.long 0x00 "LPDDR2_NVM_TIMING_SHADOW,LPDDR2_NVM_TIMING_SHADOW" bitfld.long 0x00 28.--30. " NVM_T_XP_SHDW ,Shadow field for reg_nvm_t_xp" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " NVM_T_WTR_SHDW ,Shadow field for reg_nvm_t_wtr" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20.--23. " NVM_T_RP_SHDW ,Shadow field for reg_nvm_t_rp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " NVM_T_WRA_SHDW ,Shadow field for reg_nvm_t_wra" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " NVM_T_RRD_SHDW ,Shadow field for reg_nvm_t_rrd" hexmask.long.byte 0x00 0.--7. 1. " NVM_T_RCDMIN_SHDW ,Shadow field for reg_nvm_t_rcdmin" group.long 0x38++0x03 line.long 0x00 "POWER_MANAGEMENT_CTRL,POWER_MANAGEMENT_CTRL" bitfld.long 0x00 12.--15. " PD_TIM ,Power Mangement timer for Power-Down" "Power-Down,16 clocks,32 clocks,64 clocks,128 clocks,256 clock,512 clocks,1024 clocks,2048 clocks,4096 clocks,8192 clocks,16384 clocks,32768 clocks,65536 clocks,131072 clocks,262144 clocks" bitfld.long 0x00 11. " DPD_EN ,Deep Power Down enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--10. " LP_MODE ,Automatic Power Management enable" "Disabled,Clock Stop,Self Refresh,Disabled,Power-Down,Disabled,Disabled,Disabled" bitfld.long 0x00 4.--7. " SR_TIM ,Power Mangement timer for Self Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CS_TIM ,Power Mangement timer for Clock Stop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x03 line.long 0x00 "POWER_MANAGEMENT_CTRL_SHADOW,POWER_MANAGEMENT_CTRL_SHADOW" bitfld.long 0x00 12.--15. " PD_TIM_SHDW ,Shadow field for reg_pd_tim" "Power-Down,16 clocks,32 clocks,64 clocks,128 clocks,256 clock,512 clocks,1024 clocks,2048 clocks,4096 clocks,8192 clocks,16384 clocks,32768 clocks,65536 clocks,131072 clocks,262144 clocks" bitfld.long 0x00 4.--7. " SR_TIM_SHDW ,Shadow field for reg_sr_tim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CS_TIM_SHDW ,Shadow field for reg_cs_tim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x03 line.long 0x00 "LPDDR2_MODE_REG_DATA,LPDDR2_MODE_REG_DATA" hexmask.long.byte 0x00 0.--6. 1. " VALUE_0 ,Mode register value" group.long 0x50++0x03 line.long 0x00 "LPDDR2_MODE_REG_CONFIG,LPDDR2_MODE_REG_CONFIG" bitfld.long 0x00 31. " CS ,Chip select to issue mode register command" "SC0,SC1" bitfld.long 0x00 30. " REFRESH_EN ,Refresh Enable after MRW write" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " ADDR ,Mode register address" group.long 0x54++0x03 line.long 0x00 "OCP_CONFIG,OCP_CONFIG" bitfld.long 0x00 24.--27. " SYS_THRESH_MAX ,System OCP Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " MPU_THRESH_MAX ,System MPU Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " LL_THRESH_MAX ,Low-latency OCP Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x58++0x03 line.long 0x00 "OCP_CONFIG_VALUE_1,OCP_CONFIG_VALUE_1" bitfld.long 0x00 30.--31. " SYS_BUS_WIDTH ,System OCP data bus width for a particular configuration" "32 bit,64 bit,128 bit,256 bit" bitfld.long 0x00 28.--29. " LL_BUS_WIDTH ,Low-latency OCP data bus width for a particular configuration" "32 bit,64 bit,128 bit,256 bit" textline " " hexmask.long.byte 0x00 8.--15. 1. " WR_FIFO_DEPTH ,Write Data FIFO depth for a particular configuration" hexmask.long.byte 0x00 0.--7. 1. " CMD_FIFO_DEPTH ,Command FIFO depth for a particular configuration" rgroup.long 0x5C++0x03 line.long 0x00 "OCP_CONFIG_VALUE_2,OCP_CONFIG_VALUE_2" hexmask.long.byte 0x00 16.--23. 1. " RREG_FIFO_DEPTH ,Register Read Data FIFO depth for a particular configuration" hexmask.long.byte 0x00 8.--15. 1. " RSD_FIFO_DEPTH ,SDRAM Read Data FIFO depth for a particular configuration" textline " " hexmask.long.byte 0x00 0.--7. 1. " RCMD_FIFO_DEPTH ,Read Command FIFO depth for a particular configuration" group.long 0x60++0x03 line.long 0x00 "IODFT_TEST_LOGIC_GLOBAL_CTRL,IODFT_TEST_LOGIC_GLOBAL_CTRL" hexmask.long.word 0x00 16.--31. 1. " TLEC ,IODFT Test Logic Execution Counter" bitfld.long 0x00 14. " MT ,MISR on/off trigger command" "Off,On" textline " " bitfld.long 0x00 13. " ACT_CAP_EN ,Active cycles capture enable" "Every clock cycle,Active cycles" bitfld.long 0x00 12. " OPG_LD ,Load pattern generators" "Not load,Load" textline " " bitfld.long 0x00 10. " RESET_PHY ,Reset DDR PHY" "No reset,Reset" bitfld.long 0x00 8. " MMS ,Chooses the source of the MISR input" "Output,Input" textline " " bitfld.long 0x00 4.--5. " MC ,MISR state" "Download,Hold,Load initial,Enable MISR" bitfld.long 0x00 1.--3. " PC ,Pattern code" "Functional mode,Output random XOR,Output random XNOR,8 bit shifter,Hold,Input random XOR,Input random XNOR,8 bit shifter" textline " " bitfld.long 0x00 0. " TM ,Functional mode enable" "IODFT,Functional" textline " " width 37. rgroup.long 0x64++0x03 line.long 0x00 "IODFT_TEST_LOGIC_CTRL_MISR_RESULT,IODFT_TEST_LOGIC_CTRL_MISR_RESULT" hexmask.long.word 0x00 12.--21. 1. " DQM_TLMR ,This result is for the DQM signals" hexmask.long.word 0x00 0.--10. 1. " CTL_TLMR ,This result is for the control signals" rgroup.long 0x68++0x03 line.long 0x00 "IODFT_TEST_LOGIC_ADDR_MISR_RESULT,IODFT_TEST_LOGIC_ADDR_MISR_RESULT" hexmask.long 0x00 0.--20. 1. " ADDR_TLMR ,This result is for the address signals" rgroup.long 0x6C++0x03 line.long 0x00 "IODFT_TEST_LOGIC_DATA_MISR_RESULT_1,IODFT_TEST_LOGIC_DATA_MISR_RESULT_1" rgroup.long 0x70++0x03 line.long 0x00 "DATA_TLMR_63_32,DATA_TLMR_63_32" rgroup.long 0x74++0x03 line.long 0x00 "IODFT_TEST_LOGIC_DATA_MISR_RESULT_3,IODFT_TEST_LOGIC_DATA_MISR_RESULT_3" bitfld.long 0x00 0.--2. " DATA_TLMR_66_64 ,DATA_TLMR_66_64" "0,1,2,3,4,5,6,7" rgroup.long 0x80++0x03 line.long 0x00 "PERFORMANCE_CTR_1,PERFORMANCE_CTR_1" rgroup.long 0x84++0x03 line.long 0x00 "PERFORMANCE_CTR_2,PERFORMANCE_CTR_2" rgroup.long 0x88++0x03 line.long 0x00 "PERFORMANCE_CTR_CONFIG,PERFORMANCE_CTR_CONFIG" bitfld.long 0x00 31. " CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register" "Disabled,Enabled" bitfld.long 0x00 30. " CNTR2_REGION_EN ,Chip Select filter enable for Performance Counter 2 register" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " CNTR2_CFG ,Filter configuration for Performance Counter 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CNTR1_REGION_EN ,Chip Select filter enable for Performance Counter 1 register" "Disabled,Enabled" bitfld.long 0x00 0.--3. " CNTR1_CFG ,Filter configuration for Performance Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " width 38. group.long 0x8C++0x03 line.long 0x00 "PERFORMANCE_CTR_MASTER_REGION_SELECT,PERFORMANCE_CTR_MASTER_REGION_SELECT" hexmask.long.byte 0x00 24.--31. 1. " MCONNID2 ,MConnID for Performance Counter 2 register" bitfld.long 0x00 16.--17. " REGION_SEL2 ,MAddrSpace for Performance Counter 2 register" "0,1,2,3" textline " " hexmask.long.byte 0x00 8.--15. 1. " MCONNID1 ,MConnID for Performance Counter 1 register" bitfld.long 0x00 0.--1. " REGION_SEL1 ,MAddrSpace for Performance Counter 1 register" "0,1,2,3" rgroup.long 0x90++0x03 line.long 0x00 "PERFORMANCE_CTR_TIME,PERFORMANCE_CTR_TIME" group.long 0x94++0x03 line.long 0x00 "MISC_REG,MISC_REG" bitfld.long 0x00 0. " DLL_CALIB_OS ,Ohy_dll_calib one shot" "Not generated,Generated" group.long 0x98++0x03 line.long 0x00 "DLL_CALIB_CTRL,DLL_CALIB_CTRL" bitfld.long 0x00 16.--19. " ACK_WAIT ,Required wait time after a phy_dll_calib after a phy_dll_calib is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--8. 1. " DLL_CALIB_INTERVAL ,Interval between phy_dll_calib generation" group.long 0x9C++0x03 line.long 0x00 "DLL_CALIB_CTRL_SHADOW,DLL_CALIB_CTRL_SHADOW" bitfld.long 0x00 16.--19. " ACK_WAIT_SHDW ,Shadow field for ack_wait" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--8. 1. " DLL_CALIB_INTERVAL_SHDW ,hadow field for dll_calib_interval" group.long 0xA0++0x03 line.long 0x00 "END_OF_INTR,END_OF_INTR" bitfld.long 0x00 0. " EOI ,Software End Of Interrupt" "OCP,Low OCP" group.long 0xA4++0x03 line.long 0x00 "SYSTEM_OCP_INTR_RAW_STS,SYSTEM_OCP_INTR_RAW_STS" bitfld.long 0x00 2. " DNV_SYS ,Raw status of system OCP interrupt for LPDDR2 NVM data not valid" "No,Yes" bitfld.long 0x00 1. " TA_SYS ,Raw status of system OCP interrupt for SDRAM temperature alert" "No,Yes" textline " " bitfld.long 0x00 0. " ERR_SYS ,Raw status of system OCP interrupt for command and address error" "No error,Error" group.long 0xA8++0x03 line.long 0x00 "LOW_LAT_OCP_INTR_RAW_STS,LOW_LAT_OCP_INTR_RAW_STS" bitfld.long 0x00 2. " DNV_LL ,Raw status of low-latency OCP interrupt for LPDDR2 NVM data not valid" "No,Yes" bitfld.long 0x00 1. " TA_LL ,Raw status of low-latency OCP interrupt for SDRAM temperature alert" "No,Yes" textline " " bitfld.long 0x00 0. " ERR_LL ,Raw status of low-latency OCP interrupt for command and address error" "No error,Error" group.long 0xAC++0x03 line.long 0x00 "SYSTEM_OCP_INTR_STS,SYSTEM_OCP_INTR_STS" eventfld.long 0x00 2. " ERR_SYS ,Enabled status of system OCP interrupt for command and address error" "No effect,Clear" eventfld.long 0x00 1. " TA_SYS ,Enabled status of system OCP interrupt for SDRAM temperature alert" "No effect,Clear" textline " " eventfld.long 0x00 0. " ERR_SYS ,Enabled status of system OCP interrupt for command and address error" "No effect,Clear" group.long 0xB0++0x03 line.long 0x00 "LOW_LAT_OCP_INTR_STS,LOW_LAT_OCP_INTR_STS" eventfld.long 0x00 2. " DNV_LL ,Enabled status of low-latency OCP interrupt for LPDDR2 NVM data not valid" "No effect,Clear" eventfld.long 0x00 1. " TA_LL , Enabled status of low-latency OCP interrupt for SDRAM temperature alert" "No effect,Clear" textline " " eventfld.long 0x00 0. " ERR_LL ,Enabled status of low-latency OCP interrupt for command and address error" "No effect,Clear" group.long 0xB4++0x03 line.long 0x00 "SYSTEM_OCP_INTR_EN_SET,SYSTEM_OCP_INTR_EN_SET" bitfld.long 0x00 2. " EN_DNV_SYS ,Enable set for system OCP interrupt for LPDDR2 NVM data not valid" "No effect,Enabled" bitfld.long 0x00 1. " EN_TA_SYS ,Enable set for system OCP interrupt for SDRAM temperature alert" "No effect,Enabled" textline " " bitfld.long 0x00 0. " EN_ERR_SYS ,Enable set for system OCP interrupt for command and address error" "No effect,Enabled" group.long 0xB8++0x03 line.long 0x00 "LOW_LAT_OCP_INTR_EN_SET,LOW_LAT_OCP_INTR_EN_SET" bitfld.long 0x00 2. " EN_DNV_LL ,Enable set for low-latency OCP interrupt for LPDDR2 NVM data not valid" "No effect,Enabled" bitfld.long 0x00 1. " EN_TA_LL ,Enable set for low-latency OCP interrupt for SDRAM temperature alert" "No effect,Enabled" textline " " bitfld.long 0x00 0. " EN_ERR_LL ,Enable set for low-latency OCP interrupt for command and address error" "No effect,Enabled" group.long 0xBC++0x03 line.long 0x00 "SYSTEM_OCP_INTR_EN_CLR,SYSTEM_OCP_INTR_EN_CLR" eventfld.long 0x00 2. " EN_DNV_SYS ,Enable clear for system OCP interrupt for LPDDR2 NVM data not valid" "No effect,Clear" eventfld.long 0x00 1. " EN_TA_SYS ,Enable clear for system OCP interrupt for SDRAM temperature alert" "No effect,Clear" textline " " eventfld.long 0x00 0. " EN_ERR_SYS ,Enable clear for system OCP interrupt for command and address error" "No effect,Clear" group.long 0xC0++0x03 line.long 0x00 "LOW_LAT_OCP_INTR_EN_CLR,LOW_LAT_OCP_INTR_EN_CLR" eventfld.long 0x00 2. " EN_DNV_LL ,Enable clear for low-latency OCP interrupt for LPDDR2 NVM data not valid" "No effect,Clear" eventfld.long 0x00 1. " EN_TA_LL ,Enable clear for low-latency OCP interrupt for SDRAM temperature alert" "No effect,Clear" textline " " eventfld.long 0x00 0. " EN_ERR_LL ,Enable clear for low-latency OCP interrupt for command and address error" "No effect,Clear" textline " " width 45. group.long 0xC8++0x03 line.long 0x00 "SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG,SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG" bitfld.long 0x00 31. " ZQ_CS1EN ,Enables ZQ calibration for CS1" "Disabled,Enabled" bitfld.long 0x00 30. " ZQ_CS0EN ,Enables ZQ calibration for CS0" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " ZQ_DUALCALEN ,ZQ Dual Calibration enable" "Disabled,Enabled" bitfld.long 0x00 28. " ZQ_SFEXITEN ,ZQCL on Self Refresh" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " ZQ_ZQINIT_MULT ,Indicates the number of ZQCL intervals that make up a ZQINIT interval" "0,1,2,3" bitfld.long 0x00 16.--17. " ZQ_ZQCL_MULT ,Indicates the number of ZQCS intervals that make up a ZQCL interval" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--15. 1. " ZQ_REFINTERVAL ,Number of refresh periods between ZQCS commands" textline " " width 33. group.long 0xCC++0x03 line.long 0x00 "TEMPERATURE_ALERT_CONFIG,TEMPERATURE_ALERT_CONFIG" bitfld.long 0x00 31. " ZQ_CS1EN ,Enables temperature alert polling for CS1" "Disabled,Enabled" bitfld.long 0x00 30. " TA_CS0EN ,Enables temperature alert polling for CS0" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " TA_SFEXITEN ,Temperature Alert Poll on Self-Refresh Active Power-Down and Precharge Power-Down exit enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " TA_DEVWDT ,Indicates how wide a physical device is" "8,16,32," textline " " bitfld.long 0x00 24.--25. " TA_DEVCNT ,Indicates which external byte lanes contain a device for temperature monitoring" "1,2,4," hexmask.long.tbyte 0x00 0.--21. 1. " TA_REFINTERVAL ,Number of refresh periods between temperature alert polls" rgroup.long 0xD0++0x03 line.long 0x00 "OCP_ERROR_LOG,OCP_ERROR_LOG" bitfld.long 0x00 14.--15. " MADDRSPACE ,Address space of the first errored transaction" "0,1,2,3" bitfld.long 0x00 11.--13. " MBURSTSEQ ,Addressing mode of the first errored transaction" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--10. " MCMD ,Command type of the first errored transaction" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " MCONNID ,Connection ID of the first errored transaction" group.long 0xD4++0x03 line.long 0x00 "READ_WRITE_LEVELING_RAMP_WINDOW,READ_WRITE_LEVELING_RAMP_WINDOW" hexmask.long.word 0x00 0.--12. 1. " RDWRLVLINC_RMP_WIN ,Incremental leveling ramp window in number of refresh periods" group.long 0xD8++0x03 line.long 0x00 "READ_WRITE_LEVELING_RAMP_CTRL,READ_WRITE_LEVELING_RAMP_CTRL" bitfld.long 0x00 31. " RDWRLVL_EN ,Read-Write Leveling enable" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " RDWRLVLINC_RMP_PRE ,Incremental leveling pre-scalar in number of refresh periods during ramp window" textline " " hexmask.long.byte 0x00 16.--23. 1. " RDLVLINC_RMP_INT ,Incremental read data eye training interval during ramp window" hexmask.long.byte 0x00 8.--15. 1. " RDLVLGATEINC_RMP_INT ,Incremental read DQS gate training interval during ramp window" textline " " hexmask.long.byte 0x00 0.--7. 1. " WRLVLINC_RMP_INT ,Incremental write leveling interval during ramp window" group.long 0xDC++0x03 line.long 0x00 "READ_WRITE_LEVELING_CTRL,READ_WRITE_LEVELING_CTRL" bitfld.long 0x00 31. " RDWRLVLFULL_START ,Full leveling trigger" "No,Yes" hexmask.long.byte 0x00 24.--30. 1. " RDWRLVLINC_PRE ,Incremental leveling pre-scalar in number of refresh periods" textline " " hexmask.long.byte 0x00 16.--23. 1. " RDLVLINC_INT ,Incremental read data eye training interval" hexmask.long.byte 0x00 8.--15. 1. " RDLVLGATEINC_INT ,Incremental read DQS gate training interval" textline " " hexmask.long.byte 0x00 0.--7. 1. " WRLVLINC_INT ,Incremental write leveling interval" group.long 0xE4++0x03 line.long 0x00 "DDR_PHY_CTRL_1,DDR_PHY_CTRL_1" bitfld.long 0x00 27. " RDLVL_MASK ,Mask read data eye training during full leveling command" "Not masked,Masked" bitfld.long 0x00 26. " RDLVLGATE_MASK ,Mask dqs gate training during full leveling command" "Not masked,Masked" textline " " bitfld.long 0x00 25. " WRLVL_MASK ,Mask write leveling training during full leveling command" "Not masked,Masked" bitfld.long 0x00 21. " PHY_HALF_DELAYS ,PHY_HALF_DELAYS" "0,1" textline " " bitfld.long 0x00 20. " PHY_CLK_STALL_LEVEL ,PHY_CLK_STALL_LEVEL" "0,1" bitfld.long 0x00 19. " PHY_DIS_CALIB_RST ,PHY_DIS_CALIB_RST" "0,1" textline " " bitfld.long 0x00 18. " PHY_INVERT_CLKOUT ,PHY_INVERT_CLKOUT" "0,1" hexmask.long.byte 0x00 10.--17. 1. " PHY_DLL_LOCK_DIFF ,PHY_DLL_LOCK_DIFF" textline " " bitfld.long 0x00 9. " PHY_FAST_DLL_LOCK ,PHY_FAST_DLL_LOCK" "0,1" bitfld.long 0x00 0.--4. " READ_LAT ,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xE8++0x03 line.long 0x00 "DDR_PHY_CTRL_1_SHADOW,DDR_PHY_CTRL_1_SHADOW" bitfld.long 0x00 27. " RDLVL_MASK_SHDW ,Mask read data eye training during full leveling command" "Not masked,Masked" bitfld.long 0x00 26. " RDLVLGATE_MASK_SHDW ,Mask dqs gate training during full leveling command" "Not masked,Masked" textline " " bitfld.long 0x00 25. " WRLVL_MASK_SHDW ,Mask write leveling training during full leveling command" "Not masked,Masked" bitfld.long 0x00 21. " PHY_HALF_DELAYS_SHDW ,PHY_HALF_DELAYS_SHDW" "0,1" textline " " bitfld.long 0x00 20. " PHY_CLK_STALL_LEVEL_SHDW ,PHY_CLK_STALL_LEVEL_SHDW" "0,1" bitfld.long 0x00 19. " PHY_DIS_CALIB_RST_SHDW ,PHY_DIS_CALIB_RST_SHDW" "0,1" textline " " bitfld.long 0x00 18. " PHY_INVERT_CLKOUT_SHDW ,PHY_INVERT_CLKOUT_SHDW" "0,1" hexmask.long.byte 0x00 10.--17. 1. " PHY_DLL_LOCK_DIFF_SHDW ,PHY_DLL_LOCK_DIFF_SHDW" textline " " bitfld.long 0x00 9. " PHY_FAST_DLL_LOCK_SHDW ,PHY_FAST_DLL_LOCK_SHDW" "0,1" bitfld.long 0x00 0.--4. " READ_LAT_SHDW ,Shadow field for reg_read_latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " width 45. group.long 0x100++0x03 line.long 0x00 "PRIORITY_TO_CLASS_OF_SERVICE_MAPPING,PRIORITY_TO_CLASS_OF_SERVICE_MAPPING" bitfld.long 0x00 31. " PRI_COS_MAP_EN ,Enable priority to class of service mapping" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PRI_7_COS ,Class of service for commands with priority of 7" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " PRI_6_COS ,Class of service for commands with priority of 6" "0,1,2,3" bitfld.long 0x00 10.--11. " PRI_5_COS ,Class of service for commands with priority of 5" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " PRI_4_COS ,Class of service for commands with priority of 4" "0,1,2,3" bitfld.long 0x00 6.--7. " PRI_3_COS ,Class of service for commands with priority of 3" "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " PRI_2_COS ,Class of service for commands with priority of 2" "0,1,2,3" bitfld.long 0x00 2.--3. " PRI_1_COS ,Class of service for commands with priority of 1" "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " PRI_0_COS ,Class of service for commands with priority of 0" "0,1,2,3" group.long 0x104++0x03 line.long 0x00 "CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING,CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING" bitfld.long 0x00 31. " CONNID_COS_1_MAP_EN ,Enable Connection ID to class of service 1 mapping" "Disabled,Enabled" hexmask.long.byte 0x00 23.--30. 1. " CONNID_1_COS ,Connection ID value 1 for class of service 1" textline " " bitfld.long 0x00 20.--22. " MSK_1_COS ,Mask for Connection ID value 1 for class of service 1" "Disabled,Bit 0,Bits 1:0,Bits 2:0,3:0,4:0,5:0,6:0" hexmask.long.byte 0x00 12.--19. 1. " CONNID_2_COS_1 ,Connection ID value 2 for class of service 1" textline " " bitfld.long 0x00 10.--11. " MSK_2_COS_1 ,Mask for Connection ID value 2 for class of service 1" "Disabled,Bit 0,Bits 1:0,Bits 2:0" hexmask.long.byte 0x00 2.--9. 1. " CONNID_3_COS_1 ,Connection ID value 3 for class of service 1" textline " " bitfld.long 0x00 0.--1. " MSK_3_COS_1 ,Mask for Connection ID value 3 for class of service 1" "Disabled,Bit 0,Bits 1:0,Bits 2:0" group.long 0x108++0x03 line.long 0x00 "CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING,CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING" bitfld.long 0x00 31. " CONNID_COS_2_MAP_EN ,Enable Connection ID to class of service 2 mapping" "Disabled,Enabled" hexmask.long.byte 0x00 23.--30. 1. " CONNID_1_COS_2 ,Connection ID value 1 for class of service 2" textline " " bitfld.long 0x00 20.--22. " MSK_1_COS_2 ,Mask for Connection ID value 1 for class of service 2" "Disabled,Bit 0,Bits 1:0,Bits 2:0,3:0,4:0,5:0,6:0" hexmask.long.byte 0x00 12.--19. 1. " CONNID_2_COS ,Connection ID value 2 for class of service 2" textline " " bitfld.long 0x00 10.--11. " MSK_2_COS ,Mask for Connection ID value 2 for class of service 2" "Disabled,Bit 0,Bits 1:0,Bits 2:0" hexmask.long.byte 0x00 2.--9. 1. " CONNID_3_COS_2 ,Connection ID value 3 for class of service 2" textline " " bitfld.long 0x00 0.--1. " MSK_3_COS_2 ,Mask for Connection ID value 3 for class of service 2" "Disabled,Bit 0,Bits 1:0,Bits 2:0" textline " " width 26. group.long 0x110++0x03 line.long 0x00 "ECC_CTRL_REG,ECC_CTRL_REG" bitfld.long 0x00 31. " REG_ECC_EN ,Enable ECC" "Disabled,Enabled" bitfld.long 0x00 30. " REG_ECC_ADDR_RGN_PROT ,Enable ECC PROT calculation" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " REG_ECC_ADDR_RGN_2_EN ,Enable ECC address range 2" "Disabled,Enabled" bitfld.long 0x00 0. " REG_ECC_ADDR_RGN_1_EN ,Enable ECC address range 1" "Disabled,Enabled" group.long 0x114++0x03 line.long 0x00 "ECC_ADDR_RANGE_1,ECC_ADDR_RANGE_1" hexmask.long.word 0x00 16.--31. 1. " REG_ECC_END_ADDR_1 ,End caddress [32:17] for ECC address range 1" hexmask.long.word 0x00 0.--15. 1. " REG_ECC_STRT_ADDR_1 ,Start caddress [32:17] for ECC address range 1" group.long 0x118++0x03 line.long 0x00 "ECC_ADDR_RANGE_2,ECC_ADDR_RANGE_2" hexmask.long.word 0x00 16.--31. 1. " REG_ECC_END_ADDR_2 ,End caddress [32:17] for ECC address range 2" hexmask.long.word 0x00 0.--15. 1. " REG_ECC_STRT_ADDR_2 ,Start caddress [32:17] for ECC address range 2" group.long 0x120++0x03 line.long 0x00 "READ_WRITE_EXECUTION_THR,READ_WRITE_EXECUTION_THR" bitfld.long 0x00 31. " MFLAG_OVERRIDE ,MFLAG_OVERRIDE" "Use MFLAG,Class of Service" bitfld.long 0x00 30. " EN_LLBUBBLE ,LL Bubble enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " WR_THRSH ,Write Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " RD_THRSH ,Read Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x124++0x03 line.long 0x00 "COS_CONFIG,COS_CONFIG" hexmask.long.byte 0x00 16.--23. 1. " COS_COUNT_1 ,Priority Raise Counter for class of service 1" hexmask.long.byte 0x00 8.--15. 1. " COS_COUNT_2 ,Priority Raise Counter for class of service 2" textline " " hexmask.long.byte 0x00 0.--7. 1. " PR_OLD_COUNT ,Priority Raise Old Counter" group.long 0x130++0x03 line.long 0x00 "1B_ECC_ERR_CNT,1B_ECC_ERR_CNT" group.long 0x134++0x03 line.long 0x00 "1B_ECC_ERR_THRSH,1B_ECC_ERR_THRSH" hexmask.long.byte 0x00 24.--31. 1. " REG_1B_ECC_ERR_THRSH ,1 bit ECC error threshold" hexmask.long.word 0x00 0.--15. 1. " REG_1B_ECC_ERR_WIN ,1 bit ECC error window in number of refresh periods" group.long 0x138++0x03 line.long 0x00 "1B_ECC_ERR_DIST_1,1B_ECC_ERR_DIST_1" group.long 0x13C++0x03 line.long 0x00 "1B_ECC_ERR_ADDR_LOG,1B_ECC_ERR_ADDR_LOG" group.long 0x140++0x03 line.long 0x00 "2B_ECC_ERR_ADDR_LOG,2B_ECC_ERR_ADDR_LOG" textline " " width 12. tree "PHY_STS_1-28" rgroup.long 0x144++0x03 line.long 0x00 "PHY_STS_1,PHY_STS_1" hexmask.long.tbyte 0x00 12.--29. 1. " PHY_REG_CTRL_DLL_SLAVE_VALUE ,DLL Slave Value" bitfld.long 0x00 4.--5. " PHY_REG_STS_DLL_LOCK ,Lock Status for Data DLLs" "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " PHY_REG_CTRL_DLL_LOCK ,Lock Status for Command DLLs" "0,1,2,3" rgroup.long 0x148++0x03 line.long 0x00 "PHY_STS_2,PHY_STS_2" rgroup.long 0x14C++0x03 line.long 0x00 "PHY_STS_3,PHY_STS_3" hexmask.long.word 0x00 16.--30. 1. " PHY_REG_RDFIFO_RDPTR ,Read FIFO Read Pointer" hexmask.long.word 0x00 0.--12. 1. " PHY_REG_STS_DLL_SLAVE_VALUE_HI ,Bits 44:32 of Phy_reg_status_dll_slave_value" rgroup.long 0x150++0x03 line.long 0x00 "PHY_STS_4,PHY_STS_4" hexmask.long.word 0x00 16.--30. 1. " PHY_REG_GATELVL_FSM ,Gate Levelling FSM" hexmask.long.word 0x00 0.--14. 1. " PHY_REG_RDFIFO_WRPTR ,Read FIFO Write Pointer" rgroup.long 0x154++0x03 line.long 0x00 "PHY_STS_5,PHY_STS_5" hexmask.long.tbyte 0x00 0.--19. 1. " PHY_REG_RD_LEVEL_FSM ,Read Levelling FSM" rgroup.long 0x158++0x03 line.long 0x00 "PHY_STS_6,PHY_STS_6" hexmask.long.word 0x00 0.--14. 1. " PHY_REG_WR_LEVEL_FSM ,Writel Levelling FSM" rgroup.long 0x15C++0x03 line.long 0x00 "PHY_STS_7,PHY_STS_7" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO1 ,Read levelling DQS ratio1" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO0 ,Read levelling DQS ratio0" rgroup.long 0x160++0x03 line.long 0x00 "PHY_STS_8,PHY_STS_8" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO3 ,Read levelling DQS ratio3" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO2 ,Read levelling DQS ratio2" rgroup.long 0x164++0x03 line.long 0x00 "PHY_STS_9,PHY_STS_9" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO5 ,Read levelling DQS ratio5" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO4 ,Read levelling DQS ratio4" rgroup.long 0x168++0x03 line.long 0x00 "PHY_STS_10,PHY_STS_10" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO7 ,Read levelling DQS ratio7" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO6 ,Read levelling DQS ratio6" rgroup.long 0x16C++0x03 line.long 0x00 "PHY_STS_11,PHY_STS_11" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO9 ,Read levelling DQS ratio9" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO8 ,Read levelling DQS ratio8" rgroup.long 0x170++0x03 line.long 0x00 "PHY_STS_12,PHY_STS_12" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO1 ,Read levelling FIFO Write Enable Ratio1" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO0 ,Read levelling FIFO Write Enable Ratio0" rgroup.long 0x174++0x03 line.long 0x00 "PHY_STS_13,PHY_STS_13" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO3 ,Read levelling FIFO Write Enable Ratio3" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO2 ,Read levelling FIFO Write Enable Ratio2" rgroup.long 0x178++0x03 line.long 0x00 "PHY_STS_14,PHY_STS_14" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO5 ,Read levelling FIFO Write Enable Ratio5" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO4 ,Read levelling FIFO Write Enable Ratio4" rgroup.long 0x17C++0x03 line.long 0x00 "PHY_STS_15,PHY_STS_15" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO7 ,Read levelling FIFO Write Enable Ratio7" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO6 ,Read levelling FIFO Write Enable Ratio6" group.long 0x180++0x03 line.long 0x00 "PHY_STS_16,PHY_STS_16" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO9 ,Read levelling FIFO Write Enable Ratio9" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO8 ,Read levelling FIFO Write Enable Ratio8" rgroup.long 0x184++0x03 line.long 0x00 "PHY_STS_17,PHY_STS_17" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO1 ,Write levelling DQ ratio1" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO0 ,Write levelling DQ ratio0" rgroup.long 0x188++0x03 line.long 0x00 "PHY_STS_18,PHY_STS_18" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO3 ,Write levelling DQ ratio3" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO2 ,Write levelling DQ ratio2" rgroup.long 0x18C++0x03 line.long 0x00 "PHY_STS_19,PHY_STS_19" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO5 ,Write levelling DQ ratio5" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO4 ,Write levelling DQ ratio4" rgroup.long 0x190++0x03 line.long 0x00 "PHY_STS_20,PHY_STS_20" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO7 ,Write levelling DQ ratio7" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO6 ,Write levelling DQ ratio6" rgroup.long 0x194++0x03 line.long 0x00 "PHY_STS_21,PHY_STS_21" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO9 ,Write levelling DQ ratio9" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO8 ,Write levelling DQ ratio8" rgroup.long 0x198++0x03 line.long 0x00 "PHY_STS_22,PHY_STS_22" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO1 ,Write levelling DQS ratio 1" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO0 ,Write levelling DQS ratio 0" rgroup.long 0x19C++0x03 line.long 0x00 "PHY_STS_23,PHY_STS_23" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO3 ,Write levelling DQS ratio 3" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO2 ,Write levelling DQS ratio2" rgroup.long 0x1A0++0x03 line.long 0x00 "PHY_STS_24,PHY_STS_24" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO5 ,Write levelling DQS ratio 5" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO4 ,Write levelling DQS ratio4" rgroup.long 0x1A4++0x03 line.long 0x00 "PHY_STS_25,PHY_STS_25" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO7 ,Write levelling DQS ratio 7" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO6 ,Write levelling DQS ratio6" rgroup.long 0x1A8++0x03 line.long 0x00 "PHY_STS_26,PHY_STS_26" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO9 ,Write levelling DQS ratio 9" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO8 ,Write levelling DQS ratio8" rgroup.long 0x1AC++0x03 line.long 0x00 "PHY_STS_27,PHY_STS_27" bitfld.long 0x00 28.--29. " PHY_REG_CTRL_MDLL_UNLOCK_STICKY ,Phy control MDLL unlock sticky" "0,1,2,3" bitfld.long 0x00 20.--24. " PHY_REG_STS_MDLL_UNLOCK_STICKY ,Phy data MDLL unlock sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x00 0.--19. 1. " PHY_REG_RDC_FIFO_RST_ERR_CNT ,RDC FIFO reset error count" group.long 0x1B0++0x03 line.long 0x00 "PHY_STS_28,PHY_STS_28" bitfld.long 0x00 24.--28. " PHY_REG_GATELVL_INC_FAIL ,Gate levelling failure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PHY_REG_WRLVL_INC_FAIL ,Write levelling failure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " PHY_REG_RDLVL_INC_FAIL ,Read levelling failure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " PHY_REG_FIFO_WE_IN_MIASALIGNED_STICKY ,FIFO write enable in misaligned stickly" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end width 24. tree "EXT_PHY_CTRL_1-31" group.long 0x200++0x03 line.long 0x00 "EXT_PHY_CTRL_1,EXT_PHY_CTRL_1" hexmask.long 0x00 0.--29. 1. " PHY_REG_CTRL_SLAVE_RATIO ,Ctrl Slave Ratio" group.long 0x204++0x03 line.long 0x00 "EXT_PHY_CTRL_1_SHADOW,EXT_PHY_CTRL_1_SHADOW" hexmask.long 0x00 0.--29. 1. " PHY_REG_CTRL_SLAVE_RATIO ,Ctrl Slave Ratio" group.long 0x208++0x03 line.long 0x00 "EXT_PHY_CTRL_2,EXT_PHY_CTRL_2" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO1 ,FIFO write enable slave ratio1" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO0 ,FIFO write enable slave ratio0" group.long 0x20C++0x03 line.long 0x00 "EXT_PHY_CTRL_2_SHADOW,EXT_PHY_CTRL_2_SHADOW" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO1 ,FIFO write enable slave ratio1" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO0 ,FIFO write enable slave ratio0" group.long 0x210++0x03 line.long 0x00 "EXT_PHY_CTRL_3,EXT_PHY_CTRL_3" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO3 ,FIFO write enable slave ratio3" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO2 ,FIFO write enable slave ratio2" group.long 0x214++0x03 line.long 0x00 "EXT_PHY_CTRL_3_SHADOW,EXT_PHY_CTRL_3_SHADOW" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO3 ,FIFO write enable slave ratio3" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO2 ,FIFO write enable slave ratio2" group.long 0x218++0x03 line.long 0x00 "EXT_PHY_CTRL_4,EXT_PHY_CTRL_4" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO5 ,FIFO write enable slave ratio5" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO4 ,FIFO write enable slave ratio4" group.long 0x21C++0x03 line.long 0x00 "EXT_PHY_CTRL_4_SHADOW,EXT_PHY_CTRL_4_SHADOW" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO5 ,FIFO write enable slave ratio5" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO4 ,FIFO write enable slave ratio4" group.long 0x220++0x03 line.long 0x00 "EXT_PHY_CTRL_5,EXT_PHY_CTRL_5" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO7 ,FIFO write enable slave ratio7" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO6 ,FIFO write enable slave ratio6" group.long 0x224++0x03 line.long 0x00 "EXT_PHY_CTRL_5_SHADOW,EXT_PHY_CTRL_5_SHADOW" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO7 ,FIFO write enable slave ratio7" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO6 ,FIFO write enable slave ratio6" group.long 0x228++0x03 line.long 0x00 "EXT_PHY_CTRL_6,EXT_PHY_CTRL_6" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO9 ,FIFO write enable slave ratio9" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO8 ,FIFO write enable slave ratio8" group.long 0x22C++0x03 line.long 0x00 "EXT_PHY_CTRL_6_SHADOW,EXT_PHY_CTRL_6_SHADOW" hexmask.long.word 0x00 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO9 ,FIFO write enable slave ratio9" hexmask.long.word 0x00 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO8 ,FIFO write enable slave ratio8" group.long 0x230++0x03 line.long 0x00 "EXT_PHY_CTRL_7,EXT_PHY_CTRL_7" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO1 ,Read DQS Slave Ratio1" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO0 ,Read DQS Slave Ratio0" group.long 0x234++0x03 line.long 0x00 "EXT_PHY_CTRL_7_SHADOW,EXT_PHY_CTRL_7_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO1 ,Read DQS Slave Ratio1" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO0 ,Read DQS Slave Ratio0" group.long 0x238++0x03 line.long 0x00 "EXT_PHY_CTRL_8,EXT_PHY_CTRL_8" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO3 ,Read DQS Slave Ratio3" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO2 ,Read DQS Slave Ratio2" group.long 0x23C++0x03 line.long 0x00 "EXT_PHY_CTRL_8_SHADOW,EXT_PHY_CTRL_8_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO3 ,Read DQS Slave Ratio3" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO2 ,Read DQS Slave Ratio2" group.long 0x240++0x03 line.long 0x00 "EXT_PHY_CTRL_9,EXT_PHY_CTRL_9" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO5 ,Read DQS Slave Ratio5" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO4 ,Read DQS Slave Ratio4" group.long 0x244++0x03 line.long 0x00 "EXT_PHY_CTRL_9_SHADOW,EXT_PHY_CTRL_9_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO5 ,Read DQS Slave Ratio5" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO4 ,Read DQS Slave Ratio4" group.long 0x248++0x03 line.long 0x00 "EXT_PHY_CTRL_10,EXT_PHY_CTRL_10" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO7 ,Read DQS Slave Ratio7" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO6 ,Read DQS Slave Ratio6" group.long 0x24C++0x03 line.long 0x00 "EXT_PHY_CTRL_10_SHADOW,EXT_PHY_CTRL_10_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO7 ,Read DQS Slave Ratio7" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO6 ,Read DQS Slave Ratio6" group.long 0x250++0x03 line.long 0x00 "EXT_PHY_CTRL_11,EXT_PHY_CTRL_11" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO9 ,Read DQS Slave Ratio9" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO8 ,Read DQS Slave Ratio8" group.long 0x254++0x03 line.long 0x00 "EXT_PHY_CTRL_11_SHADOW,EXT_PHY_CTRL_11_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO9 ,Read DQS Slave Ratio9" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO8 ,Read DQS Slave Ratio8" group.long 0x258++0x03 line.long 0x00 "EXT_PHY_CTRL_12,EXT_PHY_CTRL_12" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO1 ,Write Data Slave Ratio1" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO0 ,Write Data Slave Ratio0" group.long 0x25C++0x03 line.long 0x00 "EXT_PHY_CTRL_12_SHADOW,EXT_PHY_CTRL_12_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO1 ,Write Data Slave Ratio1" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO0 ,Write Data Slave Ratio0" group.long 0x260++0x03 line.long 0x00 "EXT_PHY_CTRL_13,EXT_PHY_CTRL_13" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO3 ,Write Data Slave Ratio3" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO2 ,Write Data Slave Ratio2" group.long 0x264++0x03 line.long 0x00 "EXT_PHY_CTRL_13_SHADOW,EXT_PHY_CTRL_13_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO3 ,Write Data Slave Ratio3" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO2 ,Write Data Slave Ratio2" group.long 0x268++0x03 line.long 0x00 "EXT_PHY_CTRL_14,EXT_PHY_CTRL_14" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO5 ,Write Data Slave Ratio5" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO4 ,Write Data Slave Ratio4" group.long 0x26C++0x03 line.long 0x00 "EXT_PHY_CTRL_14_SHADOW,EXT_PHY_CTRL_14_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO5 ,Write Data Slave Ratio5" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO4 ,Write Data Slave Ratio4" group.long 0x270++0x03 line.long 0x00 "EXT_PHY_CTRL_15,EXT_PHY_CTRL_15" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO7 ,Write Data Slave Ratio7" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO6 ,Write Data Slave Ratio6" group.long 0x274++0x03 line.long 0x00 "EXT_PHY_CTRL_15_SHADOW,EXT_PHY_CTRL_15_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO7 ,Write Data Slave Ratio7" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO6 ,Write Data Slave Ratio6" group.long 0x278++0x03 line.long 0x00 "EXT_PHY_CTRL_16,EXT_PHY_CTRL_16" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO9 ,Write Data Slave Ratio9" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO8 ,Write Data Slave Ratio8" group.long 0x27C++0x03 line.long 0x00 "EXT_PHY_CTRL_16_SHADOW,EXT_PHY_CTRL_16_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO9 ,Write Data Slave Ratio9" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO8 ,Write Data Slave Ratio8" group.long 0x280++0x03 line.long 0x00 "EXT_PHY_CTRL_17,EXT_PHY_CTRL_17" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO1 ,Write Data Slave Ratio1" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO0 ,Write Data Slave Ratio0" group.long 0x284++0x03 line.long 0x00 "EXT_PHY_CTRL_17_SHADOW,EXT_PHY_CTRL_17_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO1 ,Write Data Slave Ratio1" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO0 ,Write Data Slave Ratio0" group.long 0x288++0x03 line.long 0x00 "EXT_PHY_CTRL_18,EXT_PHY_CTRL_18" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO3 ,Write Data Slave Ratio3" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO2 ,Write Data Slave Ratio2" group.long 0x28C++0x03 line.long 0x00 "EXT_PHY_CTRL_18_SHADOW,EXT_PHY_CTRL_18_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO3 ,Write Data Slave Ratio3" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO2 ,Write Data Slave Ratio2" group.long 0x290++0x03 line.long 0x00 "EXT_PHY_CTRL_19,EXT_PHY_CTRL_19" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO5 ,Write Data Slave Ratio5" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO4 ,Write Data Slave Ratio4" group.long 0x294++0x03 line.long 0x00 "EXT_PHY_CTRL_19_SHADOW,EXT_PHY_CTRL_19_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO5 ,Write Data Slave Ratio5" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO4 ,Write Data Slave Ratio4" group.long 0x298++0x03 line.long 0x00 "EXT_PHY_CTRL_20,EXT_PHY_CTRL_20" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO7 ,Write Data Slave Ratio7" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO6 ,Write Data Slave Ratio6" group.long 0x29C++0x03 line.long 0x00 "EXT_PHY_CTRL_20_SHADOW,EXT_PHY_CTRL_20_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO7 ,Write Data Slave Ratio7" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO6 ,Write Data Slave Ratio6" group.long 0x2A0++0x03 line.long 0x00 "EXT_PHY_CTRL_21,EXT_PHY_CTRL_21" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO9 ,Write Data Slave Ratio9" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO8 ,Write Data Slave Ratio8" group.long 0x2A4++0x03 line.long 0x00 "EXT_PHY_CTRL_21_SHADOW,EXT_PHY_CTRL_21_SHADOW" hexmask.long.word 0x00 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO9 ,Write Data Slave Ratio9" hexmask.long.word 0x00 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO8 ,Write Data Slave Ratio8" group.long 0x2A8++0x03 line.long 0x00 "EXT_PHY_CTRL_22,EXT_PHY_CTRL_22" hexmask.long.word 0x00 16.--24. 1. " PHY_REG_FIFO_WE_IN_DELAY ,FIFO write enable in delay" hexmask.long.word 0x00 0.--8. 1. " PHY_REG_CTRL_SLAVE_DELAY ,Ctrl slave delay" group.long 0x2AC++0x03 line.long 0x00 "EXT_PHY_CTRL_22_SHADOW,EXT_PHY_CTRL_22_SHADOW" hexmask.long.word 0x00 16.--24. 1. " PHY_REG_FIFO_WE_IN_DELAY ,FIFO write enable in delay" hexmask.long.word 0x00 0.--8. 1. " PHY_REG_CTRL_SLAVE_DELAY ,Ctrl slave delay" group.long 0x2B0++0x03 line.long 0x00 "EXT_PHY_CTRL_23,EXT_PHY_CTRL_23" hexmask.long.word 0x00 16.--24. 1. " PHY_REG_WR_DQS_SLAVE_DELAY ,Write DQS Slave delay" hexmask.long.word 0x00 0.--8. 1. " PHY_REG_RD_DQS_SLAVE_DELAY ,Read DQS Slave delay" group.long 0x2B4++0x03 line.long 0x00 "EXT_PHY_CTRL_23_SHADOW,EXT_PHY_CTRL_23_SHADOW" hexmask.long.word 0x00 16.--24. 1. " PHY_REG_WR_DQS_SLAVE_DELAY ,Write DQS Slave delay" hexmask.long.word 0x00 0.--8. 1. " PHY_REG_RD_DQS_SLAVE_DELAY ,Read DQS Slave delay" group.long 0x2B8++0x03 line.long 0x00 "EXT_PHY_CTRL_24,EXT_PHY_CTRL_24" hexmask.long.byte 0x00 24.--30. 1. " REG_PHY_DQ_OFFSET_HI ,Phy DQ Offset bits 34:28" bitfld.long 0x00 16. " REG_PHY_GATELVL_INIT_MODE ,Gate levelling init mode" "0,1" textline " " bitfld.long 0x00 12. " REG_PHY_USE_RANK0_DELAYS ,Use rank0 delays" "0,1" hexmask.long.word 0x00 0.--8. 1. " REG_PHY_WR_DATA_SLAVE_DELAY ,Wirte data slave delay" group.long 0x2BC++0x03 line.long 0x00 "EXT_PHY_CTRL_24_SHADOW,EXT_PHY_CTRL_24_SHADOW" hexmask.long.byte 0x00 24.--30. 1. " REG_PHY_DQ_OFFSET_HI ,Phy DQ Offset bits 34:28" bitfld.long 0x00 16. " REG_PHY_GATELVL_INIT_MODE ,Gate levelling init mode" "0,1" textline " " bitfld.long 0x00 12. " REG_PHY_USE_RANK0_DELAYS ,Use rank0 delays" "0,1" hexmask.long.word 0x00 0.--8. 1. " REG_PHY_WR_DATA_SLAVE_DELAY ,Wirte data slave delay" group.long 0x2C0++0x03 line.long 0x00 "EXT_PHY_CTRL_25,EXT_PHY_CTRL_25" hexmask.long 0x00 0.--27. 1. " REG_PHY_DQ_OFFSET ,DQ offset" group.long 0x2C4++0x03 line.long 0x00 "EXT_PHY_CTRL_25_SHADOW,EXT_PHY_CTRL_25_SHADOW" hexmask.long 0x00 0.--27. 1. " REG_PHY_DQ_OFFSET ,DQ offset" group.long 0x2C8++0x03 line.long 0x00 "EXT_PHY_CTRL_26,EXT_PHY_CTRL_26" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO1 ,Gate levelling init ratio1" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO0 ,Gate levelling init ratio0" group.long 0x2CC++0x03 line.long 0x00 "EXT_PHY_CTRL_26_SHADOW,EXT_PHY_CTRL_26_SHADOW" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO1 ,Gate levelling init ratio1" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO0 ,Gate levelling init ratio0" group.long 0x2D0++0x03 line.long 0x00 "EXT_PHY_CTRL_27,EXT_PHY_CTRL_27" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO3 ,Gate levelling init ratio3" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO2 ,Gate levelling init ratio2" group.long 0x2D4++0x03 line.long 0x00 "EXT_PHY_CTRL_27_SHADOW,EXT_PHY_CTRL_27_SHADOW" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO3 ,Gate levelling init ratio3" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO2 ,Gate levelling init ratio2" group.long 0x2D8++0x03 line.long 0x00 "EXT_PHY_CTRL_28,EXT_PHY_CTRL_28" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO5 ,Gate levelling init ratio5" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO4 ,Gate levelling init ratio4" group.long 0x2DC++0x03 line.long 0x00 "EXT_PHY_CTRL_28_SHADOW,EXT_PHY_CTRL_28_SHADOW" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO5 ,Gate levelling init ratio5" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO4 ,Gate levelling init ratio4" group.long 0x2E0++0x03 line.long 0x00 "EXT_PHY_CTRL_29,EXT_PHY_CTRL_29" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO7 ,Gate levelling init ratio7" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO6 ,Gate levelling init ratio6" group.long 0x2E4++0x03 line.long 0x00 "EXT_PHY_CTRL_29_SHADOW,EXT_PHY_CTRL_29_SHADOW" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO7 ,Gate levelling init ratio7" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO6 ,Gate levelling init ratio6" group.long 0x2E8++0x03 line.long 0x00 "EXT_PHY_CTRL_30,EXT_PHY_CTRL_30" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO9 ,Gate levelling init ratio9" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO8 ,Gate levelling init ratio8" group.long 0x2EC++0x03 line.long 0x00 "EXT_PHY_CTRL_30_SHADOW,EXT_PHY_CTRL_30_SHADOW" hexmask.long.word 0x00 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO9 ,Gate levelling init ratio9" hexmask.long.word 0x00 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO8 ,Gate levelling init ratio8" group.long 0x2F0++0x03 line.long 0x00 "EXT_PHY_CTRL_31,EXT_PHY_CTRL_31" hexmask.long.byte 0x00 16.--21. 1. " REG_PHY_WRLVL_INIT_RATIO1 ,Write levelling init ratio1" hexmask.long.byte 0x00 0.--5. 1. " REG_PHY_WRLVL_INIT_RATIO0 ,Write levelling init ratio0" group.long 0x2F4++0x03 line.long 0x00 "EXT_PHY_CTRL_31_SHADOW,EXT_PHY_CTRL_31_SHADOW" hexmask.long.word 0x00 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO3 ,Write levelling init ratio3" hexmask.long.word 0x00 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO2 ,Write levelling init ratio2" group.long 0x2F8++0x03 line.long 0x00 "EXT_PHY_CTRL_32,EXT_PHY_CTRL_32" hexmask.long.word 0x00 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO3 ,Write levelling init ratio3" hexmask.long.word 0x00 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO2 ,Write levelling init ratio2" group.long 0x2FC++0x03 line.long 0x00 "EXT_PHY_CTRL_32_SHADOW,EXT_PHY_CTRL_32_SHADOW" hexmask.long.word 0x00 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO3 ,Write levelling init ratio3" hexmask.long.word 0x00 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO2 ,Write levelling init ratio2" group.long 0x300++0x03 line.long 0x00 "EXT_PHY_CTRL_33,EXT_PHY_CTRL_33" hexmask.long.word 0x00 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO5 ,Write levelling init ratio5" hexmask.long.word 0x00 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO4 ,Write levelling init ratio4" group.long 0x304++0x03 line.long 0x00 "EXT_PHY_CTRL_33_SHADOW,EXT_PHY_CTRL_33_SHADOW" hexmask.long.word 0x00 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO5 ,Write levelling init ratio5" hexmask.long.word 0x00 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO4 ,Write levelling init ratio4" group.long 0x308++0x03 line.long 0x00 "EXT_PHY_CTRL_34,EXT_PHY_CTRL_34" hexmask.long.word 0x00 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO7 ,Write levelling init ratio7" hexmask.long.word 0x00 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO6 ,Write levelling init ratio6" group.long 0x30C++0x03 line.long 0x00 "EXT_PHY_CTRL_34_SHADOW,EXT_PHY_CTRL_34_SHADOW" hexmask.long.word 0x00 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO7 ,Write levelling init ratio7" hexmask.long.word 0x00 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO6 ,Write levelling init ratio6" group.long 0x310++0x03 line.long 0x00 "EXT_PHY_CTRL_35,EXT_PHY_CTRL_35" hexmask.long.word 0x00 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO9 ,Write levelling init ratio9" hexmask.long.word 0x00 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO8 ,Write levelling init ratio8" group.long 0x314++0x03 line.long 0x00 "EXT_PHY_CTRL_35_SHADOW,EXT_PHY_CTRL_35_SHADOW" hexmask.long.word 0x00 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO9 ,Write levelling init ratio9" hexmask.long.word 0x00 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO8 ,Write levelling init ratio8" group.long 0x318++0x03 line.long 0x00 "EXT_PHY_CTRL_36,EXT_PHY_CTRL_36" bitfld.long 0x00 10. " REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR ,RDC FIFO Reset Error Count Clear" "Not clear,Clear" bitfld.long 0x00 9. " REG_PHY_MDLL_UNLOCK_CLR ,MDLL Unlock Clear" "Not clear,Clear" textline " " bitfld.long 0x00 8. " REG_PHY_FIFO_WE_IN_MISALIGNED_CLR ,FIFO Write Enable In Misaligned Clear" "Not clear,Clear" bitfld.long 0x00 4.--7. " REG_PHY_WRLVL_NUM_OF_DQ0 ,Write levelling number of DQ0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " REG_PHY_GATELVL_NUM_OF_DQ0 ,Gate levelling number of DQ0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x31C++0x03 line.long 0x00 "EXT_PHY_CTRL_36_SHADOW,EXT_PHY_CTRL_36_SHADOW" bitfld.long 0x00 10. " REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR ,RDC FIFO Reset Error Count Clear" "Not clear,Clear" bitfld.long 0x00 9. " REG_PHY_MDLL_UNLOCK_CLR ,MDLL Unlock Clear" "Not clear,Clear" textline " " bitfld.long 0x00 8. " REG_PHY_FIFO_WE_IN_MISALIGNED_CLR ,FIFO Write Enable In Misaligned Clear" "Not clear,Clear" bitfld.long 0x00 4.--7. " REG_PHY_WRLVL_NUM_OF_DQ0 ,Write levelling number of DQ0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " REG_PHY_GATELVL_NUM_OF_DQ0 ,Gate levelling number of DQ0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end width 11. tree.end tree "ELM" width 17. rgroup.long 0x000++0x03 line.long 0x00 "REVISION,This register contains the IP revision code." group.long 0x010++0x03 line.long 0x00 "SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 8. " CLOCKACTIVITYOCPZ , OCP Clock activity when module is in IDLE mode" "Switch-off,Maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management (IDLE req/ack control)" "FORCE Idle,NO idle,SMART Idle," textline " " bitfld.long 0x00 1. " SOFTRESET ,Module software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOGATING ,nternal OCP clock gating strategy" "Free-running,Gating strategy" rgroup.long 0x014++0x03 line.long 0x00 "SYSSTS," bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Done" group.long 0x018++0x03 line.long 0x00 "IRQSTS,This register doubles as a status register for the error-location processes." bitfld.long 0x00 8. " PAGE_VALID ,Error-location status for a full page" "Invalid,Valid" bitfld.long 0x00 7. " LOC_VALID_7 ,Error-location status for syndrome polynomial 7" "No in progress,Completed" bitfld.long 0x00 6. " LOC_VALID_6 ,Error-location status for syndrome polynomial 6" "No in progress,Completed" bitfld.long 0x00 5. " LOC_VALID_5 ,Error-location status for syndrome polynomial 5" "No in progress,Completed" textline " " bitfld.long 0x00 4. " LOC_VALID_4 ,Error-location status for syndrome polynomial 4" "No in progress,Completed" bitfld.long 0x00 3. " LOC_VALID_3 ,Error-location status for syndrome polynomial 3" "No in progress,Completed" bitfld.long 0x00 2. " LOC_VALID_2 ,Error-location status for syndrome polynomial 2" "No in progress,Completed" bitfld.long 0x00 1. " LOC_VALID_1 ,Error-location status for syndrome polynomial 1" "No in progress,Completed" textline " " bitfld.long 0x00 0. " LOC_VALID_0 ,Error-location status for syndrome polynomial 0" "No in progress,Completed" group.long 0x01C++0x03 line.long 0x00 "IRQEN,IRQEN" bitfld.long 0x00 8. " PAGE_MASK ,Page interrupt mask bit" "Disabled,Enabled" bitfld.long 0x00 7. " LOCATION_MASK_7 ,Error-location interrupt mask bit for syndrome polynomial 7" "Disabled,Enabled" bitfld.long 0x00 6. " LOCATION_MASK_6 ,Error-location interrupt mask bit for syndrome polynomial 6" "Disabled,Enabled" bitfld.long 0x00 5. " LOCATION_MASK_5 ,Error-location interrupt mask bit for syndrome polynomial 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " LOCATION_MASK_4 ,Error-location interrupt mask bit for syndrome polynomial 4" "Disabled,Enabled" bitfld.long 0x00 3. " LOCATION_MASK_3 ,Error-location interrupt mask bit for syndrome polynomial 3" "Disabled,Enabled" bitfld.long 0x00 2. " LOCATION_MASK_2 ,Error-location interrupt mask bit for syndrome polynomial 2" "Disabled,Enabled" bitfld.long 0x00 1. " LOCATION_MASK_1 ,Error-location interrupt mask bit for syndrome polynomial 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " LOCATION_MASK_0 ,Error-location interrupt mask bit for syndrome polynomial 0" "Disabled,Enabled" group.long 0x020++0x03 line.long 0x00 "LOCATION_CONFIG,LOCATION_CONFIG" hexmask.long.word 0x00 16.--26. 1. " ECC_SIZE , Maximum size of the buffers for which the error-location engine is used" bitfld.long 0x00 0.--1. " ECC_BCH_LEVEL ,Error correction level" "4 bits,8 bits,16 bits," group.long 0x080++0x03 line.long 0x00 "PAGE_CTRL,PAGE_CTRL" bitfld.long 0x00 7. " SECTOR_7 ,Syndrome polynomial 7 mode" "Page mode,Continuous mode" bitfld.long 0x00 6. " SECTOR_6 ,Syndrome polynomial 6 mode" "Page mode,Continuous mode" bitfld.long 0x00 5. " SECTOR_5 ,Syndrome polynomial 5 mode" "Page mode,Continuous mode" bitfld.long 0x00 4. " SECTOR_4 ,Syndrome polynomial 4 mode" "Page mode,Continuous mode" textline " " bitfld.long 0x00 3. " SECTOR_3 ,Syndrome polynomial 3 mode" "Page mode,Continuous mode" bitfld.long 0x00 2. " SECTOR_2 ,Syndrome polynomial 2 mode" "Page mode,Continuous mode" bitfld.long 0x00 1. " SECTOR_1 ,Syndrome polynomial 1 mode" "Page mode,Continuous mode" bitfld.long 0x00 0. " SECTOR_0 ,Syndrome polynomial 0 mode" "Page mode,Continuous mode" width 23. tree "SYNDROME 0" group.long 0x400++0x03 line.long 0x00 "SYNDROME_FRAGMENT_0,Syndrome bits 0 to 31" group.long 0x404++0x03 line.long 0x00 "SYNDROME_FRAGMENT_1_0,Syndrome bits 32 to 63" group.long 0x408++0x03 line.long 0x00 "SYNDROME_FRAGMENT_2_0,Syndrome bits 64 to 95" group.long 0x40C++0x03 line.long 0x00 "SYNDROME_FRAGMENT_3_0,Syndrome bits 96 to 127" group.long 0x410++0x03 line.long 0x00 "SYNDROME_FRAGMENT_4_0,Syndrome bits 128 to 159" group.long 0x414++0x03 line.long 0x00 "SYNDROME_FRAGMENT_5_0,Syndrome bits 160 to 191" group.long 0x418++0x03 line.long 0x00 "SYNDROME_FRAGMENT_6_0,Syndrome bits 192 to 207" bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit" "Not valid,Valid" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 , Syndrome bits 192 to 207" tree.end tree "SYNDROME 1" group.long 0x440++0x03 line.long 0x00 "SYNDROME_FRAGMENT_0_1,Syndrome bits 0 to 31" group.long 0x444++0x03 line.long 0x00 "SYNDROME_FRAGMENT_1,Syndrome bits 32 to 63" group.long 0x448++0x03 line.long 0x00 "SYNDROME_FRAGMENT_2_1,Syndrome bits 64 to 95" group.long 0x44C++0x03 line.long 0x00 "SYNDROME_FRAGMENT_3_1,Syndrome bits 96 to 127" group.long 0x450++0x03 line.long 0x00 "SYNDROME_FRAGMENT_4_1,Syndrome bits 128 to 159" group.long 0x454++0x03 line.long 0x00 "SYNDROME_FRAGMENT_5_1,Syndrome bits 160 to 191" group.long 0x458++0x03 line.long 0x00 "SYNDROME_FRAGMENT_6_1,Syndrome bits 192 to 207" bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit" "Not valid,Valid" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" tree.end tree "SYNDROME 2" group.long 0x480++0x03 line.long 0x00 "SYNDROME_FRAGMENT_0_2,Syndrome bits 0 to 31" group.long 0x484++0x03 line.long 0x00 "SYNDROME_FRAGMENT_1_2,Syndrome bits 32 to 63" group.long 0x488++0x03 line.long 0x00 "SYNDROME_FRAGMENT_2,Syndrome bits 64 to 95" group.long 0x48C++0x03 line.long 0x00 "SYNDROME_FRAGMENT_3_2,Syndrome bits 96 to 127" group.long 0x490++0x03 line.long 0x00 "SYNDROME_FRAGMENT_4_2,Syndrome bits 128 to 159" group.long 0x494++0x03 line.long 0x00 "SYNDROME_FRAGMENT_5_2,Syndrome bits 160 to 191" group.long 0x498++0x03 line.long 0x00 "SYNDROME_FRAGMENT_6_2,Syndrome bits 192 to 207" bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit" "Not valid,Valid" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 , Syndrome bits 192 to 207" tree.end tree "SYNDROME 3" group.long 0x4C0++0x03 line.long 0x00 "SYNDROME_FRAGMENT_0_3,Syndrome bits 0 to 31" group.long 0x4C4++0x03 line.long 0x00 "SYNDROME_FRAGMENT_1_3,Syndrome bits 32 to 63" group.long 0x4C8++0x03 line.long 0x00 "SYNDROME_FRAGMENT_2_3,Syndrome bits 64 to 95" group.long 0x4CC++0x03 line.long 0x00 "SYNDROME_FRAGMENT_3,Syndrome bits 96 to 127" group.long 0x4D0++0x03 line.long 0x00 "SYNDROME_FRAGMENT_4_3,Syndrome bits 128 to 159" group.long 0x4D4++0x03 line.long 0x00 "SYNDROME_FRAGMENT_5_3,Syndrome bits 160 to 191" group.long 0x4D8++0x03 line.long 0x00 "SYNDROME_FRAGMENT_6_3," bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit" "Not valid,Valid" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 , Syndrome bits 192 to 207" tree.end tree "SYNDROME 4" group.long 0x500++0x03 line.long 0x00 "SYNDROME_FRAGMENT_0_4,Syndrome bits 0 to 31" group.long 0x504++0x03 line.long 0x00 "SYNDROME_FRAGMENT_1_4,Syndrome bits 32 to 63" group.long 0x508++0x03 line.long 0x00 "SYNDROME_FRAGMENT_2_4,Syndrome bits 64 to 95" group.long 0x50C++0x03 line.long 0x00 "SYNDROME_FRAGMENT_3_4,Syndrome bits 96 to 127" group.long 0x510++0x03 line.long 0x00 "SYNDROME_FRAGMENT_4,Syndrome bits 128 to 159" group.long 0x514++0x03 line.long 0x00 "SYNDROME_FRAGMENT_5_4,Syndrome bits 160 to 191" group.long 0x518++0x03 line.long 0x00 "SYNDROME_FRAGMENT_6_4,Syndrome bits 192 to 207" bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit" "Not valid,Valid" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 , Syndrome bits 192 to 207" tree.end tree "SYNDROME 5" group.long 0x540++0x03 line.long 0x00 "SYNDROME_FRAGMENT_0_5,Syndrome bits 0 to 31" group.long 0x544++0x03 line.long 0x00 "SYNDROME_FRAGMENT_1_5,Syndrome bits 32 to 63" group.long 0x548++0x03 line.long 0x00 "SYNDROME_FRAGMENT_2_5,Syndrome bits 64 to 95" group.long 0x54C++0x03 line.long 0x00 "SYNDROME_FRAGMENT_3_5,Syndrome bits 96 to 127" group.long 0x550++0x03 line.long 0x00 "SYNDROME_FRAGMENT_4_5,Syndrome bits 128 to 159" group.long 0x554++0x03 line.long 0x00 "SYNDROME_FRAGMENT_5,Syndrome bits 160 to 191" group.long 0x558++0x03 line.long 0x00 "SYNDROME_FRAGMENT_6_5," bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit" "Not valid,Valid" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 , Syndrome bits 192 to 207, value 0 to FFFFh." tree.end tree "SYNDROME 6" group.long 0x580++0x03 line.long 0x00 "SYNDROME_FRAGMENT_0_6,Syndrome bits 0 to 31" group.long 0x584++0x03 line.long 0x00 "SYNDROME_FRAGMENT_1_6,Syndrome bits 32 to 63" group.long 0x588++0x03 line.long 0x00 "SYNDROME_FRAGMENT_2_6,Syndrome bits 64 to 95" group.long 0x58C++0x03 line.long 0x00 "SYNDROME_FRAGMENT_3_6,Syndrome bits 96 to 127" group.long 0x590++0x03 line.long 0x00 "SYNDROME_FRAGMENT_4_6,Syndrome bits 128 to 159" group.long 0x594++0x03 line.long 0x00 "SYNDROME_FRAGMENT_5_6,Syndrome bits 160 to 191" group.long 0x598++0x03 line.long 0x00 "SYNDROME_FRAGMENT_6,Syndrome bits 192 to 207" bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit" "Not valid,Valid" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 , Syndrome bits 192 to 207" tree.end tree "SYNDROME 7" group.long 0x5C0++0x03 line.long 0x00 "SYNDROME_FRAGMENT_0_7,Syndrome bits 0 to 31" group.long 0x5C4++0x03 line.long 0x00 "SYNDROME_FRAGMENT_1_7,Syndrome bits 32 to 63" group.long 0x5C8++0x03 line.long 0x00 "SYNDROME_FRAGMENT_2_7,Syndrome bits 64 to 95" group.long 0x5CC++0x03 line.long 0x00 "SYNDROME_FRAGMENT_3_7,Syndrome bits 96 to 127" group.long 0x5D0++0x03 line.long 0x00 "SYNDROME_FRAGMENT_4_7,Syndrome bits 128 to 159" group.long 0x5D4++0x03 line.long 0x00 "SYNDROME_FRAGMENT_5_7,Syndrome bits 160 to 191" group.long 0x5D8++0x03 line.long 0x00 "SYNDROME_FRAGMENT_6_7,Syndrome bits 192 to 207" bitfld.long 0x00 16. " SYNDROME_VALID ,Syndrome valid bit" "Not valid,Valid" hexmask.long.word 0x00 0.--15. 1. " SYNDROME_6 , Syndrome bits 192 to 207" tree.end width 21. tree "LOCATION 0" rgroup.long 0x800++0x03 line.long 0x00 "LOCATION_STS_0,LOCATION_STS_0" bitfld.long 0x00 8. " ECC_CORRECTABL ,Error-location process exit status" "Failed,Located" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS , Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x880++0x03 line.long 0x00 "ERROR_LOCATION_0,ERROR_LOCATION_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x884++0x03 line.long 0x00 "ERROR_LOCATION_1_0,ERROR_LOCATION_1_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x888++0x03 line.long 0x00 "ERROR_LOCATION_2_0,ERROR_LOCATION_2_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x88C++0x03 line.long 0x00 "ERROR_LOCATION_3_0,ERROR_LOCATION_3_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x890++0x03 line.long 0x00 "ERROR_LOCATION_4_0,ERROR_LOCATION_4_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x894++0x03 line.long 0x00 "ERROR_LOCATION_5_0,ERROR_LOCATION_5_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x898++0x03 line.long 0x00 "ERROR_LOCATION_6_0,ERROR_LOCATION_6_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x89C++0x03 line.long 0x00 "ERROR_LOCATION_7_0,ERROR_LOCATION_7_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x8A0++0x03 line.long 0x00 "ERROR_LOCATION_8_0,ERROR_LOCATION_8_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x8A4++0x03 line.long 0x00 "ERROR_LOCATION_9_0,ERROR_LOCATION_9_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x8A8++0x03 line.long 0x00 "ERROR_LOCATION_10_0,ERROR_LOCATION_10_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x8AC++0x03 line.long 0x00 "ERROR_LOCATION_11_0,ERROR_LOCATION_11_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x8B0++0x03 line.long 0x00 "ERROR_LOCATION_12_0,ERROR_LOCATION_12_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x8B4++0x03 line.long 0x00 "ERROR_LOCATION_13_0,ERROR_LOCATION_13_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x8B8++0x03 line.long 0x00 "ERROR_LOCATION_14_0,ERROR_LOCATION_14_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x8BC++0x03 line.long 0x00 "ERROR_LOCATION_15_0,ERROR_LOCATION_15_0" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" tree.end tree "LOCATION 1" rgroup.long 0x900++0x03 line.long 0x00 "LOCATION_STS_1,LOCATION_STS_1" bitfld.long 0x00 8. " ECC_CORRECTABL ,Error-location process exit status" "Failed,Located" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS , Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x980++0x03 line.long 0x00 "ERROR_LOCATION_0_1,ERROR_LOCATION_0_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x984++0x03 line.long 0x00 "ERROR_LOCATION_1,ERROR_LOCATION_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x988++0x03 line.long 0x00 "ERROR_LOCATION_2_1,ERROR_LOCATION_2_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x98C++0x03 line.long 0x00 "ERROR_LOCATION_3_1,ERROR_LOCATION_3_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x990++0x03 line.long 0x00 "ERROR_LOCATION_4_1,ERROR_LOCATION_4_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x994++0x03 line.long 0x00 "ERROR_LOCATION_5_1,ERROR_LOCATION_5_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x998++0x03 line.long 0x00 "ERROR_LOCATION_6_1,ERROR_LOCATION_6_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x99C++0x03 line.long 0x00 "ERROR_LOCATION_7_1,ERROR_LOCATION_7_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x9A0++0x03 line.long 0x00 "ERROR_LOCATION_8_1,ERROR_LOCATION_8_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x9A4++0x03 line.long 0x00 "ERROR_LOCATION_9_1,ERROR_LOCATION_9_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x9A8++0x03 line.long 0x00 "ERROR_LOCATION_10_1,ERROR_LOCATION_10_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x9AC++0x03 line.long 0x00 "ERROR_LOCATION_11_1,ERROR_LOCATION_11_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x9B0++0x03 line.long 0x00 "ERROR_LOCATION_12_1,ERROR_LOCATION_12_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x9B4++0x03 line.long 0x00 "ERROR_LOCATION_13_1,ERROR_LOCATION_13_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x9B8++0x03 line.long 0x00 "ERROR_LOCATION_14_1,ERROR_LOCATION_14_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0x9BC++0x03 line.long 0x00 "ERROR_LOCATION_15_1,ERROR_LOCATION_15_1" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" tree.end tree "LOCATION 2" rgroup.long 0xA00++0x03 line.long 0x00 "LOCATION_STS_2,LOCATION_STS_2" bitfld.long 0x00 8. " ECC_CORRECTABL ,Error-location process exit status" "Failed,Located" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS , Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA80++0x03 line.long 0x00 "ERROR_LOCATION_0_2,ERROR_LOCATION_0_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xA84++0x03 line.long 0x00 "ERROR_LOCATION_1_2,ERROR_LOCATION_1_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xA88++0x03 line.long 0x00 "ERROR_LOCATION_2,ERROR_LOCATION_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xA8C++0x03 line.long 0x00 "ERROR_LOCATION_3_2,ERROR_LOCATION_3_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xA90++0x03 line.long 0x00 "ERROR_LOCATION_4_2,ERROR_LOCATION_4_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xA94++0x03 line.long 0x00 "ERROR_LOCATION_5_2,ERROR_LOCATION_5_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xA98++0x03 line.long 0x00 "ERROR_LOCATION_6_2,ERROR_LOCATION_6_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xA9C++0x03 line.long 0x00 "ERROR_LOCATION_7_2,ERROR_LOCATION_7_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xAA0++0x03 line.long 0x00 "ERROR_LOCATION_8_2,ERROR_LOCATION_8_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xAA4++0x03 line.long 0x00 "ERROR_LOCATION_9_2,ERROR_LOCATION_9_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xAA8++0x03 line.long 0x00 "ERROR_LOCATION_10_2,ERROR_LOCATION_10_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xAAC++0x03 line.long 0x00 "ERROR_LOCATION_11_2,ERROR_LOCATION_11_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xAB0++0x03 line.long 0x00 "ERROR_LOCATION_12_2,ERROR_LOCATION_12_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xAB4++0x03 line.long 0x00 "ERROR_LOCATION_13_2,ERROR_LOCATION_13_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xAB8++0x03 line.long 0x00 "ERROR_LOCATION_14_2,ERROR_LOCATION_14_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xABC++0x03 line.long 0x00 "ERROR_LOCATION_15_2,ERROR_LOCATION_15_2" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" tree.end tree "LOCATION 3" rgroup.long 0xC00++0x03 line.long 0x00 "LOCATION_STS_3,LOCATION_STS_3" bitfld.long 0x00 8. " ECC_CORRECTABL ,Error-location process exit status" "Failed,Located" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS , Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xB80++0x03 line.long 0x00 "ERROR_LOCATION_0_3,ERROR_LOCATION_0_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xB84++0x03 line.long 0x00 "ERROR_LOCATION_1_3,ERROR_LOCATION_1_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xB88++0x03 line.long 0x00 "ERROR_LOCATION_2_3,ERROR_LOCATION_2_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xB8C++0x03 line.long 0x00 "ERROR_LOCATION_3,ERROR_LOCATION_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xB90++0x03 line.long 0x00 "ERROR_LOCATION_4_3,ERROR_LOCATION_4_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xB94++0x03 line.long 0x00 "ERROR_LOCATION_5_3,ERROR_LOCATION_5_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xB98++0x03 line.long 0x00 "ERROR_LOCATION_6_3,ERROR_LOCATION_6_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xB9C++0x03 line.long 0x00 "ERROR_LOCATION_7_3,ERROR_LOCATION_7_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xBA0++0x03 line.long 0x00 "ERROR_LOCATION_8_3,ERROR_LOCATION_8_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xBA4++0x03 line.long 0x00 "ERROR_LOCATION_9_3,ERROR_LOCATION_9_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xBA8++0x03 line.long 0x00 "ERROR_LOCATION_10_3,ERROR_LOCATION_10_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xBAC++0x03 line.long 0x00 "ERROR_LOCATION_11_3,ERROR_LOCATION_11_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xBB0++0x03 line.long 0x00 "ERROR_LOCATION_12_3,ERROR_LOCATION_12_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xBB4++0x03 line.long 0x00 "ERROR_LOCATION_13_3,ERROR_LOCATION_13_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xBB8++0x03 line.long 0x00 "ERROR_LOCATION_14_3,ERROR_LOCATION_14_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xBBC++0x03 line.long 0x00 "ERROR_LOCATION_15_3,ERROR_LOCATION_15_3" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" tree.end tree "LOCATION 4" rgroup.long 0xE00++0x03 line.long 0x00 "LOCATION_STS_4,LOCATION_STS_4" bitfld.long 0x00 8. " ECC_CORRECTABL ,Error-location process exit status" "Failed,Located" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS , Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xC80++0x03 line.long 0x00 "ERROR_LOCATION_0_4,ERROR_LOCATION_0_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xC84++0x03 line.long 0x00 "ERROR_LOCATION_1_4,ERROR_LOCATION_1_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xC88++0x03 line.long 0x00 "ERROR_LOCATION_2_4,ERROR_LOCATION_2_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xC8C++0x03 line.long 0x00 "ERROR_LOCATION_3_4,ERROR_LOCATION_3_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xC90++0x03 line.long 0x00 "ERROR_LOCATION_4,ERROR_LOCATION_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xC94++0x03 line.long 0x00 "ERROR_LOCATION_5_4,ERROR_LOCATION_5_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xC98++0x03 line.long 0x00 "ERROR_LOCATION_6_4,ERROR_LOCATION_6_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xC9C++0x03 line.long 0x00 "ERROR_LOCATION_7_4,ERROR_LOCATION_7_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xCA0++0x03 line.long 0x00 "ERROR_LOCATION_8_4,ERROR_LOCATION_8_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xCA4++0x03 line.long 0x00 "ERROR_LOCATION_9_4,ERROR_LOCATION_9_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xCA8++0x03 line.long 0x00 "ERROR_LOCATION_10_4,ERROR_LOCATION_10_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xCAC++0x03 line.long 0x00 "ERROR_LOCATION_11_4,ERROR_LOCATION_11_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xCB0++0x03 line.long 0x00 "ERROR_LOCATION_12_4,ERROR_LOCATION_12_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xCB4++0x03 line.long 0x00 "ERROR_LOCATION_13_4,ERROR_LOCATION_13_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xCB8++0x03 line.long 0x00 "ERROR_LOCATION_14_4,ERROR_LOCATION_14_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xCBC++0x03 line.long 0x00 "ERROR_LOCATION_15_4,ERROR_LOCATION_15_4" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" tree.end tree "LOCATION 5" rgroup.long 0x1000++0x03 line.long 0x00 "LOCATION_STS_5,LOCATION_STS_5" bitfld.long 0x00 8. " ECC_CORRECTABL ,Error-location process exit status" "Failed,Located" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS , Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xD80++0x03 line.long 0x00 "ERROR_LOCATION_0_5,ERROR_LOCATION_0_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xD84++0x03 line.long 0x00 "ERROR_LOCATION_1_5,ERROR_LOCATION_1_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xD88++0x03 line.long 0x00 "ERROR_LOCATION_2_5,ERROR_LOCATION_2_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xD8C++0x03 line.long 0x00 "ERROR_LOCATION_3_5,ERROR_LOCATION_3_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xD90++0x03 line.long 0x00 "ERROR_LOCATION_4_5,ERROR_LOCATION_4_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xD94++0x03 line.long 0x00 "ERROR_LOCATION_5,ERROR_LOCATION_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xD98++0x03 line.long 0x00 "ERROR_LOCATION_6_5,ERROR_LOCATION_6_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xD9C++0x03 line.long 0x00 "ERROR_LOCATION_7_5,ERROR_LOCATION_7_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xDA0++0x03 line.long 0x00 "ERROR_LOCATION_8_5,ERROR_LOCATION_8_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xDA4++0x03 line.long 0x00 "ERROR_LOCATION_9_5,ERROR_LOCATION_9_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xDA8++0x03 line.long 0x00 "ERROR_LOCATION_10_5,ERROR_LOCATION_10_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xDAC++0x03 line.long 0x00 "ERROR_LOCATION_11_5,ERROR_LOCATION_11_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xDB0++0x03 line.long 0x00 "ERROR_LOCATION_12_5,ERROR_LOCATION_12_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xDB4++0x03 line.long 0x00 "ERROR_LOCATION_13_5,ERROR_LOCATION_13_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xDB8++0x03 line.long 0x00 "ERROR_LOCATION_14_5,ERROR_LOCATION_14_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xDBC++0x03 line.long 0x00 "ERROR_LOCATION_15_5,ERROR_LOCATION_15_5" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" tree.end tree "LOCATION 6" rgroup.long 0x1200++0x03 line.long 0x00 "LOCATION_STS_6,LOCATION_STS_6" bitfld.long 0x00 8. " ECC_CORRECTABL ,Error-location process exit status" "Failed,Located" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS , Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xE80++0x03 line.long 0x00 "ERROR_LOCATION_0_6,ERROR_LOCATION_0_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xE84++0x03 line.long 0x00 "ERROR_LOCATION_1_6,ERROR_LOCATION_1_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xE88++0x03 line.long 0x00 "ERROR_LOCATION_2_6,ERROR_LOCATION_2_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xE8C++0x03 line.long 0x00 "ERROR_LOCATION_3_6,ERROR_LOCATION_3_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xE90++0x03 line.long 0x00 "ERROR_LOCATION_4_6,ERROR_LOCATION_4_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xE94++0x03 line.long 0x00 "ERROR_LOCATION_5_6,ERROR_LOCATION_5_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xE98++0x03 line.long 0x00 "ERROR_LOCATION_6,ERROR_LOCATION_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xE9C++0x03 line.long 0x00 "ERROR_LOCATION_7_6,ERROR_LOCATION_7_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xEA0++0x03 line.long 0x00 "ERROR_LOCATION_8_6,ERROR_LOCATION_8_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xEA4++0x03 line.long 0x00 "ERROR_LOCATION_9_6,ERROR_LOCATION_9_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xEA8++0x03 line.long 0x00 "ERROR_LOCATION_10_6,ERROR_LOCATION_10_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xEAC++0x03 line.long 0x00 "ERROR_LOCATION_11_6,ERROR_LOCATION_11_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xEB0++0x03 line.long 0x00 "ERROR_LOCATION_12_6,ERROR_LOCATION_12_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xEB4++0x03 line.long 0x00 "ERROR_LOCATION_13_6,ERROR_LOCATION_13_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xEB8++0x03 line.long 0x00 "ERROR_LOCATION_14_6,ERROR_LOCATION_14_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xEBC++0x03 line.long 0x00 "ERROR_LOCATION_15_6,ERROR_LOCATION_15_6" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" tree.end tree "LOCATION 7" rgroup.long 0x1400++0x03 line.long 0x00 "LOCATION_STS_7,LOCATION_STS_7" bitfld.long 0x00 8. " ECC_CORRECTABL ,Error-location process exit status" "Failed,Located" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS , Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xF80++0x03 line.long 0x00 "ERROR_LOCATION_0_7,ERROR_LOCATION_0_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xF84++0x03 line.long 0x00 "ERROR_LOCATION_1_7,ERROR_LOCATION_1_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xF88++0x03 line.long 0x00 "ERROR_LOCATION_2_7,ERROR_LOCATION_2_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xF8C++0x03 line.long 0x00 "ERROR_LOCATION_3_7,ERROR_LOCATION_3_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xF90++0x03 line.long 0x00 "ERROR_LOCATION_4_7,ERROR_LOCATION_4_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xF94++0x03 line.long 0x00 "ERROR_LOCATION_5_7,ERROR_LOCATION_5_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xF98++0x03 line.long 0x00 "ERROR_LOCATION_6_7,ERROR_LOCATION_6_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xF9C++0x03 line.long 0x00 "ERROR_LOCATION_7,ERROR_LOCATION_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xFA0++0x03 line.long 0x00 "ERROR_LOCATION_8_7,ERROR_LOCATION_8_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xFA4++0x03 line.long 0x00 "ERROR_LOCATION_9_7,ERROR_LOCATION_9_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xFA8++0x03 line.long 0x00 "ERROR_LOCATION_10_7,ERROR_LOCATION_10_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xFAC++0x03 line.long 0x00 "ERROR_LOCATION_11_7,ERROR_LOCATION_11_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xFB0++0x03 line.long 0x00 "ERROR_LOCATION_12_7,ERROR_LOCATION_12_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xFB4++0x03 line.long 0x00 "ERROR_LOCATION_13_7,ERROR_LOCATION_13_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xFB8++0x03 line.long 0x00 "ERROR_LOCATION_14_7,ERROR_LOCATION_14_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" rgroup.long 0xFBC++0x03 line.long 0x00 "ERROR_LOCATION_15_7,ERROR_LOCATION_15_7" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION , Error-location bit address" tree.end tree.end tree.end tree "EDMA(Enhanced Direct Memory Access)" tree "EDMA3CC" base ad:0x49000000 width 11. rgroup.long 0x00++0x01 line.word 0x00 "PID,The peripheral identification register" hexmask.word 0x00 0.--15. 1. " PID ,Peripheral identifier uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC" rgroup.long 0x04++0x03 line.long 0x00 "CCCFG,The EDMA3CC configuration register" bitfld.long 0x00 25. " MP_EXIST ,Memory protection existence" "Not included,Included" bitfld.long 0x00 24. " CHMAP_EXIST ,Channel mapping existence" "Not included,Included" bitfld.long 0x00 20.--21. " NUM_REGN ,Number of MP and shadow regions" ",,4," bitfld.long 0x00 16.--18. " NUM_EVQUE ,umber of queues/number of TCs" ",,3,,,,," textline " " bitfld.long 0x00 12.--14. " NUM_PAENTRY ,Number of PaRAM sets" ",,,,256,,," bitfld.long 0x00 8.--10. " NUM_INTCH ,Number of interrupt channels" ",,,,64,,," bitfld.long 0x00 4.--6. " NUM_QDMACH ,Number of QDMA channels" ",,,,8,,," bitfld.long 0x00 0.--2. " NUM_DMACH ,Number of DMA channels" ",,,,,64,," group.long 0x10++0x03 line.long 0x00 "SYSCONFIG,The EDMA3CC system configuration register" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" width 12. tree "DCHMAP - array[64]" group.long 0x0100++0x03 line.long 0x00 "DCHMAP[0],DCHMAP[0]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 0" group.long 0x0104++0x03 line.long 0x00 "DCHMAP[1],DCHMAP[1]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 1" group.long 0x0108++0x03 line.long 0x00 "DCHMAP[2],DCHMAP[2]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 2" group.long 0x010C++0x03 line.long 0x00 "DCHMAP[3],DCHMAP[3]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 3" group.long 0x0110++0x03 line.long 0x00 "DCHMAP[4],DCHMAP[4]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 4" group.long 0x0114++0x03 line.long 0x00 "DCHMAP[5],DCHMAP[5]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 5" group.long 0x0118++0x03 line.long 0x00 "DCHMAP[6],DCHMAP[6]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 6" group.long 0x011C++0x03 line.long 0x00 "DCHMAP[7],DCHMAP[7]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 7" group.long 0x0120++0x03 line.long 0x00 "DCHMAP[8],DCHMAP[8]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 8" group.long 0x0124++0x03 line.long 0x00 "DCHMAP[9],DCHMAP[9]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 9" group.long 0x0128++0x03 line.long 0x00 "DCHMAP[10],DCHMAP[10]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 10" group.long 0x012C++0x03 line.long 0x00 "DCHMAP[11],DCHMAP[11]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 11" group.long 0x0130++0x03 line.long 0x00 "DCHMAP[12],DCHMAP[12]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 12" group.long 0x0134++0x03 line.long 0x00 "DCHMAP[13],DCHMAP[13]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 13" group.long 0x0138++0x03 line.long 0x00 "DCHMAP[14],DCHMAP[14]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 14" group.long 0x013C++0x03 line.long 0x00 "DCHMAP[15],DCHMAP[15]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 15" group.long 0x0140++0x03 line.long 0x00 "DCHMAP[16],DCHMAP[16]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 16" group.long 0x0144++0x03 line.long 0x00 "DCHMAP[17],DCHMAP[17]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 17" group.long 0x0148++0x03 line.long 0x00 "DCHMAP[18],DCHMAP[18]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 18" group.long 0x014C++0x03 line.long 0x00 "DCHMAP[19],DCHMAP[19]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 19" group.long 0x0150++0x03 line.long 0x00 "DCHMAP[20],DCHMAP[20]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 20" group.long 0x0154++0x03 line.long 0x00 "DCHMAP[21],DCHMAP[21]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 21" group.long 0x0158++0x03 line.long 0x00 "DCHMAP[22],DCHMAP[22]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 22" group.long 0x015C++0x03 line.long 0x00 "DCHMAP[23],DCHMAP[23]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 23" group.long 0x0160++0x03 line.long 0x00 "DCHMAP[24],DCHMAP[24]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 24" group.long 0x0164++0x03 line.long 0x00 "DCHMAP[25],DCHMAP[25]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 25" group.long 0x0168++0x03 line.long 0x00 "DCHMAP[26],DCHMAP[26]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 26" group.long 0x016C++0x03 line.long 0x00 "DCHMAP[27],DCHMAP[27]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 27" group.long 0x0170++0x03 line.long 0x00 "DCHMAP[28],DCHMAP[28]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 28" group.long 0x0174++0x03 line.long 0x00 "DCHMAP[29],DCHMAP[29]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 29" group.long 0x0178++0x03 line.long 0x00 "DCHMAP[30],DCHMAP[30]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 30" group.long 0x017C++0x03 line.long 0x00 "DCHMAP[31],DCHMAP[31]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 31" group.long 0x0180++0x03 line.long 0x00 "DCHMAP[32],DCHMAP[32]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 32" group.long 0x0184++0x03 line.long 0x00 "DCHMAP[33],DCHMAP[33]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 33" group.long 0x0188++0x03 line.long 0x00 "DCHMAP[34],DCHMAP[34]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 34" group.long 0x018C++0x03 line.long 0x00 "DCHMAP[35],DCHMAP[35]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 35" group.long 0x0190++0x03 line.long 0x00 "DCHMAP[36],DCHMAP[36]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 36" group.long 0x0194++0x03 line.long 0x00 "DCHMAP[37],DCHMAP[37]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 37" group.long 0x0198++0x03 line.long 0x00 "DCHMAP[38],DCHMAP[38]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 38" group.long 0x019C++0x03 line.long 0x00 "DCHMAP[39],DCHMAP[39]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 39" group.long 0x01A0++0x03 line.long 0x00 "DCHMAP[40],DCHMAP[40]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 40" group.long 0x01A4++0x03 line.long 0x00 "DCHMAP[41],DCHMAP[41]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 41" group.long 0x01A8++0x03 line.long 0x00 "DCHMAP[42],DCHMAP[42]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 42" group.long 0x01AC++0x03 line.long 0x00 "DCHMAP[43],DCHMAP[43]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 43" group.long 0x01B0++0x03 line.long 0x00 "DCHMAP[44],DCHMAP[44]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 44" group.long 0x01B4++0x03 line.long 0x00 "DCHMAP[45],DCHMAP[45]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 45" group.long 0x01B8++0x03 line.long 0x00 "DCHMAP[46],DCHMAP[46]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 46" group.long 0x01BC++0x03 line.long 0x00 "DCHMAP[47],DCHMAP[47]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 47" group.long 0x01C0++0x03 line.long 0x00 "DCHMAP[48],DCHMAP[48]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 48" group.long 0x01C4++0x03 line.long 0x00 "DCHMAP[49],DCHMAP[49]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 49" group.long 0x01C8++0x03 line.long 0x00 "DCHMAP[50],DCHMAP[50]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 50" group.long 0x01CC++0x03 line.long 0x00 "DCHMAP[51],DCHMAP[51]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 51" group.long 0x01D0++0x03 line.long 0x00 "DCHMAP[52],DCHMAP[52]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 52" group.long 0x01D4++0x03 line.long 0x00 "DCHMAP[53],DCHMAP[53]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 53" group.long 0x01D8++0x03 line.long 0x00 "DCHMAP[54],DCHMAP[54]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 54" group.long 0x01DC++0x03 line.long 0x00 "DCHMAP[55],DCHMAP[55]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 55" group.long 0x01E0++0x03 line.long 0x00 "DCHMAP[56],DCHMAP[56]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 56" group.long 0x01E4++0x03 line.long 0x00 "DCHMAP[57],DCHMAP[57]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 57" group.long 0x01E8++0x03 line.long 0x00 "DCHMAP[58],DCHMAP[58]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 58" group.long 0x01EC++0x03 line.long 0x00 "DCHMAP[59],DCHMAP[59]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 59" group.long 0x01F0++0x03 line.long 0x00 "DCHMAP[60],DCHMAP[60]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 60" group.long 0x01F4++0x03 line.long 0x00 "DCHMAP[61],DCHMAP[61]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 60" group.long 0x01F8++0x03 line.long 0x00 "DCHMAP[62],DCHMAP[62]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 62" group.long 0x01FC++0x03 line.long 0x00 "DCHMAP[63],DCHMAP[63]" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 63" tree.end width 11. tree "QCHMAP - array[8]" group.long 0x0200++0x03 line.long 0x00 "QCHMAP[0],QDMA Channel Mapping Registers 0" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel" bitfld.long 0x00 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x0204++0x03 line.long 0x00 "QCHMAP[1],QDMA Channel Mapping Registers 1" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel" bitfld.long 0x00 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x0208++0x03 line.long 0x00 "QCHMAP[2],QDMA Channel Mapping Registers 2" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel" bitfld.long 0x00 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x020C++0x03 line.long 0x00 "QCHMAP[3],QDMA Channel Mapping Registers 3" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel" bitfld.long 0x00 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x0210++0x03 line.long 0x00 "QCHMAP[4],QDMA Channel Mapping Registers 4" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel" bitfld.long 0x00 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x0214++0x03 line.long 0x00 "QCHMAP[5],QDMA Channel Mapping Registers 5" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel" bitfld.long 0x00 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x0218++0x03 line.long 0x00 "QCHMAP[6],QDMA Channel Mapping Registers 6" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel" bitfld.long 0x00 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7" group.long 0x021C++0x03 line.long 0x00 "QCHMAP[7],QDMA Channel Mapping Registers 7" hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel" bitfld.long 0x00 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7" tree.end width 12. tree "DMAQNUM - array[8]" group.long 0x0240++0x03 line.long 0x00 "DMAQNUM[0],DMA Queue Number Register 0" bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,Q2,,,,," textline " " bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,Q2,,,,," group.long 0x0244++0x03 line.long 0x00 "DMAQNUM[1],DMA Queue Number Registers 1" bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,Q2,,,,," textline " " bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,Q2,,,,," group.long 0x0248++0x03 line.long 0x00 "DMAQNUM[2],DMA Queue Number Registers 2" bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,Q2,,,,," textline " " bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,Q2,,,,," group.long 0x024C++0x03 line.long 0x00 "DMAQNUM[3],DMA Queue Number Registers 3" bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,Q2,,,,," textline " " bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,Q2,,,,," group.long 0x0250++0x03 line.long 0x00 "DMAQNUM[4],DMA Queue Number Registers 4" bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,Q2,,,,," textline " " bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,Q2,,,,," group.long 0x0254++0x03 line.long 0x00 "DMAQNUM[5],DMA Queue Number Registers 5" bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,Q2,,,,," textline " " bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,Q2,,,,," group.long 0x0258++0x03 line.long 0x00 "DMAQNUM[6],DMA Queue Number Registers 6" bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,Q2,,,,," textline " " bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,Q2,,,,," group.long 0x025C++0x03 line.long 0x00 "DMAQNUM[7],DMA Queue Number Registers 7" bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,Q2,,,,," textline " " bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,Q2,,,,," tree.end textline " " width 10. group.long 0x0260++0x03 line.long 0x00 "QDMAQNUM,QDMA Queue Number Register" bitfld.long 0x00 28.--30. " E7 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 24.--26. " E6 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 20.--22. " E5 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 16.--18. " E4 ,DMA queue number" "Q0,Q1,Q2,,,,," textline " " bitfld.long 0x00 12.--14. " E3 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 8.--10. " E2 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 4.--6. " E1 ,DMA queue number" "Q0,Q1,Q2,,,,," bitfld.long 0x00 0.--2. " E0 ,DMA queue number" "Q0,Q1,Q2,,,,," group.long 0x0284++0x03 line.long 0x00 "QUEPRI,Queue Priority Register" bitfld.long 0x00 8.--10. " PRIQ2 ,Priority level for queue 2" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 4.--6. " PRIQ1 ,Priority level for queue 1" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 0.--2. " PRIQ0 ,Priority level for queue 0" "Highest,1,2,3,4,5,6,Lowest" rgroup.long 0x0300++0x03 line.long 0x00 "EMR,Event Missed Register" bitfld.long 0x00 31. " En_31 ,Channel 31 event missed" "No missed,Missed" bitfld.long 0x00 30. " En_30 ,Channel 30 event missed" "No missed,Missed" bitfld.long 0x00 29. " En_29 ,Channel 29 event missed" "No missed,Missed" bitfld.long 0x00 28. " En_28 ,Channel 28 event missed" "No missed,Missed" textline " " bitfld.long 0x00 27. " En_27 ,Channel 27 event missed" "No missed,Missed" bitfld.long 0x00 26. " En_26 ,Channel 26 event missed" "No missed,Missed" bitfld.long 0x00 25. " En_25 ,Channel 25 event missed" "No missed,Missed" bitfld.long 0x00 24. " En_24 ,Channel 24 event missed" "No missed,Missed" textline " " bitfld.long 0x00 23. " En_23 ,Channel 23 event missed" "No missed,Missed" bitfld.long 0x00 22. " En_22 ,Channel 22 event missed" "No missed,Missed" bitfld.long 0x00 21. " En_21 ,Channel 21 event missed" "No missed,Missed" bitfld.long 0x00 20. " En_20 ,Channel 20 event missed" "No missed,Missed" textline " " bitfld.long 0x00 19. " En_19 ,Channel 19 event missed" "No missed,Missed" bitfld.long 0x00 18. " En_18 ,Channel 18 event missed" "No missed,Missed" bitfld.long 0x00 17. " En_17 ,Channel 17 event missed" "No missed,Missed" bitfld.long 0x00 16. " En_16 ,Channel 16 event missed" "No missed,Missed" textline " " bitfld.long 0x00 15. " En_15 ,Channel 15 event missed" "No missed,Missed" bitfld.long 0x00 14. " En_14 ,Channel 14 event missed" "No missed,Missed" bitfld.long 0x00 13. " En_13 ,Channel 13 event missed" "No missed,Missed" bitfld.long 0x00 12. " En_12 ,Channel 12 event missed" "No missed,Missed" textline " " bitfld.long 0x00 11. " En_11 ,Channel 11 event missed" "No missed,Missed" bitfld.long 0x00 10. " En_10 ,Channel 10 event missed" "No missed,Missed" bitfld.long 0x00 9. " En_9 ,Channel 9 event missed" "No missed,Missed" bitfld.long 0x00 8. " En_8 ,Channel 8 event missed" "No missed,Missed" textline " " bitfld.long 0x00 7. " En_7 ,Channel 7 event missed" "No missed,Missed" bitfld.long 0x00 6. " En_6 ,Channel 6 event missed" "No missed,Missed" bitfld.long 0x00 5. " En_5 ,Channel 5 event missed" "No missed,Missed" bitfld.long 0x00 4. " En_4 ,Channel 4 event missed" "No missed,Missed" textline " " bitfld.long 0x00 3. " En_3 ,Channel 3 event missed" "No missed,Missed" bitfld.long 0x00 2. " En_2 ,Channel 2 event missed" "No missed,Missed" bitfld.long 0x00 1. " En_1 ,Channel 1 event missed" "No missed,Missed" bitfld.long 0x00 0. " En_0 ,Channel 0 event missed" "No missed,Missed" rgroup.long 0x0304++0x03 line.long 0x00 "EMRH,Event Missed Register High" bitfld.long 0x00 31. " En_63 ,Channel 63 event missed" "No missed,Missed" bitfld.long 0x00 30. " En_62 ,Channel 62 event missed" "No missed,Missed" bitfld.long 0x00 29. " En_61 ,Channel 61 event missed" "No missed,Missed" bitfld.long 0x00 28. " En_60 ,Channel 60 event missed" "No missed,Missed" textline " " bitfld.long 0x00 27. " En_59 ,Channel 59 event missed" "No missed,Missed" bitfld.long 0x00 26. " En_58 ,Channel 58 event missed" "No missed,Missed" bitfld.long 0x00 25. " En_57 ,Channel 57 event missed" "No missed,Missed" bitfld.long 0x00 24. " En_56 ,Channel 56 event missed" "No missed,Missed" textline " " bitfld.long 0x00 23. " En_55 ,Channel 55 event missed" "No missed,Missed" bitfld.long 0x00 22. " En_54 ,Channel 54 event missed" "No missed,Missed" bitfld.long 0x00 21. " En_53 ,Channel 53 event missed" "No missed,Missed" bitfld.long 0x00 20. " En_52 ,Channel 52 event missed" "No missed,Missed" textline " " bitfld.long 0x00 19. " En_51 ,Channel 51 event missed" "No missed,Missed" bitfld.long 0x00 18. " En_50 ,Channel 50 event missed" "No missed,Missed" bitfld.long 0x00 17. " En_49 ,Channel 49 event missed" "No missed,Missed" bitfld.long 0x00 16. " En_48 ,Channel 48 event missed" "No missed,Missed" textline " " bitfld.long 0x00 15. " En_47 ,Channel 47 event missed" "No missed,Missed" bitfld.long 0x00 14. " En_46 ,Channel 46 event missed" "No missed,Missed" bitfld.long 0x00 13. " En_45 ,Channel 45 event missed" "No missed,Missed" bitfld.long 0x00 12. " En_44 ,Channel 44 event missed" "No missed,Missed" textline " " bitfld.long 0x00 11. " En_43 ,Channel 43 event missed" "No missed,Missed" bitfld.long 0x00 10. " En_42 ,Channel 42 event missed" "No missed,Missed" bitfld.long 0x00 9. " En_41 ,Channel 41 event missed" "No missed,Missed" bitfld.long 0x00 8. " En_40 ,Channel 40 event missed" "No missed,Missed" textline " " bitfld.long 0x00 7. " En_39 ,Channel 39 event missed" "No missed,Missed" bitfld.long 0x00 6. " En_38 ,Channel 38 event missed" "No missed,Missed" bitfld.long 0x00 5. " En_37 ,Channel 37 event missed" "No missed,Missed" bitfld.long 0x00 4. " En_36 ,Channel 36 event missed" "No missed,Missed" textline " " bitfld.long 0x00 3. " En_35 ,Channel 35 event missed" "No missed,Missed" bitfld.long 0x00 2. " En_34 ,Channel 34 event missed" "No missed,Missed" bitfld.long 0x00 1. " En_33 ,Channel 33 event missed" "No missed,Missed" bitfld.long 0x00 0. " En_32 ,Channel 32 event missed" "No missed,Missed" wgroup.long 0x0308++0x03 line.long 0x00 "EMCR,Event Missed Clear Register" bitfld.long 0x00 31. " En_31 ,Event missed 31 clear" "No effect,Cleared" bitfld.long 0x00 30. " En_30 ,Event missed 30 clear" "No effect,Cleared" bitfld.long 0x00 29. " En_29 ,Event missed 29 clear" "No effect,Cleared" bitfld.long 0x00 28. " En_28 ,Event missed 28 clear" "No effect,Cleared" textline " " bitfld.long 0x00 27. " En_27 ,Event missed 27 clear" "No effect,Cleared" bitfld.long 0x00 26. " En_26 ,Event missed 26 clear" "No effect,Cleared" bitfld.long 0x00 25. " En_25 ,Event missed 25 clear" "No effect,Cleared" bitfld.long 0x00 24. " En_24 ,Event missed 24 clear" "No effect,Cleared" textline " " bitfld.long 0x00 23. " En_23 ,Event missed 23 clear" "No effect,Cleared" bitfld.long 0x00 22. " En_22 ,Event missed 22 clear" "No effect,Cleared" bitfld.long 0x00 21. " En_21 ,Event missed 21 clear" "No effect,Cleared" bitfld.long 0x00 20. " En_20 ,Event missed 20 clear" "No effect,Cleared" textline " " bitfld.long 0x00 19. " En_19 ,Event missed 19 clear" "No effect,Cleared" bitfld.long 0x00 18. " En_18 ,Event missed 18 clear" "No effect,Cleared" bitfld.long 0x00 17. " En_17 ,Event missed 17 clear" "No effect,Cleared" bitfld.long 0x00 16. " En_16 ,Event missed 16 clear" "No effect,Cleared" textline " " bitfld.long 0x00 15. " En_15 ,Event missed 15 clear" "No effect,Cleared" bitfld.long 0x00 14. " En_14 ,Event missed 14 clear" "No effect,Cleared" bitfld.long 0x00 13. " En_13 ,Event missed 13 clear" "No effect,Cleared" bitfld.long 0x00 12. " En_12 ,Event missed 12 clear" "No effect,Cleared" textline " " bitfld.long 0x00 11. " En_11 ,Event missed 11 clear" "No effect,Cleared" bitfld.long 0x00 10. " En_10 ,Event missed 10 clear" "No effect,Cleared" bitfld.long 0x00 9. " En_9 ,Event missed 9 clear" "No effect,Cleared" bitfld.long 0x00 8. " En_8 ,Event missed 8 clear" "No effect,Cleared" textline " " bitfld.long 0x00 7. " En_7 ,Event missed 7 clear" "No effect,Cleared" bitfld.long 0x00 6. " En_6 ,Event missed 6 clear" "No effect,Cleared" bitfld.long 0x00 5. " En_5 ,Event missed 5 clear" "No effect,Cleared" bitfld.long 0x00 4. " En_4 ,Event missed 4 clear" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_3 ,Event missed 3 clear" "No effect,Cleared" bitfld.long 0x00 2. " En_2 ,Event missed 2 clear" "No effect,Cleared" bitfld.long 0x00 1. " En_1 ,Event missed 1 clear" "No effect,Cleared" bitfld.long 0x00 0. " En_0 ,Event missed 0 clear" "No effect,Cleared" wgroup.long 0x030C++0x03 line.long 0x00 "EMCRH,Event Missed Clear Register High" bitfld.long 0x00 31. " En_63 ,Event missed 63 clear" "No effect,Cleared" bitfld.long 0x00 30. " En_62 ,Event missed 62 clear" "No effect,Cleared" bitfld.long 0x00 29. " En_61 ,Event missed 61 clear" "No effect,Cleared" bitfld.long 0x00 28. " En_60 ,Event missed 60 clear" "No effect,Cleared" textline " " bitfld.long 0x00 27. " En_59 ,Event missed 59 clear" "No effect,Cleared" bitfld.long 0x00 26. " En_58 ,Event missed 58 clear" "No effect,Cleared" bitfld.long 0x00 25. " En_57 ,Event missed 57 clear" "No effect,Cleared" bitfld.long 0x00 24. " En_56 ,Event missed 56 clear" "No effect,Cleared" textline " " bitfld.long 0x00 23. " En_55 ,Event missed 55 clear" "No effect,Cleared" bitfld.long 0x00 22. " En_54 ,Event missed 54 clear" "No effect,Cleared" bitfld.long 0x00 21. " En_53 ,Event missed 53 clear" "No effect,Cleared" bitfld.long 0x00 20. " En_52 ,Event missed 52 clear" "No effect,Cleared" textline " " bitfld.long 0x00 19. " En_51 ,Event missed 51 clear" "No effect,Cleared" bitfld.long 0x00 18. " En_50 ,Event missed 50 clear" "No effect,Cleared" bitfld.long 0x00 17. " En_49 ,Event missed 49 clear" "No effect,Cleared" bitfld.long 0x00 16. " En_48 ,Event missed 48 clear" "No effect,Cleared" textline " " bitfld.long 0x00 15. " En_47 ,Event missed 47 clear" "No effect,Cleared" bitfld.long 0x00 14. " En_46 ,Event missed 46 clear" "No effect,Cleared" bitfld.long 0x00 13. " En_45 ,Event missed 45 clear" "No effect,Cleared" bitfld.long 0x00 12. " En_44 ,Event missed 44 clear" "No effect,Cleared" textline " " bitfld.long 0x00 11. " En_43 ,Event missed 43 clear" "No effect,Cleared" bitfld.long 0x00 10. " En_42 ,Event missed 42 clear" "No effect,Cleared" bitfld.long 0x00 9. " En_41 ,Event missed 41 clear" "No effect,Cleared" bitfld.long 0x00 8. " En_40 ,Event missed 40 clear" "No effect,Cleared" textline " " bitfld.long 0x00 7. " En_39 ,Event missed 39 clear" "No effect,Cleared" bitfld.long 0x00 6. " En_38 ,Event missed 38 clear" "No effect,Cleared" bitfld.long 0x00 5. " En_37 ,Event missed 37 clear" "No effect,Cleared" bitfld.long 0x00 4. " En_36 ,Event missed 36 clear" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_35 ,Event missed 35 clear" "No effect,Cleared" bitfld.long 0x00 2. " En_34 ,Event missed 34 clear" "No effect,Cleared" bitfld.long 0x00 1. " En_33 ,Event missed 33 clear" "No effect,Cleared" bitfld.long 0x00 0. " En_32 ,Event missed 32 clear" "No effect,Cleared" rgroup.long 0x0310++0x03 line.long 0x00 "QEMR,QDMA Event Missed Register" bitfld.long 0x00 7. " En_7 ,Channel 7 QDMA event missed" "No missed,Missed" bitfld.long 0x00 6. " En_6 ,Channel 6 QDMA event missed" "No missed,Missed" bitfld.long 0x00 5. " En_5 ,Channel 5 QDMA event missed" "No missed,Missed" bitfld.long 0x00 4. " En_4 ,Channel 4 QDMA event missed" "No missed,Missed" textline " " bitfld.long 0x00 3. " En_3 ,Channel 3 QDMA event missed" "No missed,Missed" bitfld.long 0x00 2. " En_2 ,Channel 2 QDMA event missed" "No missed,Missed" bitfld.long 0x00 1. " En_1 ,Channel 1 QDMA event missed" "No missed,Missed" bitfld.long 0x00 0. " En_0 ,Channel 0 QDMA event missed" "No missed,Missed" wgroup.long 0x0314++0x03 line.long 0x00 "QEMCR,QDMA Event Missed Clear Register" bitfld.long 0x00 7. " En_7 ,QDMA event missed clear" "No effect,Cleared" bitfld.long 0x00 6. " En_6 ,QDMA event missed clear" "No effect,Cleared" bitfld.long 0x00 5. " En_5 ,QDMA event missed clear" "No effect,Cleared" bitfld.long 0x00 4. " En_4 ,QDMA event missed clear" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_3 ,QDMA event missed clear" "No effect,Cleared" bitfld.long 0x00 2. " En_2 ,QDMA event missed clear" "No effect,Cleared" bitfld.long 0x00 1. " En_1 ,QDMA event missed clear" "No effect,Cleared" bitfld.long 0x00 0. " En_0 ,QDMA event missed clear" "No effect,Cleared" rgroup.long 0x0318++0x03 line.long 0x00 "CCERR,EDMA3CC Error Register" bitfld.long 0x00 16. " TCCERR ,Transfer completion code error" "Not reached,Reached" bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error for queue 2" "Not exceeded,Exceeded" bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error for queue 1" "Not exceeded,Exceeded" bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error for queue 0" "Not exceeded,Exceeded" wgroup.long 0x031C++0x03 line.long 0x00 "CCERRCLR,EDMA3CC Error Clear Register" bitfld.long 0x00 16. " TCCERR ,Transfer completion code error clear" "No effect,Cleared" bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error clear for queue 3" "No effect,Cleared" bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error clear for queue 2" "No effect,Cleared" textline " " bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error clear for queue 1" "No effect,Cleared" bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error clear for queue 0" "No effect,Cleared" wgroup.long 0x0320++0x03 line.long 0x00 "EEVAL,Error Evaluate Register" bitfld.long 0x00 0. " EVAL ,Error interrupt evaluate" "No effect,Cleared" width 10. tree "DRAE, DRAEH - array[8]" group.long 0x0340++0x03 line.long 0x00 "DRAE[0],DMA Region Access Enable Register for Region 0" bitfld.long 0x00 31. " En_31 ,DMA region access enable for bit 31" "Not allowed,Allowed" bitfld.long 0x00 30. " En_30 ,DMA region access enable for bit 30" "Not allowed,Allowed" bitfld.long 0x00 29. " En_29 ,DMA region access enable for bit 29" "Not allowed,Allowed" bitfld.long 0x00 28. " En_28 ,DMA region access enable for bit 28" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_27 ,DMA region access enable for bit 27" "Not allowed,Allowed" bitfld.long 0x00 26. " En_26 ,DMA region access enable for bit 26" "Not allowed,Allowed" bitfld.long 0x00 25. " En_25 ,DMA region access enable for bit 25" "Not allowed,Allowed" bitfld.long 0x00 24. " En_24 ,DMA region access enable for bit 24" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_23 ,DMA region access enable for bit 23" "Not allowed,Allowed" bitfld.long 0x00 22. " En_22 ,DMA region access enable for bit 22" "Not allowed,Allowed" bitfld.long 0x00 21. " En_21 ,DMA region access enable for bit 21" "Not allowed,Allowed" bitfld.long 0x00 20. " En_20 ,DMA region access enable for bit 20" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_19 ,DMA region access enable for bit 19" "Not allowed,Allowed" bitfld.long 0x00 18. " En_18 ,DMA region access enable for bit 18" "Not allowed,Allowed" bitfld.long 0x00 17. " En_17 ,DMA region access enable for bit 17" "Not allowed,Allowed" bitfld.long 0x00 16. " En_16 ,DMA region access enable for bit 16" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_15 ,DMA region access enable for bit 15" "Not allowed,Allowed" bitfld.long 0x00 14. " En_14 ,DMA region access enable for bit 14" "Not allowed,Allowed" bitfld.long 0x00 13. " En_13 ,DMA region access enable for bit 13" "Not allowed,Allowed" bitfld.long 0x00 12. " En_12 ,DMA region access enable for bit 12" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_11 ,DMA region access enable for bit 11" "Not allowed,Allowed" bitfld.long 0x00 10. " En_10 ,DMA region access enable for bit 10" "Not allowed,Allowed" bitfld.long 0x00 9. " En_9 ,DMA region access enable for bit 9" "Not allowed,Allowed" bitfld.long 0x00 8. " En_8 ,DMA region access enable for bit 8" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_7 ,DMA region access enable for bit 7" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,DMA region access enable for bit 6" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,DMA region access enable for bit 5" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,DMA region access enable for bit 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,DMA region access enable for bit 3" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,DMA region access enable for bit 2" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,DMA region access enable for bit 1" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,DMA region access enable for bit 0" "Not allowed,Allowed" group.long 0x0344++0x03 line.long 0x00 "DRAEH[0],DMA Region Access Enable Register High for Region 0" bitfld.long 0x00 31. " En_63 ,DMA region access enable for bit 63" "Not allowed,Allowed" bitfld.long 0x00 30. " En_62 ,DMA region access enable for bit 62" "Not allowed,Allowed" bitfld.long 0x00 29. " En_61 ,DMA region access enable for bit 61" "Not allowed,Allowed" bitfld.long 0x00 28. " En_60 ,DMA region access enable for bit 60" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_59 ,DMA region access enable for bit 59" "Not allowed,Allowed" bitfld.long 0x00 26. " En_58 ,DMA region access enable for bit 58" "Not allowed,Allowed" bitfld.long 0x00 25. " En_57 ,DMA region access enable for bit 57" "Not allowed,Allowed" bitfld.long 0x00 24. " En_56 ,DMA region access enable for bit 56" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_55 ,DMA region access enable for bit 55" "Not allowed,Allowed" bitfld.long 0x00 22. " En_54 ,DMA region access enable for bit 54" "Not allowed,Allowed" bitfld.long 0x00 21. " En_53 ,DMA region access enable for bit 53" "Not allowed,Allowed" bitfld.long 0x00 20. " En_52 ,DMA region access enable for bit 52" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_51 ,DMA region access enable for bit 51" "Not allowed,Allowed" bitfld.long 0x00 18. " En_50 ,DMA region access enable for bit 50" "Not allowed,Allowed" bitfld.long 0x00 17. " En_49 ,DMA region access enable for bit 49" "Not allowed,Allowed" bitfld.long 0x00 16. " En_48 ,DMA region access enable for bit 48" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_47 ,DMA region access enable for bit 47" "Not allowed,Allowed" bitfld.long 0x00 14. " En_46 ,DMA region access enable for bit 46" "Not allowed,Allowed" bitfld.long 0x00 13. " En_45 ,DMA region access enable for bit 45" "Not allowed,Allowed" bitfld.long 0x00 12. " En_44 ,DMA region access enable for bit 44" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_43 ,DMA region access enable for bit 43" "Not allowed,Allowed" bitfld.long 0x00 10. " En_42 ,DMA region access enable for bit 42" "Not allowed,Allowed" bitfld.long 0x00 9. " En_41 ,DMA region access enable for bit 41" "Not allowed,Allowed" bitfld.long 0x00 8. " En_40 ,DMA region access enable for bit 40" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_39 ,DMA region access enable for bit 39" "Not allowed,Allowed" bitfld.long 0x00 6. " En_38 ,DMA region access enable for bit 38" "Not allowed,Allowed" bitfld.long 0x00 5. " En_37 ,DMA region access enable for bit 37" "Not allowed,Allowed" bitfld.long 0x00 4. " En_36 ,DMA region access enable for bit 36" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_35 ,DMA region access enable for bit 35" "Not allowed,Allowed" bitfld.long 0x00 2. " En_34 ,DMA region access enable for bit 34" "Not allowed,Allowed" bitfld.long 0x00 1. " En_33 ,DMA region access enable for bit 33" "Not allowed,Allowed" bitfld.long 0x00 0. " En_32 ,DMA region access enable for bit 32" "Not allowed,Allowed" group.long 0x0348++0x03 line.long 0x00 "DRAE[1],DMA Region Access Enable Register for Region 1" bitfld.long 0x00 31. " En_31 ,DMA region access enable for bit 31" "Not allowed,Allowed" bitfld.long 0x00 30. " En_30 ,DMA region access enable for bit 30" "Not allowed,Allowed" bitfld.long 0x00 29. " En_29 ,DMA region access enable for bit 29" "Not allowed,Allowed" bitfld.long 0x00 28. " En_28 ,DMA region access enable for bit 28" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_27 ,DMA region access enable for bit 27" "Not allowed,Allowed" bitfld.long 0x00 26. " En_26 ,DMA region access enable for bit 26" "Not allowed,Allowed" bitfld.long 0x00 25. " En_25 ,DMA region access enable for bit 25" "Not allowed,Allowed" bitfld.long 0x00 24. " En_24 ,DMA region access enable for bit 24" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_23 ,DMA region access enable for bit 23" "Not allowed,Allowed" bitfld.long 0x00 22. " En_22 ,DMA region access enable for bit 22" "Not allowed,Allowed" bitfld.long 0x00 21. " En_21 ,DMA region access enable for bit 21" "Not allowed,Allowed" bitfld.long 0x00 20. " En_20 ,DMA region access enable for bit 20" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_19 ,DMA region access enable for bit 19" "Not allowed,Allowed" bitfld.long 0x00 18. " En_18 ,DMA region access enable for bit 18" "Not allowed,Allowed" bitfld.long 0x00 17. " En_17 ,DMA region access enable for bit 17" "Not allowed,Allowed" bitfld.long 0x00 16. " En_16 ,DMA region access enable for bit 16" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_15 ,DMA region access enable for bit 15" "Not allowed,Allowed" bitfld.long 0x00 14. " En_14 ,DMA region access enable for bit 14" "Not allowed,Allowed" bitfld.long 0x00 13. " En_13 ,DMA region access enable for bit 13" "Not allowed,Allowed" bitfld.long 0x00 12. " En_12 ,DMA region access enable for bit 12" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_11 ,DMA region access enable for bit 11" "Not allowed,Allowed" bitfld.long 0x00 10. " En_10 ,DMA region access enable for bit 10" "Not allowed,Allowed" bitfld.long 0x00 9. " En_9 ,DMA region access enable for bit 9" "Not allowed,Allowed" bitfld.long 0x00 8. " En_8 ,DMA region access enable for bit 8" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_7 ,DMA region access enable for bit 7" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,DMA region access enable for bit 6" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,DMA region access enable for bit 5" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,DMA region access enable for bit 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,DMA region access enable for bit 3" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,DMA region access enable for bit 2" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,DMA region access enable for bit 1" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,DMA region access enable for bit 0" "Not allowed,Allowed" group.long 0x034C++0x03 line.long 0x00 "DRAEH[1],DMA Region Access Enable Register High for Region 1" bitfld.long 0x00 31. " En_63 ,DMA region access enable for bit 63" "Not allowed,Allowed" bitfld.long 0x00 30. " En_62 ,DMA region access enable for bit 62" "Not allowed,Allowed" bitfld.long 0x00 29. " En_61 ,DMA region access enable for bit 61" "Not allowed,Allowed" bitfld.long 0x00 28. " En_60 ,DMA region access enable for bit 60" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_59 ,DMA region access enable for bit 59" "Not allowed,Allowed" bitfld.long 0x00 26. " En_58 ,DMA region access enable for bit 58" "Not allowed,Allowed" bitfld.long 0x00 25. " En_57 ,DMA region access enable for bit 57" "Not allowed,Allowed" bitfld.long 0x00 24. " En_56 ,DMA region access enable for bit 56" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_55 ,DMA region access enable for bit 55" "Not allowed,Allowed" bitfld.long 0x00 22. " En_54 ,DMA region access enable for bit 54" "Not allowed,Allowed" bitfld.long 0x00 21. " En_53 ,DMA region access enable for bit 53" "Not allowed,Allowed" bitfld.long 0x00 20. " En_52 ,DMA region access enable for bit 52" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_51 ,DMA region access enable for bit 51" "Not allowed,Allowed" bitfld.long 0x00 18. " En_50 ,DMA region access enable for bit 50" "Not allowed,Allowed" bitfld.long 0x00 17. " En_49 ,DMA region access enable for bit 49" "Not allowed,Allowed" bitfld.long 0x00 16. " En_48 ,DMA region access enable for bit 48" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_47 ,DMA region access enable for bit 47" "Not allowed,Allowed" bitfld.long 0x00 14. " En_46 ,DMA region access enable for bit 46" "Not allowed,Allowed" bitfld.long 0x00 13. " En_45 ,DMA region access enable for bit 45" "Not allowed,Allowed" bitfld.long 0x00 12. " En_44 ,DMA region access enable for bit 44" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_43 ,DMA region access enable for bit 43" "Not allowed,Allowed" bitfld.long 0x00 10. " En_42 ,DMA region access enable for bit 42" "Not allowed,Allowed" bitfld.long 0x00 9. " En_41 ,DMA region access enable for bit 41" "Not allowed,Allowed" bitfld.long 0x00 8. " En_40 ,DMA region access enable for bit 40" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_39 ,DMA region access enable for bit 39" "Not allowed,Allowed" bitfld.long 0x00 6. " En_38 ,DMA region access enable for bit 38" "Not allowed,Allowed" bitfld.long 0x00 5. " En_37 ,DMA region access enable for bit 37" "Not allowed,Allowed" bitfld.long 0x00 4. " En_36 ,DMA region access enable for bit 36" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_35 ,DMA region access enable for bit 35" "Not allowed,Allowed" bitfld.long 0x00 2. " En_34 ,DMA region access enable for bit 34" "Not allowed,Allowed" bitfld.long 0x00 1. " En_33 ,DMA region access enable for bit 33" "Not allowed,Allowed" bitfld.long 0x00 0. " En_32 ,DMA region access enable for bit 32" "Not allowed,Allowed" group.long 0x0350++0x03 line.long 0x00 "DRAE[2],DMA Region Access Enable Register for Region 2" bitfld.long 0x00 31. " En_31 ,DMA region access enable for bit 31" "Not allowed,Allowed" bitfld.long 0x00 30. " En_30 ,DMA region access enable for bit 30" "Not allowed,Allowed" bitfld.long 0x00 29. " En_29 ,DMA region access enable for bit 29" "Not allowed,Allowed" bitfld.long 0x00 28. " En_28 ,DMA region access enable for bit 28" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_27 ,DMA region access enable for bit 27" "Not allowed,Allowed" bitfld.long 0x00 26. " En_26 ,DMA region access enable for bit 26" "Not allowed,Allowed" bitfld.long 0x00 25. " En_25 ,DMA region access enable for bit 25" "Not allowed,Allowed" bitfld.long 0x00 24. " En_24 ,DMA region access enable for bit 24" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_23 ,DMA region access enable for bit 23" "Not allowed,Allowed" bitfld.long 0x00 22. " En_22 ,DMA region access enable for bit 22" "Not allowed,Allowed" bitfld.long 0x00 21. " En_21 ,DMA region access enable for bit 21" "Not allowed,Allowed" bitfld.long 0x00 20. " En_20 ,DMA region access enable for bit 20" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_19 ,DMA region access enable for bit 19" "Not allowed,Allowed" bitfld.long 0x00 18. " En_18 ,DMA region access enable for bit 18" "Not allowed,Allowed" bitfld.long 0x00 17. " En_17 ,DMA region access enable for bit 17" "Not allowed,Allowed" bitfld.long 0x00 16. " En_16 ,DMA region access enable for bit 16" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_15 ,DMA region access enable for bit 15" "Not allowed,Allowed" bitfld.long 0x00 14. " En_14 ,DMA region access enable for bit 14" "Not allowed,Allowed" bitfld.long 0x00 13. " En_13 ,DMA region access enable for bit 13" "Not allowed,Allowed" bitfld.long 0x00 12. " En_12 ,DMA region access enable for bit 12" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_11 ,DMA region access enable for bit 11" "Not allowed,Allowed" bitfld.long 0x00 10. " En_10 ,DMA region access enable for bit 10" "Not allowed,Allowed" bitfld.long 0x00 9. " En_9 ,DMA region access enable for bit 9" "Not allowed,Allowed" bitfld.long 0x00 8. " En_8 ,DMA region access enable for bit 8" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_7 ,DMA region access enable for bit 7" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,DMA region access enable for bit 6" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,DMA region access enable for bit 5" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,DMA region access enable for bit 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,DMA region access enable for bit 3" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,DMA region access enable for bit 2" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,DMA region access enable for bit 1" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,DMA region access enable for bit 0" "Not allowed,Allowed" group.long 0x0354++0x03 line.long 0x00 "DRAEH[2],DMA Region Access Enable Register High for Region 2" bitfld.long 0x00 31. " En_63 ,DMA region access enable for bit 63" "Not allowed,Allowed" bitfld.long 0x00 30. " En_62 ,DMA region access enable for bit 62" "Not allowed,Allowed" bitfld.long 0x00 29. " En_61 ,DMA region access enable for bit 61" "Not allowed,Allowed" bitfld.long 0x00 28. " En_60 ,DMA region access enable for bit 60" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_59 ,DMA region access enable for bit 59" "Not allowed,Allowed" bitfld.long 0x00 26. " En_58 ,DMA region access enable for bit 58" "Not allowed,Allowed" bitfld.long 0x00 25. " En_57 ,DMA region access enable for bit 57" "Not allowed,Allowed" bitfld.long 0x00 24. " En_56 ,DMA region access enable for bit 56" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_55 ,DMA region access enable for bit 55" "Not allowed,Allowed" bitfld.long 0x00 22. " En_54 ,DMA region access enable for bit 54" "Not allowed,Allowed" bitfld.long 0x00 21. " En_53 ,DMA region access enable for bit 53" "Not allowed,Allowed" bitfld.long 0x00 20. " En_52 ,DMA region access enable for bit 52" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_51 ,DMA region access enable for bit 51" "Not allowed,Allowed" bitfld.long 0x00 18. " En_50 ,DMA region access enable for bit 50" "Not allowed,Allowed" bitfld.long 0x00 17. " En_49 ,DMA region access enable for bit 49" "Not allowed,Allowed" bitfld.long 0x00 16. " En_48 ,DMA region access enable for bit 48" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_47 ,DMA region access enable for bit 47" "Not allowed,Allowed" bitfld.long 0x00 14. " En_46 ,DMA region access enable for bit 46" "Not allowed,Allowed" bitfld.long 0x00 13. " En_45 ,DMA region access enable for bit 45" "Not allowed,Allowed" bitfld.long 0x00 12. " En_44 ,DMA region access enable for bit 44" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_43 ,DMA region access enable for bit 43" "Not allowed,Allowed" bitfld.long 0x00 10. " En_42 ,DMA region access enable for bit 42" "Not allowed,Allowed" bitfld.long 0x00 9. " En_41 ,DMA region access enable for bit 41" "Not allowed,Allowed" bitfld.long 0x00 8. " En_40 ,DMA region access enable for bit 40" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_39 ,DMA region access enable for bit 39" "Not allowed,Allowed" bitfld.long 0x00 6. " En_38 ,DMA region access enable for bit 38" "Not allowed,Allowed" bitfld.long 0x00 5. " En_37 ,DMA region access enable for bit 37" "Not allowed,Allowed" bitfld.long 0x00 4. " En_36 ,DMA region access enable for bit 36" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_35 ,DMA region access enable for bit 35" "Not allowed,Allowed" bitfld.long 0x00 2. " En_34 ,DMA region access enable for bit 34" "Not allowed,Allowed" bitfld.long 0x00 1. " En_33 ,DMA region access enable for bit 33" "Not allowed,Allowed" bitfld.long 0x00 0. " En_32 ,DMA region access enable for bit 32" "Not allowed,Allowed" group.long 0x0358++0x03 line.long 0x00 "DRAE[3],DMA Region Access Enable Register for Region 3" bitfld.long 0x00 31. " En_31 ,DMA region access enable for bit 31" "Not allowed,Allowed" bitfld.long 0x00 30. " En_30 ,DMA region access enable for bit 30" "Not allowed,Allowed" bitfld.long 0x00 29. " En_29 ,DMA region access enable for bit 29" "Not allowed,Allowed" bitfld.long 0x00 28. " En_28 ,DMA region access enable for bit 28" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_27 ,DMA region access enable for bit 27" "Not allowed,Allowed" bitfld.long 0x00 26. " En_26 ,DMA region access enable for bit 26" "Not allowed,Allowed" bitfld.long 0x00 25. " En_25 ,DMA region access enable for bit 25" "Not allowed,Allowed" bitfld.long 0x00 24. " En_24 ,DMA region access enable for bit 24" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_23 ,DMA region access enable for bit 23" "Not allowed,Allowed" bitfld.long 0x00 22. " En_22 ,DMA region access enable for bit 22" "Not allowed,Allowed" bitfld.long 0x00 21. " En_21 ,DMA region access enable for bit 21" "Not allowed,Allowed" bitfld.long 0x00 20. " En_20 ,DMA region access enable for bit 20" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_19 ,DMA region access enable for bit 19" "Not allowed,Allowed" bitfld.long 0x00 18. " En_18 ,DMA region access enable for bit 18" "Not allowed,Allowed" bitfld.long 0x00 17. " En_17 ,DMA region access enable for bit 17" "Not allowed,Allowed" bitfld.long 0x00 16. " En_16 ,DMA region access enable for bit 16" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_15 ,DMA region access enable for bit 15" "Not allowed,Allowed" bitfld.long 0x00 14. " En_14 ,DMA region access enable for bit 14" "Not allowed,Allowed" bitfld.long 0x00 13. " En_13 ,DMA region access enable for bit 13" "Not allowed,Allowed" bitfld.long 0x00 12. " En_12 ,DMA region access enable for bit 12" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_11 ,DMA region access enable for bit 11" "Not allowed,Allowed" bitfld.long 0x00 10. " En_10 ,DMA region access enable for bit 10" "Not allowed,Allowed" bitfld.long 0x00 9. " En_9 ,DMA region access enable for bit 9" "Not allowed,Allowed" bitfld.long 0x00 8. " En_8 ,DMA region access enable for bit 8" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_7 ,DMA region access enable for bit 7" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,DMA region access enable for bit 6" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,DMA region access enable for bit 5" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,DMA region access enable for bit 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,DMA region access enable for bit 3" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,DMA region access enable for bit 2" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,DMA region access enable for bit 1" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,DMA region access enable for bit 0" "Not allowed,Allowed" group.long 0x035C++0x03 line.long 0x00 "DRAEH[3],DMA Region Access Enable Register High for Region 3" bitfld.long 0x00 31. " En_63 ,DMA region access enable for bit 63" "Not allowed,Allowed" bitfld.long 0x00 30. " En_62 ,DMA region access enable for bit 62" "Not allowed,Allowed" bitfld.long 0x00 29. " En_61 ,DMA region access enable for bit 61" "Not allowed,Allowed" bitfld.long 0x00 28. " En_60 ,DMA region access enable for bit 60" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_59 ,DMA region access enable for bit 59" "Not allowed,Allowed" bitfld.long 0x00 26. " En_58 ,DMA region access enable for bit 58" "Not allowed,Allowed" bitfld.long 0x00 25. " En_57 ,DMA region access enable for bit 57" "Not allowed,Allowed" bitfld.long 0x00 24. " En_56 ,DMA region access enable for bit 56" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_55 ,DMA region access enable for bit 55" "Not allowed,Allowed" bitfld.long 0x00 22. " En_54 ,DMA region access enable for bit 54" "Not allowed,Allowed" bitfld.long 0x00 21. " En_53 ,DMA region access enable for bit 53" "Not allowed,Allowed" bitfld.long 0x00 20. " En_52 ,DMA region access enable for bit 52" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_51 ,DMA region access enable for bit 51" "Not allowed,Allowed" bitfld.long 0x00 18. " En_50 ,DMA region access enable for bit 50" "Not allowed,Allowed" bitfld.long 0x00 17. " En_49 ,DMA region access enable for bit 49" "Not allowed,Allowed" bitfld.long 0x00 16. " En_48 ,DMA region access enable for bit 48" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_47 ,DMA region access enable for bit 47" "Not allowed,Allowed" bitfld.long 0x00 14. " En_46 ,DMA region access enable for bit 46" "Not allowed,Allowed" bitfld.long 0x00 13. " En_45 ,DMA region access enable for bit 45" "Not allowed,Allowed" bitfld.long 0x00 12. " En_44 ,DMA region access enable for bit 44" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_43 ,DMA region access enable for bit 43" "Not allowed,Allowed" bitfld.long 0x00 10. " En_42 ,DMA region access enable for bit 42" "Not allowed,Allowed" bitfld.long 0x00 9. " En_41 ,DMA region access enable for bit 41" "Not allowed,Allowed" bitfld.long 0x00 8. " En_40 ,DMA region access enable for bit 40" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_39 ,DMA region access enable for bit 39" "Not allowed,Allowed" bitfld.long 0x00 6. " En_38 ,DMA region access enable for bit 38" "Not allowed,Allowed" bitfld.long 0x00 5. " En_37 ,DMA region access enable for bit 37" "Not allowed,Allowed" bitfld.long 0x00 4. " En_36 ,DMA region access enable for bit 36" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_35 ,DMA region access enable for bit 35" "Not allowed,Allowed" bitfld.long 0x00 2. " En_34 ,DMA region access enable for bit 34" "Not allowed,Allowed" bitfld.long 0x00 1. " En_33 ,DMA region access enable for bit 33" "Not allowed,Allowed" bitfld.long 0x00 0. " En_32 ,DMA region access enable for bit 32" "Not allowed,Allowed" group.long 0x0360++0x03 line.long 0x00 "DRAE[4],DMA Region Access Enable Register for Region 4" bitfld.long 0x00 31. " En_31 ,DMA region access enable for bit 31" "Not allowed,Allowed" bitfld.long 0x00 30. " En_30 ,DMA region access enable for bit 30" "Not allowed,Allowed" bitfld.long 0x00 29. " En_29 ,DMA region access enable for bit 29" "Not allowed,Allowed" bitfld.long 0x00 28. " En_28 ,DMA region access enable for bit 28" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_27 ,DMA region access enable for bit 27" "Not allowed,Allowed" bitfld.long 0x00 26. " En_26 ,DMA region access enable for bit 26" "Not allowed,Allowed" bitfld.long 0x00 25. " En_25 ,DMA region access enable for bit 25" "Not allowed,Allowed" bitfld.long 0x00 24. " En_24 ,DMA region access enable for bit 24" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_23 ,DMA region access enable for bit 23" "Not allowed,Allowed" bitfld.long 0x00 22. " En_22 ,DMA region access enable for bit 22" "Not allowed,Allowed" bitfld.long 0x00 21. " En_21 ,DMA region access enable for bit 21" "Not allowed,Allowed" bitfld.long 0x00 20. " En_20 ,DMA region access enable for bit 20" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_19 ,DMA region access enable for bit 19" "Not allowed,Allowed" bitfld.long 0x00 18. " En_18 ,DMA region access enable for bit 18" "Not allowed,Allowed" bitfld.long 0x00 17. " En_17 ,DMA region access enable for bit 17" "Not allowed,Allowed" bitfld.long 0x00 16. " En_16 ,DMA region access enable for bit 16" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_15 ,DMA region access enable for bit 15" "Not allowed,Allowed" bitfld.long 0x00 14. " En_14 ,DMA region access enable for bit 14" "Not allowed,Allowed" bitfld.long 0x00 13. " En_13 ,DMA region access enable for bit 13" "Not allowed,Allowed" bitfld.long 0x00 12. " En_12 ,DMA region access enable for bit 12" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_11 ,DMA region access enable for bit 11" "Not allowed,Allowed" bitfld.long 0x00 10. " En_10 ,DMA region access enable for bit 10" "Not allowed,Allowed" bitfld.long 0x00 9. " En_9 ,DMA region access enable for bit 9" "Not allowed,Allowed" bitfld.long 0x00 8. " En_8 ,DMA region access enable for bit 8" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_7 ,DMA region access enable for bit 7" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,DMA region access enable for bit 6" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,DMA region access enable for bit 5" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,DMA region access enable for bit 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,DMA region access enable for bit 3" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,DMA region access enable for bit 2" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,DMA region access enable for bit 1" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,DMA region access enable for bit 0" "Not allowed,Allowed" group.long 0x0364++0x03 line.long 0x00 "DRAEH[4],DMA Region Access Enable Register High for Region 4" bitfld.long 0x00 31. " En_63 ,DMA region access enable for bit 63" "Not allowed,Allowed" bitfld.long 0x00 30. " En_62 ,DMA region access enable for bit 62" "Not allowed,Allowed" bitfld.long 0x00 29. " En_61 ,DMA region access enable for bit 61" "Not allowed,Allowed" bitfld.long 0x00 28. " En_60 ,DMA region access enable for bit 60" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_59 ,DMA region access enable for bit 59" "Not allowed,Allowed" bitfld.long 0x00 26. " En_58 ,DMA region access enable for bit 58" "Not allowed,Allowed" bitfld.long 0x00 25. " En_57 ,DMA region access enable for bit 57" "Not allowed,Allowed" bitfld.long 0x00 24. " En_56 ,DMA region access enable for bit 56" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_55 ,DMA region access enable for bit 55" "Not allowed,Allowed" bitfld.long 0x00 22. " En_54 ,DMA region access enable for bit 54" "Not allowed,Allowed" bitfld.long 0x00 21. " En_53 ,DMA region access enable for bit 53" "Not allowed,Allowed" bitfld.long 0x00 20. " En_52 ,DMA region access enable for bit 52" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_51 ,DMA region access enable for bit 51" "Not allowed,Allowed" bitfld.long 0x00 18. " En_50 ,DMA region access enable for bit 50" "Not allowed,Allowed" bitfld.long 0x00 17. " En_49 ,DMA region access enable for bit 49" "Not allowed,Allowed" bitfld.long 0x00 16. " En_48 ,DMA region access enable for bit 48" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_47 ,DMA region access enable for bit 47" "Not allowed,Allowed" bitfld.long 0x00 14. " En_46 ,DMA region access enable for bit 46" "Not allowed,Allowed" bitfld.long 0x00 13. " En_45 ,DMA region access enable for bit 45" "Not allowed,Allowed" bitfld.long 0x00 12. " En_44 ,DMA region access enable for bit 44" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_43 ,DMA region access enable for bit 43" "Not allowed,Allowed" bitfld.long 0x00 10. " En_42 ,DMA region access enable for bit 42" "Not allowed,Allowed" bitfld.long 0x00 9. " En_41 ,DMA region access enable for bit 41" "Not allowed,Allowed" bitfld.long 0x00 8. " En_40 ,DMA region access enable for bit 40" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_39 ,DMA region access enable for bit 39" "Not allowed,Allowed" bitfld.long 0x00 6. " En_38 ,DMA region access enable for bit 38" "Not allowed,Allowed" bitfld.long 0x00 5. " En_37 ,DMA region access enable for bit 37" "Not allowed,Allowed" bitfld.long 0x00 4. " En_36 ,DMA region access enable for bit 36" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_35 ,DMA region access enable for bit 35" "Not allowed,Allowed" bitfld.long 0x00 2. " En_34 ,DMA region access enable for bit 34" "Not allowed,Allowed" bitfld.long 0x00 1. " En_33 ,DMA region access enable for bit 33" "Not allowed,Allowed" bitfld.long 0x00 0. " En_32 ,DMA region access enable for bit 32" "Not allowed,Allowed" group.long 0x0368++0x03 line.long 0x00 "DRAE[5],DMA Region Access Enable Register for Region 5" bitfld.long 0x00 31. " En_31 ,DMA region access enable for bit 31" "Not allowed,Allowed" bitfld.long 0x00 30. " En_30 ,DMA region access enable for bit 30" "Not allowed,Allowed" bitfld.long 0x00 29. " En_29 ,DMA region access enable for bit 29" "Not allowed,Allowed" bitfld.long 0x00 28. " En_28 ,DMA region access enable for bit 28" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_27 ,DMA region access enable for bit 27" "Not allowed,Allowed" bitfld.long 0x00 26. " En_26 ,DMA region access enable for bit 26" "Not allowed,Allowed" bitfld.long 0x00 25. " En_25 ,DMA region access enable for bit 25" "Not allowed,Allowed" bitfld.long 0x00 24. " En_24 ,DMA region access enable for bit 24" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_23 ,DMA region access enable for bit 23" "Not allowed,Allowed" bitfld.long 0x00 22. " En_22 ,DMA region access enable for bit 22" "Not allowed,Allowed" bitfld.long 0x00 21. " En_21 ,DMA region access enable for bit 21" "Not allowed,Allowed" bitfld.long 0x00 20. " En_20 ,DMA region access enable for bit 20" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_19 ,DMA region access enable for bit 19" "Not allowed,Allowed" bitfld.long 0x00 18. " En_18 ,DMA region access enable for bit 18" "Not allowed,Allowed" bitfld.long 0x00 17. " En_17 ,DMA region access enable for bit 17" "Not allowed,Allowed" bitfld.long 0x00 16. " En_16 ,DMA region access enable for bit 16" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_15 ,DMA region access enable for bit 15" "Not allowed,Allowed" bitfld.long 0x00 14. " En_14 ,DMA region access enable for bit 14" "Not allowed,Allowed" bitfld.long 0x00 13. " En_13 ,DMA region access enable for bit 13" "Not allowed,Allowed" bitfld.long 0x00 12. " En_12 ,DMA region access enable for bit 12" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_11 ,DMA region access enable for bit 11" "Not allowed,Allowed" bitfld.long 0x00 10. " En_10 ,DMA region access enable for bit 10" "Not allowed,Allowed" bitfld.long 0x00 9. " En_9 ,DMA region access enable for bit 9" "Not allowed,Allowed" bitfld.long 0x00 8. " En_8 ,DMA region access enable for bit 8" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_7 ,DMA region access enable for bit 7" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,DMA region access enable for bit 6" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,DMA region access enable for bit 5" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,DMA region access enable for bit 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,DMA region access enable for bit 3" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,DMA region access enable for bit 2" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,DMA region access enable for bit 1" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,DMA region access enable for bit 0" "Not allowed,Allowed" group.long 0x036C++0x03 line.long 0x00 "DRAEH[5],DMA Region Access Enable Register High for Region 5" bitfld.long 0x00 31. " En_63 ,DMA region access enable for bit 63" "Not allowed,Allowed" bitfld.long 0x00 30. " En_62 ,DMA region access enable for bit 62" "Not allowed,Allowed" bitfld.long 0x00 29. " En_61 ,DMA region access enable for bit 61" "Not allowed,Allowed" bitfld.long 0x00 28. " En_60 ,DMA region access enable for bit 60" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_59 ,DMA region access enable for bit 59" "Not allowed,Allowed" bitfld.long 0x00 26. " En_58 ,DMA region access enable for bit 58" "Not allowed,Allowed" bitfld.long 0x00 25. " En_57 ,DMA region access enable for bit 57" "Not allowed,Allowed" bitfld.long 0x00 24. " En_56 ,DMA region access enable for bit 56" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_55 ,DMA region access enable for bit 55" "Not allowed,Allowed" bitfld.long 0x00 22. " En_54 ,DMA region access enable for bit 54" "Not allowed,Allowed" bitfld.long 0x00 21. " En_53 ,DMA region access enable for bit 53" "Not allowed,Allowed" bitfld.long 0x00 20. " En_52 ,DMA region access enable for bit 52" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_51 ,DMA region access enable for bit 51" "Not allowed,Allowed" bitfld.long 0x00 18. " En_50 ,DMA region access enable for bit 50" "Not allowed,Allowed" bitfld.long 0x00 17. " En_49 ,DMA region access enable for bit 49" "Not allowed,Allowed" bitfld.long 0x00 16. " En_48 ,DMA region access enable for bit 48" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_47 ,DMA region access enable for bit 47" "Not allowed,Allowed" bitfld.long 0x00 14. " En_46 ,DMA region access enable for bit 46" "Not allowed,Allowed" bitfld.long 0x00 13. " En_45 ,DMA region access enable for bit 45" "Not allowed,Allowed" bitfld.long 0x00 12. " En_44 ,DMA region access enable for bit 44" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_43 ,DMA region access enable for bit 43" "Not allowed,Allowed" bitfld.long 0x00 10. " En_42 ,DMA region access enable for bit 42" "Not allowed,Allowed" bitfld.long 0x00 9. " En_41 ,DMA region access enable for bit 41" "Not allowed,Allowed" bitfld.long 0x00 8. " En_40 ,DMA region access enable for bit 40" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_39 ,DMA region access enable for bit 39" "Not allowed,Allowed" bitfld.long 0x00 6. " En_38 ,DMA region access enable for bit 38" "Not allowed,Allowed" bitfld.long 0x00 5. " En_37 ,DMA region access enable for bit 37" "Not allowed,Allowed" bitfld.long 0x00 4. " En_36 ,DMA region access enable for bit 36" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_35 ,DMA region access enable for bit 35" "Not allowed,Allowed" bitfld.long 0x00 2. " En_34 ,DMA region access enable for bit 34" "Not allowed,Allowed" bitfld.long 0x00 1. " En_33 ,DMA region access enable for bit 33" "Not allowed,Allowed" bitfld.long 0x00 0. " En_32 ,DMA region access enable for bit 32" "Not allowed,Allowed" group.long 0x0370++0x03 line.long 0x00 "DRAE[6],DMA Region Access Enable Register for Region 6" bitfld.long 0x00 31. " En_31 ,DMA region access enable for bit 31" "Not allowed,Allowed" bitfld.long 0x00 30. " En_30 ,DMA region access enable for bit 30" "Not allowed,Allowed" bitfld.long 0x00 29. " En_29 ,DMA region access enable for bit 29" "Not allowed,Allowed" bitfld.long 0x00 28. " En_28 ,DMA region access enable for bit 28" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_27 ,DMA region access enable for bit 27" "Not allowed,Allowed" bitfld.long 0x00 26. " En_26 ,DMA region access enable for bit 26" "Not allowed,Allowed" bitfld.long 0x00 25. " En_25 ,DMA region access enable for bit 25" "Not allowed,Allowed" bitfld.long 0x00 24. " En_24 ,DMA region access enable for bit 24" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_23 ,DMA region access enable for bit 23" "Not allowed,Allowed" bitfld.long 0x00 22. " En_22 ,DMA region access enable for bit 22" "Not allowed,Allowed" bitfld.long 0x00 21. " En_21 ,DMA region access enable for bit 21" "Not allowed,Allowed" bitfld.long 0x00 20. " En_20 ,DMA region access enable for bit 20" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_19 ,DMA region access enable for bit 19" "Not allowed,Allowed" bitfld.long 0x00 18. " En_18 ,DMA region access enable for bit 18" "Not allowed,Allowed" bitfld.long 0x00 17. " En_17 ,DMA region access enable for bit 17" "Not allowed,Allowed" bitfld.long 0x00 16. " En_16 ,DMA region access enable for bit 16" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_15 ,DMA region access enable for bit 15" "Not allowed,Allowed" bitfld.long 0x00 14. " En_14 ,DMA region access enable for bit 14" "Not allowed,Allowed" bitfld.long 0x00 13. " En_13 ,DMA region access enable for bit 13" "Not allowed,Allowed" bitfld.long 0x00 12. " En_12 ,DMA region access enable for bit 12" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_11 ,DMA region access enable for bit 11" "Not allowed,Allowed" bitfld.long 0x00 10. " En_10 ,DMA region access enable for bit 10" "Not allowed,Allowed" bitfld.long 0x00 9. " En_9 ,DMA region access enable for bit 9" "Not allowed,Allowed" bitfld.long 0x00 8. " En_8 ,DMA region access enable for bit 8" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_7 ,DMA region access enable for bit 7" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,DMA region access enable for bit 6" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,DMA region access enable for bit 5" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,DMA region access enable for bit 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,DMA region access enable for bit 3" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,DMA region access enable for bit 2" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,DMA region access enable for bit 1" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,DMA region access enable for bit 0" "Not allowed,Allowed" group.long 0x0374++0x03 line.long 0x00 "DRAEH[6],DMA Region Access Enable Register High for Region 6" bitfld.long 0x00 31. " En_63 ,DMA region access enable for bit 63" "Not allowed,Allowed" bitfld.long 0x00 30. " En_62 ,DMA region access enable for bit 62" "Not allowed,Allowed" bitfld.long 0x00 29. " En_61 ,DMA region access enable for bit 61" "Not allowed,Allowed" bitfld.long 0x00 28. " En_60 ,DMA region access enable for bit 60" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_59 ,DMA region access enable for bit 59" "Not allowed,Allowed" bitfld.long 0x00 26. " En_58 ,DMA region access enable for bit 58" "Not allowed,Allowed" bitfld.long 0x00 25. " En_57 ,DMA region access enable for bit 57" "Not allowed,Allowed" bitfld.long 0x00 24. " En_56 ,DMA region access enable for bit 56" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_55 ,DMA region access enable for bit 55" "Not allowed,Allowed" bitfld.long 0x00 22. " En_54 ,DMA region access enable for bit 54" "Not allowed,Allowed" bitfld.long 0x00 21. " En_53 ,DMA region access enable for bit 53" "Not allowed,Allowed" bitfld.long 0x00 20. " En_52 ,DMA region access enable for bit 52" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_51 ,DMA region access enable for bit 51" "Not allowed,Allowed" bitfld.long 0x00 18. " En_50 ,DMA region access enable for bit 50" "Not allowed,Allowed" bitfld.long 0x00 17. " En_49 ,DMA region access enable for bit 49" "Not allowed,Allowed" bitfld.long 0x00 16. " En_48 ,DMA region access enable for bit 48" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_47 ,DMA region access enable for bit 47" "Not allowed,Allowed" bitfld.long 0x00 14. " En_46 ,DMA region access enable for bit 46" "Not allowed,Allowed" bitfld.long 0x00 13. " En_45 ,DMA region access enable for bit 45" "Not allowed,Allowed" bitfld.long 0x00 12. " En_44 ,DMA region access enable for bit 44" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_43 ,DMA region access enable for bit 43" "Not allowed,Allowed" bitfld.long 0x00 10. " En_42 ,DMA region access enable for bit 42" "Not allowed,Allowed" bitfld.long 0x00 9. " En_41 ,DMA region access enable for bit 41" "Not allowed,Allowed" bitfld.long 0x00 8. " En_40 ,DMA region access enable for bit 40" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_39 ,DMA region access enable for bit 39" "Not allowed,Allowed" bitfld.long 0x00 6. " En_38 ,DMA region access enable for bit 38" "Not allowed,Allowed" bitfld.long 0x00 5. " En_37 ,DMA region access enable for bit 37" "Not allowed,Allowed" bitfld.long 0x00 4. " En_36 ,DMA region access enable for bit 36" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_35 ,DMA region access enable for bit 35" "Not allowed,Allowed" bitfld.long 0x00 2. " En_34 ,DMA region access enable for bit 34" "Not allowed,Allowed" bitfld.long 0x00 1. " En_33 ,DMA region access enable for bit 33" "Not allowed,Allowed" bitfld.long 0x00 0. " En_32 ,DMA region access enable for bit 32" "Not allowed,Allowed" group.long 0x0378++0x03 line.long 0x00 "DRAE[7],DMA Region Access Enable Register for Region 7" bitfld.long 0x00 31. " En_31 ,DMA region access enable for bit 31" "Not allowed,Allowed" bitfld.long 0x00 30. " En_30 ,DMA region access enable for bit 30" "Not allowed,Allowed" bitfld.long 0x00 29. " En_29 ,DMA region access enable for bit 29" "Not allowed,Allowed" bitfld.long 0x00 28. " En_28 ,DMA region access enable for bit 28" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_27 ,DMA region access enable for bit 27" "Not allowed,Allowed" bitfld.long 0x00 26. " En_26 ,DMA region access enable for bit 26" "Not allowed,Allowed" bitfld.long 0x00 25. " En_25 ,DMA region access enable for bit 25" "Not allowed,Allowed" bitfld.long 0x00 24. " En_24 ,DMA region access enable for bit 24" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_23 ,DMA region access enable for bit 23" "Not allowed,Allowed" bitfld.long 0x00 22. " En_22 ,DMA region access enable for bit 22" "Not allowed,Allowed" bitfld.long 0x00 21. " En_21 ,DMA region access enable for bit 21" "Not allowed,Allowed" bitfld.long 0x00 20. " En_20 ,DMA region access enable for bit 20" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_19 ,DMA region access enable for bit 19" "Not allowed,Allowed" bitfld.long 0x00 18. " En_18 ,DMA region access enable for bit 18" "Not allowed,Allowed" bitfld.long 0x00 17. " En_17 ,DMA region access enable for bit 17" "Not allowed,Allowed" bitfld.long 0x00 16. " En_16 ,DMA region access enable for bit 16" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_15 ,DMA region access enable for bit 15" "Not allowed,Allowed" bitfld.long 0x00 14. " En_14 ,DMA region access enable for bit 14" "Not allowed,Allowed" bitfld.long 0x00 13. " En_13 ,DMA region access enable for bit 13" "Not allowed,Allowed" bitfld.long 0x00 12. " En_12 ,DMA region access enable for bit 12" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_11 ,DMA region access enable for bit 11" "Not allowed,Allowed" bitfld.long 0x00 10. " En_10 ,DMA region access enable for bit 10" "Not allowed,Allowed" bitfld.long 0x00 9. " En_9 ,DMA region access enable for bit 9" "Not allowed,Allowed" bitfld.long 0x00 8. " En_8 ,DMA region access enable for bit 8" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_7 ,DMA region access enable for bit 7" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,DMA region access enable for bit 6" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,DMA region access enable for bit 5" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,DMA region access enable for bit 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,DMA region access enable for bit 3" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,DMA region access enable for bit 2" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,DMA region access enable for bit 1" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,DMA region access enable for bit 0" "Not allowed,Allowed" group.long 0x037C++0x03 line.long 0x00 "DRAEH[7],DMA Region Access Enable Register High for Region 7" bitfld.long 0x00 31. " En_63 ,DMA region access enable for bit 63" "Not allowed,Allowed" bitfld.long 0x00 30. " En_62 ,DMA region access enable for bit 62" "Not allowed,Allowed" bitfld.long 0x00 29. " En_61 ,DMA region access enable for bit 61" "Not allowed,Allowed" bitfld.long 0x00 28. " En_60 ,DMA region access enable for bit 60" "Not allowed,Allowed" textline " " bitfld.long 0x00 27. " En_59 ,DMA region access enable for bit 59" "Not allowed,Allowed" bitfld.long 0x00 26. " En_58 ,DMA region access enable for bit 58" "Not allowed,Allowed" bitfld.long 0x00 25. " En_57 ,DMA region access enable for bit 57" "Not allowed,Allowed" bitfld.long 0x00 24. " En_56 ,DMA region access enable for bit 56" "Not allowed,Allowed" textline " " bitfld.long 0x00 23. " En_55 ,DMA region access enable for bit 55" "Not allowed,Allowed" bitfld.long 0x00 22. " En_54 ,DMA region access enable for bit 54" "Not allowed,Allowed" bitfld.long 0x00 21. " En_53 ,DMA region access enable for bit 53" "Not allowed,Allowed" bitfld.long 0x00 20. " En_52 ,DMA region access enable for bit 52" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " En_51 ,DMA region access enable for bit 51" "Not allowed,Allowed" bitfld.long 0x00 18. " En_50 ,DMA region access enable for bit 50" "Not allowed,Allowed" bitfld.long 0x00 17. " En_49 ,DMA region access enable for bit 49" "Not allowed,Allowed" bitfld.long 0x00 16. " En_48 ,DMA region access enable for bit 48" "Not allowed,Allowed" textline " " bitfld.long 0x00 15. " En_47 ,DMA region access enable for bit 47" "Not allowed,Allowed" bitfld.long 0x00 14. " En_46 ,DMA region access enable for bit 46" "Not allowed,Allowed" bitfld.long 0x00 13. " En_45 ,DMA region access enable for bit 45" "Not allowed,Allowed" bitfld.long 0x00 12. " En_44 ,DMA region access enable for bit 44" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " En_43 ,DMA region access enable for bit 43" "Not allowed,Allowed" bitfld.long 0x00 10. " En_42 ,DMA region access enable for bit 42" "Not allowed,Allowed" bitfld.long 0x00 9. " En_41 ,DMA region access enable for bit 41" "Not allowed,Allowed" bitfld.long 0x00 8. " En_40 ,DMA region access enable for bit 40" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " En_39 ,DMA region access enable for bit 39" "Not allowed,Allowed" bitfld.long 0x00 6. " En_38 ,DMA region access enable for bit 38" "Not allowed,Allowed" bitfld.long 0x00 5. " En_37 ,DMA region access enable for bit 37" "Not allowed,Allowed" bitfld.long 0x00 4. " En_36 ,DMA region access enable for bit 36" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_35 ,DMA region access enable for bit 35" "Not allowed,Allowed" bitfld.long 0x00 2. " En_34 ,DMA region access enable for bit 34" "Not allowed,Allowed" bitfld.long 0x00 1. " En_33 ,DMA region access enable for bit 33" "Not allowed,Allowed" bitfld.long 0x00 0. " En_32 ,DMA region access enable for bit 32" "Not allowed,Allowed" tree.end width 9. tree "QRAE - array[8]" group.long 0x0380++0x03 line.long 0x00 "QRAE[0],QDMA Region Access Enable Registers for Region 0" bitfld.long 0x00 7. " En_7 ,QDMA region access enable for bit 7/QDMA channel 7 in region 0" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,QDMA region access enable for bit 6/QDMA channel 6 in region 0" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,QDMA region access enable for bit 5/QDMA channel 5 in region 0" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,QDMA region access enable for bit 4/QDMA channel 4 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,QDMA region access enable for bit 3/QDMA channel 3 in region 0" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,QDMA region access enable for bit 2/QDMA channel 2 in region 0" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,QDMA region access enable for bit 1/QDMA channel 1 in region 0" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,QDMA region access enable for bit 0/QDMA channel 0 in region 0" "Not allowed,Allowed" group.long 0x0384++0x03 line.long 0x00 "QRAE[1],QDMA Region Access Enable Registers for Region 1" bitfld.long 0x00 7. " En_7 ,QDMA region access enable for bit 7/QDMA channel 7 in region 1" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,QDMA region access enable for bit 6/QDMA channel 6 in region 1" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,QDMA region access enable for bit 5/QDMA channel 5 in region 1" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,QDMA region access enable for bit 4/QDMA channel 4 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,QDMA region access enable for bit 3/QDMA channel 3 in region 1" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,QDMA region access enable for bit 2/QDMA channel 2 in region 1" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,QDMA region access enable for bit 1/QDMA channel 1 in region 1" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,QDMA region access enable for bit 0/QDMA channel 0 in region 1" "Not allowed,Allowed" group.long 0x0388++0x03 line.long 0x00 "QRAE[2],QDMA Region Access Enable Registers for Region 2" bitfld.long 0x00 7. " En_7 ,QDMA region access enable for bit 7/QDMA channel 7 in region 2" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,QDMA region access enable for bit 6/QDMA channel 6 in region 2" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,QDMA region access enable for bit 5/QDMA channel 5 in region 2" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,QDMA region access enable for bit 4/QDMA channel 4 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,QDMA region access enable for bit 3/QDMA channel 3 in region 2" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,QDMA region access enable for bit 2/QDMA channel 2 in region 2" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,QDMA region access enable for bit 1/QDMA channel 1 in region 2" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,QDMA region access enable for bit 0/QDMA channel 0 in region 2" "Not allowed,Allowed" group.long 0x038C++0x03 line.long 0x00 "QRAE[3],QDMA Region Access Enable Registers for Region 3" bitfld.long 0x00 7. " En_7 ,QDMA region access enable for bit 7/QDMA channel 7 in region 3" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,QDMA region access enable for bit 6/QDMA channel 6 in region 3" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,QDMA region access enable for bit 5/QDMA channel 5 in region 3" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,QDMA region access enable for bit 4/QDMA channel 4 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,QDMA region access enable for bit 3/QDMA channel 3 in region 3" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,QDMA region access enable for bit 2/QDMA channel 2 in region 3" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,QDMA region access enable for bit 1/QDMA channel 1 in region 3" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,QDMA region access enable for bit 0/QDMA channel 0 in region 3" "Not allowed,Allowed" group.long 0x0390++0x03 line.long 0x00 "QRAE[4],QDMA Region Access Enable Registers for Region 4" bitfld.long 0x00 7. " En_7 ,QDMA region access enable for bit 7/QDMA channel 7 in region 4" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,QDMA region access enable for bit 6/QDMA channel 6 in region 4" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,QDMA region access enable for bit 5/QDMA channel 5 in region 4" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,QDMA region access enable for bit 4/QDMA channel 4 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,QDMA region access enable for bit 3/QDMA channel 3 in region 4" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,QDMA region access enable for bit 2/QDMA channel 2 in region 4" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,QDMA region access enable for bit 1/QDMA channel 1 in region 4" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,QDMA region access enable for bit 0/QDMA channel 0 in region 4" "Not allowed,Allowed" group.long 0x0394++0x03 line.long 0x00 "QRAE[5],QDMA Region Access Enable Registers for Region 5" bitfld.long 0x00 7. " En_7 ,QDMA region access enable for bit 7/QDMA channel 7 in region 5" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,QDMA region access enable for bit 6/QDMA channel 6 in region 5" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,QDMA region access enable for bit 5/QDMA channel 5 in region 5" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,QDMA region access enable for bit 4/QDMA channel 4 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,QDMA region access enable for bit 3/QDMA channel 3 in region 5" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,QDMA region access enable for bit 2/QDMA channel 2 in region 5" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,QDMA region access enable for bit 1/QDMA channel 1 in region 5" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,QDMA region access enable for bit 0/QDMA channel 0 in region 5" "Not allowed,Allowed" group.long 0x0398++0x03 line.long 0x00 "QRAE[6],QDMA Region Access Enable Registers for Region 6" bitfld.long 0x00 7. " En_7 ,QDMA region access enable for bit 7/QDMA channel 7 in region 6" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,QDMA region access enable for bit 6/QDMA channel 6 in region 6" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,QDMA region access enable for bit 5/QDMA channel 5 in region 6" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,QDMA region access enable for bit 4/QDMA channel 4 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,QDMA region access enable for bit 3/QDMA channel 3 in region 6" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,QDMA region access enable for bit 2/QDMA channel 2 in region 6" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,QDMA region access enable for bit 1/QDMA channel 1 in region 6" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,QDMA region access enable for bit 0/QDMA channel 0 in region 6" "Not allowed,Allowed" group.long 0x039C++0x03 line.long 0x00 "QRAE[7],QDMA Region Access Enable Registers for Region 7" bitfld.long 0x00 7. " En_7 ,QDMA region access enable for bit 7/QDMA channel 7 in region 7" "Not allowed,Allowed" bitfld.long 0x00 6. " En_6 ,QDMA region access enable for bit 6/QDMA channel 6 in region 7" "Not allowed,Allowed" bitfld.long 0x00 5. " En_5 ,QDMA region access enable for bit 5/QDMA channel 5 in region 7" "Not allowed,Allowed" bitfld.long 0x00 4. " En_4 ,QDMA region access enable for bit 4/QDMA channel 4 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " En_3 ,QDMA region access enable for bit 3/QDMA channel 3 in region 7" "Not allowed,Allowed" bitfld.long 0x00 2. " En_2 ,QDMA region access enable for bit 2/QDMA channel 2 in region 7" "Not allowed,Allowed" bitfld.long 0x00 1. " En_1 ,QDMA region access enable for bit 1/QDMA channel 1 in region 7" "Not allowed,Allowed" bitfld.long 0x00 0. " En_0 ,QDMA region access enable for bit 0/QDMA channel 0 in region 7" "Not allowed,Allowed" tree.end tree "Q0E - array[16]" rgroup.long 0x400++0x03 line.long 0x00 "Q0E[0],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x404++0x03 line.long 0x00 "Q0E[1],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x408++0x03 line.long 0x00 "Q0E[2],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x40C++0x03 line.long 0x00 "Q0E[3],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x410++0x03 line.long 0x00 "Q0E[4],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x414++0x03 line.long 0x00 "Q0E[5],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x418++0x03 line.long 0x00 "Q0E[6],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x41C++0x03 line.long 0x00 "Q0E[7],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x420++0x03 line.long 0x00 "Q0E[8],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x424++0x03 line.long 0x00 "Q0E[9],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x428++0x03 line.long 0x00 "Q0E[10],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x42C++0x03 line.long 0x00 "Q0E[11],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x430++0x03 line.long 0x00 "Q0E[12],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x434++0x03 line.long 0x00 "Q0E[13],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x438++0x03 line.long 0x00 "Q0E[14],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x43C++0x03 line.long 0x00 "Q0E[15],Event Queue 0 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Q1E - array[16]" rgroup.long 0x440++0x03 line.long 0x00 "Q1E[0],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x444++0x03 line.long 0x00 "Q1E[1],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x448++0x03 line.long 0x00 "Q1E[2],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x44C++0x03 line.long 0x00 "Q1E[3],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x450++0x03 line.long 0x00 "Q1E[4],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x454++0x03 line.long 0x00 "Q1E[5],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x458++0x03 line.long 0x00 "Q1E[6],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x45C++0x03 line.long 0x00 "Q1E[7],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x460++0x03 line.long 0x00 "Q1E[8],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x464++0x03 line.long 0x00 "Q1E[9],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x468++0x03 line.long 0x00 "Q1E[10],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x46C++0x03 line.long 0x00 "Q1E[11],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x470++0x03 line.long 0x00 "Q1E[12],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x474++0x03 line.long 0x00 "Q1E[13],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x478++0x03 line.long 0x00 "Q1E[14],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x47C++0x03 line.long 0x00 "Q1E[15],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "Q2E - array[16]" group.long 0x480++0x03 line.long 0x00 "Q2E[0],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x484++0x03 line.long 0x00 "Q2E[1],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x488++0x03 line.long 0x00 "Q2E[2],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x48C++0x03 line.long 0x00 "Q2E[3],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x490++0x03 line.long 0x00 "Q2E[4],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x494++0x03 line.long 0x00 "Q2E[5],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x498++0x03 line.long 0x00 "Q2E[6],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x49C++0x03 line.long 0x00 "Q2E[7],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4A0++0x03 line.long 0x00 "Q2E[8],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4A4++0x03 line.long 0x00 "Q2E[9],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4A8++0x03 line.long 0x00 "Q2E[10],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4AC++0x03 line.long 0x00 "Q2E[11],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4B0++0x03 line.long 0x00 "Q2E[12],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4B4++0x03 line.long 0x00 "Q2E[13],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4B8++0x03 line.long 0x00 "Q2E[14],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4BC++0x03 line.long 0x00 "Q2E[15],Event Queue 1 Entry y Register" bitfld.long 0x00 6.--7. " ETYPE ,Event entry y in queue 0" "ER,QER,," bitfld.long 0x00 0.--5. " ENUM ,Event entry y in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end width 10. tree "QSTAT - array[3]" rgroup.long 0x0600++0x03 line.long 0x00 "QSTAT[0],Queue Status Registers 0" bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x0604++0x03 line.long 0x00 "QSTAT[1],Queue Status Registers 1" bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x0608++0x03 line.long 0x00 "QSTAT[2],Queue Status Registers 2" bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end textline " " width 9. group.long 0x0620++0x03 line.long 0x00 "QWMTHRA,Queue Watermark Threshold A Register" bitfld.long 0x00 16.--20. " Q2 ,Queue threshold for queue 2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,,,,,,,,,,,,,," bitfld.long 0x00 8.--12. " Q1 ,Queue threshold for queue 1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,,,,,,,,,,,,,," bitfld.long 0x00 0.--4. " Q0 ,Queue threshold for queue 0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,,,,,,,,,,,,,," rgroup.long 0x0640++0x03 line.long 0x00 "CCSTAT,EDMA3CC Status Register" bitfld.long 0x00 18. " QUEACTV2 ,Queue 2 active" "No event,Event" bitfld.long 0x00 17. " QUEACTV1 ,Queue 1 active" "No event,Event" bitfld.long 0x00 16. " QUEACTV0 ,Queue 0 active" "No event,Event" bitfld.long 0x00 8.--13. " COMPACTV ,Completion request active" "No request,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 4. " ACTV ,Channel controller active" "Idle,Busy" bitfld.long 0x00 2. " TRACTV ,Transfer request active" "Inactive,Active" bitfld.long 0x00 1. " QEVTACTV ,QDMA event active" "Inactive,Active" bitfld.long 0x00 0. " EVTACTV ,DMA event active" "Inactive,Active" rgroup.long 0x0800++0x03 line.long 0x00 "MPFAR,Memory Protection Fault Address Register" rgroup.long 0x0804++0x03 line.long 0x00 "MPFSR,Memory Protection Fault Status Register" bitfld.long 0x00 9.--12. " FID ,Faulted identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " SRE ,Supervisor read error" "No error,Error" bitfld.long 0x00 4. " SWE ,Supervisor write error" "No error,Error" textline " " bitfld.long 0x00 3. " SXE ,Supervisor execute error" "No error,Error" bitfld.long 0x00 2. " URE ,User read error" "No error,Error" bitfld.long 0x00 1. " UWE ,User write error" "No error,Error" bitfld.long 0x00 0. " UXE ,User execute error" "No error,Error" wgroup.long 0x0808++0x03 line.long 0x00 "MPFCR,Memory Protection Fault Command Register" bitfld.long 0x00 0. " MPFCLR ,Fault clear register" "No effect,Cleared" group.long 0x080C++0x03 line.long 0x00 "MPPAG,Memory Protection Page Attribute Register Global" bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed" bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed" bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed" bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed" bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed" bitfld.long 0x00 9. " EXT ,External Allowed ID" "Not allowed,Allowed" bitfld.long 0x00 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed" tree "MPPA - array[8]" group.long 0x0810++0x03 line.long 0x00 "MPPA[0],Memory Protection Page Attribute Register" bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed" bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed" bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed" bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed" bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed" bitfld.long 0x00 10. " EXT ,External Allowed ID" "Not allowed,Allowed" bitfld.long 0x00 6. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 5. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 4. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 3. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " UX ,User execute permission" "Not allowed,Allowed" group.long 0x0814++0x03 line.long 0x00 "MPPA[1],Memory Protection Page Attribute Register" bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed" bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed" bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed" bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed" bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed" bitfld.long 0x00 10. " EXT ,External Allowed ID" "Not allowed,Allowed" bitfld.long 0x00 6. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 5. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 4. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 3. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " UX ,User execute permission" "Not allowed,Allowed" group.long 0x0818++0x03 line.long 0x00 "MPPA[2],Memory Protection Page Attribute Register" bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed" bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed" bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed" bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed" bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed" bitfld.long 0x00 10. " EXT ,External Allowed ID" "Not allowed,Allowed" bitfld.long 0x00 6. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 5. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 4. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 3. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " UX ,User execute permission" "Not allowed,Allowed" group.long 0x081C++0x03 line.long 0x00 "MPPA[3],Memory Protection Page Attribute Register" bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed" bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed" bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed" bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed" bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed" bitfld.long 0x00 10. " EXT ,External Allowed ID" "Not allowed,Allowed" bitfld.long 0x00 6. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 5. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 4. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 3. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " UX ,User execute permission" "Not allowed,Allowed" group.long 0x0820++0x03 line.long 0x00 "MPPA[4],Memory Protection Page Attribute Register" bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed" bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed" bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed" bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed" bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed" bitfld.long 0x00 10. " EXT ,External Allowed ID" "Not allowed,Allowed" bitfld.long 0x00 6. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 5. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 4. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 3. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " UX ,User execute permission" "Not allowed,Allowed" group.long 0x0824++0x03 line.long 0x00 "MPPA[5],Memory Protection Page Attribute Register" bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed" bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed" bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed" bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed" bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed" bitfld.long 0x00 10. " EXT ,External Allowed ID" "Not allowed,Allowed" bitfld.long 0x00 6. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 5. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 4. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 3. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " UX ,User execute permission" "Not allowed,Allowed" group.long 0x0828++0x03 line.long 0x00 "MPPA[6],Memory Protection Page Attribute Register" bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed" bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed" bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed" bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed" bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed" bitfld.long 0x00 10. " EXT ,External Allowed ID" "Not allowed,Allowed" bitfld.long 0x00 6. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 5. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 4. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 3. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " UX ,User execute permission" "Not allowed,Allowed" group.long 0x082C++0x03 line.long 0x00 "MPPA[7],Memory Protection Page Attribute Register" bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed" bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed" bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed" bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed" bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed" bitfld.long 0x00 10. " EXT ,External Allowed ID" "Not allowed,Allowed" bitfld.long 0x00 6. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 5. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 4. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 3. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " UX ,User execute permission" "Not allowed,Allowed" tree.end textline " " width 7. rgroup.long 0x1000++0x03 line.long 0x00 "ER,Event Register" bitfld.long 0x00 31. " En_31 ,Event 31" "Not asserted,Asserted" bitfld.long 0x00 30. " En_30 ,Event 30" "Not asserted,Asserted" bitfld.long 0x00 29. " En_29 ,Event 29" "Not asserted,Asserted" bitfld.long 0x00 28. " En_28 ,Event 28" "Not asserted,Asserted" textline " " bitfld.long 0x00 27. " En_27 ,Event 27" "Not asserted,Asserted" bitfld.long 0x00 26. " En_26 ,Event 26" "Not asserted,Asserted" bitfld.long 0x00 25. " En_25 ,Event 25" "Not asserted,Asserted" bitfld.long 0x00 24. " En_24 ,Event 24" "Not asserted,Asserted" textline " " bitfld.long 0x00 23. " En_23 ,Event 23" "Not asserted,Asserted" bitfld.long 0x00 22. " En_22 ,Event 22" "Not asserted,Asserted" bitfld.long 0x00 21. " En_21 ,Event 21" "Not asserted,Asserted" bitfld.long 0x00 20. " En_20 ,Event 20" "Not asserted,Asserted" textline " " bitfld.long 0x00 19. " En_19 ,Event 19" "Not asserted,Asserted" bitfld.long 0x00 18. " En_18 ,Event 18" "Not asserted,Asserted" bitfld.long 0x00 17. " En_17 ,Event 17" "Not asserted,Asserted" bitfld.long 0x00 16. " En_16 ,Event 16" "Not asserted,Asserted" textline " " bitfld.long 0x00 15. " En_15 ,Event 15" "Not asserted,Asserted" bitfld.long 0x00 14. " En_14 ,Event 14" "Not asserted,Asserted" bitfld.long 0x00 13. " En_13 ,Event 13" "Not asserted,Asserted" bitfld.long 0x00 12. " En_12 ,Event 12" "Not asserted,Asserted" textline " " bitfld.long 0x00 11. " En_11 ,Event 11" "Not asserted,Asserted" bitfld.long 0x00 10. " En_10 ,Event 10" "Not asserted,Asserted" bitfld.long 0x00 9. " En_9 ,Event 9" "Not asserted,Asserted" bitfld.long 0x00 8. " En_8 ,Event 8" "Not asserted,Asserted" textline " " bitfld.long 0x00 7. " En_7 ,Event 7" "Not asserted,Asserted" bitfld.long 0x00 6. " En_6 ,Event 6" "Not asserted,Asserted" bitfld.long 0x00 5. " En_5 ,Event 5" "Not asserted,Asserted" bitfld.long 0x00 4. " En_4 ,Event 4" "Not asserted,Asserted" textline " " bitfld.long 0x00 3. " En_3 ,Event 3" "Not asserted,Asserted" bitfld.long 0x00 2. " En_2 ,Event 2" "Not asserted,Asserted" bitfld.long 0x00 1. " En_1 ,Event 1" "Not asserted,Asserted" bitfld.long 0x00 0. " En_0 ,Event 0" "Not asserted,Asserted" rgroup.long 0x1004++0x03 line.long 0x00 "ERH,Event Register High" bitfld.long 0x00 31. " En_63 ,Event 63" "Not asserted,Asserted" bitfld.long 0x00 30. " En_62 ,Event 62" "Not asserted,Asserted" bitfld.long 0x00 29. " En_61 ,Event 61" "Not asserted,Asserted" bitfld.long 0x00 28. " En_60 ,Event 60" "Not asserted,Asserted" textline " " bitfld.long 0x00 27. " En_59 ,Event 59" "Not asserted,Asserted" bitfld.long 0x00 26. " En_58 ,Event 58" "Not asserted,Asserted" bitfld.long 0x00 25. " En_57 ,Event 57" "Not asserted,Asserted" bitfld.long 0x00 24. " En_56 ,Event 56" "Not asserted,Asserted" textline " " bitfld.long 0x00 23. " En_55 ,Event 55" "Not asserted,Asserted" bitfld.long 0x00 22. " En_54 ,Event 54" "Not asserted,Asserted" bitfld.long 0x00 21. " En_53 ,Event 53" "Not asserted,Asserted" bitfld.long 0x00 20. " En_52 ,Event 52" "Not asserted,Asserted" textline " " bitfld.long 0x00 19. " En_51 ,Event 51" "Not asserted,Asserted" bitfld.long 0x00 18. " En_50 ,Event 50" "Not asserted,Asserted" bitfld.long 0x00 17. " En_49 ,Event 49" "Not asserted,Asserted" bitfld.long 0x00 16. " En_48 ,Event 48" "Not asserted,Asserted" textline " " bitfld.long 0x00 15. " En_47 ,Event 47" "Not asserted,Asserted" bitfld.long 0x00 14. " En_46 ,Event 46" "Not asserted,Asserted" bitfld.long 0x00 13. " En_45 ,Event 45" "Not asserted,Asserted" bitfld.long 0x00 12. " En_44 ,Event 44" "Not asserted,Asserted" textline " " bitfld.long 0x00 11. " En_43 ,Event 43" "Not asserted,Asserted" bitfld.long 0x00 10. " En_42 ,Event 42" "Not asserted,Asserted" bitfld.long 0x00 9. " En_41 ,Event 41" "Not asserted,Asserted" bitfld.long 0x00 8. " En_40 ,Event 40" "Not asserted,Asserted" textline " " bitfld.long 0x00 7. " En_39 ,Event 39" "Not asserted,Asserted" bitfld.long 0x00 6. " En_38 ,Event 38" "Not asserted,Asserted" bitfld.long 0x00 5. " En_37 ,Event 37" "Not asserted,Asserted" bitfld.long 0x00 4. " En_36 ,Event 36" "Not asserted,Asserted" textline " " bitfld.long 0x00 3. " En_35 ,Event 35" "Not asserted,Asserted" bitfld.long 0x00 2. " En_34 ,Event 34" "Not asserted,Asserted" bitfld.long 0x00 1. " En_33 ,Event 33" "Not asserted,Asserted" bitfld.long 0x00 0. " En_32 ,Event 32" "Not asserted,Asserted" wgroup.long 0x1008++0x03 line.long 0x00 "ECR,Event Clear Register" bitfld.long 0x00 31. " En_31 ,Event clear for event 31" "No effect,Cleared" bitfld.long 0x00 30. " En_30 ,Event clear for event 30" "No effect,Cleared" bitfld.long 0x00 29. " En_29 ,Event clear for event 29" "No effect,Cleared" bitfld.long 0x00 28. " En_28 ,Event clear for event 28" "No effect,Cleared" textline " " bitfld.long 0x00 27. " En_27 ,Event clear for event 27" "No effect,Cleared" bitfld.long 0x00 26. " En_26 ,Event clear for event 26" "No effect,Cleared" bitfld.long 0x00 25. " En_25 ,Event clear for event 25" "No effect,Cleared" bitfld.long 0x00 24. " En_24 ,Event clear for event 24" "No effect,Cleared" textline " " bitfld.long 0x00 23. " En_23 ,Event clear for event 23" "No effect,Cleared" bitfld.long 0x00 22. " En_22 ,Event clear for event 22" "No effect,Cleared" bitfld.long 0x00 21. " En_21 ,Event clear for event 21" "No effect,Cleared" bitfld.long 0x00 20. " En_20 ,Event clear for event 20" "No effect,Cleared" textline " " bitfld.long 0x00 19. " En_19 ,Event clear for event 19" "No effect,Cleared" bitfld.long 0x00 18. " En_18 ,Event clear for event 18" "No effect,Cleared" bitfld.long 0x00 17. " En_17 ,Event clear for event 17" "No effect,Cleared" bitfld.long 0x00 16. " En_16 ,Event clear for event 16" "No effect,Cleared" textline " " bitfld.long 0x00 15. " En_15 ,Event clear for event 15" "No effect,Cleared" bitfld.long 0x00 14. " En_14 ,Event clear for event 14" "No effect,Cleared" bitfld.long 0x00 13. " En_13 ,Event clear for event 13" "No effect,Cleared" bitfld.long 0x00 12. " En_12 ,Event clear for event 12" "No effect,Cleared" textline " " bitfld.long 0x00 11. " En_11 ,Event clear for event 11" "No effect,Cleared" bitfld.long 0x00 10. " En_10 ,Event clear for event 10" "No effect,Cleared" bitfld.long 0x00 9. " En_9 ,Event clear for event 9" "No effect,Cleared" bitfld.long 0x00 8. " En_8 ,Event clear for event 8" "No effect,Cleared" textline " " bitfld.long 0x00 7. " En_7 ,Event clear for event 7" "No effect,Cleared" bitfld.long 0x00 6. " En_6 ,Event clear for event 6" "No effect,Cleared" bitfld.long 0x00 5. " En_5 ,Event clear for event 5" "No effect,Cleared" bitfld.long 0x00 4. " En_4 ,Event clear for event 4" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_3 ,Event clear for event 3" "No effect,Cleared" bitfld.long 0x00 2. " En_2 ,Event clear for event 2" "No effect,Cleared" bitfld.long 0x00 1. " En_1 ,Event clear for event 1" "No effect,Cleared" bitfld.long 0x00 0. " En_0 ,Event clear for event 0" "No effect,Cleared" wgroup.long 0x100C++0x03 line.long 0x00 "ECRH,Event Clear Register High" bitfld.long 0x00 31. " En_63 ,Event clear for event 63" "No effect,Cleared" bitfld.long 0x00 30. " En_62 ,Event clear for event 62" "No effect,Cleared" bitfld.long 0x00 29. " En_61 ,Event clear for event 61" "No effect,Cleared" bitfld.long 0x00 28. " En_60 ,Event clear for event 60" "No effect,Cleared" textline " " bitfld.long 0x00 27. " En_59 ,Event clear for event 59" "No effect,Cleared" bitfld.long 0x00 26. " En_58 ,Event clear for event 58" "No effect,Cleared" bitfld.long 0x00 25. " En_57 ,Event clear for event 57" "No effect,Cleared" bitfld.long 0x00 24. " En_56 ,Event clear for event 56" "No effect,Cleared" textline " " bitfld.long 0x00 23. " En_55 ,Event clear for event 55" "No effect,Cleared" bitfld.long 0x00 22. " En_54 ,Event clear for event 54" "No effect,Cleared" bitfld.long 0x00 21. " En_53 ,Event clear for event 53" "No effect,Cleared" bitfld.long 0x00 20. " En_52 ,Event clear for event 52" "No effect,Cleared" textline " " bitfld.long 0x00 19. " En_51 ,Event clear for event 51" "No effect,Cleared" bitfld.long 0x00 18. " En_50 ,Event clear for event 50" "No effect,Cleared" bitfld.long 0x00 17. " En_49 ,Event clear for event 49" "No effect,Cleared" bitfld.long 0x00 16. " En_48 ,Event clear for event 48" "No effect,Cleared" textline " " bitfld.long 0x00 15. " En_47 ,Event clear for event 47" "No effect,Cleared" bitfld.long 0x00 14. " En_46 ,Event clear for event 46" "No effect,Cleared" bitfld.long 0x00 13. " En_45 ,Event clear for event 45" "No effect,Cleared" bitfld.long 0x00 12. " En_44 ,Event clear for event 44" "No effect,Cleared" textline " " bitfld.long 0x00 11. " En_43 ,Event clear for event 43" "No effect,Cleared" bitfld.long 0x00 10. " En_42 ,Event clear for event 42" "No effect,Cleared" bitfld.long 0x00 9. " En_41 ,Event clear for event 41" "No effect,Cleared" bitfld.long 0x00 8. " En_40 ,Event clear for event 40" "No effect,Cleared" textline " " bitfld.long 0x00 7. " En_39 ,Event clear for event 39" "No effect,Cleared" bitfld.long 0x00 6. " En_38 ,Event clear for event 38" "No effect,Cleared" bitfld.long 0x00 5. " En_37 ,Event clear for event 37" "No effect,Cleared" bitfld.long 0x00 4. " En_36 ,Event clear for event 36" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_35 ,Event clear for event 35" "No effect,Cleared" bitfld.long 0x00 2. " En_34 ,Event clear for event 34" "No effect,Cleared" bitfld.long 0x00 1. " En_33 ,Event clear for event 33" "No effect,Cleared" bitfld.long 0x00 0. " En_32 ,Event clear for event 32" "No effect,Cleared" group.long 0x1010++0x03 line.long 0x00 "ESR,Event Set Register" bitfld.long 0x00 31. " En_31 ,Event set for event 31" "No effect,Set" bitfld.long 0x00 30. " En_30 ,Event set for event 30" "No effect,Set" bitfld.long 0x00 29. " En_29 ,Event set for event 29" "No effect,Set" bitfld.long 0x00 28. " En_28 ,Event set for event 28" "No effect,Set" textline " " bitfld.long 0x00 27. " En_27 ,Event set for event 27" "No effect,Set" bitfld.long 0x00 26. " En_26 ,Event set for event 26" "No effect,Set" bitfld.long 0x00 25. " En_25 ,Event set for event 25" "No effect,Set" bitfld.long 0x00 24. " En_24 ,Event set for event 24" "No effect,Set" textline " " bitfld.long 0x00 23. " En_23 ,Event set for event 23" "No effect,Set" bitfld.long 0x00 22. " En_22 ,Event set for event 22" "No effect,Set" bitfld.long 0x00 21. " En_21 ,Event set for event 21" "No effect,Set" bitfld.long 0x00 20. " En_20 ,Event set for event 20" "No effect,Set" textline " " bitfld.long 0x00 19. " En_19 ,Event set for event 19" "No effect,Set" bitfld.long 0x00 18. " En_18 ,Event set for event 18" "No effect,Set" bitfld.long 0x00 17. " En_17 ,Event set for event 17" "No effect,Set" bitfld.long 0x00 16. " En_16 ,Event set for event 16" "No effect,Set" textline " " bitfld.long 0x00 15. " En_15 ,Event set for event 15" "No effect,Set" bitfld.long 0x00 14. " En_14 ,Event set for event 14" "No effect,Set" bitfld.long 0x00 13. " En_13 ,Event set for event 13" "No effect,Set" bitfld.long 0x00 12. " En_12 ,Event set for event 12" "No effect,Set" textline " " bitfld.long 0x00 11. " En_11 ,Event set for event 11" "No effect,Set" bitfld.long 0x00 10. " En_10 ,Event set for event 10" "No effect,Set" bitfld.long 0x00 9. " En_9 ,Event set for event 9" "No effect,Set" bitfld.long 0x00 8. " En_8 ,Event set for event 8" "No effect,Set" textline " " bitfld.long 0x00 7. " En_7 ,Event set for event 7" "No effect,Set" bitfld.long 0x00 6. " En_6 ,Event set for event 6" "No effect,Set" bitfld.long 0x00 5. " En_5 ,Event set for event 5" "No effect,Set" bitfld.long 0x00 4. " En_4 ,Event set for event 4" "No effect,Set" textline " " bitfld.long 0x00 3. " En_3 ,Event set for event 3" "No effect,Set" bitfld.long 0x00 2. " En_2 ,Event set for event 2" "No effect,Set" bitfld.long 0x00 1. " En_1 ,Event set for event 1" "No effect,Set" bitfld.long 0x00 0. " En_0 ,Event set for event 0" "No effect,Set" group.long 0x1014++0x03 line.long 0x00 "ESRH,Event Set Register High" bitfld.long 0x00 31. " En_63 ,Event set for event 63" "No effect,Set" bitfld.long 0x00 30. " En_62 ,Event set for event 62" "No effect,Set" bitfld.long 0x00 29. " En_61 ,Event set for event 61" "No effect,Set" bitfld.long 0x00 28. " En_60 ,Event set for event 60" "No effect,Set" textline " " bitfld.long 0x00 27. " En_59 ,Event set for event 59" "No effect,Set" bitfld.long 0x00 26. " En_58 ,Event set for event 58" "No effect,Set" bitfld.long 0x00 25. " En_57 ,Event set for event 57" "No effect,Set" bitfld.long 0x00 24. " En_56 ,Event set for event 56" "No effect,Set" textline " " bitfld.long 0x00 23. " En_55 ,Event set for event 55" "No effect,Set" bitfld.long 0x00 22. " En_54 ,Event set for event 54" "No effect,Set" bitfld.long 0x00 21. " En_53 ,Event set for event 53" "No effect,Set" bitfld.long 0x00 20. " En_52 ,Event set for event 52" "No effect,Set" textline " " bitfld.long 0x00 19. " En_51 ,Event set for event 51" "No effect,Set" bitfld.long 0x00 18. " En_50 ,Event set for event 50" "No effect,Set" bitfld.long 0x00 17. " En_49 ,Event set for event 49" "No effect,Set" bitfld.long 0x00 16. " En_48 ,Event set for event 48" "No effect,Set" textline " " bitfld.long 0x00 15. " En_47 ,Event set for event 47" "No effect,Set" bitfld.long 0x00 14. " En_46 ,Event set for event 46" "No effect,Set" bitfld.long 0x00 13. " En_45 ,Event set for event 45" "No effect,Set" bitfld.long 0x00 12. " En_44 ,Event set for event 44" "No effect,Set" textline " " bitfld.long 0x00 11. " En_43 ,Event set for event 43" "No effect,Set" bitfld.long 0x00 10. " En_42 ,Event set for event 42" "No effect,Set" bitfld.long 0x00 9. " En_41 ,Event set for event 41" "No effect,Set" bitfld.long 0x00 8. " En_40 ,Event set for event 40" "No effect,Set" textline " " bitfld.long 0x00 7. " En_39 ,Event set for event 39" "No effect,Set" bitfld.long 0x00 6. " En_38 ,Event set for event 38" "No effect,Set" bitfld.long 0x00 5. " En_37 ,Event set for event 37" "No effect,Set" bitfld.long 0x00 4. " En_36 ,Event set for event 36" "No effect,Set" textline " " bitfld.long 0x00 3. " En_35 ,Event set for event 35" "No effect,Set" bitfld.long 0x00 2. " En_34 ,Event set for event 34" "No effect,Set" bitfld.long 0x00 1. " En_33 ,Event set for event 33" "No effect,Set" bitfld.long 0x00 0. " En_32 ,Event set for event 32" "No effect,Set" rgroup.long 0x1018++0x03 line.long 0x00 "CER,Chained Event Register" bitfld.long 0x00 31. " En_31 ,Chained event for event 31" "No effect,Trigger" bitfld.long 0x00 30. " En_30 ,Chained event for event 30" "No effect,Trigger" bitfld.long 0x00 29. " En_29 ,Chained event for event 29" "No effect,Trigger" bitfld.long 0x00 28. " En_28 ,Chained event for event 28" "No effect,Trigger" textline " " bitfld.long 0x00 27. " En_27 ,Chained event for event 27" "No effect,Trigger" bitfld.long 0x00 26. " En_26 ,Chained event for event 26" "No effect,Trigger" bitfld.long 0x00 25. " En_25 ,Chained event for event 25" "No effect,Trigger" bitfld.long 0x00 24. " En_24 ,Chained event for event 24" "No effect,Trigger" textline " " bitfld.long 0x00 23. " En_23 ,Chained event for event 23" "No effect,Trigger" bitfld.long 0x00 22. " En_22 ,Chained event for event 22" "No effect,Trigger" bitfld.long 0x00 21. " En_21 ,Chained event for event 21" "No effect,Trigger" bitfld.long 0x00 20. " En_20 ,Chained event for event 20" "No effect,Trigger" textline " " bitfld.long 0x00 19. " En_19 ,Chained event for event 19" "No effect,Trigger" bitfld.long 0x00 18. " En_18 ,Chained event for event 18" "No effect,Trigger" bitfld.long 0x00 17. " En_17 ,Chained event for event 17" "No effect,Trigger" bitfld.long 0x00 16. " En_16 ,Chained event for event 16" "No effect,Trigger" textline " " bitfld.long 0x00 15. " En_15 ,Chained event for event 15" "No effect,Trigger" bitfld.long 0x00 14. " En_14 ,Chained event for event 14" "No effect,Trigger" bitfld.long 0x00 13. " En_13 ,Chained event for event 13" "No effect,Trigger" bitfld.long 0x00 12. " En_12 ,Chained event for event 12" "No effect,Trigger" textline " " bitfld.long 0x00 11. " En_11 ,Chained event for event 11" "No effect,Trigger" bitfld.long 0x00 10. " En_10 ,Chained event for event 10" "No effect,Trigger" bitfld.long 0x00 9. " En_9 ,Chained event for event 9" "No effect,Trigger" bitfld.long 0x00 8. " En_8 ,Chained event for event 8" "No effect,Trigger" textline " " bitfld.long 0x00 7. " En_7 ,Chained event for event 7" "No effect,Trigger" bitfld.long 0x00 6. " En_6 ,Chained event for event 6" "No effect,Trigger" bitfld.long 0x00 5. " En_5 ,Chained event for event 5" "No effect,Trigger" bitfld.long 0x00 4. " En_4 ,Chained event for event 4" "No effect,Trigger" textline " " bitfld.long 0x00 3. " En_3 ,Chained event for event 3" "No effect,Trigger" bitfld.long 0x00 2. " En_2 ,Chained event for event 2" "No effect,Trigger" bitfld.long 0x00 1. " En_1 ,Chained event for event 1" "No effect,Trigger" bitfld.long 0x00 0. " En_0 ,Chained event for event 0" "No effect,Trigger" rgroup.long 0x101C++0x03 line.long 0x00 "CERH,Chained Event Register High" bitfld.long 0x00 31. " En_63 ,Chained event for event 63" "No effect,Trigger" bitfld.long 0x00 30. " En_62 ,Chained event for event 62" "No effect,Trigger" bitfld.long 0x00 29. " En_61 ,Chained event for event 61" "No effect,Trigger" bitfld.long 0x00 28. " En_60 ,Chained event for event 60" "No effect,Trigger" textline " " bitfld.long 0x00 27. " En_59 ,Chained event for event 59" "No effect,Trigger" bitfld.long 0x00 26. " En_58 ,Chained event for event 58" "No effect,Trigger" bitfld.long 0x00 25. " En_57 ,Chained event for event 57" "No effect,Trigger" bitfld.long 0x00 24. " En_56 ,Chained event for event 56" "No effect,Trigger" textline " " bitfld.long 0x00 23. " En_55 ,Chained event for event 55" "No effect,Trigger" bitfld.long 0x00 22. " En_54 ,Chained event for event 54" "No effect,Trigger" bitfld.long 0x00 21. " En_53 ,Chained event for event 53" "No effect,Trigger" bitfld.long 0x00 20. " En_52 ,Chained event for event 52" "No effect,Trigger" textline " " bitfld.long 0x00 19. " En_51 ,Chained event for event 51" "No effect,Trigger" bitfld.long 0x00 18. " En_50 ,Chained event for event 50" "No effect,Trigger" bitfld.long 0x00 17. " En_49 ,Chained event for event 49" "No effect,Trigger" bitfld.long 0x00 16. " En_48 ,Chained event for event 48" "No effect,Trigger" textline " " bitfld.long 0x00 15. " En_47 ,Chained event for event 47" "No effect,Trigger" bitfld.long 0x00 14. " En_46 ,Chained event for event 46" "No effect,Trigger" bitfld.long 0x00 13. " En_45 ,Chained event for event 45" "No effect,Trigger" bitfld.long 0x00 12. " En_44 ,Chained event for event 44" "No effect,Trigger" textline " " bitfld.long 0x00 11. " En_43 ,Chained event for event 43" "No effect,Trigger" bitfld.long 0x00 10. " En_42 ,Chained event for event 42" "No effect,Trigger" bitfld.long 0x00 9. " En_41 ,Chained event for event 41" "No effect,Trigger" bitfld.long 0x00 8. " En_40 ,Chained event for event 40" "No effect,Trigger" textline " " bitfld.long 0x00 7. " En_39 ,Chained event for event 39" "No effect,Trigger" bitfld.long 0x00 6. " En_38 ,Chained event for event 38" "No effect,Trigger" bitfld.long 0x00 5. " En_37 ,Chained event for event 37" "No effect,Trigger" bitfld.long 0x00 4. " En_36 ,Chained event for event 36" "No effect,Trigger" textline " " bitfld.long 0x00 3. " En_35 ,Chained event for event 35" "No effect,Trigger" bitfld.long 0x00 2. " En_34 ,Chained event for event 34" "No effect,Trigger" bitfld.long 0x00 1. " En_33 ,Chained event for event 33" "No effect,Trigger" bitfld.long 0x00 0. " En_32 ,Chained event for event 32" "No effect,Trigger" rgroup.long 0x1020++0x03 line.long 0x00 "EER,Event Enable Register" bitfld.long 0x00 31. " En_31 ,Event enable for events 31" "Disabled,Enabled" bitfld.long 0x00 30. " En_30 ,Event enable for events 30" "Disabled,Enabled" bitfld.long 0x00 29. " En_29 ,Event enable for events 29" "Disabled,Enabled" bitfld.long 0x00 28. " En_28 ,Event enable for events 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " En_27 ,Event enable for events 27" "Disabled,Enabled" bitfld.long 0x00 26. " En_26 ,Event enable for events 26" "Disabled,Enabled" bitfld.long 0x00 25. " En_25 ,Event enable for events 25" "Disabled,Enabled" bitfld.long 0x00 24. " En_24 ,Event enable for events 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " En_23 ,Event enable for events 23" "Disabled,Enabled" bitfld.long 0x00 22. " En_22 ,Event enable for events 22" "Disabled,Enabled" bitfld.long 0x00 21. " En_21 ,Event enable for events 21" "Disabled,Enabled" bitfld.long 0x00 20. " En_20 ,Event enable for events 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " En_19 ,Event enable for events 19" "Disabled,Enabled" bitfld.long 0x00 18. " En_18 ,Event enable for events 18" "Disabled,Enabled" bitfld.long 0x00 17. " En_17 ,Event enable for events 17" "Disabled,Enabled" bitfld.long 0x00 16. " En_16 ,Event enable for events 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " En_15 ,Event enable for events 15" "Disabled,Enabled" bitfld.long 0x00 14. " En_14 ,Event enable for events 14" "Disabled,Enabled" bitfld.long 0x00 13. " En_13 ,Event enable for events 13" "Disabled,Enabled" bitfld.long 0x00 12. " En_12 ,Event enable for events 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " En_11 ,Event enable for events 11" "Disabled,Enabled" bitfld.long 0x00 10. " En_10 ,Event enable for events 10" "Disabled,Enabled" bitfld.long 0x00 9. " En_9 ,Event enable for events 9" "Disabled,Enabled" bitfld.long 0x00 8. " En_8 ,Event enable for events 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " En_7 ,Event enable for events 7" "Disabled,Enabled" bitfld.long 0x00 6. " En_6 ,Event enable for events 6" "Disabled,Enabled" bitfld.long 0x00 5. " En_5 ,Event enable for events 5" "Disabled,Enabled" bitfld.long 0x00 4. " En_4 ,Event enable for events 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " En_3 ,Event enable for events 3" "Disabled,Enabled" bitfld.long 0x00 2. " En_2 ,Event enable for events 2" "Disabled,Enabled" bitfld.long 0x00 1. " En_1 ,Event enable for events 1" "Disabled,Enabled" bitfld.long 0x00 0. " En_0 ,Event enable for events 0" "Disabled,Enabled" rgroup.long 0x1024++0x03 line.long 0x00 "EERH,Event Enable Register High" bitfld.long 0x00 31. " En_63 ,Event enable for events 63" "Disabled,Enabled" bitfld.long 0x00 30. " En_62 ,Event enable for events 62" "Disabled,Enabled" bitfld.long 0x00 29. " En_61 ,Event enable for events 61" "Disabled,Enabled" bitfld.long 0x00 28. " En_60 ,Event enable for events 60" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " En_59 ,Event enable for events 59" "Disabled,Enabled" bitfld.long 0x00 26. " En_58 ,Event enable for events 58" "Disabled,Enabled" bitfld.long 0x00 25. " En_57 ,Event enable for events 57" "Disabled,Enabled" bitfld.long 0x00 24. " En_56 ,Event enable for events 56" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " En_55 ,Event enable for events 55" "Disabled,Enabled" bitfld.long 0x00 22. " En_54 ,Event enable for events 54" "Disabled,Enabled" bitfld.long 0x00 21. " En_53 ,Event enable for events 53" "Disabled,Enabled" bitfld.long 0x00 20. " En_52 ,Event enable for events 52" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " En_51 ,Event enable for events 51" "Disabled,Enabled" bitfld.long 0x00 18. " En_50 ,Event enable for events 50" "Disabled,Enabled" bitfld.long 0x00 17. " En_49 ,Event enable for events 49" "Disabled,Enabled" bitfld.long 0x00 16. " En_48 ,Event enable for events 48" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " En_47 ,Event enable for events 47" "Disabled,Enabled" bitfld.long 0x00 14. " En_46 ,Event enable for events 46" "Disabled,Enabled" bitfld.long 0x00 13. " En_45 ,Event enable for events 45" "Disabled,Enabled" bitfld.long 0x00 12. " En_44 ,Event enable for events 44" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " En_43 ,Event enable for events 43" "Disabled,Enabled" bitfld.long 0x00 10. " En_42 ,Event enable for events 42" "Disabled,Enabled" bitfld.long 0x00 9. " En_41 ,Event enable for events 41" "Disabled,Enabled" bitfld.long 0x00 8. " En_40 ,Event enable for events 40" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " En_39 ,Event enable for events 39" "Disabled,Enabled" bitfld.long 0x00 6. " En_38 ,Event enable for events 38" "Disabled,Enabled" bitfld.long 0x00 5. " En_37 ,Event enable for events 37" "Disabled,Enabled" bitfld.long 0x00 4. " En_36 ,Event enable for events 36" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " En_35 ,Event enable for events 35" "Disabled,Enabled" bitfld.long 0x00 2. " En_34 ,Event enable for events 34" "Disabled,Enabled" bitfld.long 0x00 1. " En_33 ,Event enable for events 33" "Disabled,Enabled" bitfld.long 0x00 0. " En_32 ,Event enable for events 32" "Disabled,Enabled" wgroup.long 0x1028++0x03 line.long 0x00 "EECR,Event Enable Clear Register" bitfld.long 0x00 31. " En_31 ,Event enable clear for events 31" "No effect,Cleared" bitfld.long 0x00 30. " En_30 ,Event enable clear for events 30" "No effect,Cleared" bitfld.long 0x00 29. " En_29 ,Event enable clear for events 29" "No effect,Cleared" bitfld.long 0x00 28. " En_28 ,Event enable clear for events 28" "No effect,Cleared" textline " " bitfld.long 0x00 27. " En_27 ,Event enable clear for events 27" "No effect,Cleared" bitfld.long 0x00 26. " En_26 ,Event enable clear for events 26" "No effect,Cleared" bitfld.long 0x00 25. " En_25 ,Event enable clear for events 25" "No effect,Cleared" bitfld.long 0x00 24. " En_24 ,Event enable clear for events 24" "No effect,Cleared" textline " " bitfld.long 0x00 23. " En_23 ,Event enable clear for events 23" "No effect,Cleared" bitfld.long 0x00 22. " En_22 ,Event enable clear for events 22" "No effect,Cleared" bitfld.long 0x00 21. " En_21 ,Event enable clear for events 21" "No effect,Cleared" bitfld.long 0x00 20. " En_20 ,Event enable clear for events 20" "No effect,Cleared" textline " " bitfld.long 0x00 19. " En_19 ,Event enable clear for events 19" "No effect,Cleared" bitfld.long 0x00 18. " En_18 ,Event enable clear for events 18" "No effect,Cleared" bitfld.long 0x00 17. " En_17 ,Event enable clear for events 17" "No effect,Cleared" bitfld.long 0x00 16. " En_16 ,Event enable clear for events 16" "No effect,Cleared" textline " " bitfld.long 0x00 15. " En_15 ,Event enable clear for events 15" "No effect,Cleared" bitfld.long 0x00 14. " En_14 ,Event enable clear for events 14" "No effect,Cleared" bitfld.long 0x00 13. " En_13 ,Event enable clear for events 13" "No effect,Cleared" bitfld.long 0x00 12. " En_12 ,Event enable clear for events 12" "No effect,Cleared" textline " " bitfld.long 0x00 11. " En_11 ,Event enable clear for events 11" "No effect,Cleared" bitfld.long 0x00 10. " En_10 ,Event enable clear for events 10" "No effect,Cleared" bitfld.long 0x00 9. " En_9 ,Event enable clear for events 9" "No effect,Cleared" bitfld.long 0x00 8. " En_8 ,Event enable clear for events 8" "No effect,Cleared" textline " " bitfld.long 0x00 7. " En_7 ,Event enable clear for events 7" "No effect,Cleared" bitfld.long 0x00 6. " En_6 ,Event enable clear for events 6" "No effect,Cleared" bitfld.long 0x00 5. " En_5 ,Event enable clear for events 5" "No effect,Cleared" bitfld.long 0x00 4. " En_4 ,Event enable clear for events 4" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_3 ,Event enable clear for events 3" "No effect,Cleared" bitfld.long 0x00 2. " En_2 ,Event enable clear for events 2" "No effect,Cleared" bitfld.long 0x00 1. " En_1 ,Event enable clear for events 1" "No effect,Cleared" bitfld.long 0x00 0. " En_0 ,Event enable clear for events 0" "No effect,Cleared" wgroup.long 0x102C++0x03 line.long 0x00 "EECRH,Event Enable Clear Register High" bitfld.long 0x00 31. " En_63 ,Event enable clear for events 63" "No effect,Cleared" bitfld.long 0x00 30. " En_62 ,Event enable clear for events 62" "No effect,Cleared" bitfld.long 0x00 29. " En_61 ,Event enable clear for events 61" "No effect,Cleared" bitfld.long 0x00 28. " En_60 ,Event enable clear for events 60" "No effect,Cleared" textline " " bitfld.long 0x00 27. " En_59 ,Event enable clear for events 59" "No effect,Cleared" bitfld.long 0x00 26. " En_58 ,Event enable clear for events 58" "No effect,Cleared" bitfld.long 0x00 25. " En_57 ,Event enable clear for events 57" "No effect,Cleared" bitfld.long 0x00 24. " En_56 ,Event enable clear for events 56" "No effect,Cleared" textline " " bitfld.long 0x00 23. " En_55 ,Event enable clear for events 55" "No effect,Cleared" bitfld.long 0x00 22. " En_54 ,Event enable clear for events 54" "No effect,Cleared" bitfld.long 0x00 21. " En_53 ,Event enable clear for events 53" "No effect,Cleared" bitfld.long 0x00 20. " En_52 ,Event enable clear for events 52" "No effect,Cleared" textline " " bitfld.long 0x00 19. " En_51 ,Event enable clear for events 51" "No effect,Cleared" bitfld.long 0x00 18. " En_50 ,Event enable clear for events 50" "No effect,Cleared" bitfld.long 0x00 17. " En_49 ,Event enable clear for events 49" "No effect,Cleared" bitfld.long 0x00 16. " En_48 ,Event enable clear for events 48" "No effect,Cleared" textline " " bitfld.long 0x00 15. " En_47 ,Event enable clear for events 47" "No effect,Cleared" bitfld.long 0x00 14. " En_46 ,Event enable clear for events 46" "No effect,Cleared" bitfld.long 0x00 13. " En_45 ,Event enable clear for events 45" "No effect,Cleared" bitfld.long 0x00 12. " En_44 ,Event enable clear for events 44" "No effect,Cleared" textline " " bitfld.long 0x00 11. " En_43 ,Event enable clear for events 43" "No effect,Cleared" bitfld.long 0x00 10. " En_42 ,Event enable clear for events 42" "No effect,Cleared" bitfld.long 0x00 9. " En_41 ,Event enable clear for events 41" "No effect,Cleared" bitfld.long 0x00 8. " En_40 ,Event enable clear for events 40" "No effect,Cleared" textline " " bitfld.long 0x00 7. " En_39 ,Event enable clear for events 39" "No effect,Cleared" bitfld.long 0x00 6. " En_38 ,Event enable clear for events 38" "No effect,Cleared" bitfld.long 0x00 5. " En_37 ,Event enable clear for events 37" "No effect,Cleared" bitfld.long 0x00 4. " En_36 ,Event enable clear for events 36" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_35 ,Event enable clear for events 35" "No effect,Cleared" bitfld.long 0x00 2. " En_34 ,Event enable clear for events 34" "No effect,Cleared" bitfld.long 0x00 1. " En_33 ,Event enable clear for events 33" "No effect,Cleared" bitfld.long 0x00 0. " En_32 ,Event enable clear for events 32" "No effect,Cleared" wgroup.long 0x1030++0x03 line.long 0x00 "EESR,Event Enable Set Register" bitfld.long 0x00 31. " En_31 ,Event enable set for events 31" "No effect,Enabled" bitfld.long 0x00 30. " En_30 ,Event enable set for events 30" "No effect,Enabled" bitfld.long 0x00 29. " En_29 ,Event enable set for events 29" "No effect,Enabled" bitfld.long 0x00 28. " En_28 ,Event enable set for events 28" "No effect,Enabled" textline " " bitfld.long 0x00 27. " En_27 ,Event enable set for events 27" "No effect,Enabled" bitfld.long 0x00 26. " En_26 ,Event enable set for events 26" "No effect,Enabled" bitfld.long 0x00 25. " En_25 ,Event enable set for events 25" "No effect,Enabled" bitfld.long 0x00 24. " En_24 ,Event enable set for events 24" "No effect,Enabled" textline " " bitfld.long 0x00 23. " En_23 ,Event enable set for events 23" "No effect,Enabled" bitfld.long 0x00 22. " En_22 ,Event enable set for events 22" "No effect,Enabled" bitfld.long 0x00 21. " En_21 ,Event enable set for events 21" "No effect,Enabled" bitfld.long 0x00 20. " En_20 ,Event enable set for events 20" "No effect,Enabled" textline " " bitfld.long 0x00 19. " En_19 ,Event enable set for events 19" "No effect,Enabled" bitfld.long 0x00 18. " En_18 ,Event enable set for events 18" "No effect,Enabled" bitfld.long 0x00 17. " En_17 ,Event enable set for events 17" "No effect,Enabled" bitfld.long 0x00 16. " En_16 ,Event enable set for events 16" "No effect,Enabled" textline " " bitfld.long 0x00 15. " En_15 ,Event enable set for events 15" "No effect,Enabled" bitfld.long 0x00 14. " En_14 ,Event enable set for events 14" "No effect,Enabled" bitfld.long 0x00 13. " En_13 ,Event enable set for events 13" "No effect,Enabled" bitfld.long 0x00 12. " En_12 ,Event enable set for events 12" "No effect,Enabled" textline " " bitfld.long 0x00 11. " En_11 ,Event enable set for events 11" "No effect,Enabled" bitfld.long 0x00 10. " En_10 ,Event enable set for events 10" "No effect,Enabled" bitfld.long 0x00 9. " En_9 ,Event enable set for events 9" "No effect,Enabled" bitfld.long 0x00 8. " En_8 ,Event enable set for events 8" "No effect,Enabled" textline " " bitfld.long 0x00 7. " En_7 ,Event enable set for events 7" "No effect,Enabled" bitfld.long 0x00 6. " En_6 ,Event enable set for events 6" "No effect,Enabled" bitfld.long 0x00 5. " En_5 ,Event enable set for events 5" "No effect,Enabled" bitfld.long 0x00 4. " En_4 ,Event enable set for events 4" "No effect,Enabled" textline " " bitfld.long 0x00 3. " En_3 ,Event enable set for events 3" "No effect,Enabled" bitfld.long 0x00 2. " En_2 ,Event enable set for events 2" "No effect,Enabled" bitfld.long 0x00 1. " En_1 ,Event enable set for events 1" "No effect,Enabled" bitfld.long 0x00 0. " En_0 ,Event enable set for events 0" "No effect,Enabled" wgroup.long 0x1034++0x03 line.long 0x00 "EESRH,Event Enable Set Register High" bitfld.long 0x00 31. " En_63 ,Event enable set for events 63" "No effect,Enabled" bitfld.long 0x00 30. " En_62 ,Event enable set for events 62" "No effect,Enabled" bitfld.long 0x00 29. " En_61 ,Event enable set for events 61" "No effect,Enabled" bitfld.long 0x00 28. " En_60 ,Event enable set for events 60" "No effect,Enabled" textline " " bitfld.long 0x00 27. " En_59 ,Event enable set for events 59" "No effect,Enabled" bitfld.long 0x00 26. " En_58 ,Event enable set for events 58" "No effect,Enabled" bitfld.long 0x00 25. " En_57 ,Event enable set for events 57" "No effect,Enabled" bitfld.long 0x00 24. " En_56 ,Event enable set for events 56" "No effect,Enabled" textline " " bitfld.long 0x00 23. " En_55 ,Event enable set for events 55" "No effect,Enabled" bitfld.long 0x00 22. " En_54 ,Event enable set for events 54" "No effect,Enabled" bitfld.long 0x00 21. " En_53 ,Event enable set for events 53" "No effect,Enabled" bitfld.long 0x00 20. " En_52 ,Event enable set for events 52" "No effect,Enabled" textline " " bitfld.long 0x00 19. " En_51 ,Event enable set for events 51" "No effect,Enabled" bitfld.long 0x00 18. " En_50 ,Event enable set for events 50" "No effect,Enabled" bitfld.long 0x00 17. " En_49 ,Event enable set for events 49" "No effect,Enabled" bitfld.long 0x00 16. " En_48 ,Event enable set for events 48" "No effect,Enabled" textline " " bitfld.long 0x00 15. " En_47 ,Event enable set for events 47" "No effect,Enabled" bitfld.long 0x00 14. " En_46 ,Event enable set for events 46" "No effect,Enabled" bitfld.long 0x00 13. " En_45 ,Event enable set for events 45" "No effect,Enabled" bitfld.long 0x00 12. " En_44 ,Event enable set for events 44" "No effect,Enabled" textline " " bitfld.long 0x00 11. " En_43 ,Event enable set for events 43" "No effect,Enabled" bitfld.long 0x00 10. " En_42 ,Event enable set for events 42" "No effect,Enabled" bitfld.long 0x00 9. " En_41 ,Event enable set for events 41" "No effect,Enabled" bitfld.long 0x00 8. " En_40 ,Event enable set for events 40" "No effect,Enabled" textline " " bitfld.long 0x00 7. " En_39 ,Event enable set for events 39" "No effect,Enabled" bitfld.long 0x00 6. " En_38 ,Event enable set for events 38" "No effect,Enabled" bitfld.long 0x00 5. " En_37 ,Event enable set for events 37" "No effect,Enabled" bitfld.long 0x00 4. " En_36 ,Event enable set for events 36" "No effect,Enabled" textline " " bitfld.long 0x00 3. " En_35 ,Event enable set for events 35" "No effect,Enabled" bitfld.long 0x00 2. " En_34 ,Event enable set for events 34" "No effect,Enabled" bitfld.long 0x00 1. " En_33 ,Event enable set for events 33" "No effect,Enabled" bitfld.long 0x00 0. " En_32 ,Event enable set for events 32" "No effect,Enabled" rgroup.long 0x1038++0x03 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " En_31 ,Event store in queue status 31" "Not stored,Stored" bitfld.long 0x00 30. " En_30 ,Event store in queue status 30" "Not stored,Stored" bitfld.long 0x00 29. " En_29 ,Event store in queue status 29" "Not stored,Stored" bitfld.long 0x00 28. " En_28 ,Event store in queue status 28" "Not stored,Stored" textline " " bitfld.long 0x00 27. " En_27 ,Event store in queue status 27" "Not stored,Stored" bitfld.long 0x00 26. " En_26 ,Event store in queue status 26" "Not stored,Stored" bitfld.long 0x00 25. " En_25 ,Event store in queue status 25" "Not stored,Stored" bitfld.long 0x00 24. " En_24 ,Event store in queue status 24" "Not stored,Stored" textline " " bitfld.long 0x00 23. " En_23 ,Event store in queue status 23" "Not stored,Stored" bitfld.long 0x00 22. " En_22 ,Event store in queue status 22" "Not stored,Stored" bitfld.long 0x00 21. " En_21 ,Event store in queue status 21" "Not stored,Stored" bitfld.long 0x00 20. " En_20 ,Event store in queue status 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " En_19 ,Event store in queue status 19" "Not stored,Stored" bitfld.long 0x00 18. " En_18 ,Event store in queue status 18" "Not stored,Stored" bitfld.long 0x00 17. " En_17 ,Event store in queue status 17" "Not stored,Stored" bitfld.long 0x00 16. " En_16 ,Event store in queue status 16" "Not stored,Stored" textline " " bitfld.long 0x00 15. " En_15 ,Event store in queue status 15" "Not stored,Stored" bitfld.long 0x00 14. " En_14 ,Event store in queue status 14" "Not stored,Stored" bitfld.long 0x00 13. " En_13 ,Event store in queue status 13" "Not stored,Stored" bitfld.long 0x00 12. " En_12 ,Event store in queue status 12" "Not stored,Stored" textline " " bitfld.long 0x00 11. " En_11 ,Event store in queue status 11" "Not stored,Stored" bitfld.long 0x00 10. " En_10 ,Event store in queue status 10" "Not stored,Stored" bitfld.long 0x00 9. " En_9 ,Event store in queue status 9" "Not stored,Stored" bitfld.long 0x00 8. " En_8 ,Event store in queue status 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " En_7 ,Event store in queue status 7" "Not stored,Stored" bitfld.long 0x00 6. " En_6 ,Event store in queue status 6" "Not stored,Stored" bitfld.long 0x00 5. " En_5 ,Event store in queue status 5" "Not stored,Stored" bitfld.long 0x00 4. " En_4 ,Event store in queue status 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " En_3 ,Event store in queue status 3" "Not stored,Stored" bitfld.long 0x00 2. " En_2 ,Event store in queue status 2" "Not stored,Stored" bitfld.long 0x00 1. " En_1 ,Event store in queue status 1" "Not stored,Stored" bitfld.long 0x00 0. " En_0 ,Event store in queue status 0" "Not stored,Stored" rgroup.long 0x103C++0x03 line.long 0x00 "SERH,Secondary Event Register High" bitfld.long 0x00 31. " En_63 ,Event store in queue status 63" "Not stored,Stored" bitfld.long 0x00 30. " En_62 ,Event store in queue status 62" "Not stored,Stored" bitfld.long 0x00 29. " En_61 ,Event store in queue status 61" "Not stored,Stored" bitfld.long 0x00 28. " En_60 ,Event store in queue status 60" "Not stored,Stored" textline " " bitfld.long 0x00 27. " En_59 ,Event store in queue status 59" "Not stored,Stored" bitfld.long 0x00 26. " En_58 ,Event store in queue status 58" "Not stored,Stored" bitfld.long 0x00 25. " En_57 ,Event store in queue status 57" "Not stored,Stored" bitfld.long 0x00 24. " En_56 ,Event store in queue status 56" "Not stored,Stored" textline " " bitfld.long 0x00 23. " En_55 ,Event store in queue status 55" "Not stored,Stored" bitfld.long 0x00 22. " En_54 ,Event store in queue status 54" "Not stored,Stored" bitfld.long 0x00 21. " En_53 ,Event store in queue status 53" "Not stored,Stored" bitfld.long 0x00 20. " En_52 ,Event store in queue status 52" "Not stored,Stored" textline " " bitfld.long 0x00 19. " En_51 ,Event store in queue status 51" "Not stored,Stored" bitfld.long 0x00 18. " En_50 ,Event store in queue status 50" "Not stored,Stored" bitfld.long 0x00 17. " En_49 ,Event store in queue status 49" "Not stored,Stored" bitfld.long 0x00 16. " En_48 ,Event store in queue status 48" "Not stored,Stored" textline " " bitfld.long 0x00 15. " En_47 ,Event store in queue status 47" "Not stored,Stored" bitfld.long 0x00 14. " En_46 ,Event store in queue status 46" "Not stored,Stored" bitfld.long 0x00 13. " En_45 ,Event store in queue status 45" "Not stored,Stored" bitfld.long 0x00 12. " En_44 ,Event store in queue status 44" "Not stored,Stored" textline " " bitfld.long 0x00 11. " En_43 ,Event store in queue status 43" "Not stored,Stored" bitfld.long 0x00 10. " En_42 ,Event store in queue status 42" "Not stored,Stored" bitfld.long 0x00 9. " En_41 ,Event store in queue status 41" "Not stored,Stored" bitfld.long 0x00 8. " En_40 ,Event store in queue status 40" "Not stored,Stored" textline " " bitfld.long 0x00 7. " En_39 ,Event store in queue status 39" "Not stored,Stored" bitfld.long 0x00 6. " En_38 ,Event store in queue status 38" "Not stored,Stored" bitfld.long 0x00 5. " En_37 ,Event store in queue status 37" "Not stored,Stored" bitfld.long 0x00 4. " En_36 ,Event store in queue status 36" "Not stored,Stored" textline " " bitfld.long 0x00 3. " En_35 ,Event store in queue status 35" "Not stored,Stored" bitfld.long 0x00 2. " En_34 ,Event store in queue status 34" "Not stored,Stored" bitfld.long 0x00 1. " En_33 ,Event store in queue status 33" "Not stored,Stored" bitfld.long 0x00 0. " En_32 ,Event store in queue status 32" "Not stored,Stored" wgroup.long 0x1040++0x03 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " En_31 ,Secondary event clear status 31" "No effect,Cleared" bitfld.long 0x00 30. " En_30 ,Secondary event clear status 30" "No effect,Cleared" bitfld.long 0x00 29. " En_29 ,Secondary event clear status 29" "No effect,Cleared" bitfld.long 0x00 28. " En_28 ,Secondary event clear status 28" "No effect,Cleared" textline " " bitfld.long 0x00 27. " En_27 ,Secondary event clear status 27" "No effect,Cleared" bitfld.long 0x00 26. " En_26 ,Secondary event clear status 26" "No effect,Cleared" bitfld.long 0x00 25. " En_25 ,Secondary event clear status 25" "No effect,Cleared" bitfld.long 0x00 24. " En_24 ,Secondary event clear status 24" "No effect,Cleared" textline " " bitfld.long 0x00 23. " En_23 ,Secondary event clear status 23" "No effect,Cleared" bitfld.long 0x00 22. " En_22 ,Secondary event clear status 22" "No effect,Cleared" bitfld.long 0x00 21. " En_21 ,Secondary event clear status 21" "No effect,Cleared" bitfld.long 0x00 20. " En_20 ,Secondary event clear status 20" "No effect,Cleared" textline " " bitfld.long 0x00 19. " En_19 ,Secondary event clear status 19" "No effect,Cleared" bitfld.long 0x00 18. " En_18 ,Secondary event clear status 18" "No effect,Cleared" bitfld.long 0x00 17. " En_17 ,Secondary event clear status 17" "No effect,Cleared" bitfld.long 0x00 16. " En_16 ,Secondary event clear status 16" "No effect,Cleared" textline " " bitfld.long 0x00 15. " En_15 ,Secondary event clear status 15" "No effect,Cleared" bitfld.long 0x00 14. " En_14 ,Secondary event clear status 14" "No effect,Cleared" bitfld.long 0x00 13. " En_13 ,Secondary event clear status 13" "No effect,Cleared" bitfld.long 0x00 12. " En_12 ,Secondary event clear status 12" "No effect,Cleared" textline " " bitfld.long 0x00 11. " En_11 ,Secondary event clear status 11" "No effect,Cleared" bitfld.long 0x00 10. " En_10 ,Secondary event clear status 10" "No effect,Cleared" bitfld.long 0x00 9. " En_9 ,Secondary event clear status 9" "No effect,Cleared" bitfld.long 0x00 8. " En_8 ,Secondary event clear status 8" "No effect,Cleared" textline " " bitfld.long 0x00 7. " En_7 ,Secondary event clear status 7" "No effect,Cleared" bitfld.long 0x00 6. " En_6 ,Secondary event clear status 6" "No effect,Cleared" bitfld.long 0x00 5. " En_5 ,Secondary event clear status 5" "No effect,Cleared" bitfld.long 0x00 4. " En_4 ,Secondary event clear status 4" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_3 ,Secondary event clear status 3" "No effect,Cleared" bitfld.long 0x00 2. " En_2 ,Secondary event clear status 2" "No effect,Cleared" bitfld.long 0x00 1. " En_1 ,Secondary event clear status 1" "No effect,Cleared" bitfld.long 0x00 0. " En_0 ,Secondary event clear status 0" "No effect,Cleared" wgroup.long 0x1044++0x03 line.long 0x00 "SECRH,Secondary Event Clear Register High" bitfld.long 0x00 31. " En_63 ,Secondary event clear status 63" "No effect,Cleared" bitfld.long 0x00 30. " En_62 ,Secondary event clear status 62" "No effect,Cleared" bitfld.long 0x00 29. " En_61 ,Secondary event clear status 61" "No effect,Cleared" bitfld.long 0x00 28. " En_60 ,Secondary event clear status 60" "No effect,Cleared" textline " " bitfld.long 0x00 27. " En_59 ,Secondary event clear status 59" "No effect,Cleared" bitfld.long 0x00 26. " En_58 ,Secondary event clear status 58" "No effect,Cleared" bitfld.long 0x00 25. " En_57 ,Secondary event clear status 57" "No effect,Cleared" bitfld.long 0x00 24. " En_56 ,Secondary event clear status 56" "No effect,Cleared" textline " " bitfld.long 0x00 23. " En_55 ,Secondary event clear status 55" "No effect,Cleared" bitfld.long 0x00 22. " En_54 ,Secondary event clear status 54" "No effect,Cleared" bitfld.long 0x00 21. " En_53 ,Secondary event clear status 53" "No effect,Cleared" bitfld.long 0x00 20. " En_52 ,Secondary event clear status 52" "No effect,Cleared" textline " " bitfld.long 0x00 19. " En_51 ,Secondary event clear status 51" "No effect,Cleared" bitfld.long 0x00 18. " En_50 ,Secondary event clear status 50" "No effect,Cleared" bitfld.long 0x00 17. " En_49 ,Secondary event clear status 49" "No effect,Cleared" bitfld.long 0x00 16. " En_48 ,Secondary event clear status 48" "No effect,Cleared" textline " " bitfld.long 0x00 15. " En_47 ,Secondary event clear status 47" "No effect,Cleared" bitfld.long 0x00 14. " En_46 ,Secondary event clear status 46" "No effect,Cleared" bitfld.long 0x00 13. " En_45 ,Secondary event clear status 45" "No effect,Cleared" bitfld.long 0x00 12. " En_44 ,Secondary event clear status 44" "No effect,Cleared" textline " " bitfld.long 0x00 11. " En_43 ,Secondary event clear status 43" "No effect,Cleared" bitfld.long 0x00 10. " En_42 ,Secondary event clear status 42" "No effect,Cleared" bitfld.long 0x00 9. " En_41 ,Secondary event clear status 41" "No effect,Cleared" bitfld.long 0x00 8. " En_40 ,Secondary event clear status 40" "No effect,Cleared" textline " " bitfld.long 0x00 7. " En_39 ,Secondary event clear status 39" "No effect,Cleared" bitfld.long 0x00 6. " En_38 ,Secondary event clear status 38" "No effect,Cleared" bitfld.long 0x00 5. " En_37 ,Secondary event clear status 37" "No effect,Cleared" bitfld.long 0x00 4. " En_36 ,Secondary event clear status 36" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_35 ,Secondary event clear status 35" "No effect,Cleared" bitfld.long 0x00 2. " En_34 ,Secondary event clear status 34" "No effect,Cleared" bitfld.long 0x00 1. " En_33 ,Secondary event clear status 33" "No effect,Cleared" bitfld.long 0x00 0. " En_32 ,Secondary event clear status 32" "No effect,Cleared" rgroup.long 0x1050++0x03 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 31. " In_31 ,Interrupt enable for channels 31" "Disabled,Enabled" bitfld.long 0x00 30. " In_30 ,Interrupt enable for channels 30" "Disabled,Enabled" bitfld.long 0x00 29. " In_29 ,Interrupt enable for channels 29" "Disabled,Enabled" bitfld.long 0x00 28. " In_28 ,Interrupt enable for channels 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " In_27 ,Interrupt enable for channels 27" "Disabled,Enabled" bitfld.long 0x00 26. " In_26 ,Interrupt enable for channels 26" "Disabled,Enabled" bitfld.long 0x00 25. " In_25 ,Interrupt enable for channels 25" "Disabled,Enabled" bitfld.long 0x00 24. " In_24 ,Interrupt enable for channels 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " In_23 ,Interrupt enable for channels 23" "Disabled,Enabled" bitfld.long 0x00 22. " In_22 ,Interrupt enable for channels 22" "Disabled,Enabled" bitfld.long 0x00 21. " In_21 ,Interrupt enable for channels 21" "Disabled,Enabled" bitfld.long 0x00 20. " In_20 ,Interrupt enable for channels 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " In_19 ,Interrupt enable for channels 19" "Disabled,Enabled" bitfld.long 0x00 18. " In_18 ,Interrupt enable for channels 18" "Disabled,Enabled" bitfld.long 0x00 17. " In_17 ,Interrupt enable for channels 17" "Disabled,Enabled" bitfld.long 0x00 16. " In_16 ,Interrupt enable for channels 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " In_15 ,Interrupt enable for channels 15" "Disabled,Enabled" bitfld.long 0x00 14. " In_14 ,Interrupt enable for channels 14" "Disabled,Enabled" bitfld.long 0x00 13. " In_13 ,Interrupt enable for channels 13" "Disabled,Enabled" bitfld.long 0x00 12. " In_12 ,Interrupt enable for channels 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " In_11 ,Interrupt enable for channels 11" "Disabled,Enabled" bitfld.long 0x00 10. " In_10 ,Interrupt enable for channels 10" "Disabled,Enabled" bitfld.long 0x00 9. " In_9 ,Interrupt enable for channels 9" "Disabled,Enabled" bitfld.long 0x00 8. " In_8 ,Interrupt enable for channels 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " In_7 ,Interrupt enable for channels 7" "Disabled,Enabled" bitfld.long 0x00 6. " In_6 ,Interrupt enable for channels 6" "Disabled,Enabled" bitfld.long 0x00 5. " In_5 ,Interrupt enable for channels 5" "Disabled,Enabled" bitfld.long 0x00 4. " In_4 ,Interrupt enable for channels 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " In_3 ,Interrupt enable for channels 3" "Disabled,Enabled" bitfld.long 0x00 2. " In_2 ,Interrupt enable for channels 2" "Disabled,Enabled" bitfld.long 0x00 1. " In_1 ,Interrupt enable for channels 1" "Disabled,Enabled" bitfld.long 0x00 0. " In_0 ,Interrupt enable for channels 0" "Disabled,Enabled" rgroup.long 0x1054++0x03 line.long 0x00 "IERH,Interrupt Enable Register High" bitfld.long 0x00 31. " In_63 ,Interrupt enable for channels 63" "Disabled,Enabled" bitfld.long 0x00 30. " In_62 ,Interrupt enable for channels 62" "Disabled,Enabled" bitfld.long 0x00 29. " In_61 ,Interrupt enable for channels 61" "Disabled,Enabled" bitfld.long 0x00 28. " In_60 ,Interrupt enable for channels 60" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " In_59 ,Interrupt enable for channels 59" "Disabled,Enabled" bitfld.long 0x00 26. " In_58 ,Interrupt enable for channels 58" "Disabled,Enabled" bitfld.long 0x00 25. " In_57 ,Interrupt enable for channels 57" "Disabled,Enabled" bitfld.long 0x00 24. " In_56 ,Interrupt enable for channels 56" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " In_55 ,Interrupt enable for channels 55" "Disabled,Enabled" bitfld.long 0x00 22. " In_54 ,Interrupt enable for channels 54" "Disabled,Enabled" bitfld.long 0x00 21. " In_53 ,Interrupt enable for channels 53" "Disabled,Enabled" bitfld.long 0x00 20. " In_52 ,Interrupt enable for channels 52" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " In_51 ,Interrupt enable for channels 51" "Disabled,Enabled" bitfld.long 0x00 18. " In_50 ,Interrupt enable for channels 50" "Disabled,Enabled" bitfld.long 0x00 17. " In_49 ,Interrupt enable for channels 49" "Disabled,Enabled" bitfld.long 0x00 16. " In_48 ,Interrupt enable for channels 48" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " In_47 ,Interrupt enable for channels 47" "Disabled,Enabled" bitfld.long 0x00 14. " In_46 ,Interrupt enable for channels 46" "Disabled,Enabled" bitfld.long 0x00 13. " In_45 ,Interrupt enable for channels 45" "Disabled,Enabled" bitfld.long 0x00 12. " In_44 ,Interrupt enable for channels 44" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " In_43 ,Interrupt enable for channels 43" "Disabled,Enabled" bitfld.long 0x00 10. " In_42 ,Interrupt enable for channels 42" "Disabled,Enabled" bitfld.long 0x00 9. " In_41 ,Interrupt enable for channels 41" "Disabled,Enabled" bitfld.long 0x00 8. " In_40 ,Interrupt enable for channels 40" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " In_39 ,Interrupt enable for channels 39" "Disabled,Enabled" bitfld.long 0x00 6. " In_38 ,Interrupt enable for channels 38" "Disabled,Enabled" bitfld.long 0x00 5. " In_37 ,Interrupt enable for channels 37" "Disabled,Enabled" bitfld.long 0x00 4. " In_36 ,Interrupt enable for channels 36" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " In_35 ,Interrupt enable for channels 35" "Disabled,Enabled" bitfld.long 0x00 2. " In_34 ,Interrupt enable for channels 34" "Disabled,Enabled" bitfld.long 0x00 1. " In_33 ,Interrupt enable for channels 33" "Disabled,Enabled" bitfld.long 0x00 0. " In_32 ,Interrupt enable for channels 32" "Disabled,Enabled" wgroup.long 0x1058++0x03 line.long 0x00 "IECR,Interrupt Enable Clear Register" bitfld.long 0x00 31. " In_31 ,Interrupt enable clear for channels 31" "No effect,Cleared" bitfld.long 0x00 30. " In_30 ,Interrupt enable clear for channels 30" "No effect,Cleared" bitfld.long 0x00 29. " In_29 ,Interrupt enable clear for channels 29" "No effect,Cleared" bitfld.long 0x00 28. " In_28 ,Interrupt enable clear for channels 28" "No effect,Cleared" textline " " bitfld.long 0x00 27. " In_27 ,Interrupt enable clear for channels 27" "No effect,Cleared" bitfld.long 0x00 26. " In_26 ,Interrupt enable clear for channels 26" "No effect,Cleared" bitfld.long 0x00 25. " In_25 ,Interrupt enable clear for channels 25" "No effect,Cleared" bitfld.long 0x00 24. " In_24 ,Interrupt enable clear for channels 24" "No effect,Cleared" textline " " bitfld.long 0x00 23. " In_23 ,Interrupt enable clear for channels 23" "No effect,Cleared" bitfld.long 0x00 22. " In_22 ,Interrupt enable clear for channels 22" "No effect,Cleared" bitfld.long 0x00 21. " In_21 ,Interrupt enable clear for channels 21" "No effect,Cleared" bitfld.long 0x00 20. " In_20 ,Interrupt enable clear for channels 20" "No effect,Cleared" textline " " bitfld.long 0x00 19. " In_19 ,Interrupt enable clear for channels 19" "No effect,Cleared" bitfld.long 0x00 18. " In_18 ,Interrupt enable clear for channels 18" "No effect,Cleared" bitfld.long 0x00 17. " In_17 ,Interrupt enable clear for channels 17" "No effect,Cleared" bitfld.long 0x00 16. " In_16 ,Interrupt enable clear for channels 16" "No effect,Cleared" textline " " bitfld.long 0x00 15. " In_15 ,Interrupt enable clear for channels 15" "No effect,Cleared" bitfld.long 0x00 14. " In_14 ,Interrupt enable clear for channels 14" "No effect,Cleared" bitfld.long 0x00 13. " In_13 ,Interrupt enable clear for channels 13" "No effect,Cleared" bitfld.long 0x00 12. " In_12 ,Interrupt enable clear for channels 12" "No effect,Cleared" textline " " bitfld.long 0x00 11. " In_11 ,Interrupt enable clear for channels 11" "No effect,Cleared" bitfld.long 0x00 10. " In_10 ,Interrupt enable clear for channels 10" "No effect,Cleared" bitfld.long 0x00 9. " In_9 ,Interrupt enable clear for channels 9" "No effect,Cleared" bitfld.long 0x00 8. " In_8 ,Interrupt enable clear for channels 8" "No effect,Cleared" textline " " bitfld.long 0x00 7. " In_7 ,Interrupt enable clear for channels 7" "No effect,Cleared" bitfld.long 0x00 6. " In_6 ,Interrupt enable clear for channels 6" "No effect,Cleared" bitfld.long 0x00 5. " In_5 ,Interrupt enable clear for channels 5" "No effect,Cleared" bitfld.long 0x00 4. " In_4 ,Interrupt enable clear for channels 4" "No effect,Cleared" textline " " bitfld.long 0x00 3. " In_3 ,Interrupt enable clear for channels 3" "No effect,Cleared" bitfld.long 0x00 2. " In_2 ,Interrupt enable clear for channels 2" "No effect,Cleared" bitfld.long 0x00 1. " In_1 ,Interrupt enable clear for channels 1" "No effect,Cleared" bitfld.long 0x00 0. " In_0 ,Interrupt enable clear for channels 0" "No effect,Cleared" wgroup.long 0x105C++0x03 line.long 0x00 "IECRH,Interrupt Enable Clear Register High" bitfld.long 0x00 31. " In_63 ,Interrupt enable clear for channels 63" "No effect,Cleared" bitfld.long 0x00 30. " In_62 ,Interrupt enable clear for channels 62" "No effect,Cleared" bitfld.long 0x00 29. " In_61 ,Interrupt enable clear for channels 61" "No effect,Cleared" bitfld.long 0x00 28. " In_60 ,Interrupt enable clear for channels 60" "No effect,Cleared" textline " " bitfld.long 0x00 27. " In_59 ,Interrupt enable clear for channels 59" "No effect,Cleared" bitfld.long 0x00 26. " In_58 ,Interrupt enable clear for channels 58" "No effect,Cleared" bitfld.long 0x00 25. " In_57 ,Interrupt enable clear for channels 57" "No effect,Cleared" bitfld.long 0x00 24. " In_56 ,Interrupt enable clear for channels 56" "No effect,Cleared" textline " " bitfld.long 0x00 23. " In_55 ,Interrupt enable clear for channels 55" "No effect,Cleared" bitfld.long 0x00 22. " In_54 ,Interrupt enable clear for channels 54" "No effect,Cleared" bitfld.long 0x00 21. " In_53 ,Interrupt enable clear for channels 53" "No effect,Cleared" bitfld.long 0x00 20. " In_52 ,Interrupt enable clear for channels 52" "No effect,Cleared" textline " " bitfld.long 0x00 19. " In_51 ,Interrupt enable clear for channels 51" "No effect,Cleared" bitfld.long 0x00 18. " In_50 ,Interrupt enable clear for channels 50" "No effect,Cleared" bitfld.long 0x00 17. " In_49 ,Interrupt enable clear for channels 49" "No effect,Cleared" bitfld.long 0x00 16. " In_48 ,Interrupt enable clear for channels 48" "No effect,Cleared" textline " " bitfld.long 0x00 15. " In_47 ,Interrupt enable clear for channels 47" "No effect,Cleared" bitfld.long 0x00 14. " In_46 ,Interrupt enable clear for channels 46" "No effect,Cleared" bitfld.long 0x00 13. " In_45 ,Interrupt enable clear for channels 45" "No effect,Cleared" bitfld.long 0x00 12. " In_44 ,Interrupt enable clear for channels 44" "No effect,Cleared" textline " " bitfld.long 0x00 11. " In_43 ,Interrupt enable clear for channels 43" "No effect,Cleared" bitfld.long 0x00 10. " In_42 ,Interrupt enable clear for channels 42" "No effect,Cleared" bitfld.long 0x00 9. " In_41 ,Interrupt enable clear for channels 41" "No effect,Cleared" bitfld.long 0x00 8. " In_40 ,Interrupt enable clear for channels 40" "No effect,Cleared" textline " " bitfld.long 0x00 7. " In_39 ,Interrupt enable clear for channels 39" "No effect,Cleared" bitfld.long 0x00 6. " In_38 ,Interrupt enable clear for channels 38" "No effect,Cleared" bitfld.long 0x00 5. " In_37 ,Interrupt enable clear for channels 37" "No effect,Cleared" bitfld.long 0x00 4. " In_36 ,Interrupt enable clear for channels 36" "No effect,Cleared" textline " " bitfld.long 0x00 3. " In_35 ,Interrupt enable clear for channels 35" "No effect,Cleared" bitfld.long 0x00 2. " In_34 ,Interrupt enable clear for channels 34" "No effect,Cleared" bitfld.long 0x00 1. " In_33 ,Interrupt enable clear for channels 33" "No effect,Cleared" bitfld.long 0x00 0. " In_32 ,Interrupt enable clear for channels 32" "No effect,Cleared" wgroup.long 0x1060++0x03 line.long 0x00 "IESR,Interrupt Enable Set Register" bitfld.long 0x00 31. " In_31 ,Interrupt enable set for channels 31" "No effect,Set" bitfld.long 0x00 30. " In_30 ,Interrupt enable set for channels 30" "No effect,Set" bitfld.long 0x00 29. " In_29 ,Interrupt enable set for channels 29" "No effect,Set" bitfld.long 0x00 28. " In_28 ,Interrupt enable set for channels 28" "No effect,Set" textline " " bitfld.long 0x00 27. " In_27 ,Interrupt enable set for channels 27" "No effect,Set" bitfld.long 0x00 26. " In_26 ,Interrupt enable set for channels 26" "No effect,Set" bitfld.long 0x00 25. " In_25 ,Interrupt enable set for channels 25" "No effect,Set" bitfld.long 0x00 24. " In_24 ,Interrupt enable set for channels 24" "No effect,Set" textline " " bitfld.long 0x00 23. " In_23 ,Interrupt enable set for channels 23" "No effect,Set" bitfld.long 0x00 22. " In_22 ,Interrupt enable set for channels 22" "No effect,Set" bitfld.long 0x00 21. " In_21 ,Interrupt enable set for channels 21" "No effect,Set" bitfld.long 0x00 20. " In_20 ,Interrupt enable set for channels 20" "No effect,Set" textline " " bitfld.long 0x00 19. " In_19 ,Interrupt enable set for channels 19" "No effect,Set" bitfld.long 0x00 18. " In_18 ,Interrupt enable set for channels 18" "No effect,Set" bitfld.long 0x00 17. " In_17 ,Interrupt enable set for channels 17" "No effect,Set" bitfld.long 0x00 16. " In_16 ,Interrupt enable set for channels 16" "No effect,Set" textline " " bitfld.long 0x00 15. " In_15 ,Interrupt enable set for channels 15" "No effect,Set" bitfld.long 0x00 14. " In_14 ,Interrupt enable set for channels 14" "No effect,Set" bitfld.long 0x00 13. " In_13 ,Interrupt enable set for channels 13" "No effect,Set" bitfld.long 0x00 12. " In_12 ,Interrupt enable set for channels 12" "No effect,Set" textline " " bitfld.long 0x00 11. " In_11 ,Interrupt enable set for channels 11" "No effect,Set" bitfld.long 0x00 10. " In_10 ,Interrupt enable set for channels 10" "No effect,Set" bitfld.long 0x00 9. " In_9 ,Interrupt enable set for channels 9" "No effect,Set" bitfld.long 0x00 8. " In_8 ,Interrupt enable set for channels 8" "No effect,Set" textline " " bitfld.long 0x00 7. " In_7 ,Interrupt enable set for channels 7" "No effect,Set" bitfld.long 0x00 6. " In_6 ,Interrupt enable set for channels 6" "No effect,Set" bitfld.long 0x00 5. " In_5 ,Interrupt enable set for channels 5" "No effect,Set" bitfld.long 0x00 4. " In_4 ,Interrupt enable set for channels 4" "No effect,Set" textline " " bitfld.long 0x00 3. " In_3 ,Interrupt enable set for channels 3" "No effect,Set" bitfld.long 0x00 2. " In_2 ,Interrupt enable set for channels 2" "No effect,Set" bitfld.long 0x00 1. " In_1 ,Interrupt enable set for channels 1" "No effect,Set" bitfld.long 0x00 0. " In_0 ,Interrupt enable set for channels 0" "No effect,Set" wgroup.long 0x1064++0x03 line.long 0x00 "IESRH,Interrupt Enable Set Register High" bitfld.long 0x00 31. " In_63 ,Interrupt enable set for channels 63" "No effect,Set" bitfld.long 0x00 30. " In_62 ,Interrupt enable set for channels 62" "No effect,Set" bitfld.long 0x00 29. " In_61 ,Interrupt enable set for channels 61" "No effect,Set" bitfld.long 0x00 28. " In_60 ,Interrupt enable set for channels 60" "No effect,Set" textline " " bitfld.long 0x00 27. " In_59 ,Interrupt enable set for channels 59" "No effect,Set" bitfld.long 0x00 26. " In_58 ,Interrupt enable set for channels 58" "No effect,Set" bitfld.long 0x00 25. " In_57 ,Interrupt enable set for channels 57" "No effect,Set" bitfld.long 0x00 24. " In_56 ,Interrupt enable set for channels 56" "No effect,Set" textline " " bitfld.long 0x00 23. " In_55 ,Interrupt enable set for channels 55" "No effect,Set" bitfld.long 0x00 22. " In_54 ,Interrupt enable set for channels 54" "No effect,Set" bitfld.long 0x00 21. " In_53 ,Interrupt enable set for channels 53" "No effect,Set" bitfld.long 0x00 20. " In_52 ,Interrupt enable set for channels 52" "No effect,Set" textline " " bitfld.long 0x00 19. " In_51 ,Interrupt enable set for channels 51" "No effect,Set" bitfld.long 0x00 18. " In_50 ,Interrupt enable set for channels 50" "No effect,Set" bitfld.long 0x00 17. " In_49 ,Interrupt enable set for channels 49" "No effect,Set" bitfld.long 0x00 16. " In_48 ,Interrupt enable set for channels 48" "No effect,Set" textline " " bitfld.long 0x00 15. " In_47 ,Interrupt enable set for channels 47" "No effect,Set" bitfld.long 0x00 14. " In_46 ,Interrupt enable set for channels 46" "No effect,Set" bitfld.long 0x00 13. " In_45 ,Interrupt enable set for channels 45" "No effect,Set" bitfld.long 0x00 12. " In_44 ,Interrupt enable set for channels 44" "No effect,Set" textline " " bitfld.long 0x00 11. " In_43 ,Interrupt enable set for channels 43" "No effect,Set" bitfld.long 0x00 10. " In_42 ,Interrupt enable set for channels 42" "No effect,Set" bitfld.long 0x00 9. " In_41 ,Interrupt enable set for channels 41" "No effect,Set" bitfld.long 0x00 8. " In_40 ,Interrupt enable set for channels 40" "No effect,Set" textline " " bitfld.long 0x00 7. " In_39 ,Interrupt enable set for channels 39" "No effect,Set" bitfld.long 0x00 6. " In_38 ,Interrupt enable set for channels 38" "No effect,Set" bitfld.long 0x00 5. " In_37 ,Interrupt enable set for channels 37" "No effect,Set" bitfld.long 0x00 4. " In_36 ,Interrupt enable set for channels 36" "No effect,Set" textline " " bitfld.long 0x00 3. " In_35 ,Interrupt enable set for channels 35" "No effect,Set" bitfld.long 0x00 2. " In_34 ,Interrupt enable set for channels 34" "No effect,Set" bitfld.long 0x00 1. " In_33 ,Interrupt enable set for channels 33" "No effect,Set" bitfld.long 0x00 0. " In_32 ,Interrupt enable set for channels 32" "No effect,Set" rgroup.long 0x1068++0x03 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " In_31 ,Interrupt pending for TCC = 31" "No detected,Detected" bitfld.long 0x00 30. " In_30 ,Interrupt pending for TCC = 30" "No detected,Detected" bitfld.long 0x00 29. " In_29 ,Interrupt pending for TCC = 29" "No detected,Detected" bitfld.long 0x00 28. " In_28 ,Interrupt pending for TCC = 28" "No detected,Detected" textline " " bitfld.long 0x00 27. " In_27 ,Interrupt pending for TCC = 27" "No detected,Detected" bitfld.long 0x00 26. " In_26 ,Interrupt pending for TCC = 26" "No detected,Detected" bitfld.long 0x00 25. " In_25 ,Interrupt pending for TCC = 25" "No detected,Detected" bitfld.long 0x00 24. " In_24 ,Interrupt pending for TCC = 24" "No detected,Detected" textline " " bitfld.long 0x00 23. " In_23 ,Interrupt pending for TCC = 23" "No detected,Detected" bitfld.long 0x00 22. " In_22 ,Interrupt pending for TCC = 22" "No detected,Detected" bitfld.long 0x00 21. " In_21 ,Interrupt pending for TCC = 21" "No detected,Detected" bitfld.long 0x00 20. " In_20 ,Interrupt pending for TCC = 20" "No detected,Detected" textline " " bitfld.long 0x00 19. " In_19 ,Interrupt pending for TCC = 19" "No detected,Detected" bitfld.long 0x00 18. " In_18 ,Interrupt pending for TCC = 18" "No detected,Detected" bitfld.long 0x00 17. " In_17 ,Interrupt pending for TCC = 17" "No detected,Detected" bitfld.long 0x00 16. " In_16 ,Interrupt pending for TCC = 16" "No detected,Detected" textline " " bitfld.long 0x00 15. " In_15 ,Interrupt pending for TCC = 15" "No detected,Detected" bitfld.long 0x00 14. " In_14 ,Interrupt pending for TCC = 14" "No detected,Detected" bitfld.long 0x00 13. " In_13 ,Interrupt pending for TCC = 13" "No detected,Detected" bitfld.long 0x00 12. " In_12 ,Interrupt pending for TCC = 12" "No detected,Detected" textline " " bitfld.long 0x00 11. " In_11 ,Interrupt pending for TCC = 11" "No detected,Detected" bitfld.long 0x00 10. " In_10 ,Interrupt pending for TCC = 10" "No detected,Detected" bitfld.long 0x00 9. " In_9 ,Interrupt pending for TCC = 9" "No detected,Detected" bitfld.long 0x00 8. " In_8 ,Interrupt pending for TCC = 8" "No detected,Detected" textline " " bitfld.long 0x00 7. " In_7 ,Interrupt pending for TCC = 7" "No detected,Detected" bitfld.long 0x00 6. " In_6 ,Interrupt pending for TCC = 6" "No detected,Detected" bitfld.long 0x00 5. " In_5 ,Interrupt pending for TCC = 5" "No detected,Detected" bitfld.long 0x00 4. " In_4 ,Interrupt pending for TCC = 4" "No detected,Detected" textline " " bitfld.long 0x00 3. " In_3 ,Interrupt pending for TCC = 3" "No detected,Detected" bitfld.long 0x00 2. " In_2 ,Interrupt pending for TCC = 2" "No detected,Detected" bitfld.long 0x00 1. " In_1 ,Interrupt pending for TCC = 1" "No detected,Detected" bitfld.long 0x00 0. " In_0 ,Interrupt pending for TCC = 0" "No detected,Detected" rgroup.long 0x106C++0x03 line.long 0x00 "IPRH,Interrupt Pending Register High" bitfld.long 0x00 31. " In_63 ,Interrupt pending for TCC = 63" "No detected,Detected" bitfld.long 0x00 30. " In_62 ,Interrupt pending for TCC = 62" "No detected,Detected" bitfld.long 0x00 29. " In_61 ,Interrupt pending for TCC = 61" "No detected,Detected" bitfld.long 0x00 28. " In_60 ,Interrupt pending for TCC = 60" "No detected,Detected" textline " " bitfld.long 0x00 27. " In_59 ,Interrupt pending for TCC = 59" "No detected,Detected" bitfld.long 0x00 26. " In_58 ,Interrupt pending for TCC = 58" "No detected,Detected" bitfld.long 0x00 25. " In_57 ,Interrupt pending for TCC = 57" "No detected,Detected" bitfld.long 0x00 24. " In_56 ,Interrupt pending for TCC = 56" "No detected,Detected" textline " " bitfld.long 0x00 23. " In_55 ,Interrupt pending for TCC = 55" "No detected,Detected" bitfld.long 0x00 22. " In_54 ,Interrupt pending for TCC = 54" "No detected,Detected" bitfld.long 0x00 21. " In_53 ,Interrupt pending for TCC = 53" "No detected,Detected" bitfld.long 0x00 20. " In_52 ,Interrupt pending for TCC = 52" "No detected,Detected" textline " " bitfld.long 0x00 19. " In_51 ,Interrupt pending for TCC = 51" "No detected,Detected" bitfld.long 0x00 18. " In_50 ,Interrupt pending for TCC = 50" "No detected,Detected" bitfld.long 0x00 17. " In_49 ,Interrupt pending for TCC = 49" "No detected,Detected" bitfld.long 0x00 16. " In_48 ,Interrupt pending for TCC = 48" "No detected,Detected" textline " " bitfld.long 0x00 15. " In_47 ,Interrupt pending for TCC = 47" "No detected,Detected" bitfld.long 0x00 14. " In_46 ,Interrupt pending for TCC = 46" "No detected,Detected" bitfld.long 0x00 13. " In_45 ,Interrupt pending for TCC = 45" "No detected,Detected" bitfld.long 0x00 12. " In_44 ,Interrupt pending for TCC = 44" "No detected,Detected" textline " " bitfld.long 0x00 11. " In_43 ,Interrupt pending for TCC = 43" "No detected,Detected" bitfld.long 0x00 10. " In_42 ,Interrupt pending for TCC = 42" "No detected,Detected" bitfld.long 0x00 9. " In_41 ,Interrupt pending for TCC = 41" "No detected,Detected" bitfld.long 0x00 8. " In_40 ,Interrupt pending for TCC = 40" "No detected,Detected" textline " " bitfld.long 0x00 7. " In_39 ,Interrupt pending for TCC = 39" "No detected,Detected" bitfld.long 0x00 6. " In_38 ,Interrupt pending for TCC = 38" "No detected,Detected" bitfld.long 0x00 5. " In_37 ,Interrupt pending for TCC = 37" "No detected,Detected" bitfld.long 0x00 4. " In_36 ,Interrupt pending for TCC = 36" "No detected,Detected" textline " " bitfld.long 0x00 3. " In_35 ,Interrupt pending for TCC = 35" "No detected,Detected" bitfld.long 0x00 2. " In_34 ,Interrupt pending for TCC = 34" "No detected,Detected" bitfld.long 0x00 1. " In_33 ,Interrupt pending for TCC = 33" "No detected,Detected" bitfld.long 0x00 0. " In_32 ,Interrupt pending for TCC = 32" "No detected,Detected" wgroup.long 0x1070++0x03 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " In_31 ,Interrupt clear for TCC 31" "No effect,Clear" bitfld.long 0x00 30. " In_30 ,Interrupt clear for TCC 30" "No effect,Clear" bitfld.long 0x00 29. " In_29 ,Interrupt clear for TCC 29" "No effect,Clear" bitfld.long 0x00 28. " In_28 ,Interrupt clear for TCC 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " In_27 ,Interrupt clear for TCC 27" "No effect,Clear" bitfld.long 0x00 26. " In_26 ,Interrupt clear for TCC 26" "No effect,Clear" bitfld.long 0x00 25. " In_25 ,Interrupt clear for TCC 25" "No effect,Clear" bitfld.long 0x00 24. " In_24 ,Interrupt clear for TCC 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " In_23 ,Interrupt clear for TCC 23" "No effect,Clear" bitfld.long 0x00 22. " In_22 ,Interrupt clear for TCC 22" "No effect,Clear" bitfld.long 0x00 21. " In_21 ,Interrupt clear for TCC 21" "No effect,Clear" bitfld.long 0x00 20. " In_20 ,Interrupt clear for TCC 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " In_19 ,Interrupt clear for TCC 19" "No effect,Clear" bitfld.long 0x00 18. " In_18 ,Interrupt clear for TCC 18" "No effect,Clear" bitfld.long 0x00 17. " In_17 ,Interrupt clear for TCC 17" "No effect,Clear" bitfld.long 0x00 16. " In_16 ,Interrupt clear for TCC 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " In_15 ,Interrupt clear for TCC 15" "No effect,Clear" bitfld.long 0x00 14. " In_14 ,Interrupt clear for TCC 14" "No effect,Clear" bitfld.long 0x00 13. " In_13 ,Interrupt clear for TCC 13" "No effect,Clear" bitfld.long 0x00 12. " In_12 ,Interrupt clear for TCC 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " In_11 ,Interrupt clear for TCC 11" "No effect,Clear" bitfld.long 0x00 10. " In_10 ,Interrupt clear for TCC 10" "No effect,Clear" bitfld.long 0x00 9. " In_9 ,Interrupt clear for TCC 9" "No effect,Clear" bitfld.long 0x00 8. " In_8 ,Interrupt clear for TCC 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " In_7 ,Interrupt clear for TCC 7" "No effect,Clear" bitfld.long 0x00 6. " In_6 ,Interrupt clear for TCC 6" "No effect,Clear" bitfld.long 0x00 5. " In_5 ,Interrupt clear for TCC 5" "No effect,Clear" bitfld.long 0x00 4. " In_4 ,Interrupt clear for TCC 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " In_3 ,Interrupt clear for TCC 3" "No effect,Clear" bitfld.long 0x00 2. " In_2 ,Interrupt clear for TCC 2" "No effect,Clear" bitfld.long 0x00 1. " In_1 ,Interrupt clear for TCC 1" "No effect,Clear" bitfld.long 0x00 0. " In_0 ,Interrupt clear for TCC 0" "No effect,Clear" wgroup.long 0x1074++0x03 line.long 0x00 "ICRH,Interrupt Clear Register High" bitfld.long 0x00 31. " In_63 ,Interrupt clear for TCC 63" "No effect,Clear" bitfld.long 0x00 30. " In_62 ,Interrupt clear for TCC 62" "No effect,Clear" bitfld.long 0x00 29. " In_61 ,Interrupt clear for TCC 61" "No effect,Clear" bitfld.long 0x00 28. " In_60 ,Interrupt clear for TCC 60" "No effect,Clear" textline " " bitfld.long 0x00 27. " In_59 ,Interrupt clear for TCC 59" "No effect,Clear" bitfld.long 0x00 26. " In_58 ,Interrupt clear for TCC 58" "No effect,Clear" bitfld.long 0x00 25. " In_57 ,Interrupt clear for TCC 57" "No effect,Clear" bitfld.long 0x00 24. " In_56 ,Interrupt clear for TCC 56" "No effect,Clear" textline " " bitfld.long 0x00 23. " In_55 ,Interrupt clear for TCC 55" "No effect,Clear" bitfld.long 0x00 22. " In_54 ,Interrupt clear for TCC 54" "No effect,Clear" bitfld.long 0x00 21. " In_53 ,Interrupt clear for TCC 53" "No effect,Clear" bitfld.long 0x00 20. " In_52 ,Interrupt clear for TCC 52" "No effect,Clear" textline " " bitfld.long 0x00 19. " In_51 ,Interrupt clear for TCC 51" "No effect,Clear" bitfld.long 0x00 18. " In_50 ,Interrupt clear for TCC 50" "No effect,Clear" bitfld.long 0x00 17. " In_49 ,Interrupt clear for TCC 49" "No effect,Clear" bitfld.long 0x00 16. " In_48 ,Interrupt clear for TCC 48" "No effect,Clear" textline " " bitfld.long 0x00 15. " In_47 ,Interrupt clear for TCC 47" "No effect,Clear" bitfld.long 0x00 14. " In_46 ,Interrupt clear for TCC 46" "No effect,Clear" bitfld.long 0x00 13. " In_45 ,Interrupt clear for TCC 45" "No effect,Clear" bitfld.long 0x00 12. " In_44 ,Interrupt clear for TCC 44" "No effect,Clear" textline " " bitfld.long 0x00 11. " In_43 ,Interrupt clear for TCC 43" "No effect,Clear" bitfld.long 0x00 10. " In_42 ,Interrupt clear for TCC 42" "No effect,Clear" bitfld.long 0x00 9. " In_41 ,Interrupt clear for TCC 41" "No effect,Clear" bitfld.long 0x00 8. " In_40 ,Interrupt clear for TCC 40" "No effect,Clear" textline " " bitfld.long 0x00 7. " In_39 ,Interrupt clear for TCC 39" "No effect,Clear" bitfld.long 0x00 6. " In_38 ,Interrupt clear for TCC 38" "No effect,Clear" bitfld.long 0x00 5. " In_37 ,Interrupt clear for TCC 37" "No effect,Clear" bitfld.long 0x00 4. " In_36 ,Interrupt clear for TCC 36" "No effect,Clear" textline " " bitfld.long 0x00 3. " In_35 ,Interrupt clear for TCC 35" "No effect,Clear" bitfld.long 0x00 2. " In_34 ,Interrupt clear for TCC 34" "No effect,Clear" bitfld.long 0x00 1. " In_33 ,Interrupt clear for TCC 33" "No effect,Clear" bitfld.long 0x00 0. " In_32 ,Interrupt clear for TCC 32" "No effect,Clear" wgroup.long 0x1078++0x03 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Pulse" rgroup.long 0x1080++0x03 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " En_7 ,QDMA event for channels 7" "No effect,Trigger" bitfld.long 0x00 6. " En_6 ,QDMA event for channels 6" "No effect,Trigger" bitfld.long 0x00 5. " En_5 ,QDMA event for channels 5" "No effect,Trigger" bitfld.long 0x00 4. " En_4 ,QDMA event for channels 4" "No effect,Trigger" textline " " bitfld.long 0x00 3. " En_3 ,QDMA event for channels 3" "No effect,Trigger" bitfld.long 0x00 2. " En_2 ,QDMA event for channels 2" "No effect,Trigger" bitfld.long 0x00 1. " En_1 ,QDMA event for channels 1" "No effect,Trigger" bitfld.long 0x00 0. " En_0 ,QDMA event for channels 0" "No effect,Trigger" rgroup.long 0x1084++0x03 line.long 0x00 "QEER,QDMA Event Enable Register" bitfld.long 0x00 7. " En_7 ,QDMA event enable for channels 7" "Disabled,Enabled" bitfld.long 0x00 6. " En_6 ,QDMA event enable for channels 6" "Disabled,Enabled" bitfld.long 0x00 5. " En_5 ,QDMA event enable for channels 5" "Disabled,Enabled" bitfld.long 0x00 4. " En_4 ,QDMA event enable for channels 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " En_3 ,QDMA event enable for channels 3" "Disabled,Enabled" bitfld.long 0x00 2. " En_2 ,QDMA event enable for channels 2" "Disabled,Enabled" bitfld.long 0x00 1. " En_1 ,QDMA event enable for channels 1" "Disabled,Enabled" bitfld.long 0x00 0. " En_0 ,QDMA event enable for channels 0" "Disabled,Enabled" wgroup.long 0x1088++0x03 line.long 0x00 "QEECR,QDMA Event Enable Clear Register" bitfld.long 0x00 7. " En_7 ,QDMA event enable clear for channels 7" "No effect,Cleared" bitfld.long 0x00 6. " En_6 ,QDMA event enable clear for channels 6" "No effect,Cleared" bitfld.long 0x00 5. " En_5 ,QDMA event enable clear for channels 5" "No effect,Cleared" bitfld.long 0x00 4. " En_4 ,QDMA event enable clear for channels 4" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_3 ,QDMA event enable clear for channels 3" "No effect,Cleared" bitfld.long 0x00 2. " En_2 ,QDMA event enable clear for channels 2" "No effect,Cleared" bitfld.long 0x00 1. " En_1 ,QDMA event enable clear for channels 1" "No effect,Cleared" bitfld.long 0x00 0. " En_0 ,QDMA event enable clear for channels 0" "No effect,Cleared" wgroup.long 0x108C++0x03 line.long 0x00 "QEESR,QDMA Event Enable Set Register" bitfld.long 0x00 7. " En_7 ,QDMA event enable set for channels 7" "No effect,Enabled" bitfld.long 0x00 6. " En_6 ,QDMA event enable set for channels 6" "No effect,Enabled" bitfld.long 0x00 5. " En_5 ,QDMA event enable set for channels 5" "No effect,Enabled" bitfld.long 0x00 4. " En_4 ,QDMA event enable set for channels 4" "No effect,Enabled" textline " " bitfld.long 0x00 3. " En_3 ,QDMA event enable set for channels 3" "No effect,Enabled" bitfld.long 0x00 2. " En_2 ,QDMA event enable set for channels 2" "No effect,Enabled" bitfld.long 0x00 1. " En_1 ,QDMA event enable set for channels 1" "No effect,Enabled" bitfld.long 0x00 0. " En_0 ,QDMA event enable set for channels 0" "No effect,Enabled" rgroup.long 0x1090++0x03 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " En_7 ,QDMA secondary event for channels 7" "Not stored,Stored" bitfld.long 0x00 6. " En_6 ,QDMA secondary event for channels 6" "Not stored,Stored" bitfld.long 0x00 5. " En_5 ,QDMA secondary event for channels 5" "Not stored,Stored" bitfld.long 0x00 4. " En_4 ,QDMA secondary event for channels 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " En_3 ,QDMA secondary event for channels 3" "Not stored,Stored" bitfld.long 0x00 2. " En_2 ,QDMA secondary event for channels 2" "Not stored,Stored" bitfld.long 0x00 1. " En_1 ,QDMA secondary event for channels 1" "Not stored,Stored" bitfld.long 0x00 0. " En_0 ,QDMA secondary event for channels 0" "Not stored,Stored" wgroup.long 0x1094++0x03 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " En_7 ,QDMA secondary event clear for channels 7" "No effect,Cleared" bitfld.long 0x00 6. " En_6 ,QDMA secondary event clear for channels 6" "No effect,Cleared" bitfld.long 0x00 5. " En_5 ,QDMA secondary event clear for channels 5" "No effect,Cleared" bitfld.long 0x00 4. " En_4 ,QDMA secondary event clear for channels 4" "No effect,Cleared" textline " " bitfld.long 0x00 3. " En_3 ,QDMA secondary event clear for channels 3" "No effect,Cleared" bitfld.long 0x00 2. " En_2 ,QDMA secondary event clear for channels 2" "No effect,Cleared" bitfld.long 0x00 1. " En_1 ,QDMA secondary event clear for channels 1" "No effect,Cleared" bitfld.long 0x00 0. " En_0 ,QDMA secondary event clear for channels 0" "No effect,Cleared" width 11. tree.end tree "EDMA3TC Registers" tree "EDMA3 Transfer Controller 0" base ad:0x49800000 width 11. rgroup.long 0x000++0x03 line.long 0x00 "PID,The peripheral identification register" hexmask.long.word 0x00 0.--15. 1. " PID , Peripheral identifier," rgroup.long 0x004++0x03 line.long 0x00 "TCCFG,EDMA3TC Configuration Register" bitfld.long 0x00 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" ",,4 entry," bitfld.long 0x00 4.--5. " BUSWIDTH ,Bus width parameterization" ",,128-bit," bitfld.long 0x00 0.--2. " FIFOSIZE ,FIFO size" ",,,,512 byte,,," group.long 0x010++0x03 line.long 0x00 "SYSCONFIG,EDMA3TC System Configuration Register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode," rgroup.long 0x100++0x03 line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register" bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3" bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,,," bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy" bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy" rgroup.long 0x120++0x03 line.long 0x00 "ERRSTAT,Error Register" bitfld.long 0x00 3. " MMRAERR ,MMR address error" "No error,Error" bitfld.long 0x00 2. " TRERR ,Transfer request (TR) error event" "No error,Error" bitfld.long 0x00 0. " BUSERR ,Bus error event" "No error,Error" group.long 0x124++0x03 line.long 0x00 "ERREN,Error Enable Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled" bitfld.long 0x00 2. " TRERR ,Interrupt enable for transfer request error" "Disabled,Enabled" bitfld.long 0x00 0. " BUSERR ,Interrupt enable for bus error" "Disabled,Enabled" wgroup.long 0x128++0x03 line.long 0x00 "ERRCLR,Error Clear Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt enable clear for the MMRAERR bit in the error status register" "No effect,Clear" bitfld.long 0x00 2. " TRERR ,Interrupt enable clear for the TRERR bit in the error status register" "No effect,Clear" bitfld.long 0x00 0. " BUSERR ,Interrupt clear for the BUSERR bit in the error status register" "No effect,Clear" rgroup.long 0x12C++0x03 line.long 0x00 "ERRDET,Error Details Register" bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled" bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code" bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error" wgroup.long 0x130++0x03 line.long 0x00 "ERRCMD,Error Interrupt Command Register" bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed" group.long 0x140++0x03 line.long 0x00 "RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. " RDRATE ,Read rate" "Fastest reads,4 cycles,8 cycles,16 cycles,32 cycles,,," rgroup.long 0x240++0x03 line.long 0x00 "SAOPT,Source Active Options Register" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID , FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" rgroup.long 0x244++0x03 line.long 0x00 "SASRC,Source Active Source Address Register" rgroup.long 0x248++0x03 line.long 0x00 "SACNT,Source Active Count Register" hexmask.long.word 0x00 16.--31. 1. " BCNT , B dimension count remaining for the Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A dimension count remaining for the Source Active Register Set" hgroup.long 0x24C++0x03 hide.long 0x00 "SADST,Source Active Destination Address Register" rgroup.long 0x250++0x03 line.long 0x00 "SABIDX,Source Active Source B-Index Register" hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays" rgroup.long 0x254++0x03 line.long 0x00 "SAMPPRXY,Source Active Memory Protection Proxy Register" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x258++0x03 line.long 0x00 "SACNTRLD,Source Active Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " ACNTRLD , A-count reload value" rgroup.long 0x25C++0x03 line.long 0x00 "SASRCBREF,Source Active Source Address B-Reference Register" hgroup.long 0x260++0x03 hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register" rgroup.long 0x280++0x03 line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. " ACNTRLD , A-count reload value for the Destination FIFO Register Set" hgroup.long 0x284++0x03 hide.long 0x00 "DFSRCBREF,Destination FIFO Set Destination Address B Reference Register" rgroup.long 0x288++0x03 line.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register" rgroup.long 0x300++0x03 line.long 0x00 "DFOPT0,Destination FIFO Options Register 0" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x304++0x03 hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0" rgroup.long 0x308++0x03 line.long 0x00 "DFCNT0,Destination FIFO Count Register 0" hexmask.long.word 0x00 16.--31. 1. " BCNT , B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A-dimension count remaining for Destination Register Set" rgroup.long 0x30C++0x03 line.long 0x00 "DFDST0,Destination FIFO Destination Address Register 0" rgroup.long 0x310++0x03 line.long 0x00 "DFBIDX0,Destination FIFO BIDX Register 0" hexmask.long.word 0x00 16.--31. 1. " DBIDX , B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX , B-Index offset between source arrays for the Destination FIFO Register Set" rgroup.long 0x314++0x03 line.long 0x00 "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x340++0x03 line.long 0x00 "DFOPT1,Destination FIFO Options Register 1" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x344++0x03 hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1" rgroup.long 0x348++0x03 line.long 0x00 "DFCNT1,Destination FIFO Count Register 1" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count remaining for Destination Register Set" rgroup.long 0x34C++0x03 line.long 0x00 "DFDST1,Destination FIFO Destination Address Register 1" rgroup.long 0x350++0x03 line.long 0x00 "DFBIDX1,Destination FIFO BIDX Register 1" hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays for the Destination FIFO Register Set" rgroup.long 0x354++0x03 line.long 0x00 "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x380++0x03 line.long 0x00 "DFOPT2,Destination FIFO Options Register 2" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x384++0x03 hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2" rgroup.long 0x388++0x03 line.long 0x00 "DFCNT2,Destination FIFO Count Register 2" hexmask.long.word 0x00 16.--31. 1. " BCNT , B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A-dimension count remaining for Destination Register Set" rgroup.long 0x38C++0x03 line.long 0x00 "DFDST2,Destination FIFO Destination Address Register 2" rgroup.long 0x390++0x03 line.long 0x00 "DFBIDX2,Destination FIFO BIDX Register 2" hexmask.long.word 0x00 16.--31. 1. " DBIDX , B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX , B-Index offset between source arrays for the Destination FIFO Register Set" rgroup.long 0x394++0x03 line.long 0x00 "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x3C0++0x03 line.long 0x00 "DFOPT3,Destination FIFO Options Register 3" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x3C4++0x03 hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3" rgroup.long 0x3C8++0x03 line.long 0x00 "DFCNT3,Destination FIFO Count Register 3" hexmask.long.word 0x00 16.--31. 1. " BCNT , B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A-dimension count remaining for Destination Register Set" rgroup.long 0x3CC++0x03 line.long 0x00 "DFDST3,Destination FIFO Destination Address Register 3" rgroup.long 0x3D0++0x03 line.long 0x00 "DFBIDX3,Destination FIFO BIDX Register 3" hexmask.long.word 0x00 16.--31. 1. " DBIDX , B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX , B-Index offset between source arrays for the Destination FIFO Register Set" group.long 0x3D4++0x03 line.long 0x00 "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 11. tree.end tree "EDMA3 Transfer Controller 1" base ad:0x49900000 width 11. rgroup.long 0x000++0x03 line.long 0x00 "PID,The peripheral identification register" hexmask.long.word 0x00 0.--15. 1. " PID , Peripheral identifier," rgroup.long 0x004++0x03 line.long 0x00 "TCCFG,EDMA3TC Configuration Register" bitfld.long 0x00 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" ",,4 entry," bitfld.long 0x00 4.--5. " BUSWIDTH ,Bus width parameterization" ",,128-bit," bitfld.long 0x00 0.--2. " FIFOSIZE ,FIFO size" ",,,,512 byte,,," group.long 0x010++0x03 line.long 0x00 "SYSCONFIG,EDMA3TC System Configuration Register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode," rgroup.long 0x100++0x03 line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register" bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3" bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,,," bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy" bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy" rgroup.long 0x120++0x03 line.long 0x00 "ERRSTAT,Error Register" bitfld.long 0x00 3. " MMRAERR ,MMR address error" "No error,Error" bitfld.long 0x00 2. " TRERR ,Transfer request (TR) error event" "No error,Error" bitfld.long 0x00 0. " BUSERR ,Bus error event" "No error,Error" group.long 0x124++0x03 line.long 0x00 "ERREN,Error Enable Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled" bitfld.long 0x00 2. " TRERR ,Interrupt enable for transfer request error" "Disabled,Enabled" bitfld.long 0x00 0. " BUSERR ,Interrupt enable for bus error" "Disabled,Enabled" wgroup.long 0x128++0x03 line.long 0x00 "ERRCLR,Error Clear Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt enable clear for the MMRAERR bit in the error status register" "No effect,Clear" bitfld.long 0x00 2. " TRERR ,Interrupt enable clear for the TRERR bit in the error status register" "No effect,Clear" bitfld.long 0x00 0. " BUSERR ,Interrupt clear for the BUSERR bit in the error status register" "No effect,Clear" rgroup.long 0x12C++0x03 line.long 0x00 "ERRDET,Error Details Register" bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled" bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code" bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error" wgroup.long 0x130++0x03 line.long 0x00 "ERRCMD,Error Interrupt Command Register" bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed" group.long 0x140++0x03 line.long 0x00 "RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. " RDRATE ,Read rate" "Fastest reads,4 cycles,8 cycles,16 cycles,32 cycles,,," rgroup.long 0x240++0x03 line.long 0x00 "SAOPT,Source Active Options Register" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID , FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" rgroup.long 0x244++0x03 line.long 0x00 "SASRC,Source Active Source Address Register" rgroup.long 0x248++0x03 line.long 0x00 "SACNT,Source Active Count Register" hexmask.long.word 0x00 16.--31. 1. " BCNT , B dimension count remaining for the Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A dimension count remaining for the Source Active Register Set" hgroup.long 0x24C++0x03 hide.long 0x00 "SADST,Source Active Destination Address Register" rgroup.long 0x250++0x03 line.long 0x00 "SABIDX,Source Active Source B-Index Register" hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays" rgroup.long 0x254++0x03 line.long 0x00 "SAMPPRXY,Source Active Memory Protection Proxy Register" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x258++0x03 line.long 0x00 "SACNTRLD,Source Active Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " ACNTRLD , A-count reload value" rgroup.long 0x25C++0x03 line.long 0x00 "SASRCBREF,Source Active Source Address B-Reference Register" hgroup.long 0x260++0x03 hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register" rgroup.long 0x280++0x03 line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. " ACNTRLD , A-count reload value for the Destination FIFO Register Set" hgroup.long 0x284++0x03 hide.long 0x00 "DFSRCBREF,Destination FIFO Set Destination Address B Reference Register" rgroup.long 0x288++0x03 line.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register" rgroup.long 0x300++0x03 line.long 0x00 "DFOPT0,Destination FIFO Options Register 0" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x304++0x03 hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0" rgroup.long 0x308++0x03 line.long 0x00 "DFCNT0,Destination FIFO Count Register 0" hexmask.long.word 0x00 16.--31. 1. " BCNT , B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A-dimension count remaining for Destination Register Set" rgroup.long 0x30C++0x03 line.long 0x00 "DFDST0,Destination FIFO Destination Address Register 0" rgroup.long 0x310++0x03 line.long 0x00 "DFBIDX0,Destination FIFO BIDX Register 0" hexmask.long.word 0x00 16.--31. 1. " DBIDX , B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX , B-Index offset between source arrays for the Destination FIFO Register Set" rgroup.long 0x314++0x03 line.long 0x00 "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x340++0x03 line.long 0x00 "DFOPT1,Destination FIFO Options Register 1" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x344++0x03 hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1" rgroup.long 0x348++0x03 line.long 0x00 "DFCNT1,Destination FIFO Count Register 1" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count remaining for Destination Register Set" rgroup.long 0x34C++0x03 line.long 0x00 "DFDST1,Destination FIFO Destination Address Register 1" rgroup.long 0x350++0x03 line.long 0x00 "DFBIDX1,Destination FIFO BIDX Register 1" hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays for the Destination FIFO Register Set" rgroup.long 0x354++0x03 line.long 0x00 "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x380++0x03 line.long 0x00 "DFOPT2,Destination FIFO Options Register 2" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x384++0x03 hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2" rgroup.long 0x388++0x03 line.long 0x00 "DFCNT2,Destination FIFO Count Register 2" hexmask.long.word 0x00 16.--31. 1. " BCNT , B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A-dimension count remaining for Destination Register Set" rgroup.long 0x38C++0x03 line.long 0x00 "DFDST2,Destination FIFO Destination Address Register 2" rgroup.long 0x390++0x03 line.long 0x00 "DFBIDX2,Destination FIFO BIDX Register 2" hexmask.long.word 0x00 16.--31. 1. " DBIDX , B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX , B-Index offset between source arrays for the Destination FIFO Register Set" rgroup.long 0x394++0x03 line.long 0x00 "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x3C0++0x03 line.long 0x00 "DFOPT3,Destination FIFO Options Register 3" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x3C4++0x03 hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3" rgroup.long 0x3C8++0x03 line.long 0x00 "DFCNT3,Destination FIFO Count Register 3" hexmask.long.word 0x00 16.--31. 1. " BCNT , B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A-dimension count remaining for Destination Register Set" rgroup.long 0x3CC++0x03 line.long 0x00 "DFDST3,Destination FIFO Destination Address Register 3" rgroup.long 0x3D0++0x03 line.long 0x00 "DFBIDX3,Destination FIFO BIDX Register 3" hexmask.long.word 0x00 16.--31. 1. " DBIDX , B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX , B-Index offset between source arrays for the Destination FIFO Register Set" group.long 0x3D4++0x03 line.long 0x00 "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 11. tree.end tree "EDMA3 Transfer Controller 1" base ad:0x49A00000 width 11. rgroup.long 0x000++0x03 line.long 0x00 "PID,The peripheral identification register" hexmask.long.word 0x00 0.--15. 1. " PID , Peripheral identifier," rgroup.long 0x004++0x03 line.long 0x00 "TCCFG,EDMA3TC Configuration Register" bitfld.long 0x00 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" ",,4 entry," bitfld.long 0x00 4.--5. " BUSWIDTH ,Bus width parameterization" ",,128-bit," bitfld.long 0x00 0.--2. " FIFOSIZE ,FIFO size" ",,,,512 byte,,," group.long 0x010++0x03 line.long 0x00 "SYSCONFIG,EDMA3TC System Configuration Register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode," rgroup.long 0x100++0x03 line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register" bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3" bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,,," bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy" bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy" rgroup.long 0x120++0x03 line.long 0x00 "ERRSTAT,Error Register" bitfld.long 0x00 3. " MMRAERR ,MMR address error" "No error,Error" bitfld.long 0x00 2. " TRERR ,Transfer request (TR) error event" "No error,Error" bitfld.long 0x00 0. " BUSERR ,Bus error event" "No error,Error" group.long 0x124++0x03 line.long 0x00 "ERREN,Error Enable Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled" bitfld.long 0x00 2. " TRERR ,Interrupt enable for transfer request error" "Disabled,Enabled" bitfld.long 0x00 0. " BUSERR ,Interrupt enable for bus error" "Disabled,Enabled" wgroup.long 0x128++0x03 line.long 0x00 "ERRCLR,Error Clear Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt enable clear for the MMRAERR bit in the error status register" "No effect,Clear" bitfld.long 0x00 2. " TRERR ,Interrupt enable clear for the TRERR bit in the error status register" "No effect,Clear" bitfld.long 0x00 0. " BUSERR ,Interrupt clear for the BUSERR bit in the error status register" "No effect,Clear" rgroup.long 0x12C++0x03 line.long 0x00 "ERRDET,Error Details Register" bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled" bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code" bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error" wgroup.long 0x130++0x03 line.long 0x00 "ERRCMD,Error Interrupt Command Register" bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed" group.long 0x140++0x03 line.long 0x00 "RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. " RDRATE ,Read rate" "Fastest reads,4 cycles,8 cycles,16 cycles,32 cycles,,," rgroup.long 0x240++0x03 line.long 0x00 "SAOPT,Source Active Options Register" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID , FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" rgroup.long 0x244++0x03 line.long 0x00 "SASRC,Source Active Source Address Register" rgroup.long 0x248++0x03 line.long 0x00 "SACNT,Source Active Count Register" hexmask.long.word 0x00 16.--31. 1. " BCNT , B dimension count remaining for the Source Active Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A dimension count remaining for the Source Active Register Set" hgroup.long 0x24C++0x03 hide.long 0x00 "SADST,Source Active Destination Address Register" rgroup.long 0x250++0x03 line.long 0x00 "SABIDX,Source Active Source B-Index Register" hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays" rgroup.long 0x254++0x03 line.long 0x00 "SAMPPRXY,Source Active Memory Protection Proxy Register" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x258++0x03 line.long 0x00 "SACNTRLD,Source Active Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " ACNTRLD , A-count reload value" rgroup.long 0x25C++0x03 line.long 0x00 "SASRCBREF,Source Active Source Address B-Reference Register" hgroup.long 0x260++0x03 hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register" rgroup.long 0x280++0x03 line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x00 0.--15. 1. " ACNTRLD , A-count reload value for the Destination FIFO Register Set" hgroup.long 0x284++0x03 hide.long 0x00 "DFSRCBREF,Destination FIFO Set Destination Address B Reference Register" rgroup.long 0x288++0x03 line.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register" rgroup.long 0x300++0x03 line.long 0x00 "DFOPT0,Destination FIFO Options Register 0" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x304++0x03 hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0" rgroup.long 0x308++0x03 line.long 0x00 "DFCNT0,Destination FIFO Count Register 0" hexmask.long.word 0x00 16.--31. 1. " BCNT , B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A-dimension count remaining for Destination Register Set" rgroup.long 0x30C++0x03 line.long 0x00 "DFDST0,Destination FIFO Destination Address Register 0" rgroup.long 0x310++0x03 line.long 0x00 "DFBIDX0,Destination FIFO BIDX Register 0" hexmask.long.word 0x00 16.--31. 1. " DBIDX , B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX , B-Index offset between source arrays for the Destination FIFO Register Set" rgroup.long 0x314++0x03 line.long 0x00 "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x340++0x03 line.long 0x00 "DFOPT1,Destination FIFO Options Register 1" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x344++0x03 hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1" rgroup.long 0x348++0x03 line.long 0x00 "DFCNT1,Destination FIFO Count Register 1" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count remaining for Destination Register Set" rgroup.long 0x34C++0x03 line.long 0x00 "DFDST1,Destination FIFO Destination Address Register 1" rgroup.long 0x350++0x03 line.long 0x00 "DFBIDX1,Destination FIFO BIDX Register 1" hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays for the Destination FIFO Register Set" rgroup.long 0x354++0x03 line.long 0x00 "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x380++0x03 line.long 0x00 "DFOPT2,Destination FIFO Options Register 2" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x384++0x03 hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2" rgroup.long 0x388++0x03 line.long 0x00 "DFCNT2,Destination FIFO Count Register 2" hexmask.long.word 0x00 16.--31. 1. " BCNT , B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A-dimension count remaining for Destination Register Set" rgroup.long 0x38C++0x03 line.long 0x00 "DFDST2,Destination FIFO Destination Address Register 2" rgroup.long 0x390++0x03 line.long 0x00 "DFBIDX2,Destination FIFO BIDX Register 2" hexmask.long.word 0x00 16.--31. 1. " DBIDX , B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX , B-Index offset between source arrays for the Destination FIFO Register Set" rgroup.long 0x394++0x03 line.long 0x00 "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x3C0++0x03 line.long 0x00 "DFOPT3,Destination FIFO Options Register 3" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC , Transfer complete code" bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bits,16-bits,32-bits,64-bits,128-bits,256-bits,," textline " " bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "0-highest,1,2,3,4,5,6,7-lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "Increment,Constant" bitfld.long 0x00 0. " SAM ,Source address mode within an array" "Increment,Constant" hgroup.long 0x3C4++0x03 hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3" rgroup.long 0x3C8++0x03 line.long 0x00 "DFCNT3,Destination FIFO Count Register 3" hexmask.long.word 0x00 16.--31. 1. " BCNT , B-dimension count remaining for Destination Register Set" hexmask.long.word 0x00 0.--15. 1. " ACNT , A-dimension count remaining for Destination Register Set" rgroup.long 0x3CC++0x03 line.long 0x00 "DFDST3,Destination FIFO Destination Address Register 3" rgroup.long 0x3D0++0x03 line.long 0x00 "DFBIDX3,Destination FIFO BIDX Register 3" hexmask.long.word 0x00 16.--31. 1. " DBIDX , B-Index offset between destination arrays for the Destination FIFO Register Set" hexmask.long.word 0x00 0.--15. 1. " SBIDX , B-Index offset between source arrays for the Destination FIFO Register Set" group.long 0x3D4++0x03 line.long 0x00 "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3" bitfld.long 0x00 8. " PRIV ,Privilege level" "User-level,Supervisor-level" bitfld.long 0x00 0.--3. " PRIVID , Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 11. tree.end tree.end tree.end tree "ADC0(Touchscreen Controller)" base ad:0x44E0D000 width 15. rgroup.long 0x000++0x03 line.long 0x00 "REVISION,Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme value" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function value" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Custom Revision value" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision value" group.long 0x010++0x03 line.long 0x00 "SYSCONFIG,SysConfig Register" bitfld.long 0x00 2.--3. " Idle_Mode ,Smart Idle with Wakeup" "Force Idle,No Idle,Smart-Idle,Smart Idle with Wakeup" group.long 0x024++0x03 line.long 0x00 "IRQSTATUS_RAW,IRQ status (unmasked)" bitfld.long 0x00 10. " PEN_IRQ_SYNCHRONIZED ,PEN_IRQ_synchronized" "Not pending,Pending" bitfld.long 0x00 9. " PEN_UP_EVT ,Pen_Up_Event" "Not pending,Pending" bitfld.long 0x00 8. " OUT_OF_RANGE ,Out_of_Range" "Not pending,Pending" bitfld.long 0x00 7. " FIFO1_UNDERFLOW ,FIFO1_Underflow" "Not pending,Pending" textline " " bitfld.long 0x00 6. " FIFO1_OVERRUN ,FIFO1_Overrun" "Not pending,Pending" bitfld.long 0x00 5. " FIFO1_THR ,FIFO1_Threshold" "Not pending,Pending" bitfld.long 0x00 4. " FIFO0_UNDERFLOW ,FIFO0_Underflow" "Not pending,Pending" bitfld.long 0x00 3. " FIFO0_OVERRUN ,FIFO0_Overrun" "Not pending,Pending" textline " " bitfld.long 0x00 2. " FIFO0_THR ,FIFO0_Threshold" "Not pending,Pending" bitfld.long 0x00 1. " END_OF_SEQUENCE ,No End_of_Sequence" "Not pending,Pending" bitfld.long 0x00 0. " HW_PEN_EVT_ASYNCHRONOUS ,HW_Pen_Event_asynchronous" "Not pending,Pending" group.long 0x028++0x03 line.long 0x00 "IRQSTATUS,IRQ status (masked)" bitfld.long 0x00 10. " HW_PEN_EVT_SYNCHRONOUS ,HW_Pen_Event_synchronous" "Not pending,Pending" bitfld.long 0x00 9. " PEN_UP_EVT ,Pen_Up_Event" "Not pending,Pending" bitfld.long 0x00 8. " OUT_OF_RANGE ,Out_of_Range" "Not pending,Pending" bitfld.long 0x00 7. " FIFO1_UNDERFLOW ,FIFO1_Underflow" "Not pending,Pending" textline " " bitfld.long 0x00 6. " FIFO1_OVERRUN ,FIFO1_Overrun" "Not pending,Pending" bitfld.long 0x00 5. " FIFO1_THR ,FIFO1_Threshold" "Not pending,Pending" bitfld.long 0x00 4. " FIFO0_UNDERFLOW ,FIFO0_Underflow" "Not pending,Pending" bitfld.long 0x00 3. " FIFO0_OVERRUN ,FIFO0_Overrun" "Not pending,Pending" textline " " bitfld.long 0x00 2. " FIFO0_THR ,FIFO0_Threshold" "Not pending,Pending" bitfld.long 0x00 1. " END_OF_SEQUENCE ,No End_of_Sequence" "Not pending,Pending" bitfld.long 0x00 0. " HW_PEN_EVT_ASYNCHRONOUS ,HW_Pen_Event_asynchronous" "Not pending,Pending" group.long 0x02C++0x03 line.long 0x00 "IRQENABLE_SET,IRQ enable set bits" bitfld.long 0x00 10. " HW_PEN_EVT_SYNCHRONOUS ,HW_Pen_Event_synchronous" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_UP_EVT ,Pen_Up_Event" "Disabled,Enabled" bitfld.long 0x00 8. " OUT_OF_RANGE ,Out_of_Range" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO1_UNDERFLOW ,FIFO1_Underflow" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " FIFO1_OVERRUN ,FIFO1_Overrun" "Disabled,Enabled" bitfld.long 0x00 5. " FIFO1_THR ,FIFO1_Threshold" "Disabled,Enabled" bitfld.long 0x00 4. " FIFO0_UNDERFLOW ,FIFO0_Underflow" "Disabled,Enabled" bitfld.long 0x00 3. " FIFO0_OVERRUN ,FIFO0_Overrun" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " FIFO0_THR ,FIFO0_Threshold" "Disabled,Enabled" bitfld.long 0x00 1. " END_OF_SEQUENCE ,No End_of_Sequence" "Disabled,Enabled" bitfld.long 0x00 0. " HW_PEN_EVT_ASYNCHRONOUS ,HW_Pen_Event_asynchronous" "Disabled,Enabled" group.long 0x030++0x03 line.long 0x00 "IRQENABLE_CLR,IRQ enable clear bits" bitfld.long 0x00 10. " HW_PEN_EVT_SYNCHRONOUS ,HW_Pen_Event_synchronous" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_UP_EVT ,Pen_Up_Event" "Disabled,Enabled" bitfld.long 0x00 8. " OUT_OF_RANGE ,Out_of_Range" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO1_UNDERFLOW ,FIFO1_Underflow" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " FIFO1_OVERRUN ,FIFO1_Overrun" "Disabled,Enabled" bitfld.long 0x00 5. " FIFO1_THR ,FIFO1_Threshold" "Disabled,Enabled" bitfld.long 0x00 4. " FIFO0_UNDERFLOW ,FIFO0_Underflow" "Disabled,Enabled" bitfld.long 0x00 3. " FIFO0_OVERRUN ,FIFO0_Overrun" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " FIFO0_THR ,FIFO0_Threshold" "Disabled,Enabled" bitfld.long 0x00 1. " END_OF_SEQUENCE ,No End_of_Sequence" "Disabled,Enabled" bitfld.long 0x00 0. " HW_PEN_EVT_ASYNCHRONOUS ,HW_Pen_Event_asynchronous" "Disabled,Enabled" group.long 0x034++0x03 line.long 0x00 "IRQWAKEUP,IRQ wakeup enable" bitfld.long 0x00 0. " WAKEEN0 ,Wakeup generation for HW Pen event" "Disabled,Enabled" group.long 0x038++0x03 line.long 0x00 "DMAENABLE_SET,Per-Line DMA set" bitfld.long 0x00 1. " EN_1 ,Enable DMA request FIFO 1" "Disabled,Enabled" bitfld.long 0x00 0. " EN_0 ,Enable DMA request FIFO 0" "Disabled,Enabled" group.long 0x03C++0x03 line.long 0x00 "DMAENABLE_CLR,Per-Line DMA clr" bitfld.long 0x00 1. " EN_1 ,Disable DMA request FIFO 1" "No,Yes" bitfld.long 0x00 0. " EN_0 ,Disable DMA request FIFO 0" "No,Yes" group.long 0x040++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 9. " HW_PREEMPT ,HW_preempt" "Not pre-empted,Pre-empted" bitfld.long 0x00 8. " HW_EVT_MAPPING ,HW_event_mapping" "Pen touch irq,HW event input" bitfld.long 0x00 7. " TOUCH_SCREEN_EN ,Touch_Screen_Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--6. " AFE_PEN_CTRL ,AFE_Pen_Ctrl" "0,1,2,3" bitfld.long 0x00 4. " POWER_DOWN ,ADC Power Down control" "Up,Down" bitfld.long 0x00 3. " ADC_BIAS_SELECT ,ADC_Bias_Select" "Internal," textline " " bitfld.long 0x00 2. " STEPCONFIG_WRITEPROTECT_N ,StepConfig_WriteProtect_n_active_low" "Protected,Not protected" bitfld.long 0x00 1. " STEP_ID_TAG ,Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO" "Not store,Store" bitfld.long 0x00 0. " EN ,TSC_ADC_SS module enable bit" "Disabled,Enabled" rgroup.long 0x044++0x03 line.long 0x00 "ADCSTAT,General Status bits for Sequencer Status " bitfld.long 0x00 7. " PEN_IRQ1 ,PEN_IRQ[1] status" "0,1" bitfld.long 0x00 6. " PEN_IRQ0 ,PEN_IRQ[0] status" "0,1" bitfld.long 0x00 5. " FSM_BUSY ,Status of OCP FSM and ADC FSM" "Idle,Busy" bitfld.long 0x00 0.--4. " STEP_ID ,STEP_ID" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Idle,Charge,,,,,,,,,,,,,," group.long 0x048++0x03 line.long 0x00 "ADCRANGE,High and Low Range Threshold for ADC Range Check" hexmask.long.word 0x00 16.--27. 1. " High_Range_Data ,Sampled ADC data is compared to this value" hexmask.long.word 0x00 0.--11. 1. " Low_Range_Data ,Sampled ADC data is compared to this value" group.long 0x04C++0x03 line.long 0x00 "ADC_CLKDIV,ADC clock divider register" hexmask.long.word 0x00 0.--15. 1. " ADC_ClkDiv ,The input ADC clock will be divided by this value and sent to the AFE" group.long 0x050++0x03 line.long 0x00 "ADC_MISC,AFE misc debug" bitfld.long 0x00 4.--7. " AFE_Spare_Output ,Connected to AFE Spare Output pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " AFE_Spare_Input ,Connected to AFE Spare Input pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x054++0x03 line.long 0x00 "STEPENABLE,Step Enable" bitfld.long 0x00 14. " STEP14 ,Enable step 14" "Disabled,Enabled" bitfld.long 0x00 13. " STEP13 ,Enable step 13" "Disabled,Enabled" bitfld.long 0x00 12. " STEP12 ,Enable step 12" "Disabled,Enabled" bitfld.long 0x00 15. " STEP15 ,Enable step 15" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " STEP16 ,Enable step 16" "Disabled,Enabled" bitfld.long 0x00 11. " STEP11 ,Enable step 11" "Disabled,Enabled" bitfld.long 0x00 10. " STEP10 ,Enable step 10" "Disabled,Enabled" bitfld.long 0x00 9. " STEP9 ,Enable step 9" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " STEP8 ,Enable step 8" "Disabled,Enabled" bitfld.long 0x00 7. " STEP7 ,Enable step 7" "Disabled,Enabled" bitfld.long 0x00 6. " STEP6 ,Enable step 6" "Disabled,Enabled" bitfld.long 0x00 5. " STEP5 ,Enable step 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " STEP4 ,Enable step 4" "Disabled,Enabled" bitfld.long 0x00 3. " STEP3 ,Enable step 3" "Disabled,Enabled" bitfld.long 0x00 2. " STEP2 ,Enable step 2" "Disabled,Enabled" bitfld.long 0x00 1. " STEP1 ,Enable step 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TS_Charge ,Enable TS Charge step" "Disabled,Enabled" group.long 0x058++0x03 line.long 0x00 "IDLECONFIG,Idle Step configuration" bitfld.long 0x00 25. " Diff_CNTRL ,Differential Control Pin" "Single,Differential" bitfld.long 0x00 23.--24. " SEL_RFM__SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA_ADC,XNUR,YNLR,VREFN" bitfld.long 0x00 19.--22. " SEL_INP_SWC ,SEL_INP pins SW configuration" ",1,2,3,4,5,6,7,8,,,,,,," bitfld.long 0x00 15.--18. " SEL_INM_SWM3_0 ,SEL_INM pins for neg differential" "1,2,3,4,5,6,7,8,,,,,,,," textline " " bitfld.long 0x00 12.--14. " VREFP ,VREFP" "VDDA_ADC,XPUL,YPLL,VREFP,,,," bitfld.long 0x00 11. " WPNSW_SWC ,WPNSW pin SW configuration" "0,1" bitfld.long 0x00 10. " YPNSW_SWC ,YPNSW pin SW configuration" "0,1" bitfld.long 0x00 9. " XNPSW_SWC ,XNPSW pin SW configuration" "0,1" textline " " bitfld.long 0x00 8. " YNNSW_SWC ,YNNSW pin SW configuration" "0,1" bitfld.long 0x00 7. " YPPSW__SWC ,YPPSW pin SW configuration" "0,1" bitfld.long 0x00 6. " XNNSW__SWC ,XNNSW pin SW configuration" "0,1" bitfld.long 0x00 5. " XPPSW_SWC ,XPPSW pin SW configuration" "0,1" textline " " width 22. group.long 0x05C++0x03 line.long 0x00 "TS_CHARGE_STEPCONFIG,TS Charge StepConfiguration" bitfld.long 0x00 25. " Diff_CNTRL ,Differential Control Pin" "Single,Differential" bitfld.long 0x00 23.--24. " SEL_RFM__SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA_ADC,XNUR,YNLR,VREFN" bitfld.long 0x00 19.--22. " SEL_INP_SWC ,SEL_INP pins SW configuration" ",1,2,3,4,5,6,7,8,,,,,,," bitfld.long 0x00 15.--18. " SEL_INM_SWM3_0 ,SEL_INM pins for neg differential" "1,2,3,4,5,6,7,8,,,,,,,," textline " " bitfld.long 0x00 12.--14. " VREFP ,VREFP" "VDDA_ADC,XPUL,YPLL,VREFP,,,," bitfld.long 0x00 11. " WPNSW_SWC ,WPNSW pin SW configuration" "0,1" bitfld.long 0x00 10. " YPNSW_SWC ,YPNSW pin SW configuration" "0,1" bitfld.long 0x00 9. " XNPSW_SWC ,XNPSW pin SW configuration" "0,1" textline " " bitfld.long 0x00 8. " YNNSW_SWC ,YNNSW pin SW configuration" "0,1" bitfld.long 0x00 7. " YPPSW__SWC ,YPPSW pin SW configuration" "0,1" bitfld.long 0x00 6. " XNNSW__SWC ,XNNSW pin SW configuration" "0,1" bitfld.long 0x00 5. " XPPSW_SWC ,XPPSW pin SW configuration" "0,1" textline " " width 17. group.long 0x060++0x03 line.long 0x00 "TS_CHARGE_DELAY,TS Charge Delay Register" hexmask.long.tbyte 0x00 0.--17. 1. " OpenDelay ,Program the # of ADC clock cycles to wait between applying the step configuration registers and going back to the IDLE state" group.long 0x064++0x03 line.long 0x00 "STEPCONFIG,Step Configuration" bitfld.long 0x00 23.--24. " SEL_RFM_SWC ,SEL_RFM pins SW configuration" "VSSA_ADC,XNUR,YNLR,VREFN" bitfld.long 0x00 19.--22. " SEL_INP_SWC ,SEL_INP pins SW configuration" "1,2,3,4,5,6,7,8,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN" bitfld.long 0x00 15.--18. " SEL_INM_SWC ,SEL_INM pins for neg differential" "1,2,3,4,5,6,7,8,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN" bitfld.long 0x00 12.--14. " SEL_RFP_SWC ,EL_RFP pins SW configuration" "VDDA_ADC,XPUL,YPLL,VREFP,INTREF,INTREF,INTREF,INTREF" textline " " bitfld.long 0x00 9. " XNPSW_SWC ,XNPSW pin SW configuration" "0,1" bitfld.long 0x00 10. " YPNSW_SWC ,YPNSW pin SW configuration" "0,1" bitfld.long 0x00 27. " RANGE_CHECK , Range_check" "Disabled,Enabled" bitfld.long 0x00 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 6. " XNNSW_SWC ,XNNSW pin SW configuration" "0,1" bitfld.long 0x00 7. " YPPSW_SWC ,YPPSW pin SW configuration" "0,1" bitfld.long 0x00 5. " XPPSW_SWC ,XPPSW pin SW configuration" "0,1" bitfld.long 0x00 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,,," textline " " bitfld.long 0x00 0.--1. " MODE ,Mode" "SW_EN_ONESHOT,SW_EN_CONTINUOUS,HW_SYNC_ONESHOT,HW_SYNC_CONTINUOUS" bitfld.long 0x00 11. " WPNSW_SWC ,WPNSW pin SW configuration" "0,1" bitfld.long 0x00 25. " Diff_CNTRL ,Differential Control Pin" "0,1" bitfld.long 0x00 8. " YNNSW_SWC ,YNNSW pin SW configuration" "0,1" group.long 0x068++0x03 line.long 0x00 "STEPDELAY,Step Delay Register" hexmask.long.byte 0x00 24.--31. 1. " SampleDelay ,This register will control the number of ADC clock cycles to sample" hexmask.long.tbyte 0x00 0.--17. 1. " OpenDelay ,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion" rgroup.long 0x0E4++0x03 line.long 0x00 "FIFO0COUNT,FIFO word count" hexmask.long.byte 0x00 0.--6. 1. " Words_in_FIFO0 ,Number of words currently in the FIFO" group.long 0x0E8++0x03 line.long 0x00 "FIFO0THRESHOLD,FIFO Threshold level trigger" hexmask.long.byte 0x00 0.--5. 1. " FIFO0_threshold_Level ,Program the desired FIFO data sample level to reach before generating interrupt to CPU" group.long 0x0EC++0x03 line.long 0x00 "DMA0REQ,FIFO DMA req (request) trigger" hexmask.long.byte 0x00 0.--5. 1. " DMA_Request_Level ,Number of words in FIFO before generating a DMA request" rgroup.long 0x100++0x03 line.long 0x00 "FIFO0DATA,ADC_ FIFO0 _READ Data " bitfld.long 0x00 16.--19. " ADCCHNLID ,Optional ID tag of channel that captured the data" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ADCDATA ,12 bit sampled ADC converted data value stored in FIFO 0." rgroup.long 0x200++0x03 line.long 0x00 "FIFO1DATA,ADC FIFO1_READ Data" bitfld.long 0x00 16.--19. " ADCCHNLID ,Optional ID tag of channel that captured the data" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ADCDATA ,12 bit sampled ADC converted data value stored in FIFO 1." tree.end tree "ADC1(Magnetic Card Reader)" base ad:0x4834C000 width 15. rgroup.long 0x000++0x03 line.long 0x00 "REVISION,Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme value" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function value" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Custom Revision value" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision value" group.long 0x010++0x03 line.long 0x00 "SYSCONFIG,SysConfig Register" bitfld.long 0x00 2.--3. " Idle_Mode ,Smart Idle with Wakeup" "Force Idle,No Idle,Smart-Idle,Smart Idle with Wakeup" group.long 0x024++0x03 line.long 0x00 "IRQSTATUS_RAW,IRQ status (unmasked)" bitfld.long 0x00 10. " PEN_IRQ_SYNCHRONIZED ,PEN_IRQ_synchronized" "Not pending,Pending" bitfld.long 0x00 9. " PEN_UP_EVT ,Pen_Up_Event" "Not pending,Pending" bitfld.long 0x00 8. " OUT_OF_RANGE ,Out_of_Range" "Not pending,Pending" bitfld.long 0x00 7. " FIFO1_UNDERFLOW ,FIFO1_Underflow" "Not pending,Pending" textline " " bitfld.long 0x00 6. " FIFO1_OVERRUN ,FIFO1_Overrun" "Not pending,Pending" bitfld.long 0x00 5. " FIFO1_THR ,FIFO1_Threshold" "Not pending,Pending" bitfld.long 0x00 4. " FIFO0_UNDERFLOW ,FIFO0_Underflow" "Not pending,Pending" bitfld.long 0x00 3. " FIFO0_OVERRUN ,FIFO0_Overrun" "Not pending,Pending" textline " " bitfld.long 0x00 2. " FIFO0_THR ,FIFO0_Threshold" "Not pending,Pending" bitfld.long 0x00 1. " END_OF_SEQUENCE ,No End_of_Sequence" "Not pending,Pending" bitfld.long 0x00 0. " HW_PEN_EVT_ASYNCHRONOUS ,HW_Pen_Event_asynchronous" "Not pending,Pending" group.long 0x028++0x03 line.long 0x00 "IRQSTATUS,IRQ status (masked)" bitfld.long 0x00 10. " HW_PEN_EVT_SYNCHRONOUS ,HW_Pen_Event_synchronous" "Not pending,Pending" bitfld.long 0x00 9. " PEN_UP_EVT ,Pen_Up_Event" "Not pending,Pending" bitfld.long 0x00 8. " OUT_OF_RANGE ,Out_of_Range" "Not pending,Pending" bitfld.long 0x00 7. " FIFO1_UNDERFLOW ,FIFO1_Underflow" "Not pending,Pending" textline " " bitfld.long 0x00 6. " FIFO1_OVERRUN ,FIFO1_Overrun" "Not pending,Pending" bitfld.long 0x00 5. " FIFO1_THR ,FIFO1_Threshold" "Not pending,Pending" bitfld.long 0x00 4. " FIFO0_UNDERFLOW ,FIFO0_Underflow" "Not pending,Pending" bitfld.long 0x00 3. " FIFO0_OVERRUN ,FIFO0_Overrun" "Not pending,Pending" textline " " bitfld.long 0x00 2. " FIFO0_THR ,FIFO0_Threshold" "Not pending,Pending" bitfld.long 0x00 1. " END_OF_SEQUENCE ,No End_of_Sequence" "Not pending,Pending" bitfld.long 0x00 0. " HW_PEN_EVT_ASYNCHRONOUS ,HW_Pen_Event_asynchronous" "Not pending,Pending" group.long 0x02C++0x03 line.long 0x00 "IRQENABLE_SET,IRQ enable set bits" bitfld.long 0x00 10. " HW_PEN_EVT_SYNCHRONOUS ,HW_Pen_Event_synchronous" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_UP_EVT ,Pen_Up_Event" "Disabled,Enabled" bitfld.long 0x00 8. " OUT_OF_RANGE ,Out_of_Range" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO1_UNDERFLOW ,FIFO1_Underflow" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " FIFO1_OVERRUN ,FIFO1_Overrun" "Disabled,Enabled" bitfld.long 0x00 5. " FIFO1_THR ,FIFO1_Threshold" "Disabled,Enabled" bitfld.long 0x00 4. " FIFO0_UNDERFLOW ,FIFO0_Underflow" "Disabled,Enabled" bitfld.long 0x00 3. " FIFO0_OVERRUN ,FIFO0_Overrun" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " FIFO0_THR ,FIFO0_Threshold" "Disabled,Enabled" bitfld.long 0x00 1. " END_OF_SEQUENCE ,No End_of_Sequence" "Disabled,Enabled" bitfld.long 0x00 0. " HW_PEN_EVT_ASYNCHRONOUS ,HW_Pen_Event_asynchronous" "Disabled,Enabled" group.long 0x030++0x03 line.long 0x00 "IRQENABLE_CLR,IRQ enable clear bits" bitfld.long 0x00 10. " HW_PEN_EVT_SYNCHRONOUS ,HW_Pen_Event_synchronous" "Disabled,Enabled" bitfld.long 0x00 9. " PEN_UP_EVT ,Pen_Up_Event" "Disabled,Enabled" bitfld.long 0x00 8. " OUT_OF_RANGE ,Out_of_Range" "Disabled,Enabled" bitfld.long 0x00 7. " FIFO1_UNDERFLOW ,FIFO1_Underflow" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " FIFO1_OVERRUN ,FIFO1_Overrun" "Disabled,Enabled" bitfld.long 0x00 5. " FIFO1_THR ,FIFO1_Threshold" "Disabled,Enabled" bitfld.long 0x00 4. " FIFO0_UNDERFLOW ,FIFO0_Underflow" "Disabled,Enabled" bitfld.long 0x00 3. " FIFO0_OVERRUN ,FIFO0_Overrun" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " FIFO0_THR ,FIFO0_Threshold" "Disabled,Enabled" bitfld.long 0x00 1. " END_OF_SEQUENCE ,No End_of_Sequence" "Disabled,Enabled" bitfld.long 0x00 0. " HW_PEN_EVT_ASYNCHRONOUS ,HW_Pen_Event_asynchronous" "Disabled,Enabled" group.long 0x034++0x03 line.long 0x00 "IRQWAKEUP,IRQ wakeup enable" bitfld.long 0x00 0. " WAKEEN0 ,Wakeup generation for HW Pen event" "Disabled,Enabled" group.long 0x038++0x03 line.long 0x00 "DMAENABLE_SET,Per-Line DMA set" bitfld.long 0x00 1. " EN_1 ,Enable DMA request FIFO 1" "Disabled,Enabled" bitfld.long 0x00 0. " EN_0 ,Enable DMA request FIFO 0" "Disabled,Enabled" group.long 0x03C++0x03 line.long 0x00 "DMAENABLE_CLR,Per-Line DMA clr" bitfld.long 0x00 1. " EN_1 ,Disable DMA request FIFO 1" "No,Yes" bitfld.long 0x00 0. " EN_0 ,Disable DMA request FIFO 0" "No,Yes" group.long 0x040++0x03 line.long 0x00 "CTRL,Control Register" bitfld.long 0x00 9. " HW_PREEMPT ,HW_preempt" "Not pre-empted,Pre-empted" bitfld.long 0x00 8. " HW_EVT_MAPPING ,HW_event_mapping" "Pen touch irq,HW event input" bitfld.long 0x00 7. " TOUCH_SCREEN_EN ,Touch_Screen_Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--6. " AFE_PEN_CTRL ,AFE_Pen_Ctrl" "0,1,2,3" bitfld.long 0x00 4. " POWER_DOWN ,ADC Power Down control" "Up,Down" bitfld.long 0x00 3. " ADC_BIAS_SELECT ,ADC_Bias_Select" "Internal," textline " " bitfld.long 0x00 2. " STEPCONFIG_WRITEPROTECT_N ,StepConfig_WriteProtect_n_active_low" "Protected,Not protected" bitfld.long 0x00 1. " STEP_ID_TAG ,Writing 1 to this bit will store the Step ID number with the captured ADC data in the FIFO" "Not store,Store" bitfld.long 0x00 0. " EN ,TSC_ADC_SS module enable bit" "Disabled,Enabled" rgroup.long 0x044++0x03 line.long 0x00 "ADCSTAT,General Status bits for Sequencer Status " bitfld.long 0x00 7. " PEN_IRQ1 ,PEN_IRQ[1] status" "0,1" bitfld.long 0x00 6. " PEN_IRQ0 ,PEN_IRQ[0] status" "0,1" bitfld.long 0x00 5. " FSM_BUSY ,Status of OCP FSM and ADC FSM" "Idle,Busy" bitfld.long 0x00 0.--4. " STEP_ID ,STEP_ID" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Idle,Charge,,,,,,,,,,,,,," group.long 0x048++0x03 line.long 0x00 "ADCRANGE,High and Low Range Threshold for ADC Range Check" hexmask.long.word 0x00 16.--27. 1. " High_Range_Data ,Sampled ADC data is compared to this value" hexmask.long.word 0x00 0.--11. 1. " Low_Range_Data ,Sampled ADC data is compared to this value" group.long 0x04C++0x03 line.long 0x00 "ADC_CLKDIV,ADC clock divider register" hexmask.long.word 0x00 0.--15. 1. " ADC_ClkDiv ,The input ADC clock will be divided by this value and sent to the AFE" group.long 0x050++0x03 line.long 0x00 "ADC_MISC,AFE misc debug" bitfld.long 0x00 4.--7. " AFE_Spare_Output ,Connected to AFE Spare Output pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " AFE_Spare_Input ,Connected to AFE Spare Input pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x054++0x03 line.long 0x00 "STEPENABLE,Step Enable" bitfld.long 0x00 14. " STEP14 ,Enable step 14" "Disabled,Enabled" bitfld.long 0x00 13. " STEP13 ,Enable step 13" "Disabled,Enabled" bitfld.long 0x00 12. " STEP12 ,Enable step 12" "Disabled,Enabled" bitfld.long 0x00 15. " STEP15 ,Enable step 15" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " STEP16 ,Enable step 16" "Disabled,Enabled" bitfld.long 0x00 11. " STEP11 ,Enable step 11" "Disabled,Enabled" bitfld.long 0x00 10. " STEP10 ,Enable step 10" "Disabled,Enabled" bitfld.long 0x00 9. " STEP9 ,Enable step 9" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " STEP8 ,Enable step 8" "Disabled,Enabled" bitfld.long 0x00 7. " STEP7 ,Enable step 7" "Disabled,Enabled" bitfld.long 0x00 6. " STEP6 ,Enable step 6" "Disabled,Enabled" bitfld.long 0x00 5. " STEP5 ,Enable step 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " STEP4 ,Enable step 4" "Disabled,Enabled" bitfld.long 0x00 3. " STEP3 ,Enable step 3" "Disabled,Enabled" bitfld.long 0x00 2. " STEP2 ,Enable step 2" "Disabled,Enabled" bitfld.long 0x00 1. " STEP1 ,Enable step 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TS_Charge ,Enable TS Charge step" "Disabled,Enabled" group.long 0x058++0x03 line.long 0x00 "IDLECONFIG,Idle Step configuration" bitfld.long 0x00 25. " Diff_CNTRL ,Differential Control Pin" "Single,Differential" bitfld.long 0x00 23.--24. " SEL_RFM__SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA_ADC,XNUR,YNLR,VREFN" bitfld.long 0x00 19.--22. " SEL_INP_SWC ,SEL_INP pins SW configuration" ",1,2,3,4,5,6,7,8,,,,,,," bitfld.long 0x00 15.--18. " SEL_INM_SWM3_0 ,SEL_INM pins for neg differential" "1,2,3,4,5,6,7,8,,,,,,,," textline " " bitfld.long 0x00 12.--14. " VREFP ,VREFP" "VDDA_ADC,XPUL,YPLL,VREFP,,,," bitfld.long 0x00 11. " WPNSW_SWC ,WPNSW pin SW configuration" "0,1" bitfld.long 0x00 10. " YPNSW_SWC ,YPNSW pin SW configuration" "0,1" bitfld.long 0x00 9. " XNPSW_SWC ,XNPSW pin SW configuration" "0,1" textline " " bitfld.long 0x00 8. " YNNSW_SWC ,YNNSW pin SW configuration" "0,1" bitfld.long 0x00 7. " YPPSW__SWC ,YPPSW pin SW configuration" "0,1" bitfld.long 0x00 6. " XNNSW__SWC ,XNNSW pin SW configuration" "0,1" bitfld.long 0x00 5. " XPPSW_SWC ,XPPSW pin SW configuration" "0,1" textline " " width 22. group.long 0x05C++0x03 line.long 0x00 "TS_CHARGE_STEPCONFIG,TS Charge StepConfiguration" bitfld.long 0x00 25. " Diff_CNTRL ,Differential Control Pin" "Single,Differential" bitfld.long 0x00 23.--24. " SEL_RFM__SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA_ADC,XNUR,YNLR,VREFN" bitfld.long 0x00 19.--22. " SEL_INP_SWC ,SEL_INP pins SW configuration" ",1,2,3,4,5,6,7,8,,,,,,," bitfld.long 0x00 15.--18. " SEL_INM_SWM3_0 ,SEL_INM pins for neg differential" "1,2,3,4,5,6,7,8,,,,,,,," textline " " bitfld.long 0x00 12.--14. " VREFP ,VREFP" "VDDA_ADC,XPUL,YPLL,VREFP,,,," bitfld.long 0x00 11. " WPNSW_SWC ,WPNSW pin SW configuration" "0,1" bitfld.long 0x00 10. " YPNSW_SWC ,YPNSW pin SW configuration" "0,1" bitfld.long 0x00 9. " XNPSW_SWC ,XNPSW pin SW configuration" "0,1" textline " " bitfld.long 0x00 8. " YNNSW_SWC ,YNNSW pin SW configuration" "0,1" bitfld.long 0x00 7. " YPPSW__SWC ,YPPSW pin SW configuration" "0,1" bitfld.long 0x00 6. " XNNSW__SWC ,XNNSW pin SW configuration" "0,1" bitfld.long 0x00 5. " XPPSW_SWC ,XPPSW pin SW configuration" "0,1" textline " " width 17. group.long 0x060++0x03 line.long 0x00 "TS_CHARGE_DELAY,TS Charge Delay Register" hexmask.long.tbyte 0x00 0.--17. 1. " OpenDelay ,Program the # of ADC clock cycles to wait between applying the step configuration registers and going back to the IDLE state" group.long 0x064++0x03 line.long 0x00 "STEPCONFIG,Step Configuration" bitfld.long 0x00 23.--24. " SEL_RFM_SWC ,SEL_RFM pins SW configuration" "VSSA_ADC,XNUR,YNLR,VREFN" bitfld.long 0x00 19.--22. " SEL_INP_SWC ,SEL_INP pins SW configuration" "1,2,3,4,5,6,7,8,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN" bitfld.long 0x00 15.--18. " SEL_INM_SWC ,SEL_INM pins for neg differential" "1,2,3,4,5,6,7,8,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN" bitfld.long 0x00 12.--14. " SEL_RFP_SWC ,EL_RFP pins SW configuration" "VDDA_ADC,XPUL,YPLL,VREFP,INTREF,INTREF,INTREF,INTREF" textline " " bitfld.long 0x00 9. " XNPSW_SWC ,XNPSW pin SW configuration" "0,1" bitfld.long 0x00 10. " YPNSW_SWC ,YPNSW pin SW configuration" "0,1" bitfld.long 0x00 27. " RANGE_CHECK , Range_check" "Disabled,Enabled" bitfld.long 0x00 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO 0,FIFO 1" textline " " bitfld.long 0x00 6. " XNNSW_SWC ,XNNSW pin SW configuration" "0,1" bitfld.long 0x00 7. " YPPSW_SWC ,YPPSW pin SW configuration" "0,1" bitfld.long 0x00 5. " XPPSW_SWC ,XPPSW pin SW configuration" "0,1" bitfld.long 0x00 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,,," textline " " bitfld.long 0x00 0.--1. " MODE ,Mode" "SW_EN_ONESHOT,SW_EN_CONTINUOUS,HW_SYNC_ONESHOT,HW_SYNC_CONTINUOUS" bitfld.long 0x00 11. " WPNSW_SWC ,WPNSW pin SW configuration" "0,1" bitfld.long 0x00 25. " Diff_CNTRL ,Differential Control Pin" "0,1" bitfld.long 0x00 8. " YNNSW_SWC ,YNNSW pin SW configuration" "0,1" group.long 0x068++0x03 line.long 0x00 "STEPDELAY,Step Delay Register" hexmask.long.byte 0x00 24.--31. 1. " SampleDelay ,This register will control the number of ADC clock cycles to sample" hexmask.long.tbyte 0x00 0.--17. 1. " OpenDelay ,Program the number of ADC clock cycles to wait after applying the step configuration registers and before sending the start of ADC conversion" rgroup.long 0x0E4++0x03 line.long 0x00 "FIFO0COUNT,FIFO word count" hexmask.long.byte 0x00 0.--6. 1. " Words_in_FIFO0 ,Number of words currently in the FIFO" group.long 0x0E8++0x03 line.long 0x00 "FIFO0THRESHOLD,FIFO Threshold level trigger" hexmask.long.byte 0x00 0.--5. 1. " FIFO0_threshold_Level ,Program the desired FIFO data sample level to reach before generating interrupt to CPU" group.long 0x0EC++0x03 line.long 0x00 "DMA0REQ,FIFO DMA req (request) trigger" hexmask.long.byte 0x00 0.--5. 1. " DMA_Request_Level ,Number of words in FIFO before generating a DMA request" rgroup.long 0x100++0x03 line.long 0x00 "FIFO0DATA,ADC_ FIFO0 _READ Data " bitfld.long 0x00 16.--19. " ADCCHNLID ,Optional ID tag of channel that captured the data" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ADCDATA ,12 bit sampled ADC converted data value stored in FIFO 0." rgroup.long 0x200++0x03 line.long 0x00 "FIFO1DATA,ADC FIFO1_READ Data" bitfld.long 0x00 16.--19. " ADCCHNLID ,Optional ID tag of channel that captured the data" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " ADCDATA ,12 bit sampled ADC converted data value stored in FIFO 1." tree.end tree "DSS(Display Subsystem)" tree "DSS_DISPC" base ad:0x4832A400 width 17. rgroup.long 0x000++0x03 line.long 0x00 "DISPC_REVISION,This register contains the IP revision code." bitfld.long 0x00 4.--7. " Major_revision ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " Minor_revision ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x010++0x03 line.long 0x00 "DISPC_SYSCONFIG,This register allows the control of various parameters of the interconnect interface" bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management" "Force standby,No standby,Smart standby," bitfld.long 0x00 8.--9. " CLOCK_ACTIVITY ,Clock activity during wakeup mode period" "IN_FUN_OFF,FUN_OFF,IN_OFF,IN_FUN_ON" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force idle,No idle,Smart idle," textline " " bitfld.long 0x00 2. " ENWAKEUP ,Wakeup feature control" "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free,Automatic" rgroup.long 0x014++0x03 line.long 0x00 "DISPC_SYSSTATUS,This register provides status information about the module" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Done" group.long 0x018++0x03 line.long 0x00 "DISPC_IRQSTATUS,This register regroup.longs all the status of module internal events that generate an interrupt" bitfld.long 0x00 16. " WAKEUP ,Wakeup" "No reset,Reset" bitfld.long 0x00 15. " SYNC_LOST_DIGITAL ,SyncLostDigital" "No reset,Reset" bitfld.long 0x00 14. " SYNC_LOST ,SyncLost" "No reset,Reset" textline " " bitfld.long 0x00 13. " VID2_END_WINDOW ,Vid2EndWindow" "No reset,Reset" bitfld.long 0x00 12. " VID2_FIFO_UFLOW ,Vid2FIFOUnderflow" "No reset,Reset" bitfld.long 0x00 11. " VID1_END_WINDOW ,Vid1EndWindow" "No reset,Reset" textline " " bitfld.long 0x00 10. " VID1_FIFO_UFLOW ,Vid1FIFOUnderflow" "No reset,Reset" bitfld.long 0x00 9. " OCP_ERROR ,OCPError" "No reset,Reset" bitfld.long 0x00 8. " PALLETE_GAMMA_LOADING ,PaletteGammaLoading" "No reset,Reset" textline " " bitfld.long 0x00 7. " GFXEND_WINDOW ,GfxEndWindow" "No reset,Reset" bitfld.long 0x00 6. " GFXFIFO_UFLOW ,GfxFIFOUnderflow" "No reset,Reset" bitfld.long 0x00 5. " PGM_LINE_NO ,ProgrammedLineNumber" "No reset,Reset" textline " " bitfld.long 0x00 4. " ACBIAS_CNT_STS ,ACBiasCountStatus" "No reset,Reset" bitfld.long 0x00 3. " EVSYNC_ODD ,EVSYNC_ODD" "No reset,Reset" bitfld.long 0x00 2. " EVSYNC_EVEN ,EVSYNC_EVEN" "No reset,Reset" textline " " bitfld.long 0x00 1. " VSYNC ,VSYNC" "No reset,Reset" bitfld.long 0x00 0. " FRAMEDONE ,FrameDone" "No reset,Reset" group.long 0x01C++0x03 line.long 0x00 "DISPC_IRQENABLE,This register allows the masking/unmasking of module internal interrupt sources, on an event-by-event basis." bitfld.long 0x00 16. " WAKEUP ,Wakeup mask" "Masked,Unmasked" bitfld.long 0x00 15. " SYNC_LOST_DIGITAL ,SyncLostDigital" "Masked,Unmasked" bitfld.long 0x00 14. " SYNC_LOST ,SyncLost" "Masked,Unmasked" textline " " bitfld.long 0x00 13. " VID2_END_WINDOW ,Vid2EndWindow" "Masked,Unmasked" bitfld.long 0x00 12. " VID2_FIFO_UFLOW ,Vid2FIFOUnderflow" "Masked,Unmasked" bitfld.long 0x00 11. " VID1_END_WINDOW ,Vid1EndWindow" "Masked,Unmasked" textline " " bitfld.long 0x00 10. " VID1_FIFO_UFLOW ,Vid1FIFOUnderflow" "Masked,Unmasked" bitfld.long 0x00 9. " OCP_ERROR ,OCPError" "Masked,Unmasked" bitfld.long 0x00 8. " PALLETE_GAMMA_LOADING ,PaletteGammaLoading" "Masked,Unmasked" textline " " bitfld.long 0x00 7. " GFXEND_WINDOW ,GfxEndWindow" "Masked,Unmasked" bitfld.long 0x00 6. " GFXFIFO_UFLOW ,GfxFIFOUnderflow" "Masked,Unmasked" bitfld.long 0x00 5. " PGM_LINE_NO ,ProgrammedLineNumber" "Masked,Unmasked" textline " " bitfld.long 0x00 4. " ACBIAS_CNT_STS ,ACBiasCountStatus" "Masked,Unmasked" bitfld.long 0x00 3. " EVSYNC_ODD ,EVSYNC_ODD" "Masked,Unmasked" bitfld.long 0x00 2. " EVSYNC_EVEN ,EVSYNC_EVEN" "Masked,Unmasked" textline " " bitfld.long 0x00 1. " VSYNC ,VSYNC" "Masked,Unmasked" bitfld.long 0x00 0. " FRAMEDONE ,FrameDone" "Masked,Unmasked" if (((d.l(ad:0x4832A400+0x40))&0x100000)==0x100000) group.long 0x040++0x03 line.long 0x00 "DISPC_CONTROL,The control register configures the display controller module" bitfld.long 0x00 30.--31. " SPATIAL_TEMPORAL_DITHER ,Spatial/Temporal dithering number of frames" "Spatial only,Sp. and tem. over 2 frames,Sp. and tem. over 4 frames," bitfld.long 0x00 29. " LCD_EN_POL ,LCD Enable Signal Polarity" "Active low,Active high" bitfld.long 0x00 28. " LCD_EN_SIGNAL ,LCD Enable Signal: LCD interface active/inactive" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " PCK_FREE_EN ,Pixel clock free-running enabled/disabled" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TDM_UNUSED_BITS ,State of unused bits (TDM mode only)" "Low level,High level,Unchanged," bitfld.long 0x00 23.--24. " TDM_CYCLE_FMT ,Cycle format (TDM mode only)" "1 cycle for 1 pixel,2 cycles for 1 pixel,3 cycles for 1 pixel,3 cycles for 2 pixels" textline " " bitfld.long 0x00 21.--22. " TDM_PARALLEL_MODE ,Output Interface width (TDM mode only)" "8-bit,9-bit,12-bit,16-bit" bitfld.long 0x00 20. " TDM_EN ,Enable the multiple cycle format" "Disabled,Enabled" bitfld.long 0x00 17.--19. " HT ,Hold Time for digital output" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16. " GPOUT1 ,General Purpose Output Signal" "Reset,Set" bitfld.long 0x00 15. " GPOUT0 ,General Purpose Output Signal" "Reset,Set" rbitfld.long 0x00 14. " GPIN1 ,General Purpose Input Signal" "Reset,Set" textline " " rbitfld.long 0x00 13. " GPIN0 ,General Purpose Input Signal" "Reset,Set" bitfld.long 0x00 12. " OVLY_OPT ,Overlay Optimization" "Fetched,Not fetched" bitfld.long 0x00 11. " STALL_MODE ,Stall mode for the LCD output" "Normal mode,Stall mode" textline " " bitfld.long 0x00 8.--9. " TFT_DATA_LINES ,Number of lines of the LCD interface" "12-bit,16-bit,18-bit,24-bit" bitfld.long 0x00 7. " ST_DITHER_EN ,Spatial temporal dithering enable" "Disabled,Enabled" bitfld.long 0x00 6. " GO_DIGITAL ,Digital GO Command" "Finished updating,Finished programming" textline " " bitfld.long 0x00 5. " GO_LCD ,LCD GO Command" "Finished updating,Finished programming" bitfld.long 0x00 4. " M8B ,Mono 8-bit mode" "4 pixel,8 pixel" bitfld.long 0x00 3. " STNTFT ,LCD display type" "Passive,Active" textline " " bitfld.long 0x00 2. " MONO_COLOR ,Monochrome/Color" "Color,Monochrome" bitfld.long 0x00 1. " DIGITAL_EN ,Digital enable" "Disabled,Enabled" bitfld.long 0x00 0. " LCDENABLE ,LCD enable" "Disabled,Enabled" else group.long 0x040++0x03 line.long 0x00 "DISPC_CONTROL,The control register configures the display controller module" bitfld.long 0x00 30.--31. " SPATIAL_TEMPORAL_DITHER ,Spatial/Temporal dithering number of frames" "Spatial only,Sp. and tem. over 2 frames,Sp. and tem. over 4 frames," bitfld.long 0x00 29. " LCD_EN_POL ,LCD Enable Signal Polarity" "Active low,Active high" bitfld.long 0x00 28. " LCD_EN_SIGNAL ,LCD Enable Signal: LCD interface active/inactive" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " PCK_FREE_EN ,Pixel clock free-running enabled/disabled" "Disabled,Enabled" bitfld.long 0x00 20. " TDM_EN ,Enable the multiple cycle format" "Disabled,Enabled" bitfld.long 0x00 17.--19. " HT ,Hold Time for digital output" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16. " GPOUT1 ,General Purpose Output Signal" "Reset,Set" bitfld.long 0x00 15. " GPOUT0 ,General Purpose Output Signal" "Reset,Set" rbitfld.long 0x00 14. " GPIN1 ,General Purpose Input Signal" "Reset,Set" textline " " rbitfld.long 0x00 13. " GPIN0 ,General Purpose Input Signal" "Reset,Set" bitfld.long 0x00 12. " OVLY_OPT ,Overlay Optimization" "Fetched,Not fetched" bitfld.long 0x00 11. " STALL_MODE ,Stall mode for the LCD output" "Normal mode,Stall mode" textline " " bitfld.long 0x00 8.--9. " TFT_DATA_LINES ,Number of lines of the LCD interface" "12-bit,16-bit,18-bit,24-bit" bitfld.long 0x00 7. " ST_DITHER_EN ,Spatial temporal dithering enable" "Disabled,Enabled" bitfld.long 0x00 6. " GO_DIGITAL ,Digital GO Command" "Finished updating,Finished programming" textline " " bitfld.long 0x00 5. " GO_LCD ,LCD GO Command" "Finished updating,Finished programming" bitfld.long 0x00 4. " M8B ,Mono 8-bit mode" "4 pixel,8 pixel" bitfld.long 0x00 3. " STNTFT ,LCD display type" "Passive,Active" textline " " bitfld.long 0x00 2. " MONO_COLOR ,Monochrome/Color" "Color,Monochrome" bitfld.long 0x00 1. " DIGITAL_EN ,Digital enable" "Disabled,Enabled" bitfld.long 0x00 0. " LCDENABLE ,LCD enable" "Disabled,Enabled" endif group.long 0x044++0x03 line.long 0x00 "DISPC_CONFIG,This control register configures the display controller module" bitfld.long 0x00 19. " TV_ALPHA_BLDR_EN ,Selects the alpha blender (TV output)" "Disabled,Enabled" bitfld.long 0x00 18. " LCD_APLHABLDR_EN ,Selects the alpha blender (LCD output)" "Disabled,Enabled" bitfld.long 0x00 17. " FIFO_FILLING ,Controls if the FIFO are refilled" "Each FIFO,One FIFO" textline " " bitfld.long 0x00 16. " FIFO_HAND_CHECK ,Controls the handshake between FIFO and RFBI STALL to prevent from underflow" "Stall only,Stall and FIFO" bitfld.long 0x00 15. " CPR ,Color phase rotation control wr: VFP" "Disabled,Enabled" bitfld.long 0x00 14. " FIFO_MERGE ,FIFO merge control" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " TCK_DIG_SELECTION ,Transparency color key selection (digital output)" "Graphics destination,Video source" bitfld.long 0x00 12. " TCK_DIG_EN ,Transparency color key enabled (digital output)" "Disabled,Enabled" bitfld.long 0x00 11. " TCK_LCD_SELECTION ,Transparency color key selection (LCD output)" "Graphics destination,Video source" textline " " bitfld.long 0x00 10. " TCK_LCD_EN ,Transparency color key enabled (LCD output)" "Disabled,Enabled" bitfld.long 0x00 9. " FUNC_GATED ,Functional clocks gated enabled" "Disabled,Enabled" bitfld.long 0x00 8. " ACBIAS_GATED ,ACBias Gated Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " VSYNC_GATED ,VSYNC Gated Enabled" "Disabled,Enabled" bitfld.long 0x00 6. " HSYNC_GATED ,HSYNC Gated Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " PIXEL_CLK_GATED ,Pixel Clock Gated Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PIXEL_DATA_GATED ,Pixel Data Gated Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " PALETTEGAMMA_TBL ,Palette/Gamma Table selection" "Palette,Table" bitfld.long 0x00 1.--2. " LOAD_MODE ,Loading Mode for the Palette/Gamma Table" "Every frame,Table loaded,Data frame,First frame" textline " " bitfld.long 0x00 0. " PIXEL_GATED ,Pixel Gated Enable (only for Active Matrix Display)" "Always toggles,When valid data" width 21. group.long 0x04C++0x03 line.long 0x00 "DISPC_DEFAULT_COLOR,The control register allows to configure the default solid background color for the LCD and for 24-bit digital output" hexmask.long.tbyte 0x00 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display" rgroup.long 0x05C++0x03 line.long 0x00 "DISPC_LINE_STATUS,The control register indicates the current LCD panel display line number" hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,Current LCD panel line number" group.long 0x060++0x03 line.long 0x00 "DISPC_LINE_NUMBER,The control register indicates the LCD panel display line number for the interrupt and the DMA request" hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,LCD panel line number programming" group.long 0x064++0x03 line.long 0x00 "DISPC_TIMING_H,The register configures the timing logic for the HSYNC signal" hexmask.long.word 0x00 20.--31. 1. " HBP ,Horizontal Back Porch" hexmask.long.word 0x00 8.--19. 1. " HFP ,Horizontal front porch" hexmask.long.byte 0x00 0.--7. 1. " HSW ,Horizontal synchronization pulse width" group.long 0x068++0x03 line.long 0x00 "DISPC_TIMING_V,The register configures the timing logic for the VSYNC signal" hexmask.long.word 0x00 20.--31. 1. " VBP ,Vertical back porch" hexmask.long.word 0x00 8.--19. 1. " VFP ,Vertical front porch" hexmask.long.byte 0x00 0.--7. 1. " VSW ,Vertical synchronization pulse width" group.long 0x06C++0x03 line.long 0x00 "DISPC_POL_FREQ,The register configures the signal configuration" bitfld.long 0x00 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/Off" "Opposite edges,Bit 16" bitfld.long 0x00 16. " RF ,Program HSYNC/VSYNC Rise or Fall" "Falling edge,Rising edge" bitfld.long 0x00 15. " IEO ,Invert output enable" "Active high,Active low" textline " " bitfld.long 0x00 14. " IPC ,Invert pixel clock" "Rising-edge,Falling-edge" bitfld.long 0x00 13. " IHS ,Invert HSYNC" "Active high,Active low" bitfld.long 0x00 12. " IVS ,Invert VSYNC" "Active high,Active low" textline " " bitfld.long 0x00 8.--11. " ACBI ,AC-bias pin transitions per interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " ACB ,AC-bias pin frequency" group.long 0x070++0x03 line.long 0x00 "DISPC_DIVISOR,The register configures the divisors" hexmask.long.byte 0x00 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor" hexmask.long.byte 0x00 0.--7. 1. " PCD ,Pixel Clock Divisor" group.long 0x074++0x03 line.long 0x00 "DISPC_GLOBAL_ALPHA,The register defines the global alpha value for the graphics and video 2 pipelines" hexmask.long.byte 0x00 16.--23. 1. " VID2GLOBALALPHA ,Global alpha value" hexmask.long.byte 0x00 0.--7. 1. " GFXGLOBALALPHA ,Global alpha value" group.long 0x078++0x03 line.long 0x00 "DISPC_SIZE_DIG,The register configures the size of the digital output field (interlace), frame (progressive) (horizontal and vertical)" hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel" hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line" group.long 0x07C++0x03 line.long 0x00 "DISPC_SIZE_LCD,The register configures the panel size (horizontal and vertical)" hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel" hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line" group.long 0x054++0x03 line.long 0x00 "DISPC_TRANS_COLOR,The register sets the transparency color value for the video/graphics overlays for the LCD output" hexmask.long.tbyte 0x00 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format" group.long 0x080++0x03 line.long 0x00 "DISPC_GFX_BA,The register configures the base address of the graphics buffer displayed in the graphics window" width 29. group.long 0x088++0x03 line.long 0x00 "DISPC_GFX_POSITION,The register configures the position of the graphics window" hexmask.long.word 0x00 16.--26. 1. " GFXPOSY ,Y position of the graphics window" hexmask.long.word 0x00 0.--10. 1. " GFXPOSX ,X position of the graphics window" group.long 0x08C++0x03 line.long 0x00 "DISPC_GFX_SIZE,The register configures the size of the graphics window" hexmask.long.word 0x00 16.--26. 1. " GFXSIZEY ,Number of lines of the graphics window" hexmask.long.word 0x00 0.--10. 1. " GFXSIZEX ,Number of pixels of the graphics window" group.long 0x0A0++0x03 line.long 0x00 "DISPC_GFX_ATTRIBUTES,The register configures the graphics attributes" bitfld.long 0x00 28. " PRE_MULTIPLY_ALPHA ,he field configures the DISPC GFX to process incoming data as pre-multiplied alpha or non premultiplied alpha" "Disabled,Enabled" bitfld.long 0x00 15. " GFX_SELF_REFRESH ,Enables the self refresh of the graphics window from its own FIFO only" "INTERCON,FIFO" bitfld.long 0x00 14. " GFX_ARBITRATION ,Determines the priority of the graphics pipeline" "Normal priority,High priority" textline " " bitfld.long 0x00 12.--13. " GFX_ROTATION ,Graphics rotation flag" "No rotation,90 degrees,180 degrees,270 degrees" bitfld.long 0x00 11. " GFX_FIFO_PRELOAD ,Graphics preload value" "Preload value,Threshold value" bitfld.long 0x00 10. " GFX_ENDIAN ,Graphics endianness" "Little,Big" textline " " bitfld.long 0x00 9. " GFX_NIBBLE_MODE ,Graphics Nibble Mode (only for 1, 2 and 4 BPP)" "Disabled,Enabled" bitfld.long 0x00 8. " GFX_CHANNEL_OUT ,Graphics Channel Out configuration" "LCD,24-bit" bitfld.long 0x00 6.--7. " GFX_BURST_SIZE ,Graphics DMA Burst Size" "4x32bit bursts,8x32bit bursts,16x32bit bursts," textline " " bitfld.long 0x00 5. " GFX_REPLICATION_EN ,Gfx Replication Enable" "Disabled,Enabled" bitfld.long 0x00 1.--4. " GFX_FMT ,Graphics format" "BITMAP 1,BITMAP 2,BITMAP 4,BITMAP 8,RGB 12,ARGB16,RGB 16,,RGB24_UNPACKED,RGB24_PACKED,,,ARGB32,RGBA32,RGBx 32," bitfld.long 0x00 0. " GFX_EN ,GfxEnable" "Disabled,Enabled" group.long 0x0A4++0x03 line.long 0x00 "DISPC_GFX_FIFO_THRESHOLD,The register configures the graphics FIFO" hexmask.long.word 0x00 16.--26. 1. " GFX_FIFO_HIGH_THR ,Graphics FIFO High Threshold" hexmask.long.word 0x00 0.--10. 1. " GFX_FIFO_LOW_THR ,Graphics FIFO Low Threshold" rgroup.long 0x0A8++0x03 line.long 0x00 "DISPC_GFX_FIFO_SIZE_STATUS,This register defines the graphics FIFO size." hexmask.long.word 0x00 0.--10. 1. " GFXFIFOSIZE ,Graphics FIFO Size" group.long 0x0AC++0x03 line.long 0x00 "DISPC_GFX_ROW_INC,The register configures the number of bytes to increment at the end of the row" group.long 0x0B0++0x03 line.long 0x00 "DISPC_GFX_PIXEL_INC,The register configures the number of bytes to increment between two pixels" hexmask.long.word 0x00 0.--15. 1. " GFXPIXELINC ,Number of bytes to increment between two pixels" group.long 0x0B4++0x03 line.long 0x00 "DISPC_GFX_WINDOW_SKIP,The register configures the number of bytes to skip during video window display" group.long 0x0B8++0x03 line.long 0x00 "DISPC_GFX_TABLE_BA,The register configures the base address of the palette buffer or the gamma table buffer" group.long 0x0BC++0x03 line.long 0x00 "DISPC_VID1_BA_0,The register configures the base address of the video buffer for video window" group.long 0x0C0++0x03 line.long 0x00 "DISPC_VID1_BA_1,The register configures the base address of the video buffer for video window" group.long 0x0C4++0x03 line.long 0x00 "DISPC_VID1_POSITION,The register configures the position of video window" hexmask.long.word 0x00 16.--26. 1. " VIDPOSY ,Y position of video window" hexmask.long.word 0x00 0.--10. 1. " VIDPOSX ,X position of video window" group.long 0x0C8++0x03 line.long 0x00 "DISPC_VID1_SIZE,The register configures the size of video window" hexmask.long.word 0x00 16.--26. 1. " VIDSIZEY ,Number of lines of video" hexmask.long.word 0x00 0.--10. 1. " VIDSIZEX ,Number of pixels of video window" group.long 0x0CC++0x03 line.long 0x00 "DISPC_VID1_ATTRIBUTES,DISPC_VID1_ATTRIBUTES" bitfld.long 0x00 28. " PRE_MULTIPLY_ALPHA ,he field configures the DISPC VID2 to process incoming data as pre-multiplied alpha or non pre-multiplied alpha" "Disabled,Enabled" bitfld.long 0x00 24. " SELF_REFRESH ,Enables the self refresh of the video window from its own FIFO only" "INTERCON,FIFO" bitfld.long 0x00 23. " VIDARBITRATION ,Determines the priority of the video pipeline" "Normal,High" textline " " bitfld.long 0x00 22. " LINE_BUFFER_SPLIT ,Video vertical line buffer split" "Not split,Two" bitfld.long 0x00 21. " VERTICAL_TAPS ,Video vertical resize tap number" "3,5" bitfld.long 0x00 20. " VIDOPTIMIZATION ,Video optimization in case of" "One pixel,Two pixels" textline " " bitfld.long 0x00 19. " FIFO_PRELOAD ,Video preload value" "Preload value,Threshold value" bitfld.long 0x00 18. " ROW_REPEAT_EN ,Video Row Repeat" "Disabled,Enabled" bitfld.long 0x00 17. " VIDENDIANNESS ,Video Endianness" "Little endian,Big endian" textline " " bitfld.long 0x00 16. " VIDCHANNELOUT ,Video Channel Out configuration" "LCD,24 bit" bitfld.long 0x00 14. " VIDBURSTSIZE ,Video DMA Burst Size" "4x32bit,8x32bit" bitfld.long 0x00 12.--13. " VIDROTATION ,Video Rotation Flag" "No rotation,90 degrees,180 degrees,270 degrees" textline " " bitfld.long 0x00 11. " FULL_RANGE ,VidFullRange" "Limited,Full" bitfld.long 0x00 10. " REPLICATION_EN ,VidReplicationEnable" "Disabled,Enabled" bitfld.long 0x00 9. " COLOR_CONV_EN ,VidColorConvEnable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " VRESIZE_CONF ,Video Vertical Resize Configuration" "Up-sampling,Down-sampling" bitfld.long 0x00 7. " HRESIZE_CONF ,Video Horizontal Resize Configuration" "Up-sampling,Down-sampling" bitfld.long 0x00 5.--6. " RESIZE_EN ,Video Resize Enable" "Disabled,Enable horizontal,Enable vertical,Enable both" textline " " bitfld.long 0x00 1.--4. " FMT ,VIDFORMAT" ",,,,RGB 12,ARGB 16,RGB 16,,RGB24_UNPACKED,RGB24_PACKED,YUV2_422,YUVY_422,ARGB 32,RGBA 32,RGBx 32," bitfld.long 0x00 0. " EN ,VidEnable" "Disabled,Enabled" group.long 0x0D0++0x03 line.long 0x00 "DISPC_VID1_FIFO_THRESHOLD,The register configures the video FIFO associated with video pipeline" hexmask.long.word 0x00 16.--26. 1. " VIDFIFOHIGHTHRESHOLD ,Video FIFO high threshold" hexmask.long.word 0x00 0.--10. 1. " VIDFIFOLOWTHRESHOLD ,Video FIFO low threshold" group.long 0x0D4++0x03 line.long 0x00 "DISPC_VID1_FIFO_SIZE_STATUS,The register defines the video FIFO size for video pipeline" hexmask.long.word 0x00 0.--10. 1. " VIDFIFOSIZE ,Video FIFO Size" group.long 0x0D8++0x03 line.long 0x00 "DISPC_VID1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with video" group.long 0x0DC++0x03 line.long 0x00 "DISPC_VID1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with video" hexmask.long.word 0x00 0.--15. 1. " VIDPIXELINC ,Number of bytes to increment at the end of the row" group.long 0x0E0++0x03 line.long 0x00 "DISPC_VID1_FIR,The register configures the resize factors for horizontal and vertical up-/down-sampling of video window" hexmask.long.word 0x00 16.--28. 1. " VIDFIRVINC ,Vertical increment of the up-/down-sampling filter" hexmask.long.word 0x00 0.--12. 1. " VIDFIRHINC ,Horizontal increment of the up-/down-sampling filter" group.long 0x0E4++0x03 line.long 0x00 "DISPC_VID1_PICTURE_SIZE,The register configures the size of the video picture associated with video layer" hexmask.long.word 0x00 16.--26. 1. " VIDORGSIZEY ,Number of lines of the video picture" hexmask.long.word 0x00 0.--10. 1. " VIDORGSIZEX ,Number of pixels of the video picture" group.long 0x0E8++0x03 line.long 0x00 "DISPC_VID1_ACCU,The register configures the resize accumulator init values for horizontal and vertical up-/down-sampling of video" hexmask.long.word 0x00 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value" hexmask.long.word 0x00 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value" group.long 0x0EC++0x03 line.long 0x00 "DISPC_VID2_ACCU,The register configures the resize accumulator init values for horizontal and vertical up-/down-sampling of video" hexmask.long.word 0x00 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value" hexmask.long.word 0x00 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value" width 26. tree "DISPC_VID1_FIR_COEF - array[8]" group.long 0xF0++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_0,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 0" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0" group.long (0xF0+0x04)++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_0,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 0" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 0" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 0" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0" group.long 0xF8++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_1,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 1" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1" group.long (0xF8+0x04)++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_1,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 1" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 1" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 1" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1" group.long 0x100++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_2,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 2" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 2" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 2" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 2" group.long (0x100+0x04)++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_2,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 2" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 2" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 2" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 2" group.long 0x108++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_3,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 3" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 3" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 3" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 3" group.long (0x108+0x04)++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_3,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 3" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 3" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 3" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 3" group.long 0x110++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_4,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 4" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 4" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 4" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 4" group.long (0x110+0x04)++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_4,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 4" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 4" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 4" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 4" group.long 0x118++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_5,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 5" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 5" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 5" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 5" group.long (0x118+0x04)++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_5,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 5" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 5" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 5" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 5" group.long 0x120++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_6,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 6" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 6" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 6" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 6" group.long (0x120+0x04)++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_6,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 6" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 6" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 6" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 6" group.long 0x128++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_H_7,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 7" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 7" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 7" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 7" group.long (0x128+0x04)++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_HV_7,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 7" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 7" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 7" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 7" tree.end textline " " width 20. group.long 0x230++0x03 line.long 0x00 "DISPC_VID1_PRELOAD,This register configures the video FIFO" hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,Video preload value" group.long 0x22C++0x03 line.long 0x00 "DISPC_GFX_PRELOAD,This register configures the graphics FIFO" hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,Graphics preload value" group.long 0x234++0x03 line.long 0x00 "DISPC_VID2_PRELOAD,This register configures the video FIFO." hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,Video preload value" width 26. tree "DISPC_VID2_FIR_COEF - array[8]" group.long 0xF0++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_0,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 0" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0" group.long (0xF0+0x04)++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_0,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 0" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 0" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 0" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0" group.long 0xF8++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_1,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 1" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1" group.long (0xF8+0x04)++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_1,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 1" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 1" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 1" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1" group.long 0x100++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_2,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 2" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 2" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 2" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 2" group.long (0x100+0x04)++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_2,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 2" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 2" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 2" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 2" group.long 0x108++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_3,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 3" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 3" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 3" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 3" group.long (0x108+0x04)++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_3,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 3" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 3" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 3" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 3" group.long 0x110++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_4,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 4" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 4" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 4" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 4" group.long (0x110+0x04)++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_4,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 4" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 4" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 4" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 4" group.long 0x118++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_5,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 5" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 5" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 5" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 5" group.long (0x118+0x04)++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_5,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 5" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 5" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 5" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 5" group.long 0x120++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_6,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 6" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 6" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 6" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 6" group.long (0x120+0x04)++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_6,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 6" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 6" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 6" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 6" group.long 0x128++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_H_7,The bank of registers configure the up-/down-scaling coefficients for the vertical and horizontal resize of the video" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 7" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Unsigned coefficient C2 for the horizontal up-/down-scaling with the phase 7" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 7" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 7" group.long (0x128+0x04)++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_HV_7,The bank of registers configure the down/up-/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with video window" hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the vertical up-/down-scaling with the phase 7" hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Unsigned coefficient C1 for the vertical up-/down-scaling with the phase 7" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the vertical up-/down-scaling with the phase 7" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 7" tree.end width 20. tree "DISPC_DATA_CYCLE - array[3]" group.long 0x1D4++0x03 line.long 0x00 "DISPC_DATA_CYCLE_0,The control register configures the output data format for 1st cycle" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits from the pixel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," group.long 0x1D4++0x03 line.long 0x00 "DISPC_DATA_CYCLE_0,The control register configures the output data format for 2nd cycle" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits from the pixel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," group.long 0x1D4++0x03 line.long 0x00 "DISPC_DATA_CYCLE_0,The control register configures the output data format for 3rd cycle" bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits from the pixel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," tree.end textline " " width 23. group.long 0x220++0x03 line.long 0x00 "DISPC_CPR_COEF_R,This register configures the color phase rotation matrix coefficients for the red component" hexmask.long.word 0x00 22.--31. 1. " RR ,RR coefficient" hexmask.long.word 0x00 11.--20. 1. " RG ,RG coefficient" hexmask.long.word 0x00 0.--9. 1. " RB ,RB coefficient" group.long 0x224++0x03 line.long 0x00 "DISPC_CPR_COEF_G,This register configures the color phase rotation matrix coefficients for the green component" hexmask.long.word 0x00 22.--31. 1. " GR ,GR coefficient" hexmask.long.word 0x00 11.--20. 1. " GG ,GG coefficient" hexmask.long.word 0x00 0.--9. 1. " GB ,GB coefficient" group.long 0x228++0x03 line.long 0x00 "DISPC_CPR_COEF_B,This register configures the color phase rotation matrix coefficients for the blue component" hexmask.long.word 0x00 22.--31. 1. " BR ,BR coefficient" hexmask.long.word 0x00 11.--20. 1. " BG ,BG coefficient" hexmask.long.word 0x00 0.--9. 1. " BB ,BB coefficient" group.long 0x130++0x03 line.long 0x00 "DISPC_VID1_CONV_COEF0,The register configures the color space conversion matrix coefficients for video pipeline 0" hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient" hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient" group.long 0x134++0x03 line.long 0x00 "DISPC_VID1_CONV_COEF1,The register configures the color space conversion matrix coefficients for video pipeline 1" hexmask.long.word 0x00 16.--26. 1. " GY ,GY Coefficient" hexmask.long.word 0x00 0.--10. 1. " RCB ,RCb Coefficient" group.long 0x138++0x03 line.long 0x00 "DISPC_VID1_CONV_COEF2,The register configures the color space conversion matrix coefficients for video pipeline 2" hexmask.long.word 0x00 16.--26. 1. " GCB ,GCb Coefficient" hexmask.long.word 0x00 0.--10. 1. " GCR ,GCr Coefficient" group.long 0x13C++0x03 line.long 0x00 "DISPC_VID1_CONV_COEF3,The register configures the color space conversion matrix coefficients for video pipeline 3" hexmask.long.word 0x00 16.--26. 1. " BCR ,BCr coefficient" hexmask.long.word 0x00 0.--10. 1. " BY ,BY coefficient" group.long 0x140++0x03 line.long 0x00 "DISPC_VID1_CONV_COEF4,The register configures the color space conversion matrix coefficients for video pipeline 4" hexmask.long.word 0x00 0.--10. 1. " BCB ,BCb Coefficient" width 26. tree "DISPC_VID1_FIR_COEF_V - array[8]" group.long 0x1E0++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V[0],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 0" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0" group.long 0x1E4++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V[1],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 1" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1" group.long 0x1E8++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V[2],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 2" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 2" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 2" group.long 0x1EC++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V[3],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 3" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 3" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 3" group.long 0x1F0++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V[4],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 4" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 4" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 4" group.long 0x1F4++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V[5],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 5" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 5" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 5" group.long 0x1F8++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V[6],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 6" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 6" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 6" group.long 0x1FC++0x03 line.long 0x00 "DISPC_VID1_FIR_COEF_V[7],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 7" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 7" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 7" tree.end textline " " width 29. group.long 0x14C++0x03 line.long 0x00 "DISPC_VID2_BA_0,The register configures the base address of the video buffer for video window 0" group.long 0x150++0x03 line.long 0x00 "DISPC_VID2_BA)1,The register configures the base address of the video buffer for video window 1" group.long 0x154++0x03 line.long 0x00 "DISPC_VID2_POSITION,The register configures the position of video window" hexmask.long.word 0x00 16.--26. 1. " VIDPOSY ,Y position of video window" hexmask.long.word 0x00 0.--10. 1. " VIDPOSX ,X position of video window" group.long 0x158++0x03 line.long 0x00 "DISPC_VID2_SIZE,The register configures the size of video window" hexmask.long.word 0x00 16.--26. 1. " VIDSIZEY ,Number of lines of video" hexmask.long.word 0x00 0.--10. 1. " VIDSIZEX ,Number of pixels of video window" group.long 0x15C++0x03 line.long 0x00 "DISPC_VID2_ATTRIBUTES," bitfld.long 0x00 28. " PRE_MULTIPLY_ALPHA ,he field configures the DISPC VID2 to process incoming data as pre-multiplied alpha or non pre-multiplied alpha" "Disabled,Enabled" bitfld.long 0x00 24. " SELF_REFRESH ,Enables the self refresh of the video window from its own FIFO only" "INTERCON,FIFO" bitfld.long 0x00 23. " VIDARBITRATION ,Determines the priority of the video pipeline" "Normal,High" textline " " bitfld.long 0x00 22. " LINE_BUFFER_SPLIT ,Video vertical line buffer split" "Not split,Two" bitfld.long 0x00 21. " VERTICAL_TAPS ,Video vertical resize tap number" "3,5" bitfld.long 0x00 20. " VIDOPTIMIZATION ,Video optimization in case of" "One pixel,Two pixels" textline " " bitfld.long 0x00 19. " FIFO_PRELOAD ,Video preload value" "Preload value,Threshold value" bitfld.long 0x00 18. " ROW_REPEAT_EN ,Video Row Repeat" "Disabled,Enabled" bitfld.long 0x00 17. " VIDENDIANNESS ,Video Endianness" "Little endian,Big endian" textline " " bitfld.long 0x00 16. " VIDCHANNELOUT ,Video Channel Out configuration" "LCD,24 bit" bitfld.long 0x00 14. " VIDBURSTSIZE ,Video DMA Burst Size" "4x32bit,8x32bit" bitfld.long 0x00 12.--13. " VIDROTATION ,Video Rotation Flag" "No rotation,90 degrees,180 degrees,270 degrees" textline " " bitfld.long 0x00 11. " FULL_RANGE ,VidFullRange" "Limited,Full" bitfld.long 0x00 10. " REPLICATION_EN ,VidReplicationEnable" "Disabled,Enabled" bitfld.long 0x00 9. " COLOR_CONV_EN ,VidColorConvEnable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " VRESIZE_CONF ,Video Vertical Resize Configuration" "Up-sampling,Down-sampling" bitfld.long 0x00 7. " HRESIZE_CONF ,Video Horizontal Resize Configuration" "Up-sampling,Down-sampling" bitfld.long 0x00 5.--6. " RESIZE_EN ,Video Resize Enable" "Disabled,Enable horizontal,Enable vertical,Enable both" textline " " bitfld.long 0x00 1.--4. " FMT ,VIDFORMAT" ",,,,RGB 12,ARGB 16,RGB 16,,RGB24_UNPACKED,RGB24_PACKED,YUV2_422,YUVY_422,ARGB 32,RGBA 32,RGBx 32," bitfld.long 0x00 0. " EN ,VidEnable" "Disabled,Enabled" group.long 0x160++0x03 line.long 0x00 "DISPC_VID2_FIFO_THRESHOLD,The register configures the video FIFO" hexmask.long.word 0x00 16.--26. 1. " FIFO_HIGH_THR ,Video FIFO high threshold" hexmask.long.word 0x00 0.--10. 1. " FIFO_LOW_THR ,Video FIFO low threshold" group.long 0x164++0x03 line.long 0x00 "DISPC_VID2_FIFO_SIZE_STATUS,The register defines the video FIFO" hexmask.long.word 0x00 0.--10. 1. " FIFO_SIZE ,Video FIFO Size" group.long 0x168++0x03 line.long 0x00 "DISPC_VID2_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with video window" group.long 0x16C++0x03 line.long 0x00 "DISPC_VID2_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with video window" hexmask.long.word 0x00 0.--15. 1. " VIDPIXELINC ,Number of bytes to increment at the end of the row" group.long 0x170++0x03 line.long 0x00 "DISPC_VID2_FIR,The register configures the resize factors for horizontal and vertical up-/down-sampling of video window" hexmask.long.word 0x00 16.--28. 1. " FIR_V_INC ,Vertical increment of the up-/down-sampling filter" hexmask.long.word 0x00 0.--12. 1. " FIR_H_INC ,Horizontal increment of the up-/down-sampling filter" group.long 0x174++0x03 line.long 0x00 "DISPC_VID2_PICTURE_SIZE,The register configures the size of the video picture associated with video layer" hexmask.long.word 0x00 16.--26. 1. " VID_ORG_SIZE_Y ,Number of lines of the video picture" hexmask.long.word 0x00 0.--10. 1. " VID_ORG_SIZE_X ,Number of pixels of the video picture" group.long 0x178++0x03 line.long 0x00 "DISPC_VID2_ACCU,The register configures the resize accumulator init values for horizontal and vertical up-/down-sampling of video window" hexmask.long.word 0x00 16.--25. 1. " VERTICAL_ACCU ,Vertical initialization accu value" hexmask.long.word 0x00 0.--9. 1. " HORIZONTAL_ACCU ,Horizontal initialization accu value" group.long 0x1C0++0x03 line.long 0x00 "DISPC_VID2_CONV_COEF0,The register configures the color space conversion matrix coefficients for video pipeline 0" hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient" hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient" group.long 0x1C4++0x03 line.long 0x00 "DISPC_VID2_CONV_COEF1,The register configures the color space conversion matrix coefficients for video pipeline 1" hexmask.long.word 0x00 16.--26. 1. " GY ,GY Coefficient" hexmask.long.word 0x00 0.--10. 1. " RCB ,RCb Coefficient" group.long 0x1C8++0x03 line.long 0x00 "DISPC_VID2_CONV_COEF2,The register configures the color space conversion matrix coefficients for video pipeline 2" hexmask.long.word 0x00 16.--26. 1. " GCB ,GCb Coefficient" hexmask.long.word 0x00 0.--10. 1. " GCR ,GCr Coefficient" group.long 0x1CC++0x03 line.long 0x00 "DISPC_VID2_CONV_COEF3,The register configures the color space conversion matrix coefficients for video pipeline 3" hexmask.long.word 0x00 16.--26. 1. " BCR ,BCr coefficient" hexmask.long.word 0x00 0.--10. 1. " BY ,BY coefficient" group.long 0x1D0++0x03 line.long 0x00 "DISPC_VID2_CONV_COEF4,The register configures the color space conversion matrix coefficients for video pipeline 4" hexmask.long.word 0x00 0.--10. 1. " BCB ,BCb Coefficient" width 26. tree "DISPC_VID2_FIR_COEF_V - array[8]" group.long 0x200++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V[0],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 0" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0" group.long 0x204++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V[1],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 1" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1" group.long 0x208++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V[2],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 2" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 2" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 2" group.long 0x20C++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V[3],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 3" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 3" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 3" group.long 0x210++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V[4],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 4" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 4" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 4" group.long 0x214++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V[5],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 5" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 5" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 5" group.long 0x218++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V[6],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 6" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 6" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 6" group.long 0x21C++0x03 line.long 0x00 "DISPC_VID2_FIR_COEF_V[7],This bank of registers configures the down/up/down-scaling coefficients for the vertical resize of the video picture associated with video window 7" hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 7" hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 7" tree.end width 11. tree.end tree "DSS_TOP" base ad:0x4832A000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DSS_REVISIONNUMBER,This register contains the DisplaySubSystem revision number" bitfld.long 0x00 4.--7. " Major_Revision ,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " Minor_revision ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "DSS_SYSCONFIG,DSS_SYSCONFIG" bitfld.long 0x00 1. " SOFTRESET ,Software Reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Enable Power management capability" "FREE_RUNNING,AUTOMATIC" rgroup.long 0x14++0x03 line.long 0x00 "DSS_SYSSTATUS,DSS_SYSSTS" bitfld.long 0x00 0. " RESETDONE ,Internal Reset monitoring" "ONGOING,DONE" rgroup.long 0x18++0x03 line.long 0x00 "DSS_IRQSTATUS,This register indicates the source of the interrupt and the status of the interrupt line." bitfld.long 0x00 0. " DISPC_IRQ ,DISPC interrupt status" "INACTIVE,ACTIVE" group.long 0x40++0x03 line.long 0x00 "DSS_CONTROL," bitfld.long 0x00 14. " RFBI_SWITCH ,Selects the Video port from DISPC between Video port #1 and Video port #2 (mux #10)" "Video Port #1,Video Port #2" bitfld.long 0x00 12. " LCD2_CLK_SWITCH ,DSS_CLK/PLL2_CLK1 clock switch (mux #3)" "DSS_CLK,PLL2_CLK1" bitfld.long 0x00 8.--9. " FCK_CLK_SWITCH ,Selects the clock source for the DISPC functional clock" "DSS_CLK,PLL1_CLK1,PLL2_CLK1,PLL3_CLK1" bitfld.long 0x00 0. " LCD1_CLK_SWITCH ,DSS_CLK/PLL1_CLK1 clock switch (mux #2)" "DSS_CLK,PLL1_CLK1" rgroup.long 0x5C++0x03 line.long 0x00 "DSS_CLK_STATUS," bitfld.long 0x00 21. " RFBI_STATUS ,Video port selection status (mux #11)" "Video Port #1,Video Port #2" bitfld.long 0x00 15.--18. " FCK_CLK_STATUS ,FCK_CLK clock selection status (mux #1)" "Switch is ongoing,DSS_CLK is used,PLL1_CLK1,,PLL2_CLK1,,,,PLL3_CLK1,,,,,,," bitfld.long 0x00 11.--12. " LCD2_CLK_STATUS ,LCD2_CLK clock selection status (mux #3)" "LCD2_CLK,DSS_CLK,PLL2_CLK2," bitfld.long 0x00 0.--1. " LCD1_CLK_STATUS ,LCD1_CLK clock selection status (mux #2)" "LCD1_CLK,DSS_CLK,PLl1_CLK1," width 11. tree.end tree "DSS_RFBI" base ad:0x4832A800 width 18. rgroup.long 0x00++0x03 line.long 0x00 "RFBI_REVISION,This Register contains the IP revision code" hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision" group.long 0x10++0x03 line.long 0x00 "RFBI_SYSCONFIG,This Register allows control of various parameters of the Interconnect Interface" bitfld.long 0x00 2.--3. " SIDLEMODE ,Slave interface power management" "Force_idle,No_ilde,Smart_idle," bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy (interconnectL4 and display controller clock)" "Free_running,Auto_gating" rgroup.long 0x14++0x03 line.long 0x00 "RFBI_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information." bitfld.long 0x00 9. " BUSYRFBIDATA ,Data are pending to be processed from interconnect FIFO" "Not pending,Pending" bitfld.long 0x00 8. " BUSY ,L4 Interface busy status bit" "Not busy,Busy" bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring" "On-going,Completed" group.long 0x40++0x03 line.long 0x00 "RFBI_CONTROL,The control register allows configuration of the RFBI module" bitfld.long 0x00 8. " SMART_DMA_REQ ,Smart DMA request" "Asserted,De-asserted" bitfld.long 0x00 7. " DISABLE_DMA_REQ ,Disable DMA request" "No,Yes" bitfld.long 0x00 5.--6. " HIGHTHRESHOLD ,Defines the interconnect FIFO high threshold used by HW to assert DMA request" "4 words,8 words,16 words," bitfld.long 0x00 4. " ITE ,Internal Trigger" "HW_wait,User" textline " " bitfld.long 0x00 2.--3. " CONFIGSELECT ,Select the CS and configuration" "No CS,CS0,CS1,CS0 and CS1" bitfld.long 0x00 1. " BYPASSMODE ,Bypass Mode" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE ,Enable/Disable flag" "Disabled,Enabled" group.long 0x44++0x03 line.long 0x00 "RFBI_PIXEL_CNT,The control register configures the RFBI pixel count value" group.long 0x48++0x03 line.long 0x00 "RFBI_LINE_NUMBER,The control register configures the number of lines to synchronize the beginning of the transfer" hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,Programmable line number" group.long 0x4C++0x03 line.long 0x00 "RFBI_CMD,The control register configures the RFBI command" hexmask.long.word 0x00 0.--15. 1. " CMD ,Command Value" group.long 0x50++0x03 line.long 0x00 "RFBI_PARAM,The control register configures the RFBI parameter" hexmask.long.word 0x00 0.--15. 1. " PARAM ,Param Value" group.long 0x54++0x03 line.long 0x00 "RFBI_DATA,The control register configures the RFBI data" group.long 0x58++0x03 line.long 0x00 "RFBI_READ,The control register configures the RFBI read" hexmask.long.word 0x00 0.--15. 1. " READ ,Read Value" group.long 0x5C++0x03 line.long 0x00 "RFBI_STATUS,The control register configures the RFBI status" hexmask.long.word 0x00 0.--15. 1. " STATUS ,Status value" group.long 0x60++0x03 line.long 0x00 "RFBI_CONFIG,The control register allows configuration #I of the RFBI module" bitfld.long 0x00 21. " HS_SYNC_POLARITY ,HSYNC polarity" "Active Low,Active High" bitfld.long 0x00 20. " TE_VSYNC_POLARITY ,TE or VSYNC Polarity" "Active Low,Active High" bitfld.long 0x00 19. " CS_POLARITY ,CS Polarity" "Active Low,Active High" textline " " bitfld.long 0x00 18. " WE_POLARITY ,WE Polarity" "Active Low,Active High" bitfld.long 0x00 17. " RE_POLARITY ,RE Polarity" "Active Low,Active High" bitfld.long 0x00 16. " A0_POLARITY ,A0 Polarity" "Active Low,Active High" textline " " bitfld.long 0x00 11.--12. " UNUSED_BITS ,State of unused bits" "Low level,High level,Unchanged," bitfld.long 0x00 9.--10. " CYCLE_FMT ,Cycle format" "1 cycle for 1 pixel,2 cycle for 1 pixel,3 cycle for 1 pixel,3 cycle for 2 pixels" bitfld.long 0x00 7.--8. " L4_FMT ,L4 Write Access format" "1 pixel per L4,2 pixels per L4 [15:0],2 pixels per L4 [31:16]," textline " " bitfld.long 0x00 5.--6. " DATA_TYPE ,Data type from the display controller and L4" "12-bit,16-bit,18-bit,24-bit" bitfld.long 0x00 4. " TIME_GRANULARITY ,Multiplies signal timing latencies by two" "Disabled,Enabled" bitfld.long 0x00 2.--3. " TRIGGER_MODE ,Trigger Mode" "Internal,External,External_HV_SYNC," textline " " bitfld.long 0x00 0.--1. " PARALLEL_MODE ,Parallel Mode" "8-bit,9-bit,12-bit,16-bit" group.long 0x64++0x03 line.long 0x00 "RFBI_ONOFF_TIME,The control register allows configuration of the RFBI timing." hexmask.long.byte 0x00 24.--29. 1. " RE_OFFTIME ,Read Enable assertion time from start access time" bitfld.long 0x00 20.--23. " RE_ONTIME ,Read Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 14.--19. 1. " WE_OFFTIME ,CS deassertion time from start access time" textline " " bitfld.long 0x00 10.--13. " WE_ONTIME ,CS deassertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 4.--9. 1. " CS_OFFTIME ,CS deassertion time from start access time" bitfld.long 0x00 0.--3. " CS_ONTIME ,CS assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x68++0x03 line.long 0x00 "RFBI_CYCLE_TIME,The control register allows configuration of the RFBI timing." hexmask.long.byte 0x00 22.--27. 1. " ACCESS_TIME ,Access Time" bitfld.long 0x00 21. " WR_EN ,Write to Read Pulse Width Enable" "Disabled,Enabled" bitfld.long 0x00 20. " WW_EN ,Read to Read Pulse Width Enable" "Disabled,Enabled" bitfld.long 0x00 19. " RR_EN ,Read to Read Pulse Width Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RW_EN ,Read to Write Pulse Width Enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " CS_PULSE_WIDTH ,CS Pulse Width" hexmask.long.byte 0x00 6.--11. 1. " RECYCLE_TIME ,RE Cycle Time" hexmask.long.byte 0x00 0.--5. 1. " WE_CYCLE_TIME ,WE Cycle Time" group.long 0x6C++0x03 line.long 0x00 "RFBI_DATA_CYCLE1,The control register configures the RFBI data format for 1st cycle." bitfld.long 0x00 24.--27. " BIT_ALIGNMENT_PIXEL2 ,Alignment of the bits from pixel #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NB_BITS_PIXEL2 ,Number of bits from the pixel #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 8.--11. " BIT_ALIGNMENT_PIXEL1 ,Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel #1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," group.long 0x70++0x03 line.long 0x00 "RFBI_DATA_CYCLE2,The control register configures the RFBI data format for 2nd cycle." bitfld.long 0x00 24.--27. " BIT_ALIGNMENT_PIXEL2 ,Alignment of the bits from pixel #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NB_BITS_PIXEL2 ,Number of bits from the pixel #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 8.--11. " BIT_ALIGNMENT_PIXEL1 ,Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel #1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," group.long 0x74++0x03 line.long 0x00 "RFBI_DATA_CYCLE3,The control register configures the RFBI data format for 3rd cycle." bitfld.long 0x00 24.--27. " BIT_ALIGNMENT_PIXEL2 ,Alignment of the bits from pixel #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " NB_BITS_PIXEL2 ,Number of bits from the pixel #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," bitfld.long 0x00 8.--11. " BIT_ALIGNMENT_PIXEL1 ,Alignment of the bits from pixel#1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits from the pixel #1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,," group.long 0x90++0x03 line.long 0x00 "RFBI_VSYNC_WIDTH,The control register configures the RFBI VSYNC minimum pulse width" hexmask.long.word 0x00 0.--15. 1. " MINVSYNCPULSEWIDTH ,Programmable min VSYNC pulse width" group.long 0x94++0x03 line.long 0x00 "RFBI_HSYNC_WIDTH,The control register configures the RFBI HSYNC minimum pulse width." hexmask.long.word 0x00 0.--15. 1. " MINHSYNCPULSEWIDTH ,Programmable min HSYNC pulse width" width 11. tree.end tree.end tree "VPFE(Camera)" tree "VPFE 0" base ad:0x48326000 width 15. rgroup.long 0x000++0x03 line.long 0x00 "VPFE_REVISION,IP Revision Identifier" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current." "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function value" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision (Y)" group.long 0x004++0x03 line.long 0x00 "VPFE_PCR,Peripheral Control Register" bitfld.long 0x00 1. " BUSY ,VPFE busy bit" "Not busy,Busy" bitfld.long 0x00 0. " ENABLE ,Enable" "Disabled,Enabled" if (((d.l(ad:0x48326000+0x008))&0x3000)==0x00) //this.INPMOD== 1 group.long 0x008++0x03 line.long 0x00 "VPFE_SYNMODE,SYNC and Mode Set Register" bitfld.long 0x00 17. " WEN ,Data write enable" "Disabled,Enabled" bitfld.long 0x00 16. " VDHDEN ,VD/HD enable" "Disabled,Enabled" bitfld.long 0x00 15. " FLDSTAT ,Field status" "Odd,Even" bitfld.long 0x00 14. " LPF ,3-tap low-pass (anti-aliasing) filter" "Off,On" textline " " bitfld.long 0x00 12.--13. " INPMOD ,Setting data input mode" "CCD_RAW,YCBCR16,YCBCR8," bitfld.long 0x00 11. " PACK8 ,Pack to 8-bit/pixel" "16 bits/pixel,8 bits/pixel" bitfld.long 0x00 8.--10. " DATSIZ ,CCD data width" "16bits,15bits,14bits,13bits,12bits,11bits,10bits,8bits" bitfld.long 0x00 7. " FLDMODE ,Sensor field mode" "Non-interlaced,Interlaced" textline " " bitfld.long 0x00 6. " DATAPOL ,Input data polarity" "Normal,One's complement" bitfld.long 0x00 5. " EXWEN ,External WEN selection" "Not use,Use" bitfld.long 0x00 4. " FLDPOL ,Field indicator polarity" "Positive,Negative" bitfld.long 0x00 3. " HDPOL ,HD sync polarity" "Positive,Negative" textline " " bitfld.long 0x00 2. " VDPOL ,VD sync polarity" "Positive,Negative" bitfld.long 0x00 1. " FLDOUT ,Field ID Direction" "INPUT,OUTPUT" bitfld.long 0x00 0. " VDHDOUT ,VD/HD Sync Direction" "INPUT,OUTPUT" else group.long 0x008++0x03 line.long 0x00 "VPFE_SYNMODE,SYNC and Mode Set Register" bitfld.long 0x00 17. " WEN ,Data write enable" "Disabled,Enabled" bitfld.long 0x00 16. " VDHDEN ,VD/HD enable" "Disabled,Enabled" bitfld.long 0x00 15. " FLDSTAT ,Field status" "Odd,Even" bitfld.long 0x00 14. " LPF ,3-tap low-pass (anti-aliasing) filter" "Off,On" textline " " bitfld.long 0x00 12.--13. " INPMOD ,Setting data input mode" "CCD_RAW,YCBCR16,YCBCR8," bitfld.long 0x00 11. " PACK8 ,Pack to 8-bit/pixel" "16 bits/pixel,8 bits/pixel" bitfld.long 0x00 7. " FLDMODE ,Sensor field mode" "Non-interlaced,Interlaced" textline " " bitfld.long 0x00 6. " DATAPOL ,Input data polarity" "Normal,One's complement" bitfld.long 0x00 5. " EXWEN ,External WEN selection" "Not use,Use" bitfld.long 0x00 4. " FLDPOL ,Field indicator polarity" "Positive,Negative" bitfld.long 0x00 3. " HDPOL ,HD sync polarity" "Positive,Negative" textline " " bitfld.long 0x00 2. " VDPOL ,VD sync polarity" "Positive,Negative" bitfld.long 0x00 1. " FLDOUT ,Field ID Direction" "INPUT,OUTPUT" bitfld.long 0x00 0. " VDHDOUT ,VD/HD Sync Direction" "INPUT,OUTPUT" endif group.long 0x00C++0x03 line.long 0x00 "VPFE_HD_VD_WID,VPFE_HD_VD_WID" hexmask.long.word 0x00 16.--27. 1. " HDW ,Width of HD sync pulse if output" hexmask.long.word 0x00 0.--11. 1. " VDW ,Width of VD sync pulse if output" group.long 0x010++0x03 line.long 0x00 "VPFE_PIX_LINES,Number of pixels in a horizontal line and number of lines in a frame" hexmask.long.word 0x00 16.--31. 1. " PPLN ,Pixels per line" hexmask.long.word 0x00 0.--15. 1. " HLPFR ,Half lines per field or frame" group.long 0x014++0x03 line.long 0x00 "VPFE_HORZ_INFO,Horizontal Pixel Information Register" hexmask.long.word 0x00 16.--30. 1. " SPH ,Start pixel" hexmask.long.word 0x00 0.--14. 1. " NPH ,Number of pixels" group.long 0x018++0x03 line.long 0x00 "VPFE_VERT_START,Vertical Line - Settings for the Starting Pixel Register" hexmask.long.word 0x00 16.--30. 1. " SLV0 ,Start line" hexmask.long.word 0x00 0.--14. 1. " SLV1 ,Start line," group.long 0x01C++0x03 line.long 0x00 "VPFE_VERT_LINES,Number of Vertical Lines Register" hexmask.long.word 0x00 0.--14. 1. " NLV ,Number of lines" group.long 0x020++0x03 line.long 0x00 "VPFE_CULLING,Culling Information in Horizontal and Vertical Directions Register" bitfld.long 0x00 31. " CULHEVN ,Horizontal Culling Pattern for Even Line 7-bit mask" "0,1" bitfld.long 0x00 30. " CULHEVN ,Horizontal Culling Pattern for Even Line 6-bit mask" "0,1" bitfld.long 0x00 29. " CULHEVN ,Horizontal Culling Pattern for Even Line 5-bit mask" "0,1" bitfld.long 0x00 28. " CULHEVN ,Horizontal Culling Pattern for Even Line 4-bit mask" "0,1" textline " " bitfld.long 0x00 27. " CULHEVN ,Horizontal Culling Pattern for Even Line 3-bit mask" "0,1" bitfld.long 0x00 26. " CULHEVN ,Horizontal Culling Pattern for Even Line 2-bit mask" "0,1" bitfld.long 0x00 25. " CULHEVN ,Horizontal Culling Pattern for Even Line 1-bit mask" "0,1" bitfld.long 0x00 24. " CULHEVN ,Horizontal Culling Pattern for Even Line 0-bit mask" "0,1" textline " " bitfld.long 0x00 23. " CULHODD ,Horizontal Culling Pattern for Odd Line 7-bit mask" "0,1" bitfld.long 0x00 22. " CULHODD ,Horizontal Culling Pattern for Odd Line 6-bit mask" "0,1" bitfld.long 0x00 21. " CULHODD ,Horizontal Culling Pattern for Odd Line 5-bit mask" "0,1" bitfld.long 0x00 20. " CULHODD ,Horizontal Culling Pattern for Odd Line 4-bit mask" "0,1" textline " " bitfld.long 0x00 19. " CULHODD ,Horizontal Culling Pattern for Odd Line 3-bit mask" "0,1" bitfld.long 0x00 18. " CULHODD ,Horizontal Culling Pattern for Odd Line 2-bit mask" "0,1" bitfld.long 0x00 17. " CULHODD ,Horizontal Culling Pattern for Odd Line 1-bit mask" "0,1" bitfld.long 0x00 16. " CULHODD ,Horizontal Culling Pattern for Odd Line 0-bit mask" "0,1" textline " " bitfld.long 0x00 7. " CULV ,Vertical Culling Pattern 7-bit mask" "0,1" bitfld.long 0x00 6. " CULV ,Vertical Culling Pattern 6-bit mask" "0,1" bitfld.long 0x00 5. " CULV ,Vertical Culling Pattern 5-bit mask" "0,1" bitfld.long 0x00 4. " CULV ,Vertical Culling Pattern 4-bit mask" "0,1" textline " " bitfld.long 0x00 3. " CULV ,Vertical Culling Pattern 3-bit mask" "0,1" bitfld.long 0x00 2. " CULV ,Vertical Culling Pattern 2-bit mask" "0,1" bitfld.long 0x00 1. " CULV ,Vertical Culling Pattern 1-bit mask" "0,1" bitfld.long 0x00 0. " CULV ,Vertical Culling Pattern 0-bit mask" "0,1" group.long 0x024++0x03 line.long 0x00 "VPFE_HSIZE_OFF,Horizontal Size Register" hexmask.long.word 0x00 0.--15. 1. " LNOFST ,Address offset for each line" group.long 0x028++0x03 line.long 0x00 "VPFE_SDOFST,External Memory Line Offset Register" bitfld.long 0x00 14. " FIINV ,Field identification signal inverse" "Non inverse,Inverse" bitfld.long 0x00 12.--13. " FOFST ,Line offset value" "+1,+2,+3,+4" textline " " bitfld.long 0x00 9.--11. " LOFTS0 ,Line offset value" "+1,+2,+3,+4,-1,-2,-3,-4" bitfld.long 0x00 6.--8. " LOFTS1 ,Line offset value" "+1,+2,+3,+4,-1,-2,-3,-4" bitfld.long 0x00 3.--5. " LOFTS2 ,Line offset value" "+1,+2,+3,+4,-1,-2,-3,-4" bitfld.long 0x00 0.--2. " LOFTS3 ,Line offset value" "+1,+2,+3,+4,-1,-2,-3,-4" group.long 0x02C++0x03 line.long 0x00 "VPFE_SDR_ADDR,External Memory Address Register" group.long 0x030++0x03 line.long 0x00 "VPFE_CLAMP,Optical Black Clamping Setting Register" bitfld.long 0x00 31. " CLAMPEN ,Clamp enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " OBSLEN ,Optical black sample length" "1,2,4,8,16,,," bitfld.long 0x00 25.--27. " OBSLN ,Optical black sample lines" "1,2,4,8,16,,," hexmask.long.word 0x00 10.--24. 1. " OBST ,Start pixel of optical black samples" bitfld.long 0x00 0.--4. " OBGAIN ,Gain to apply to the optical black average" "0 + 0/16,0 + 1/16,0 + 2/16,0 + 3/16,0 + 4/16,0 + 5/16,0 + 6/16,0 + 7/16,0 + 8/16,0 + 9/16,0 + 10/16,0 + 11/16,0 + 12/16,0 + 13/16,0 + 14/16,0 + 15/16,1 + 0/16,1 + 1/16,1 + 2/16,1 + 3/16,1 + 4/16,1 + 5/16,1 + 6/16,1 + 7/16,1 + 8/16,1 + 9/16,1 + 10/16,1 + 11/16,1 + 12/16,1 + 13/16,1 + 14/16,1 + 15/16" group.long 0x034++0x03 line.long 0x00 "VPFE_DCSUB,DC Clamp Register" hexmask.long.word 0x00 0.--13. 1. " DCSUB ,DC level to subtract from CCD data" group.long 0x038++0x03 line.long 0x00 "VPFE_COLPTN,CCD Color Pattern Register" bitfld.long 0x00 30.--31. " CP3LPC3 ,Color Pattern for 3rd Line, Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 28.--29. " CP3LPC2 ,Color Pattern for 3rd Line, Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 26.--27. " CP3LPC1 ,Color Pattern for 3rd Line, Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 24.--25. " CP3LPC0 ,Color Pattern for 3rd Line, Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg" textline " " bitfld.long 0x00 22.--23. " CP2LPC3 ,Color Pattern for 2nd Line, Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 20.--21. " CP2LPC2 ,Color Pattern for 2nd Line, Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 18.--19. " CP2LPC1 ,Color Pattern for 2nd Line, Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 16.--17. " CP2LPC0 ,Color Pattern for 2nd Line, Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg" textline " " bitfld.long 0x00 14.--15. " CP1LPC3 ,Color Pattern for 1st Line, Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 12.--13. " CP1LPC2 ,Color Pattern for 1st Line, Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 10.--11. " CP1LPC1 ,Color Pattern for 1st Line, Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 8.--9. " CP1LPC0 ,Color Pattern for 1st Line, Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg" textline " " bitfld.long 0x00 6.--7. " CP0LPC3 ,Color Pattern for 0th Line, Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 4.--5. " CP0LPC2 ,Color Pattern for 0th Line, Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 2.--3. " CP0LPC1 ,Color Pattern for 0th Line, Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 0.--1. " CP0LPC0 ,Color Pattern for 0th Line, Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg" group.long 0x03C++0x03 line.long 0x00 "VPFE_BLKCMP,Black Compensation Register" hexmask.long.byte 0x00 24.--31. 1. " RYE ,Black level compensation for R/Ye pixels" hexmask.long.byte 0x00 16.--23. 1. " GRCY ,Black level compensation for Gr/Cy pixels" hexmask.long.byte 0x00 8.--15. 1. " GBG ,Black level compensation for Gb/G pixels" hexmask.long.byte 0x00 0.--7. 1. " BMG ,Black level compensation for B/Mg pixels" group.long 0x048++0x03 line.long 0x00 "VPFE_VDINT,VPFE Interrupt Control Register" hexmask.long.word 0x00 16.--30. 1. " VDINT0 ,CCDC_VD0_INT interrupt timing" hexmask.long.word 0x00 0.--14. 1. " VDINT1 ,CCDC_VD1_INT interrupt timing" group.long 0x04C++0x03 line.long 0x00 "VPFE_ALAW,ALAW Configuration Register" bitfld.long 0x00 3. " CCDTBL ,Apply Gamma (A-LAW) to VPFE data saved to external memory" "Disabled,Enabled" bitfld.long 0x00 0.--2. " GWDI ,A-law Width Input" "Bits 15-6,Bits 14-5,Bits 13-4,Bits 12-3,Bits 11-2,Bits 10-1,Bits 9-0," group.long 0x050++0x03 line.long 0x00 "VPFE_REC656IF,REC656IF Configuration Register" bitfld.long 0x00 1. " ECCFVH ,FVH error correction enable" "Disabled,Enabled" bitfld.long 0x00 0. " R656ON ,REC656 interface enable" "Disabled,Enabled" group.long 0x054++0x03 line.long 0x00 "VPFE_CCDCFG,CCD Configuration Register" bitfld.long 0x00 15. " VDLC ,Enable latching function registers on internal VSYNC" "Latched,Not latched" bitfld.long 0x00 14. " MSBINVO ,MSB of Chroma signal output inverted" "Normal,Inverted" bitfld.long 0x00 13. " MSBINVI ,MSB of Chroma input signal stored to SDRAM inverted" "Normal,Inverted" textline " " bitfld.long 0x00 12. " BSWD ,Byte Swap Data stored to SDRAM" "Normal,Swap" bitfld.long 0x00 11. " Y8POS ,Location of Y signal when YCbCr 8bit data is input" "Even pixel,Odd pixel" bitfld.long 0x00 8. " WENLOG ,Specifies CCD valid area" "AND,OR" textline " " bitfld.long 0x00 5. " BW656 ,The data width in CCIR656 input mode" "8bits,10bits" bitfld.long 0x00 4. " YCINSWP ,Y input (YIN[7:0]) and C input (CIN[7:0]) are swapped" "0,1" bitfld.long 0x00 2. " YCOUTSWP ,Y output (YOUT[7:0]) and C output (COUT[7:0]) are swapped" "0,1" group.long 0x098++0x03 line.long 0x00 "VPFE_DMA_CNTL,DMA Status and Control" bitfld.long 0x00 31. " OVERFLOW ,DMA Overflow Flag" "No overflow,Overflow" bitfld.long 0x00 0.--2. " PRIORITY ,Sets the priority that all command should be sent with on the DMA bus" "Highest,1,2,3,4,5,6,Lowest" group.long 0x104++0x03 line.long 0x00 "VPFE_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "FORCE_STANDBY,NO_STANDBY,SMART_STANDBY,SMART_STANDBY_WAKEUP_CAPABLE" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "FORCE_IDLE,NO_IDLE,SMART_IDLE,SMART_IDLE_WAKEUP_CAPABLE" group.long 0x108++0x03 line.long 0x00 "VPFE_CONFIG,Module configuration register" bitfld.long 0x00 2. " VPFE_ST ,VPFE Master OCP interface Status" "OCP_ACTIVE,OCP_STANDBY" bitfld.long 0x00 1. " VPFE_EN ,VPFE Master OCP interface enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCLK_INV ,Pixel clock inversion enable" "NOT_INV,INV" group.long 0x110++0x03 line.long 0x00 "VPFE_IRQ_EOI,Module EOI register" bitfld.long 0x00 0. " EOI ,EOI for VPFE" "Not generated,Generated" textline " " width 21. group.long 0x114++0x03 line.long 0x00 "VPFE_IRQ_STATUS_RAW,Interrupt raw status register" bitfld.long 0x00 2. " VD2_INT_RAW ,CCDC VD2 interrupt status raw value" "No interrupt,Interrupt" bitfld.long 0x00 1. " VD1_INT_RAW ,CCDC VD1 interrupt status raw value" "No interrupt,Interrupt" bitfld.long 0x00 0. " VD0_INT_RAW ,CCDC VD0 interrupt status raw value" "No interrupt,Interrupt" group.long 0x118++0x03 line.long 0x00 "VPFE_IRQ_STATUS,Interrupt status register" bitfld.long 0x00 2. " VD2_INT ,CCDC VD2 interrupt status value" "No interrupt,Interrupt" bitfld.long 0x00 1. " VD1_INT ,CCDC VD1 interrupt status value" "No interrupt,Interrupt" bitfld.long 0x00 0. " VD0_INT ,CCDC VD0 interrupt status value" "No interrupt,Interrupt" group.long 0x11C++0x03 line.long 0x00 "VPFE_IRQ_ENABLE_SET,Interrupt enable set" bitfld.long 0x00 2. " VD2_INT_EN ,CCDC VD2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " VD1_INT_EN ,CCDC VD1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " VD0_INT_EN ,CCDC VD0 interrupt enable" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "VPFE_IRQ_ENABLE_CLR,Interrupt enable clear" bitfld.long 0x00 2. " VD2_INT_DIS ,CCDC VD2 interrupt disable" "No,Yes" bitfld.long 0x00 1. " VD1_INT_DIS ,CCDC VD1 interrupt disable" "No,Yes" bitfld.long 0x00 0. " VD0_INT_DIS ,CCDC VD0 interrupt disable" "No,Yes" width 11. tree.end tree "VPFE 1" base ad:0x48328000 width 15. rgroup.long 0x000++0x03 line.long 0x00 "VPFE_REVISION,IP Revision Identifier" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current." "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function value" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision (Y)" group.long 0x004++0x03 line.long 0x00 "VPFE_PCR,Peripheral Control Register" bitfld.long 0x00 1. " BUSY ,VPFE busy bit" "Not busy,Busy" bitfld.long 0x00 0. " ENABLE ,Enable" "Disabled,Enabled" if (((d.l(ad:0x48328000+0x008))&0x3000)==0x00) //this.INPMOD== 1 group.long 0x008++0x03 line.long 0x00 "VPFE_SYNMODE,SYNC and Mode Set Register" bitfld.long 0x00 17. " WEN ,Data write enable" "Disabled,Enabled" bitfld.long 0x00 16. " VDHDEN ,VD/HD enable" "Disabled,Enabled" bitfld.long 0x00 15. " FLDSTAT ,Field status" "Odd,Even" bitfld.long 0x00 14. " LPF ,3-tap low-pass (anti-aliasing) filter" "Off,On" textline " " bitfld.long 0x00 12.--13. " INPMOD ,Setting data input mode" "CCD_RAW,YCBCR16,YCBCR8," bitfld.long 0x00 11. " PACK8 ,Pack to 8-bit/pixel" "16 bits/pixel,8 bits/pixel" bitfld.long 0x00 8.--10. " DATSIZ ,CCD data width" "16bits,15bits,14bits,13bits,12bits,11bits,10bits,8bits" bitfld.long 0x00 7. " FLDMODE ,Sensor field mode" "Non-interlaced,Interlaced" textline " " bitfld.long 0x00 6. " DATAPOL ,Input data polarity" "Normal,One's complement" bitfld.long 0x00 5. " EXWEN ,External WEN selection" "Not use,Use" bitfld.long 0x00 4. " FLDPOL ,Field indicator polarity" "Positive,Negative" bitfld.long 0x00 3. " HDPOL ,HD sync polarity" "Positive,Negative" textline " " bitfld.long 0x00 2. " VDPOL ,VD sync polarity" "Positive,Negative" bitfld.long 0x00 1. " FLDOUT ,Field ID Direction" "INPUT,OUTPUT" bitfld.long 0x00 0. " VDHDOUT ,VD/HD Sync Direction" "INPUT,OUTPUT" else group.long 0x008++0x03 line.long 0x00 "VPFE_SYNMODE,SYNC and Mode Set Register" bitfld.long 0x00 17. " WEN ,Data write enable" "Disabled,Enabled" bitfld.long 0x00 16. " VDHDEN ,VD/HD enable" "Disabled,Enabled" bitfld.long 0x00 15. " FLDSTAT ,Field status" "Odd,Even" bitfld.long 0x00 14. " LPF ,3-tap low-pass (anti-aliasing) filter" "Off,On" textline " " bitfld.long 0x00 12.--13. " INPMOD ,Setting data input mode" "CCD_RAW,YCBCR16,YCBCR8," bitfld.long 0x00 11. " PACK8 ,Pack to 8-bit/pixel" "16 bits/pixel,8 bits/pixel" bitfld.long 0x00 7. " FLDMODE ,Sensor field mode" "Non-interlaced,Interlaced" textline " " bitfld.long 0x00 6. " DATAPOL ,Input data polarity" "Normal,One's complement" bitfld.long 0x00 5. " EXWEN ,External WEN selection" "Not use,Use" bitfld.long 0x00 4. " FLDPOL ,Field indicator polarity" "Positive,Negative" bitfld.long 0x00 3. " HDPOL ,HD sync polarity" "Positive,Negative" textline " " bitfld.long 0x00 2. " VDPOL ,VD sync polarity" "Positive,Negative" bitfld.long 0x00 1. " FLDOUT ,Field ID Direction" "INPUT,OUTPUT" bitfld.long 0x00 0. " VDHDOUT ,VD/HD Sync Direction" "INPUT,OUTPUT" endif group.long 0x00C++0x03 line.long 0x00 "VPFE_HD_VD_WID,VPFE_HD_VD_WID" hexmask.long.word 0x00 16.--27. 1. " HDW ,Width of HD sync pulse if output" hexmask.long.word 0x00 0.--11. 1. " VDW ,Width of VD sync pulse if output" group.long 0x010++0x03 line.long 0x00 "VPFE_PIX_LINES,Number of pixels in a horizontal line and number of lines in a frame" hexmask.long.word 0x00 16.--31. 1. " PPLN ,Pixels per line" hexmask.long.word 0x00 0.--15. 1. " HLPFR ,Half lines per field or frame" group.long 0x014++0x03 line.long 0x00 "VPFE_HORZ_INFO,Horizontal Pixel Information Register" hexmask.long.word 0x00 16.--30. 1. " SPH ,Start pixel" hexmask.long.word 0x00 0.--14. 1. " NPH ,Number of pixels" group.long 0x018++0x03 line.long 0x00 "VPFE_VERT_START,Vertical Line - Settings for the Starting Pixel Register" hexmask.long.word 0x00 16.--30. 1. " SLV0 ,Start line" hexmask.long.word 0x00 0.--14. 1. " SLV1 ,Start line," group.long 0x01C++0x03 line.long 0x00 "VPFE_VERT_LINES,Number of Vertical Lines Register" hexmask.long.word 0x00 0.--14. 1. " NLV ,Number of lines" group.long 0x020++0x03 line.long 0x00 "VPFE_CULLING,Culling Information in Horizontal and Vertical Directions Register" bitfld.long 0x00 31. " CULHEVN ,Horizontal Culling Pattern for Even Line 7-bit mask" "0,1" bitfld.long 0x00 30. " CULHEVN ,Horizontal Culling Pattern for Even Line 6-bit mask" "0,1" bitfld.long 0x00 29. " CULHEVN ,Horizontal Culling Pattern for Even Line 5-bit mask" "0,1" bitfld.long 0x00 28. " CULHEVN ,Horizontal Culling Pattern for Even Line 4-bit mask" "0,1" textline " " bitfld.long 0x00 27. " CULHEVN ,Horizontal Culling Pattern for Even Line 3-bit mask" "0,1" bitfld.long 0x00 26. " CULHEVN ,Horizontal Culling Pattern for Even Line 2-bit mask" "0,1" bitfld.long 0x00 25. " CULHEVN ,Horizontal Culling Pattern for Even Line 1-bit mask" "0,1" bitfld.long 0x00 24. " CULHEVN ,Horizontal Culling Pattern for Even Line 0-bit mask" "0,1" textline " " bitfld.long 0x00 23. " CULHODD ,Horizontal Culling Pattern for Odd Line 7-bit mask" "0,1" bitfld.long 0x00 22. " CULHODD ,Horizontal Culling Pattern for Odd Line 6-bit mask" "0,1" bitfld.long 0x00 21. " CULHODD ,Horizontal Culling Pattern for Odd Line 5-bit mask" "0,1" bitfld.long 0x00 20. " CULHODD ,Horizontal Culling Pattern for Odd Line 4-bit mask" "0,1" textline " " bitfld.long 0x00 19. " CULHODD ,Horizontal Culling Pattern for Odd Line 3-bit mask" "0,1" bitfld.long 0x00 18. " CULHODD ,Horizontal Culling Pattern for Odd Line 2-bit mask" "0,1" bitfld.long 0x00 17. " CULHODD ,Horizontal Culling Pattern for Odd Line 1-bit mask" "0,1" bitfld.long 0x00 16. " CULHODD ,Horizontal Culling Pattern for Odd Line 0-bit mask" "0,1" textline " " bitfld.long 0x00 7. " CULV ,Vertical Culling Pattern 7-bit mask" "0,1" bitfld.long 0x00 6. " CULV ,Vertical Culling Pattern 6-bit mask" "0,1" bitfld.long 0x00 5. " CULV ,Vertical Culling Pattern 5-bit mask" "0,1" bitfld.long 0x00 4. " CULV ,Vertical Culling Pattern 4-bit mask" "0,1" textline " " bitfld.long 0x00 3. " CULV ,Vertical Culling Pattern 3-bit mask" "0,1" bitfld.long 0x00 2. " CULV ,Vertical Culling Pattern 2-bit mask" "0,1" bitfld.long 0x00 1. " CULV ,Vertical Culling Pattern 1-bit mask" "0,1" bitfld.long 0x00 0. " CULV ,Vertical Culling Pattern 0-bit mask" "0,1" group.long 0x024++0x03 line.long 0x00 "VPFE_HSIZE_OFF,Horizontal Size Register" hexmask.long.word 0x00 0.--15. 1. " LNOFST ,Address offset for each line" group.long 0x028++0x03 line.long 0x00 "VPFE_SDOFST,External Memory Line Offset Register" bitfld.long 0x00 14. " FIINV ,Field identification signal inverse" "Non inverse,Inverse" bitfld.long 0x00 12.--13. " FOFST ,Line offset value" "+1,+2,+3,+4" textline " " bitfld.long 0x00 9.--11. " LOFTS0 ,Line offset value" "+1,+2,+3,+4,-1,-2,-3,-4" bitfld.long 0x00 6.--8. " LOFTS1 ,Line offset value" "+1,+2,+3,+4,-1,-2,-3,-4" bitfld.long 0x00 3.--5. " LOFTS2 ,Line offset value" "+1,+2,+3,+4,-1,-2,-3,-4" bitfld.long 0x00 0.--2. " LOFTS3 ,Line offset value" "+1,+2,+3,+4,-1,-2,-3,-4" group.long 0x02C++0x03 line.long 0x00 "VPFE_SDR_ADDR,External Memory Address Register" group.long 0x030++0x03 line.long 0x00 "VPFE_CLAMP,Optical Black Clamping Setting Register" bitfld.long 0x00 31. " CLAMPEN ,Clamp enable" "Disabled,Enabled" bitfld.long 0x00 28.--30. " OBSLEN ,Optical black sample length" "1,2,4,8,16,,," bitfld.long 0x00 25.--27. " OBSLN ,Optical black sample lines" "1,2,4,8,16,,," hexmask.long.word 0x00 10.--24. 1. " OBST ,Start pixel of optical black samples" bitfld.long 0x00 0.--4. " OBGAIN ,Gain to apply to the optical black average" "0 + 0/16,0 + 1/16,0 + 2/16,0 + 3/16,0 + 4/16,0 + 5/16,0 + 6/16,0 + 7/16,0 + 8/16,0 + 9/16,0 + 10/16,0 + 11/16,0 + 12/16,0 + 13/16,0 + 14/16,0 + 15/16,1 + 0/16,1 + 1/16,1 + 2/16,1 + 3/16,1 + 4/16,1 + 5/16,1 + 6/16,1 + 7/16,1 + 8/16,1 + 9/16,1 + 10/16,1 + 11/16,1 + 12/16,1 + 13/16,1 + 14/16,1 + 15/16" group.long 0x034++0x03 line.long 0x00 "VPFE_DCSUB,DC Clamp Register" hexmask.long.word 0x00 0.--13. 1. " DCSUB ,DC level to subtract from CCD data" group.long 0x038++0x03 line.long 0x00 "VPFE_COLPTN,CCD Color Pattern Register" bitfld.long 0x00 30.--31. " CP3LPC3 ,Color Pattern for 3rd Line, Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 28.--29. " CP3LPC2 ,Color Pattern for 3rd Line, Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 26.--27. " CP3LPC1 ,Color Pattern for 3rd Line, Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 24.--25. " CP3LPC0 ,Color Pattern for 3rd Line, Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg" textline " " bitfld.long 0x00 22.--23. " CP2LPC3 ,Color Pattern for 2nd Line, Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 20.--21. " CP2LPC2 ,Color Pattern for 2nd Line, Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 18.--19. " CP2LPC1 ,Color Pattern for 2nd Line, Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 16.--17. " CP2LPC0 ,Color Pattern for 2nd Line, Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg" textline " " bitfld.long 0x00 14.--15. " CP1LPC3 ,Color Pattern for 1st Line, Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 12.--13. " CP1LPC2 ,Color Pattern for 1st Line, Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 10.--11. " CP1LPC1 ,Color Pattern for 1st Line, Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 8.--9. " CP1LPC0 ,Color Pattern for 1st Line, Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg" textline " " bitfld.long 0x00 6.--7. " CP0LPC3 ,Color Pattern for 0th Line, Pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 4.--5. " CP0LPC2 ,Color Pattern for 0th Line, Pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 2.--3. " CP0LPC1 ,Color Pattern for 0th Line, Pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg" bitfld.long 0x00 0.--1. " CP0LPC0 ,Color Pattern for 0th Line, Pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg" group.long 0x03C++0x03 line.long 0x00 "VPFE_BLKCMP,Black Compensation Register" hexmask.long.byte 0x00 24.--31. 1. " RYE ,Black level compensation for R/Ye pixels" hexmask.long.byte 0x00 16.--23. 1. " GRCY ,Black level compensation for Gr/Cy pixels" hexmask.long.byte 0x00 8.--15. 1. " GBG ,Black level compensation for Gb/G pixels" hexmask.long.byte 0x00 0.--7. 1. " BMG ,Black level compensation for B/Mg pixels" group.long 0x048++0x03 line.long 0x00 "VPFE_VDINT,VPFE Interrupt Control Register" hexmask.long.word 0x00 16.--30. 1. " VDINT0 ,CCDC_VD0_INT interrupt timing" hexmask.long.word 0x00 0.--14. 1. " VDINT1 ,CCDC_VD1_INT interrupt timing" group.long 0x04C++0x03 line.long 0x00 "VPFE_ALAW,ALAW Configuration Register" bitfld.long 0x00 3. " CCDTBL ,Apply Gamma (A-LAW) to VPFE data saved to external memory" "Disabled,Enabled" bitfld.long 0x00 0.--2. " GWDI ,A-law Width Input" "Bits 15-6,Bits 14-5,Bits 13-4,Bits 12-3,Bits 11-2,Bits 10-1,Bits 9-0," group.long 0x050++0x03 line.long 0x00 "VPFE_REC656IF,REC656IF Configuration Register" bitfld.long 0x00 1. " ECCFVH ,FVH error correction enable" "Disabled,Enabled" bitfld.long 0x00 0. " R656ON ,REC656 interface enable" "Disabled,Enabled" group.long 0x054++0x03 line.long 0x00 "VPFE_CCDCFG,CCD Configuration Register" bitfld.long 0x00 15. " VDLC ,Enable latching function registers on internal VSYNC" "Latched,Not latched" bitfld.long 0x00 14. " MSBINVO ,MSB of Chroma signal output inverted" "Normal,Inverted" bitfld.long 0x00 13. " MSBINVI ,MSB of Chroma input signal stored to SDRAM inverted" "Normal,Inverted" textline " " bitfld.long 0x00 12. " BSWD ,Byte Swap Data stored to SDRAM" "Normal,Swap" bitfld.long 0x00 11. " Y8POS ,Location of Y signal when YCbCr 8bit data is input" "Even pixel,Odd pixel" bitfld.long 0x00 8. " WENLOG ,Specifies CCD valid area" "AND,OR" textline " " bitfld.long 0x00 5. " BW656 ,The data width in CCIR656 input mode" "8bits,10bits" bitfld.long 0x00 4. " YCINSWP ,Y input (YIN[7:0]) and C input (CIN[7:0]) are swapped" "0,1" bitfld.long 0x00 2. " YCOUTSWP ,Y output (YOUT[7:0]) and C output (COUT[7:0]) are swapped" "0,1" group.long 0x098++0x03 line.long 0x00 "VPFE_DMA_CNTL,DMA Status and Control" bitfld.long 0x00 31. " OVERFLOW ,DMA Overflow Flag" "No overflow,Overflow" bitfld.long 0x00 0.--2. " PRIORITY ,Sets the priority that all command should be sent with on the DMA bus" "Highest,1,2,3,4,5,6,Lowest" group.long 0x104++0x03 line.long 0x00 "VPFE_SYSCONFIG,Clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "FORCE_STANDBY,NO_STANDBY,SMART_STANDBY,SMART_STANDBY_WAKEUP_CAPABLE" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "FORCE_IDLE,NO_IDLE,SMART_IDLE,SMART_IDLE_WAKEUP_CAPABLE" group.long 0x108++0x03 line.long 0x00 "VPFE_CONFIG,Module configuration register" bitfld.long 0x00 2. " VPFE_ST ,VPFE Master OCP interface Status" "OCP_ACTIVE,OCP_STANDBY" bitfld.long 0x00 1. " VPFE_EN ,VPFE Master OCP interface enable" "Disabled,Enabled" bitfld.long 0x00 0. " PCLK_INV ,Pixel clock inversion enable" "NOT_INV,INV" group.long 0x110++0x03 line.long 0x00 "VPFE_IRQ_EOI,Module EOI register" bitfld.long 0x00 0. " EOI ,EOI for VPFE" "Not generated,Generated" textline " " width 21. group.long 0x114++0x03 line.long 0x00 "VPFE_IRQ_STATUS_RAW,Interrupt raw status register" bitfld.long 0x00 2. " VD2_INT_RAW ,CCDC VD2 interrupt status raw value" "No interrupt,Interrupt" bitfld.long 0x00 1. " VD1_INT_RAW ,CCDC VD1 interrupt status raw value" "No interrupt,Interrupt" bitfld.long 0x00 0. " VD0_INT_RAW ,CCDC VD0 interrupt status raw value" "No interrupt,Interrupt" group.long 0x118++0x03 line.long 0x00 "VPFE_IRQ_STATUS,Interrupt status register" bitfld.long 0x00 2. " VD2_INT ,CCDC VD2 interrupt status value" "No interrupt,Interrupt" bitfld.long 0x00 1. " VD1_INT ,CCDC VD1 interrupt status value" "No interrupt,Interrupt" bitfld.long 0x00 0. " VD0_INT ,CCDC VD0 interrupt status value" "No interrupt,Interrupt" group.long 0x11C++0x03 line.long 0x00 "VPFE_IRQ_ENABLE_SET,Interrupt enable set" bitfld.long 0x00 2. " VD2_INT_EN ,CCDC VD2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " VD1_INT_EN ,CCDC VD1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " VD0_INT_EN ,CCDC VD0 interrupt enable" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "VPFE_IRQ_ENABLE_CLR,Interrupt enable clear" bitfld.long 0x00 2. " VD2_INT_DIS ,CCDC VD2 interrupt disable" "No,Yes" bitfld.long 0x00 1. " VD1_INT_DIS ,CCDC VD1 interrupt disable" "No,Yes" bitfld.long 0x00 0. " VD0_INT_DIS ,CCDC VD0 interrupt disable" "No,Yes" width 11. tree.end tree.end tree "ES(Ethernet Subsystem Registers)" tree "CPSW_ALE Registers" base ad:0x4A100D00 width 23. rgroup.long 0x00++0x03 line.long 0x00 "CPSW_ALE_IDVER,ADDRESS LOOKUP ENGINE ID/VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " IDENT , ALE Identification Value" hexmask.long.byte 0x00 8.--15. 1. " MAJ_VER , ALE Major Version Value" hexmask.long.byte 0x00 0.--7. 1. " MINOR_VER , ALE Minor Version Value" group.long 0x08++0x03 line.long 0x00 "CPSW_ALE_CTRL,ADDRESS LOOKUP ENGINE CONTROL REGISTER" bitfld.long 0x00 31. " en_2_0x1 ,Enable ALE" "Disabled,Enabled" bitfld.long 0x00 30. " CLR_TBL , Clear ALE address table" "Not clear,Clear" textline " " bitfld.long 0x00 29. " AGE_OUT_NOW , Age Out Address Table Now" "Not removed,Removed" bitfld.long 0x00 8. " EN_P0_UNI_FLOOD ,Enable Port 0 (Host Port) unicast flood" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEARN_NO_VID ,Learn No VID" "Learned,Not learned" bitfld.long 0x00 6. " EN_VID0_MODE ,Process the packet with VID = 0." "VID = PORT_VLAN[11 to 0],VID = 0" textline " " bitfld.long 0x00 5. " EN_OUI_DENY , Enable OUI Deny Mode" "Disabled,Enabled" bitfld.long 0x00 4. " BYPASS , ALE Bypass" "Not send,Send" textline " " bitfld.long 0x00 3. " RATE_LIMIT_TX ,Rate Limit Transmit mode" "Received,Transmit" bitfld.long 0x00 2. " VLAN_AWARE ,Determines what is done if VLAN not found" "Flood if VLAN not found,Drop packet if VLAN not found" textline " " bitfld.long 0x00 1. " EN_AUTH_MODE ,Enable MAC Authorization Mode" "Not authorization,Authorization" bitfld.long 0x00 0. " EN_RATE_LIMIT ,Enable Broadcast and Multicast Rate Limit" "Not limited,Limited" group.long 0x10++0x03 line.long 0x00 "CPSW_ALE_PRESCALE,ADDRESS LOOKUP ENGINE PRESCALE REGISTER" hexmask.long.tbyte 0x00 0.--19. 1. " PRESCALE , ALE Prescale Register" group.long 0x18++0x03 line.long 0x00 "CPSW_ALE_UNKNOWN_VLAN,ADDRESS LOOKUP ENGINE UNKNOWN VLAN REGISTER" hexmask.long.byte 0x00 24.--29. 1. " UNKNOWN_FORCE_UNTAGGED_EGRESS , Unknown VLAN Force Untagged Egress." hexmask.long.byte 0x00 16.--21. 1. " UNKNOWN_REG_MCAST_FLOOD_MASK , Unknown VLAN Registered Multicast Flood Mask" textline " " hexmask.long.byte 0x00 8.--13. 1. " UNKNOWN_MCAST_FLOOD_MASK , Unknown VLAN Multicast Flood Mask" hexmask.long.byte 0x00 0.--5. 1. " UNKNOWN_VLAN_MEMBER_LIST , Unknown VLAN Member List" group.long 0x20++0x03 line.long 0x00 "CPSW_ALE_TBLCTL,ADDRESS LOOKUP ENGINE TABLE CONTROL" bitfld.long 0x00 31. " WRITE_RDZ , Write Bit" "0,1" hexmask.long.word 0x00 0.--9. 1. " ENTRY_POINTER , Table Entry Pointer" group.long 0x34++0x03 line.long 0x00 "CPSW_ALE_TBLW2,ADDRESS LOOKUP ENGINE TABLE WORD 2 REGISTER" hexmask.long.byte 0x00 0.--7. 1. " ENTRY71_64 , Table entry bits 71:64" group.long 0x38++0x03 line.long 0x00 "CPSW_ALE_TBLW1,ADDRESS LOOKUP ENGINE TABLE WORD 1 REGISTER" hexmask.long 0x00 0.--31. 1. " ENTRY63_32 , Table entry bits 63:32" group.long 0x3C++0x03 line.long 0x00 "CPSW_ALE_TBLW0,ADDRESS LOOKUP ENGINE TABLE WORD 0 REGISTER" hexmask.long 0x00 0.--31. 1. " ENTRY31_0 , Table entry bits 31:0" width 21. tree "CPSW_ALE_PORTCTL - array[6]" group.long 0x40++0x03 line.long 0x00 "CPSW_ALE_PORTCTL[0],ADDRESS LOOKUP ENGINE PORT x CONTROL REGISTER" hexmask.long.byte 0x00 24.--31. 1. " BCAST_LIMIT , Broadcast Packet Rate Limit" hexmask.long.byte 0x00 16.--23. 1. " MCAST_LIMIT , Multicast Packet Rate Limit" bitfld.long 0x00 5. " NO_SA_UPDATE , No Souce Address Update" "No,Yes" textline " " bitfld.long 0x00 4. " NO_LEARN , No Learn Mode" "Disabled,Enabled" bitfld.long 0x00 3. " VID_INGRESS_CHECK , VLAN ID Ingress Check" "Not checked,Checked" bitfld.long 0x00 2. " DROP_UNTAGGED , Drop Untagged Packets" "Not dropped,Dropped" textline " " bitfld.long 0x00 0.--1. " PORT_STATE ,PORT STATE" "Disabled,Blocked,Learn,Forward" group.long 0x44++0x03 line.long 0x00 "CPSW_ALE_PORTCTL[1],ADDRESS LOOKUP ENGINE PORT x CONTROL REGISTER" hexmask.long.byte 0x00 24.--31. 1. " BCAST_LIMIT , Broadcast Packet Rate Limit" hexmask.long.byte 0x00 16.--23. 1. " MCAST_LIMIT , Multicast Packet Rate Limit" bitfld.long 0x00 5. " NO_SA_UPDATE , No Souce Address Update" "No,Yes" textline " " bitfld.long 0x00 4. " NO_LEARN , No Learn Mode" "Disabled,Enabled" bitfld.long 0x00 3. " VID_INGRESS_CHECK , VLAN ID Ingress Check" "Not checked,Checked" bitfld.long 0x00 2. " DROP_UNTAGGED , Drop Untagged Packets" "Not dropped,Dropped" textline " " bitfld.long 0x00 0.--1. " PORT_STATE ,PORT STATE" "Disabled,Blocked,Learn,Forward" group.long 0x48++0x03 line.long 0x00 "CPSW_ALE_PORTCTL[2],ADDRESS LOOKUP ENGINE PORT x CONTROL REGISTER" hexmask.long.byte 0x00 24.--31. 1. " BCAST_LIMIT , Broadcast Packet Rate Limit" hexmask.long.byte 0x00 16.--23. 1. " MCAST_LIMIT , Multicast Packet Rate Limit" bitfld.long 0x00 5. " NO_SA_UPDATE , No Souce Address Update" "No,Yes" textline " " bitfld.long 0x00 4. " NO_LEARN , No Learn Mode" "Disabled,Enabled" bitfld.long 0x00 3. " VID_INGRESS_CHECK , VLAN ID Ingress Check" "Not checked,Checked" bitfld.long 0x00 2. " DROP_UNTAGGED , Drop Untagged Packets" "Not dropped,Dropped" textline " " bitfld.long 0x00 0.--1. " PORT_STATE ,PORT STATE" "Disabled,Blocked,Learn,Forward" group.long 0x4C++0x03 line.long 0x00 "CPSW_ALE_PORTCTL[3],ADDRESS LOOKUP ENGINE PORT x CONTROL REGISTER" hexmask.long.byte 0x00 24.--31. 1. " BCAST_LIMIT , Broadcast Packet Rate Limit" hexmask.long.byte 0x00 16.--23. 1. " MCAST_LIMIT , Multicast Packet Rate Limit" bitfld.long 0x00 5. " NO_SA_UPDATE , No Souce Address Update" "No,Yes" textline " " bitfld.long 0x00 4. " NO_LEARN , No Learn Mode" "Disabled,Enabled" bitfld.long 0x00 3. " VID_INGRESS_CHECK , VLAN ID Ingress Check" "Not checked,Checked" bitfld.long 0x00 2. " DROP_UNTAGGED , Drop Untagged Packets" "Not dropped,Dropped" textline " " bitfld.long 0x00 0.--1. " PORT_STATE ,PORT STATE" "Disabled,Blocked,Learn,Forward" group.long 0x50++0x03 line.long 0x00 "CPSW_ALE_PORTCTL[4],ADDRESS LOOKUP ENGINE PORT x CONTROL REGISTER" hexmask.long.byte 0x00 24.--31. 1. " BCAST_LIMIT , Broadcast Packet Rate Limit" hexmask.long.byte 0x00 16.--23. 1. " MCAST_LIMIT , Multicast Packet Rate Limit" bitfld.long 0x00 5. " NO_SA_UPDATE , No Souce Address Update" "No,Yes" textline " " bitfld.long 0x00 4. " NO_LEARN , No Learn Mode" "Disabled,Enabled" bitfld.long 0x00 3. " VID_INGRESS_CHECK , VLAN ID Ingress Check" "Not checked,Checked" bitfld.long 0x00 2. " DROP_UNTAGGED , Drop Untagged Packets" "Not dropped,Dropped" textline " " bitfld.long 0x00 0.--1. " PORT_STATE ,PORT STATE" "Disabled,Blocked,Learn,Forward" group.long 0x54++0x03 line.long 0x00 "CPSW_ALE_PORTCTL[5],ADDRESS LOOKUP ENGINE PORT x CONTROL REGISTER" hexmask.long.byte 0x00 24.--31. 1. " BCAST_LIMIT , Broadcast Packet Rate Limit" hexmask.long.byte 0x00 16.--23. 1. " MCAST_LIMIT , Multicast Packet Rate Limit" bitfld.long 0x00 5. " NO_SA_UPDATE , No Souce Address Update" "No,Yes" textline " " bitfld.long 0x00 4. " NO_LEARN , No Learn Mode" "Disabled,Enabled" bitfld.long 0x00 3. " VID_INGRESS_CHECK , VLAN ID Ingress Check" "Not checked,Checked" bitfld.long 0x00 2. " DROP_UNTAGGED , Drop Untagged Packets" "Not dropped,Dropped" textline " " bitfld.long 0x00 0.--1. " PORT_STATE ,PORT STATE" "Disabled,Blocked,Learn,Forward" tree.end width 11. tree.end tree "CPSW_CPDMA Registers" base ad:0x4A100800 width 25. rgroup.long 0x00++0x03 line.long 0x00 "CPSW_TX_IDVER,CPDMA_REGS TX IDENTIFICATION AND VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " TX_IDENT ,TX Identification" hexmask.long.byte 0x00 8.--15. 1. " TX_MAJOR_VER ,TX Major Version" hexmask.long.byte 0x00 0.--7. 1. " TX_MINOR_VER ,TX Minor Version" group.long 0x4++0x03 line.long 0x00 "CPSW_TX_CTRL,CPDMA_REGS TX CONTROL REGISTER" bitfld.long 0x00 0. " TX_EN , TX Enable" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "CPSW_TX_TEARDOWN,CPDMA_REGS TX TEARDOWN REGISTER" rbitfld.long 0x00 31. " TX_TDN_RDY , Tx Teardown Ready" "0,1" bitfld.long 0x00 0.--2. " TX_TDN_CH ,Tx Teardown Channel" "0,1,2,3,4,5,6,7" rgroup.long 0x10++0x03 line.long 0x00 "CPSW_RX_IDVER,CPDMA_REGS RX IDENTIFICATION AND VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " RX_IDENT ,TX Identification" hexmask.long.byte 0x00 8.--15. 1. " RX_MAJOR_VER ,TX Major Version" hexmask.long.byte 0x00 0.--7. 1. " RX_MINOR_VER ,TX Minor Version" group.long 0x14++0x03 line.long 0x00 "CPSW_RX_CTRL,CPDMA_REGS RX CONTROL REGISTER" bitfld.long 0x00 0. " RX_EN ,RX DMA Enable" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "CPSW_RX_TEARDOWN,CPDMA_REGS RX TEARDOWN REGISTER" rbitfld.long 0x00 31. " RX_TDN_RDY ,Rx Teardown Ready" "0,1" bitfld.long 0x00 0.--2. " RX_TDN_CH ,Rx Teardown Channel" "0,1,2,3,4,5,6,7" group.long 0x1C++0x03 line.long 0x00 "CPSW_CPDMA_SOFT_RESET,CPDMA_REGS SOFT RESET REGISTER" bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "Not reset,Reset" group.long 0x20++0x03 line.long 0x00 "CPSW_DMACTRL,CPDMA_REGS CPDMA CONTROL REGISTER" hexmask.long.byte 0x00 8.--15. 1. " TX_RLIM ,Transmit Rate Limit" bitfld.long 0x00 4. " RX_CEF ,RX Copy Error Frames Enable" "Disabled,Enabled" bitfld.long 0x00 3. " CMD_IDLE ,Command Idle" "Not commanded,Commanded" textline " " bitfld.long 0x00 2. " RX_OFFLEN_BLOCK ,Receive Offset/Length word write block" "Do not block,Block all" bitfld.long 0x00 1. " RX_OWNERSHIP ,Receive Ownership Write Bit Value" "0,1" bitfld.long 0x00 0. " TX_PTYPE ,Transmit Queue Priority Type" "Round robin,Fixed" hgroup.long 0x24++0x03 hide.long 0x00 "CPSW_DMASTS,CPDMA_REGS CPDMA STATUS REGISTER" in group.long 0x28++0x03 line.long 0x00 "CPSW_RX_BUFFER_OFFSET,CPDMA_REGS RECEIVE BUFFER OFFSET" hexmask.long.word 0x00 0.--15. 1. " RX_BUFFER_OFFSET ,Receive Buffer Offset Value" group.long 0x2C++0x03 line.long 0x00 "CPSW_EMCTRL,CPDMA_REGS EMULATION CONTROL" bitfld.long 0x00 0. " SOFT ,Emulation Soft Bit" "0,1" bitfld.long 0x00 0. " FREE ,Emulation Free Bit" "0,1" group.long 0x30++0x03 line.long 0x00 "CPSW_TX_PRI0_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 0 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" group.long 0x34++0x03 line.long 0x00 "CPSW_TX_PRI1_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 1 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" group.long 0x38++0x03 line.long 0x00 "CPSW_TX_PRI2_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 2 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" group.long 0x3C++0x03 line.long 0x00 "CPSW_TX_PRI3_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 3 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" group.long 0x40++0x03 line.long 0x00 "CPSW_TX_PRI4_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 4 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" group.long 0x44++0x03 line.long 0x00 "CPSW_TX_PRI5_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 5 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" group.long 0x48++0x03 line.long 0x00 "CPSW_TX_PRI6_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 6 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" group.long 0x4C++0x03 line.long 0x00 "CPSW_TX_PRI7_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 7 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT , Priority ( 7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT , Priority ( 7:0) send count" rgroup.long 0x80++0x03 line.long 0x00 "CPSW_TX_INTSTAT_RAW,CPDMA_INT TX INTERRUPT STATUS REGISTER (RAW VALUE)" bitfld.long 0x00 7. " TX7_PEND , TX7_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 6. " TX6_PEND , TX6_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 5. " TX5_PEND , TX5_PEND raw int read (before mask)." "Not pended,Pended" textline " " bitfld.long 0x00 4. " TX4_PEND , TX4_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 3. " TX3_PEND , TX3_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 2. " TX2_PEND , TX2_PEND raw int read (before mask)." "Not pended,Pended" textline " " bitfld.long 0x00 1. " TX1_PEND , TX1_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 0. " TX0_PEND , TX0_PEND raw int read (before mask)." "Not pended,Pended" rgroup.long 0x84++0x03 line.long 0x00 "CPSW_TX_INTSTAT_MASKED,CPDMA_INT TX INTERRUPT STATUS REGISTER (MASKED VALUE)" bitfld.long 0x00 7. " TX7_PEND , TX7_PEND masked interrupt read." "Not masked,Masked" bitfld.long 0x00 6. " TX6_PEND , TX6_PEND masked interrupt read." "Not masked,Masked" bitfld.long 0x00 5. " TX5_PEND , TX5_PEND masked interrupt read." "Not masked,Masked" textline " " bitfld.long 0x00 4. " TX4_PEND , TX4_PEND masked interrupt read." "Not masked,Masked" bitfld.long 0x00 3. " TX3_PEND , TX3_PEND masked interrupt read." "Not masked,Masked" bitfld.long 0x00 2. " TX2_PEND , TX2_PEND masked interrupt read." "Not masked,Masked" textline " " bitfld.long 0x00 1. " TX1_PEND , TX1_PEND masked interrupt read." "Not masked,Masked" bitfld.long 0x00 0. " TX0_PEND , TX0_PEND masked interrupt read." "Not masked,Masked" group.long 0x88++0x03 line.long 0x00 "CPSW_TX_INTMASK_SET,CPDMA_INT TX INTERRUPT MASK SET REGISTER" bitfld.long 0x00 7. " TX7_MASK , TX Channel 7 Mask - Write one to enable interrupt." "Not interrupt,Interrupt" rbitfld.long 0x00 6. " TX6_MASK , TX Channel 6 Mask - Write one to enable interrupt." "Not interrupt,Interrupt" bitfld.long 0x00 5. " TX5_MASK , TX Channel 5 Mask - Write one to enable interrupt." "Not interrupt,Interrupt" textline " " rbitfld.long 0x00 4. " TX4_MASK , TX Channel 4 Mask - Write one to enable interrupt." "Not interrupt,Interrupt" bitfld.long 0x00 3. " TX3_MASK , TX Channel 3 Mask - Write one to enable interrupt." "Not interrupt,Interrupt" rbitfld.long 0x00 2. " TX2_MASK , TX Channel 2 Mask - Write one to enable interrupt." "Not interrupt,Interrupt" textline " " bitfld.long 0x00 1. " TX1_MASK , TX Channel 1 Mask - Write one to enable interrupt." "Not interrupt,Interrupt" rbitfld.long 0x00 0. " TX0_MASK , TX Channel 0 Mask - Write one to enable interrupt." "Not interrupt,Interrupt" group.long 0x8C++0x03 line.long 0x00 "CPSW_TX_INTMASK_CLR,CPDMA_INT TX INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x00 7. " TX7_MASK , TX Channel 7 Mask - Write one to disable interrupt." "No,Yes" rbitfld.long 0x00 6. " TX6_MASK , TX Channel 6 Mask - Write one to disable interrupt." "No,Yes" bitfld.long 0x00 5. " TX5_MASK , TX Channel 5 Mask - Write one to disable interrupt." "No,Yes" textline " " rbitfld.long 0x00 4. " TX4_MASK , TX Channel 4 Mask - Write one to disable interrupt." "No,Yes" bitfld.long 0x00 3. " TX3_MASK , TX Channel 3 Mask - Write one to disable interrupt." "No,Yes" rbitfld.long 0x00 2. " TX2_MASK , TX Channel 2 Mask - Write one to disable interrupt." "No,Yes" textline " " bitfld.long 0x00 1. " TX1_MASK , TX Channel 1 Mask - Write one to disable interrupt." "No,Yes" rbitfld.long 0x00 0. " TX0_MASK , TX Channel 0 Mask - Write one to disable interrupt." "No,Yes" rgroup.long 0x90++0x03 line.long 0x00 "CPSW_CPDMA_IN_VECTOR,CPDMA_INT INPUT VECTOR (READ ONLY)" hexmask.long 0x00 0.--31. 1. " DMA_IN_VECTOR , DMA Input Vector" group.long 0x94++0x03 line.long 0x00 "CPSW_CPDMA_EOI_VECTOR,CPDMA_INT END OF INTERRUPT VECTOR" bitfld.long 0x00 0.--4. " DMA_EOI_VECTOR , DMA End of Interrupt Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA0++0x03 line.long 0x00 "CPSW_RX_INTSTAT_RAW,CPDMA_INT RX INTERRUPT STATUS REGISTER (RAW VALUE)" bitfld.long 0x00 15. " RX7_THRESH_PEND , RX7_THRESH_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 14. " RX6_THRESH_PEND , RX6_THRESH_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 13. " RX5_THRESH_PEND , RX5_THRESH_PEND raw int read (before mask)." "Not pended,Pended" textline " " bitfld.long 0x00 12. " RX4_THRESH_PEND , RX4_THRESH_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 11. " RX3_THRESH_PEND , RX3_THRESH_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 10. " RX2_THRESH_PEND , RX2_THRESH_PEND raw int read (before mask)." "Not pended,Pended" textline " " bitfld.long 0x00 9. " RX1_THRESH_PEND , RX1_THRESH_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 8. " RX0_THRESH_PEND , RX0_THRESH_PEND raw int read (before mask)." "Not pended,Pended" textline " " bitfld.long 0x00 7. " RX7_PEND , RX7_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 6. " RX6_PEND , RX6_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 5. " RX5_PEND , RX5_PEND raw int read (before mask)." "Not pended,Pended" textline " " bitfld.long 0x00 4. " RX4_PEND , RX4_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 3. " RX3_PEND , RX3_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 2. " RX2_PEND , RX2_PEND raw int read (before mask)." "Not pended,Pended" textline " " bitfld.long 0x00 1. " RX1_PEND , RX1_PEND raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 0. " RX0_PEND , RX0_PEND raw int read (before mask)." "Not pended,Pended" rgroup.long 0xA4++0x03 line.long 0x00 "CPSW_RX_INTSTAT_MASKED,CPDMA_INT RX INTERRUPT STATUS REGISTER (MASKED VALUE)" bitfld.long 0x00 15. " RX7_THRESH_PEND , RX7_THRESH_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 14. " RX6_THRESH_PEND , RX6_THRESH_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 13. " RX5_THRESH_PEND , RX5_THRESH_PEND masked int read." "Not masked,Masked" textline " " bitfld.long 0x00 12. " RX4_THRESH_PEND , RX4_THRESH_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 11. " RX3_THRESH_PEND , RX3_THRESH_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 10. " RX2_THRESH_PEND , RX2_THRESH_PEND masked int read." "Not masked,Masked" textline " " bitfld.long 0x00 9. " RX1_THRESH_PEND , RX1_THRESH_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 8. " RX0_THRESH_PEND , RX0_THRESH_PEND masked int read." "Not masked,Masked" textline " " bitfld.long 0x00 7. " RX7_PEND , RX7_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 6. " RX6_PEND , RX6_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 5. " RX5_PEND , RX5_PEND masked int read." "Not masked,Masked" textline " " bitfld.long 0x00 4. " RX4_PEND , RX4_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 3. " RX3_PEND , RX3_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 2. " RX2_PEND , RX2_PEND masked int read." "Not masked,Masked" textline " " bitfld.long 0x00 1. " RX1_PEND , RX1_PEND masked int read." "Not masked,Masked" bitfld.long 0x00 0. " RX0_PEND , RX0_PEND masked int read." "Not masked,Masked" group.long 0xA8++0x03 line.long 0x00 "CPSW_RX_INTMASK_SET,CPDMA_INT RX INTERRUPT MASK SET REGISTER" bitfld.long 0x00 15. " RX7_THRESH_PEND_MASK , RX Channel 7 Threshold Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 14. " RX6_THRESH_PEND_MASK , RX Channel 6 Threshold Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 13. " RX5_THRESH_PEND_MASK , RX Channel 5 Threshold Pending mask enable interrupt" "Not interrupt,Interrupt" textline " " bitfld.long 0x00 12. " RX4_THRESH_PEND_MASK , RX Channel 4 Threshold Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 11. " RX3_THRESH_PEND_MASK , RX Channel 3 Threshold Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 10. " RX2_THRESH_PEND_MASK , RX Channel 2 Threshold Pending mask enable interrupt" "Not interrupt,Interrupt" textline " " bitfld.long 0x00 9. " RX1_THRESH_PEND_MASK , RX Channel 1 Threshold Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 8. " RX0_THRESH_PEND_MASK , RX Channel 0 Threshold Pending mask enable interrupt" "Not interrupt,Interrupt" textline " " bitfld.long 0x00 7. " RX7_PEND_MASK , RX Channel 7 Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 6. " RX6_PEND_MASK , RX Channel 6 Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 5. " RX5_PEND_MASK , RX Channel 5 Pending mask enable interrupt" "Not interrupt,Interrupt" textline " " bitfld.long 0x00 4. " RX4_PEND_MASK , RX Channel 4 Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 3. " RX3_PEND_MASK , RX Channel 3 Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 2. " RX2_PEND_MASK , RX Channel 2 Pending mask enable interrupt" "Not interrupt,Interrupt" textline " " bitfld.long 0x00 1. " RX1_PEND_MASK , RX Channel 1 Pending mask enable interrupt" "Not interrupt,Interrupt" bitfld.long 0x00 0. " RX0_PEND_MASK , RX Channel 0 Pending mask enable interrupt" "Not interrupt,Interrupt" group.long 0xAC++0x03 line.long 0x00 "CPSW_RX_INTMASK_CLR,CPDMA_INT RX INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x00 15. " RX7_THRESH_PEND_MASK , RX Channel 7 Threshold Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 14. " RX6_THRESH_PEND_MASK , RX Channel 6 Threshold Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 13. " RX5_THRESH_PEND_MASK , RX Channel 5 Threshold Pending Int. Mask - Write one to disable Int." "No,Yes" textline " " bitfld.long 0x00 12. " RX4_THRESH_PEND_MASK , RX Channel 4 Threshold Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 11. " RX3_THRESH_PEND_MASK , RX Channel 3 Threshold Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 10. " RX2_THRESH_PEND_MASK , RX Channel 2 Threshold Pending Int. Mask - Write one to disable Int." "No,Yes" textline " " bitfld.long 0x00 9. " RX1_THRESH_PEND_MASK , RX Channel 1 Threshold Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 8. " RX0_THRESH_PEND_MASK , RX Channel 0 Threshold Pending Int. Mask - Write one to disable Int." "No,Yes" textline " " bitfld.long 0x00 7. " RX7_PEND_MASK , RX Channel 7 Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 6. " RX6_PEND_MASK , RX Channel 6 Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 5. " RX5_PEND_MASK , RX Channel 5 Pending Int. Mask - Write one to disable Int." "No,Yes" textline " " bitfld.long 0x00 4. " RX4_PEND_MASK , RX Channel 4 Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 3. " RX3_PEND_MASK , RX Channel 3 Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 2. " RX2_PEND_MASK , RX Channel 2 Pending Int. Mask - Write one to disable Int." "No,Yes" textline " " bitfld.long 0x00 1. " RX1_PEND_MASK , RX Channel 1 Pending Int. Mask - Write one to disable Int." "No,Yes" bitfld.long 0x00 0. " RX0_PEND_MASK , RX Channel 0 Pending Int. Mask - Write one to disable Int." "No,Yes" rgroup.long 0xB0++0x03 line.long 0x00 "CPSW_DMA_INTSTAT_RAW,CPDMA_INT DMA INTERRUPT STATUS REGISTER (RAW VALUE)" bitfld.long 0x00 1. " HOST_PEND , Host Pending Interrupt - raw int read (before mask)." "Not pended,Pended" bitfld.long 0x00 0. " STAT_PEND , Statistics Pending Interrupt - raw int read (before mask)." "Not pended,Pended" group.long 0xB4++0x03 line.long 0x00 "CPSW_DMA_INTSTAT_MASKED,CPDMA_INT DMA INTERRUPT STATUS REGISTER (MASKED VALUE)" bitfld.long 0x00 1. " HOST_PEND , Host Pending Interrupt - masked interrupt read." "Not masked,Masked" bitfld.long 0x00 0. " STAT_PEND , Statistics Pending Interrupt - masked interrupt read." "Not masked,Masked" group.long 0xB8++0x03 line.long 0x00 "CPSW_DMA_INTMASK_SET,CPDMA_INT DMA INTERRUPT MASK SET REGISTER" bitfld.long 0x00 0. " STAT_INT_MASK , Statistics Interrupt Mask - Write one to enable interrupt." "Not interrupt,Interrupt" rbitfld.long 0x00 1. " HOST_ERR_INT_MASK , Host Error Interrupt Mask - Write one to enable interrupt." "Not interrupt,Interrupt" group.long 0xBC++0x03 line.long 0x00 "CPSW_DMA_INTMASK_CLR,CPDMA_INT DMA INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x00 0. " STAT_INT_MASK , Statistics Interrupt Mask - Write one to disable interrupt." "No,Yes" bitfld.long 0x00 1. " HOST_ERR_INT_MASK , Host Error Interrupt Mask - Write one to disable interrupt." "No,Yes" group.long 0xC0++0x03 line.long 0x00 "CPSW_RX0_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 0" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH , Rx Flow Threshold" group.long 0xC4++0x03 line.long 0x00 "CPSW_RX1_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 1" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH , Rx Flow Threshold" group.long 0xC8++0x03 line.long 0x00 "CPSW_RX2_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 2" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH , Rx Flow Threshold" group.long 0xCC++0x03 line.long 0x00 "CPSW_RX3_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 3" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH , Rx Flow Threshold" group.long 0xD0++0x03 line.long 0x00 "CPSW_RX4_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 4" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH , Rx Flow Threshold" group.long 0xD4++0x03 line.long 0x00 "CPSW_RX5_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 5" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH , Rx Flow Threshold" group.long 0xD8++0x03 line.long 0x00 "CPSW_RX6_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 6" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH , Rx Flow Threshold" group.long 0xDC++0x03 line.long 0x00 "CPSW_RX7_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 7" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH , Rx Flow Threshold" wgroup.long 0xE0++0x03 line.long 0x00 "CPSW_RX0_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 0" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER , Rx Free Buffer Count" wgroup.long 0xE4++0x03 line.long 0x00 "CPSW_RX1_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 1" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER , Rx Free Buffer Count" wgroup.long 0xE8++0x03 line.long 0x00 "CPSW_RX2_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 2" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER , Rx Free Buffer Count" wgroup.long 0xEC++0x03 line.long 0x00 "CPSW_RX3_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 3" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER , Rx Free Buffer Count" wgroup.long 0xF0++0x03 line.long 0x00 "CPSW_RX4_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 4" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER , Rx Free Buffer Count" wgroup.long 0xF4++0x03 line.long 0x00 "CPSW_RX5_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 5" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER , Rx Free Buffer Count" wgroup.long 0xF8++0x03 line.long 0x00 "CPSW_RX6_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 6" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER , Rx Free Buffer Count" wgroup.long 0xFC++0x03 line.long 0x00 "CPSW_RX7_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 7" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER , Rx Free Buffer Count" width 11. tree.end tree "CPSW_CPTS Registers" base ad:0x4A100C00 width 26. group.long 0x00++0x03 line.long 0x00 "CPSW_CPTS_IDVER,IDENTIFICATION AND VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " TX_IDENT , TX Identification Value" bitfld.long 0x00 11.--15. " RTL_VER , RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR_VER , Major Version Value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " MINOR_VER , Minor Version Value" group.long 0x04++0x03 line.long 0x00 "CPSW_CPTS_CTRL,TIME SYNC CONTROL REGISTER" bitfld.long 0x00 28.--31. " TS_SYNC_SEL , TS_SYNC output timestamp counter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " HW8_TS_PUSH_EN , Hardware push 8 enable" "Disabled,Enabled" bitfld.long 0x00 14. " HW7_TS_PUSH_EN , Hardware push 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " HW5_6_TS_PUSH_EN , Hardware push 5 & 6 enable" "Disabled,Enabled" bitfld.long 0x00 11. " HW4_TS_PUSH_EN , Hardware push 4 enable" "Disabled,Enabled" bitfld.long 0x00 10. " HW3_TS_PUSH_EN , Hardware push 3 enable" "Disabled,Enabled" bitfld.long 0x00 9. " HW2_TS_PUSH_EN , Hardware push 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HW1_TS_PUSH_EN , Hardware push 1 enable" "Disabled,Enabled" bitfld.long 0x00 1. " INT_TEST , Interrupt Test" "Not allowed,Allowed" bitfld.long 0x00 0. " CPTS_EN ,Time Sync Enabled" "Disabled,Enabled" if (((d.l(ad:0x4A100C00+0x04))&0x01)==0x01) //CPSW_CPTS_CTRL.CPTS_EN== "ENABLED" rgroup.long 0x08++0x03 line.long 0x00 "CPSW_RFTCLK_SEL,RFTCLK SELECT REGISTER" bitfld.long 0x00 0.--4. " RFTCLK_SEL , Reference Clock Select " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x08++0x03 line.long 0x00 "CPSW_RFTCLK_SEL,RFTCLK SELECT REGISTER" bitfld.long 0x00 0.--4. " RFTCLK_SEL , Reference Clock Select " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif wgroup.long 0x0C++0x03 line.long 0x00 "CPSW_CPTS_PUSH,TIME STAMP EVENT PUSH REGISTER" bitfld.long 0x00 0. " TS_PUSH , Time stamp event push" "No,Pushed" group.long 0x10++0x03 line.long 0x00 "CPSW_CPTS_LOAD_VAL,TIME STAMP LOAD VALUE REGISTER" wgroup.long 0x14++0x03 line.long 0x00 "CPSW_CPTS_LOAD_EN,TIME STAMP LOAD ENABLE REGISTER" bitfld.long 0x00 0. " TS_LOAD_EN , Time Stamp Load" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "CPSW_CPTS_COMP_VAL,TIME STAMP COMPARISON VALUE REGISTER" group.long 0x1C++0x03 line.long 0x00 "CPSW_CPTS_COMP_LENGTH,TIME STAMP COMPARISON LENGTH REGISTER" hexmask.long.word 0x00 0.--15. 1. " TS_COMP_LENGTH , Time Stamp Comparison Length" if (((d.l(ad:0x4A100C00+0x04))&0x02)==0x02) //CPSW_CPTS_CTRL.INT_TEST== "Allowed" group.long 0x20++0x03 line.long 0x00 "CPSW_CPTS_INTSTAT_RAW,TIME SYNC INTERRUPT STATUS RAW REGISTER" bitfld.long 0x00 0. " TS_PEND_RAW ,Indicates that there is one or more events in the event FIFO" "No,One or more" else rgroup.long 0x20++0x03 line.long 0x00 "CPSW_CPTS_INTSTAT_RAW,TIME SYNC INTERRUPT STATUS RAW REGISTER" bitfld.long 0x00 0. " TS_PEND_RAW ,Indicates that there is one or more events in the event FIFO" "No,One or more" endif rgroup.long 0x24++0x03 line.long 0x00 "CPSW_CPTS_INTSTAT_MASKED,TIME SYNC INTERRUPT STATUS MASKED REGISTER" bitfld.long 0x00 0. " TS_PEND , TS_PEND masked interrupt read" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "CPSW_CPTS_INT_EN,TIME SYNC INTERRUPT ENABLE REGISTER" bitfld.long 0x00 0. " TS_PEND_EN , TS_PEND masked interrupt enable." "Disabled,Enabled" wgroup.long 0x30++0x03 line.long 0x00 "CPSW_CPTS_EVT_POP,EVENT INTERRUPT POP REGISTER" bitfld.long 0x00 0. " EVT_POP , Event Pop" "On,Off" rgroup.long 0x34++0x03 line.long 0x00 "CPSW_CPTS_EVT_LOW,LOWER 32-BITS OF THE EVENT VALUE" if (((d.l(ad:0x4A100C00+0x38))&0xF00000)==0x400000)||(((d.l(ad:0x4A100C00+0x38))&0xF00000)==0x500000) //this.EVT_TYPE== "transmit" or " receive" group.long 0x38++0x03 line.long 0x00 "CPSW_CPTS_EVT_MID,MIDDLE 32-BITS OF THE EVENT VALUE" bitfld.long 0x00 24.--28. " PORT_NUMBER , Port Number" ",1,2,3,4,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 20.--23. " EVT_TYPE ,Ethernet Transmit Event" "Push Event,Rollover Event,Half Rollover Event,Push Event,Ethernet Receive,Ethernet Transmit,,,,,,,,,," bitfld.long 0x00 16.--19. " MESSAGE_TYPE , Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " SEQUENCE_ID , Sequence ID" rgroup.long 0x3C++0x03 line.long 0x00 "CPSW_CPTS_EVT_HIGH,UPPER 32-BITS OF THE EVENT VALUE" hexmask.long.byte 0x00 0.--7. 1. " DOMAIN , Domain The [[br]]8-bit domain is the value that was contained in an Ethernet transmit or receive time sync packet. [[br]]This field is valid only for Ethernet transmit or receive events." else //CPSW_CPTS_CTRL.INT_TEST== "Allowed" group.long 0x38++0x03 line.long 0x00 "CPSW_CPTS_EVT_MID,MIDDLE 32-BITS OF THE EVENT VALUE" bitfld.long 0x00 24.--28. " PORT_NUMBER , Port Number - indicates the port number of an ethernet event or the hardware push pin number (1 to 4)." ",1,2,3,4,,,,,,,,,,,,,,,,,,,,,,,,,,," bitfld.long 0x00 20.--23. " EVT_TYPE ,Ethernet Transmit Event" "Push Event,Rollover Event,Half Rollover Event,Push Event,Ethernet Receive,Ethernet Transmit,,,,,,,,,," endif width 11. tree.end tree "CPDMA_STATERAM Registers" base ad:0x4A100A00 width 23. group.long 0x00++0x03 line.long 0x00 "CPSW_STATERAM_TX0_HDP,CPDMA_STATERAM TX CHANNEL 0 HEAD DESC POINTER" group.long 0x04++0x03 line.long 0x00 "CPSW_STATERAM_TX1_HDP,CPDMA_STATERAM TX CHANNEL 1 HEAD DESC POINTER" group.long 0x08++0x03 line.long 0x00 "CPSW_STATERAM_TX2_HDP,CPDMA_STATERAM TX CHANNEL 2 HEAD DESC POINTER" group.long 0x0C++0x03 line.long 0x00 "CPSW_STATERAM_TX3_HDP,CPDMA_STATERAM TX CHANNEL 3 HEAD DESC POINTER" group.long 0x10++0x03 line.long 0x00 "CPSW_STATERAM_TX4_HDP,CPDMA_STATERAM TX CHANNEL 4 HEAD DESC POINTER" group.long 0x14++0x03 line.long 0x00 "CPSW_STATERAM_TX5_HDP,CPDMA_STATERAM TX CHANNEL 5 HEAD DESC POINTER" group.long 0x18++0x03 line.long 0x00 "CPSW_STATERAM_TX6_HDP,CPDMA_STATERAM TX CHANNEL 6 HEAD DESC POINTER" group.long 0x1C++0x03 line.long 0x00 "CPSW_STATERAM_TX7_HDP,CPDMA_STATERAM TX CHANNEL 7 HEAD DESC POINTER" group.long 0x20++0x03 line.long 0x00 "CPSW_STATERAM_RX0_HDP,CPDMA_STATERAM RX 0 CHANNEL 0 HEAD DESC POINTER" group.long 0x24++0x03 line.long 0x00 "CPSW_STATERAM_RX1_HDP,CPDMA_STATERAM RX 1 CHANNEL 1 HEAD DESC POINTER" group.long 0x28++0x03 line.long 0x00 "CPSW_STATERAM_RX2_HDP,CPDMA_STATERAM RX 2 CHANNEL 2 HEAD DESC POINTER" group.long 0x2C++0x03 line.long 0x00 "CPSW_STATERAM_RX3_HDP,CPDMA_STATERAM RX 3 CHANNEL 3 HEAD DESC POINTER" group.long 0x30++0x03 line.long 0x00 "CPSW_STATERAM_RX4_HDP,CPDMA_STATERAM RX 4 CHANNEL 4 HEAD DESC POINTER" group.long 0x34++0x03 line.long 0x00 "CPSW_STATERAM_RX5_HDP,CPDMA_STATERAM RX 5 CHANNEL 5 HEAD DESC POINTER" group.long 0x38++0x03 line.long 0x00 "CPSW_STATERAM_RX6_HDP,CPDMA_STATERAM RX 6 CHANNEL 6 HEAD DESC POINTER" group.long 0x3C++0x03 line.long 0x00 "CPSW_STATERAM_RX7_HDP,CPDMA_STATERAM RX 7 CHANNEL 7 HEAD DESC POINTER" group.long 0x40++0x03 line.long 0x00 "CPSW_STATERAM_TX0_CP,CPDMA_STATERAM TX CHANNEL 0 COMPLETION POINTER REGISTER" group.long 0x44++0x03 line.long 0x00 "CPSW_STATERAM_TX1_CP,CPDMA_STATERAM TX CHANNEL 1 COMPLETION POINTER REGISTER" group.long 0x48++0x03 line.long 0x00 "CPSW_STATERAM_TX2_CP,CPDMA_STATERAM TX CHANNEL 2 COMPLETION POINTER REGISTER" group.long 0x4C++0x03 line.long 0x00 "CPSW_STATERAM_TX3_CP,CPDMA_STATERAM TX CHANNEL 3 COMPLETION POINTER REGISTER" group.long 0x50++0x03 line.long 0x00 "CPSW_STATERAM_TX4_CP,CPDMA_STATERAM TX CHANNEL 4 COMPLETION POINTER REGISTER" group.long 0x54++0x03 line.long 0x00 "CPSW_STATERAM_TX5_CP,CPDMA_STATERAM TX CHANNEL 5 COMPLETION POINTER REGISTER" group.long 0x58++0x03 line.long 0x00 "CPSW_STATERAM_TX6_CP,CPDMA_STATERAM TX CHANNEL 6 COMPLETION POINTER REGISTER" group.long 0x5C++0x03 line.long 0x00 "CPSW_STATERAM_TX7_CP,CPDMA_STATERAM TX CHANNEL 7 COMPLETION POINTER REGISTER" group.long 0x60++0x03 line.long 0x00 "CPSW_STATERAM_RX0_CP,CPDMA_STATERAM RX CHANNEL 0 COMPLETION POINTER REGISTER" group.long 0x64++0x03 line.long 0x00 "CPSW_STATERAM_RX1_CP,CPDMA_STATERAM RX CHANNEL 1 COMPLETION POINTER REGISTER" group.long 0x68++0x03 line.long 0x00 "CPSW_STATERAM_RX2_CP,CPDMA_STATERAM RX CHANNEL 2 COMPLETION POINTER REGISTER" group.long 0x6C++0x03 line.long 0x00 "CPSW_STATERAM_RX3_CP,CPDMA_STATERAM RX CHANNEL 3 COMPLETION POINTER REGISTER" group.long 0x70++0x03 line.long 0x00 "CPSW_STATERAM_RX4_CP,CPDMA_STATERAM RX CHANNEL 4 COMPLETION POINTER REGISTER" group.long 0x74++0x03 line.long 0x00 "CPSW_STATERAM_RX5_CP,CPDMA_STATERAM RX CHANNEL 5 COMPLETION POINTER REGISTER" group.long 0x78++0x03 line.long 0x00 "CPSW_STATERAM_RX6_CP,CPDMA_STATERAM RX CHANNEL 6 COMPLETION POINTER REGISTER" group.long 0x7C++0x03 line.long 0x00 "CPSW_STATERAM_RX7_CP,CPDMA_STATERAM RX CHANNEL 7 COMPLETION POINTER REGISTER" width 11. tree.end tree "CPSW_PORT Registers" base ad:0x4A100100 width 21. group.long 0x24C++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP7,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7" bitfld.long 0x00 28.--30. " PRI63 ,Priority 63. A packet TOS of 0d63 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI62 ,Priority 62. A packet TOS of 0d62 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI61 ,Priority 61. A packet TOS of 0d61 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI60 ,Priority 60. A packet TOS of 0d60 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI59 ,Priority 59. A packet TOS of 0d59 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI58 ,Priority 58. A packet TOS of 0d58 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI57 ,Priority 57. A packet TOS of 0d57 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI56 ,Priority 56. A packet TOS of 0d56 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x210++0x03 line.long 0x00 "P2_TX_IN_CTL,CPSW PORT 2 TRANSMIT FIFO CONTROL" bitfld.long 0x00 24.--27. " HOST_BLKS_REM ,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "NORMAL,,RATE_LIMIT," textline " " bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode and blocks to subtract on non rate-limited traffic in rate-limit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue" rgroup.long 0x20C++0x03 line.long 0x00 "P2_BLK_CNT,CPSW PORT 2 FIFO BLOCK USAGE COUNT (READ ONLY)" bitfld.long 0x00 4.--8. " P2_TX_BLK_CNT ,Port 2 Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P2_RX_BLK_CNT ,Port 2 Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP0,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0" bitfld.long 0x00 28.--30. " PRI7 ,Priority 7. A packet TOS of 0d7 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6. A packet TOS of 0d6 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5. A packet TOS of 0d5 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4. A packet TOS of 0d4 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3. A packet TOS of 0d3 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2. A packet TOS of 0d2 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1. A packet TOS of 0d1 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0. A packet TOS of 0d0 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x120++0x03 line.long 0x00 "P1_SA_LO,CPSW CPGMAC_SL1 SOURCE ADDRESS LOW REGISTER" hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_7_0 ,Source Address Lower 8 bits (byte 0)" hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_15_8 ,Source Address bits 15 to 8 (byte 1)" group.long 0x234++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP1,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1" bitfld.long 0x00 28.--30. " PRI15 ,Priority 15. A packet TOS of 0d15 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI14 ,Priority 14. A packet TOS of 0d14 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI13 ,Priority 13. A packet TOS of 0d13 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI12 ,Priority 12. A packet TOS of 0d12 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI11 ,Priority 11. A packet TOS of 0d11 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI10 ,Priority 10. A packet TOS of 0d10 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI9 ,Priority 9. A packet TOS of 0d9 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI8 ,Priority 8. A packet TOS of 0d8 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x4C++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP7,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7" bitfld.long 0x00 28.--30. " PRI63 ,Priority 63. A packet TOS of 0d63 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI62 ,Priority 62. A packet TOS of 0d62 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI61 ,Priority 61. A packet TOS of 0d61 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI60 ,Priority 60. A packet TOS of 0d60 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI59 ,Priority 59. A packet TOS of 0d59 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI58 ,Priority 58. A packet TOS of 0d58 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI57 ,Priority 57. A packet TOS of 0d57 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI56 ,Priority 56. A packet TOS of 0d56 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x08++0x03 line.long 0x00 "P0_MAX_BLKS,CPSW PORT 0 MAXIMUM FIFO BLOCKS REGISTER" bitfld.long 0x00 4.--8. " P0_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" ",,,,,,,,,,,,,,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P0_RX_MAX_BLKS ,Receive FIFO Maximum Blocks " ",,,Min,4,5,Max,,,,,,,,," group.long 0x100++0x03 line.long 0x00 "P1_CONTROL,CPSW PORT 1 CONTROL REGISTER" bitfld.long 0x00 25. " P1_TX_CLKSTOP_EN ,Port 1 Transmit clockstop enable" "Disabled,Enabled" bitfld.long 0x00 24. " P1_PASS_PRI_TAGGED ,Port 1 Pass Priority Tagged" "REPLACED,UNCHANGED" bitfld.long 0x00 21. " P1_VLAN_LTYPE2_EN ,Port 1 VLAN LTYPE 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " P1_VLAN_LTYPE1_EN ,Port 1 VLAN LTYPE 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " P1_DSCP_PRI_EN ,Port 1 DSCP Priority Enable" "Disabled,Enabled" bitfld.long 0x00 15. " P1_TS_107 ,Port 1 Time Sync Destination IP Address 107 enable" "Disabled,Enabled" bitfld.long 0x00 14. " P1_TS_320 ,Port 1 Time Sync Destination Port Number 320 enable" "Disabled,Enabled" bitfld.long 0x00 13. " P1_TS_319 ,Port 1 Time Sync Destination Port Number 319 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " P1_TS_132 ,Port 1 Time Sync Destination IP Address 132 enable" "Disabled,Enabled" bitfld.long 0x00 11. " P1_TS_131 ,Port 1 Time Sync Destination IP Address 131 enable" "Disabled,Enabled" bitfld.long 0x00 10. " P1_TS_130 ,Port 1 Time Sync Destination IP Address 130 enable" "Disabled,Enabled" bitfld.long 0x00 9. " P1_TS_129 ,Port 1 Time Sync Destination IP Address 129 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " P1_TS_TTL_NONZERO ,Port 1 Time Sync Time To Live Non-zero enable" "Zero,Any value" bitfld.long 0x00 7. " P1_TS_UNI_EN ,Port 1 Time Sync Unicast Enable" "Disabled,Enabled" bitfld.long 0x00 6. " P1_TS_ANNEX_F_EN ,Port 1 Time Sync Annex F enable" "Disabled,Enabled" bitfld.long 0x00 5. " P1_TS_ANNEX_E_EN ,Port 1 Time Sync Annex E enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " P1_TS_ANNEX_D_EN ,Port 1 Time Sync Annex D enable" "Disabled,Enabled" bitfld.long 0x00 3. " P1_TS_LTYPE2_EN ,Port 1 Time Sync LTYPE 2 enable" "Disabled,Enabled" bitfld.long 0x00 2. " P1_TS_LTYPE1_EN ,Port 1 Time Sync LTYPE 1 enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1_TS_TX_EN ,Port 1 Time Sync Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " P1_TS_RX_EN ,Port 1 Time Sync Receive Enable" "Disabled,Enabled" group.long 0x218++0x03 line.long 0x00 "P2_TX_PRI_MAP,CPSW PORT 2 TX HEADER PRIORITY TO SWITCH PRI MAPPING REGISTER" bitfld.long 0x00 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue pri." "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue pri." "0,1,2,3" group.long 0x238++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP2,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2" bitfld.long 0x00 28.--30. " PRI23 ,Priority 23. A packet TOS of 0d23 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI22 ,Priority 22. A packet TOS of 0d22 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI21 ,Priority 21. A packet TOS of 0d21 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI20 ,Priority 20. A packet TOS of 0d20 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI19 ,Priority 19. A packet TOS of 0d19 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI18 ,Priority 18. A packet TOS of 0d18 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI17 ,Priority 17. A packet TOS of 0d17 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI16 ,Priority 16. A packet TOS of 0d16 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x224++0x03 line.long 0x00 "P2_SA_HI,CPSW CPGMAC_SL2 SOURCE ADDRESS HIGH REGISTER" hexmask.long.byte 0x00 24.--31. 1. " MACSRCADDR_23_16 ,Source Address bits 23 to 16 (byte 2)" hexmask.long.byte 0x00 16.--23. 1. " MACSRCADDR_31_23 ,Source Address bits 31 to 23 (byte 3)" hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_39_32 ,Source Address bits 39 to 32 (byte 4)" hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_47_40 ,Source Address bits 47 to 40 (byte 5)" group.long 0x220++0x03 line.long 0x00 "P2_SA_LO,CPSW CPGMAC_SL2 SOURCE ADDRESS LOW REGISTER" hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_7_0 ,Source Address Lower 8 bits (byte 0)" hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_15_8 ,Source Address bits 15 to 8 (byte 1)" group.long 0x1C++0x03 line.long 0x00 "P0_CPDMA_TX_PRI_MAP,CPSW CPDMA TX (PORT 0 RX) PKT PRIORITY TO HEADER PRIORITY" bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet pri of 0x7 is mapped (changed) to this header packet pri." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet pri of 0x6 is mapped (changed) to this header packet pri." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet pri of 0x5 is mapped (changed) to this header packet pri." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet pri of 0x4 is mapped (changed) to this header packet pri." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet pri of 0x3 is mapped (changed) to this header packet pri." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet pri of 0x2 is mapped (changed) to this header packet pri." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet pri of 0x1 is mapped (changed) to this header packet pri." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet pri of 0x0 is mapped (changed) to this header packet pri." "0,1,2,3,4,5,6,7" group.long 0x240++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP4,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4" bitfld.long 0x00 28.--30. " PRI39 ,Priority 39. A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI38 ,Priority 38. A packet TOS of 0d38 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI37 ,Priority 37. A packet TOS of 0d37 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI36 ,Priority 36. A packet TOS of 0d36 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI35 ,Priority 35. A packet TOS of 0d35 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI34 ,Priority 34. A packet TOS of 0d34 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI33 ,Priority 33. A packet TOS of 0d33 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI32 ,Priority 32. A packet TOS of 0d32 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" Rgroup.long 0x0C++0x03 line.long 0x00 "P0_BLK_CNT,CPSW PORT 0 FIFO BLOCK USAGE COUNT" bitfld.long 0x00 4.--8. " P0_TX_BLK_CNT ,Port 0 Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P0_RX_BLK_CNT ,Port 0 Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP0,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0" bitfld.long 0x00 28.--30. " PRI7 ,Priority 7. A packet TOS of 0d7 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6. A packet TOS of 0d6 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5. A packet TOS of 0d5 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4. A packet TOS of 0d4 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3. A packet TOS of 0d3 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2. A packet TOS of 0d2 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1. A packet TOS of 0d1 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0. A packet TOS of 0d0 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x10++0x03 line.long 0x00 "P0_TX_IN_CTL,CPSW PORT 0 TRANSMIT FIFO CONTROL" bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "NORMAL,DUALMAC,RATELIMIT," bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue" group.long 0x44++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP5,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5" bitfld.long 0x00 28.--30. " PRI47 ,Priority 47. A packet TOS of 0d47 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI46 ,Priority 46. A packet TOS of 0d46 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI45 ,Priority 45. A packet TOS of 0d45 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI44 ,Priority 44. A packet TOS of 0d44 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI43 ,Priority 43. A packet TOS of 0d43 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI42 ,Priority 42. A packet TOS of 0d42 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI41 ,Priority 41. A packet TOS of 0d41 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI40 ,Priority 40. A packet TOS of 0d40 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x228++0x03 line.long 0x00 "P2_SEND_PERCENT,CPSW PORT 2 TRANSMIT QUEUE SEND PERCENTAGES" hexmask.long.byte 0x00 16.--22. 1. " PRI3_SEND_PERCENT ,Priority 3 Transmit Percentage" hexmask.long.byte 0x00 8.--14. 1. " PRI2_SEND_PERCENT ,Priority 2 Transmit Percentage" hexmask.long.byte 0x00 0.--6. 1. " PRI1_SEND_PERCENT ,Priority 1 Transmit Percentage" group.long 0x14C++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP7,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7" bitfld.long 0x00 28.--30. " PRI63 ,Priority 63. A packet TOS of 0d63 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI62 ,Priority 62. A packet TOS of 0d62 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI61 ,Priority 61. A packet TOS of 0d61 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI60 ,Priority 60. A packet TOS of 0d60 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI59 ,Priority 59. A packet TOS of 0d59 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI58 ,Priority 58. A packet TOS of 0d58 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI57 ,Priority 57. A packet TOS of 0d57 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI56 ,Priority 56. A packet TOS of 0d56 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x34++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP1,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1" bitfld.long 0x00 28.--30. " PRI15 ,Priority 15. A packet TOS of 0d15 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI14 ,Priority 14. A packet TOS of 0d14 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI13 ,Priority 13. A packet TOS of 0d13 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI12 ,Priority 12. A packet TOS of 0d12 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI11 ,Priority 11. A packet TOS of 0d11 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI10 ,Priority 10. A packet TOS of 0d10 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI9 ,Priority 9. A packet TOS of 0d9 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI8 ,Priority 8. A packet TOS of 0d8 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x134++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP1,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1" bitfld.long 0x00 28.--30. " PRI15 ,Priority 15. A packet TOS of 0d15 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI14 ,Priority 14. A packet TOS of 0d14 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI13 ,Priority 13. A packet TOS of 0d13 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI12 ,Priority 12. A packet TOS of 0d12 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI11 ,Priority 11. A packet TOS of 0d11 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI10 ,Priority 10. A packet TOS of 0d10 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI9 ,Priority 9. A packet TOS of 0d9 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI8 ,Priority 8. A packet TOS of 0d8 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x110++0x03 line.long 0x00 "P1_TX_IN_CTL,CPSW PORT 1 TRANSMIT FIFO CONTROL" bitfld.long 0x00 24.--27. " HOST_BLKS_REM ,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO. " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "NORMAL,,RATE_LIMIT," textline " " bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode and blocks to subtract on non rate-limited traffic in rate-limit mode. " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue" group.long 0x40++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP4,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4" bitfld.long 0x00 28.--30. " PRI39 ,Priority 39. A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI38 ,Priority 38. A packet TOS of 0d38 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI37 ,Priority 37. A packet TOS of 0d37 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI36 ,Priority 36. A packet TOS of 0d36 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI35 ,Priority 35. A packet TOS of 0d35 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI34 ,Priority 34. A packet TOS of 0d34 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI33 ,Priority 33. A packet TOS of 0d33 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI32 ,Priority 32. A packet TOS of 0d32 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x21C++0x03 line.long 0x00 "P2_TS_SEQ_MTYPE,CPSW_3GF PORT 2 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE." hexmask.long.byte 0x00 16.--21. 1. " P2_TS_SEQ_ID_OFFSET ,Port 2 Time Sync Sequence ID Offset" bitfld.long 0x00 15. " P2_TS_MSG_TYPE_EN_15 ,Port 2 Time Sync Message Type Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " P2_TS_MSG_TYPE_EN_14 ,Port 2 Time Sync Message Type Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " P2_TS_MSG_TYPE_EN_13 ,Port 2 Time Sync Message Type Enable 13" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " P2_TS_MSG_TYPE_EN_12 ,Port 2 Time Sync Message Type Enable 12" "Disabled,Enabled" bitfld.long 0x00 11. " P2_TS_MSG_TYPE_EN_11 ,Port 2 Time Sync Message Type Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " P2_TS_MSG_TYPE_EN_10 ,Port 2 Time Sync Message Type Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " P2_TS_MSG_TYPE_EN_9 ,Port 2 Time Sync Message Type Enable 9" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " P2_TS_MSG_TYPE_EN_8 ,Port 2 Time Sync Message Type Enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " P2_TS_MSG_TYPE_EN_7 ,Port 2 Time Sync Message Type Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " P2_TS_MSG_TYPE_EN_6 ,Port 2 Time Sync Message Type Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " P2_TS_MSG_TYPE_EN_5 ,Port 2 Time Sync Message Type Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " P2_TS_MSG_TYPE_EN_4 ,Port 2 Time Sync Message Type Enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " P2_TS_MSG_TYPE_EN_3 ,Port 2 Time Sync Message Type Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " P2_TS_MSG_TYPE_EN_2 ,Port 2 Time Sync Message Type Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " P2_TS_MSG_TYPE_EN_1 ,Port 2 Time Sync Message Type Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " P2_TS_MSG_TYPE_EN_0 ,Port 2 Time Sync Message Type Enable 0" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "P0_PORT_VLAN,CPSW PORT 0 VLAN REGISTER" bitfld.long 0x00 13.--15. " PORT_PRI ,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12. " PORT_CFI ,Port CFI bit" "0,1" hexmask.long.word 0x00 0.--11. 1. " PORT_VID ,Port VLAN ID" group.long 0x140++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP4,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4" bitfld.long 0x00 28.--30. " PRI39 ,Priority 39. A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI38 ,Priority 38. A packet TOS of 0d38 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI37 ,Priority 37. A packet TOS of 0d37 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI36 ,Priority 36. A packet TOS of 0d36 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI35 ,Priority 35. A packet TOS of 0d35 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI34 ,Priority 34. A packet TOS of 0d34 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI33 ,Priority 33. A packet TOS of 0d33 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI32 ,Priority 32. A packet TOS of 0d32 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x244++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP5,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5" bitfld.long 0x00 28.--30. " PRI47 ,Priority 47. A packet TOS of 0d47 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI46 ,Priority 46. A packet TOS of 0d46 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI45 ,Priority 45. A packet TOS of 0d45 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI44 ,Priority 44. A packet TOS of 0d44 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI43 ,Priority 43. A packet TOS of 0d43 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI42 ,Priority 42. A packet TOS of 0d42 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI41 ,Priority 41. A packet TOS of 0d41 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI40 ,Priority 40. A packet TOS of 0d40 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x200++0x03 line.long 0x00 "P2_CONTROL,CPSW_3GF PORT 2 CONTROL REGISTER" bitfld.long 0x00 25. " P2_TX_CLKSTOP_EN ,Port 2 Transmit clockstop enable" "Disabled,Enabled" bitfld.long 0x00 24. " P2_PASS_PRI_TAGGED ,Port 2 Pass Priority Tagged" "REPLACED,UNCHANGED" bitfld.long 0x00 21. " P2_VLAN_LTYPE2_EN ,Port 2 VLAN LTYPE 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " P2_VLAN_LTYPE1_EN ,Port 2 VLAN LTYPE 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " P2_DSCP_PRI_EN ,Port 2 DSCP Priority Enable" "Disabled,Enabled" bitfld.long 0x00 15. " P2_TS_107 ,Port 2 Time Sync Destination IP Address 107 enable" "Disabled,Enabled" bitfld.long 0x00 14. " P2_TS_320 ,Port 2 Time Sync Destination Port Number 320 enable" "Disabled,Enabled" bitfld.long 0x00 13. " P2_TS_319 ,Port 2 Time Sync Destination Port Number 319 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " P2_TS_132 ,Port 2 Time Sync Destination IP Address 132 enable" "Disabled,Enabled" bitfld.long 0x00 11. " P2_TS_131 ,Port 2 Time Sync Destination IP Address 131 enable" "Disabled,Enabled" bitfld.long 0x00 10. " P2_TS_130 ,Port 2 Time Sync Destination IP Address 130 enable" "Disabled,Enabled" bitfld.long 0x00 9. " P2_TS_129 ,Port 2 Time Sync Destination IP Address 129 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " P2_TS_TTL_NONZERO ,Port 2 Time Sync Time To Live Non-zero enable" "Zero,Any value" bitfld.long 0x00 7. " P2_TS_UNI_EN ,Port 2 Time Sync Unicast Enable" "Disabled,Enabled" bitfld.long 0x00 6. " P2_TS_ANNEX_F_EN ,Port 2 Time Sync Annex F enable" "Disabled,Enabled" bitfld.long 0x00 5. " P2_TS_ANNEX_E_EN ,Port 2 Time Sync Annex E enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " P2_TS_ANNEX_D_EN ,Port 2 Time Sync Annex D enable" "Disabled,Enabled" bitfld.long 0x00 3. " P2_TS_LTYPE2_EN ,Port 2 Time Sync LTYPE 2 enable" "Disabled,Enabled" bitfld.long 0x00 2. " P2_TS_LTYPE1_EN ,Port 2 Time Sync LTYPE 1 enable" "Disabled,Enabled" bitfld.long 0x00 1. " P2_TS_TX_EN ,Port 2 Time Sync Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " P2_TS_RX_EN ,Port 2 Time Sync Receive Enable" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP5,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5" bitfld.long 0x00 28.--30. " PRI47 ,Priority 47. A packet TOS of 0d47 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI46 ,Priority 46. A packet TOS of 0d46 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI45 ,Priority 45. A packet TOS of 0d45 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI44 ,Priority 44. A packet TOS of 0d44 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI43 ,Priority 43. A packet TOS of 0d43 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI42 ,Priority 42. A packet TOS of 0d42 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI41 ,Priority 41. A packet TOS of 0d41 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI40 ,Priority 40. A packet TOS of 0d40 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "P0_CPDMA_RX_CH_MAP,CPSW CPDMA RX (PORT 0 TX) SWITCH PRIORITY TO DMA CHANNEL" bitfld.long 0x00 28.--30. " P2_PRI3 ,Port 2 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " P2_PRI2 ,Port 2 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " P2_PRI1 ,Port 2 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " P2_PRI0 ,Port 2 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " P1_PRI3 ,Port 1 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " P1_PRI2 ,Port 1 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " P1_PRI1 ,Port 1 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " P1_PRI0 ,Port 1 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" group.long 0x138++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP2,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2" bitfld.long 0x00 28.--30. " PRI23 ,Priority 23. A packet TOS of 0d23 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI22 ,Priority 22. A packet TOS of 0d22 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI21 ,Priority 21. A packet TOS of 0d21 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI20 ,Priority 20. A packet TOS of 0d20 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI19 ,Priority 19. A packet TOS of 0d19 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI18 ,Priority 18. A packet TOS of 0d18 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI17 ,Priority 17. A packet TOS of 0d17 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI16 ,Priority 16. A packet TOS of 0d16 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x108++0x03 line.long 0x00 "P1_MAX_BLKS,CPSW PORT 1 MAXIMUM FIFO BLOCKS REGISTER" bitfld.long 0x00 4.--8. " P1_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" ",,,,,,,,,,,,,,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P1_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" ",,,3,4,5,6,,,,,,,,," group.long 0x13C++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP3,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3" bitfld.long 0x00 28.--30. " PRI31 ,Priority 31. A packet TOS of 0d31 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI30 ,Priority 30. A packet TOS of 0d30 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI29 ,Priority 29. A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI28 ,Priority 28. A packet TOS of 0d28 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI27 ,Priority 27. A packet TOS of 0d27 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI26 ,Priority 26. A packet TOS of 0d26 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI25 ,Priority 25. A packet TOS of 0d25 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI24 ,Priority 24. A packet TOS of 0d24 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x118++0x03 line.long 0x00 "P1_TX_PRI_MAP,CPSW PORT 1 TX HEADER PRIORITY TO SWITCH PRI MAPPING REGISTER" bitfld.long 0x00 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue pri." "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue pri." "0,1,2,3" group.long 0x23C++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP3,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3" bitfld.long 0x00 28.--30. " PRI31 ,Priority 31. A packet TOS of 0d31 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI30 ,Priority 30. A packet TOS of 0d30 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI29 ,Priority 29. A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI28 ,Priority 28. A packet TOS of 0d28 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI27 ,Priority 27. A packet TOS of 0d27 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI26 ,Priority 26. A packet TOS of 0d26 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI25 ,Priority 25. A packet TOS of 0d25 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI24 ,Priority 24. A packet TOS of 0d24 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x148++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP6,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6" bitfld.long 0x00 28.--30. " PRI55 ,Priority 55. A packet TOS of 0d55 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI54 ,Priority 54. A packet TOS of 0d54 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI53 ,Priority 53. A packet TOS of 0d53 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI52 ,Priority 52. A packet TOS of 0d52 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI51 ,Priority 51. A packet TOS of 0d51 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI50 ,Priority 50. A packet TOS of 0d50 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI49 ,Priority 49. A packet TOS of 0d49 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI48 ,Priority 48. A packet TOS of 0d48 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x124++0x03 line.long 0x00 "P1_SA_HI,CPSW CPGMAC_SL1 SOURCE ADDRESS HIGH REGISTER" hexmask.long.byte 0x00 24.--31. 1. " MACSRCADDR_23_16 ,Source Address bits 23 to 16 (byte 2)" hexmask.long.byte 0x00 16.--23. 1. " MACSRCADDR_31_24 ,Source Address bits 31 to 24 (byte 3)" hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_39_32 ,Source Address bits 39 to 32 (byte 4)" hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_47_40 ,Source Address bits 47 to 40 (byte 5)" group.long 0x248++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP6,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6" bitfld.long 0x00 28.--30. " PRI55 ,Priority 55. A packet TOS of 0d55 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI54 ,Priority 54. A packet TOS of 0d54 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI53 ,Priority 53. A packet TOS of 0d53 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI52 ,Priority 52. A packet TOS of 0d52 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI51 ,Priority 51. A packet TOS of 0d51 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI50 ,Priority 50. A packet TOS of 0d50 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI49 ,Priority 49. A packet TOS of 0d49 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI48 ,Priority 48. A packet TOS of 0d48 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x208++0x03 line.long 0x00 "P2_MAX_BLKS,CPSW PORT 2 MAXIMUM FIFO BLOCKS REGISTER" bitfld.long 0x00 4.--8. " P2_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" ",,,,,,,,,,,,,,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P2_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" ",,,3,4,5,6,,,,,,,,," group.long 0x3C++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP3,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3" bitfld.long 0x00 28.--30. " PRI31 ,Priority 31. A packet TOS of 0d31 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI30 ,Priority 30. A packet TOS of 0d30 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI29 ,Priority 29. A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI28 ,Priority 28. A packet TOS of 0d28 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI27 ,Priority 27. A packet TOS of 0d27 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI26 ,Priority 26. A packet TOS of 0d26 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI25 ,Priority 25. A packet TOS of 0d25 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI24 ,Priority 24. A packet TOS of 0d24 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x18++0x03 line.long 0x00 "P0_TX_PRI_MAP,CPSW PORT 0 TX HEADER PRI TO SWITCH PRI MAPPING REGISTER" bitfld.long 0x00 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue pri." "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue pri." "0,1,2,3" bitfld.long 0x00 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue pri." "0,1,2,3" group.long 0x11C++0x03 line.long 0x00 "P1_TS_SEQ_MTYPE,CPSW PORT 1 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE." hexmask.long.byte 0x00 16.--21. 1. " P1_TS_SEQ_ID_OFFSET ,Port 1 Time Sync Sequence ID Offset" bitfld.long 0x00 15. " P1_TS_MSG_TYPE_EN_15 ,Port 1 Time Sync Message Type Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " P1_TS_MSG_TYPE_EN_14 ,Port 1 Time Sync Message Type Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " P1_TS_MSG_TYPE_EN_13 ,Port 1 Time Sync Message Type Enable 13" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " P1_TS_MSG_TYPE_EN_12 ,Port 1 Time Sync Message Type Enable 12" "Disabled,Enabled" bitfld.long 0x00 11. " P1_TS_MSG_TYPE_EN_11 ,Port 1 Time Sync Message Type Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " P1_TS_MSG_TYPE_EN_10 ,Port 1 Time Sync Message Type Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " P1_TS_MSG_TYPE_EN_9 ,Port 1 Time Sync Message Type Enable 9" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " P1_TS_MSG_TYPE_EN_8 ,Port 1 Time Sync Message Type Enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " P1_TS_MSG_TYPE_EN_7 ,Port 1 Time Sync Message Type Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " P1_TS_MSG_TYPE_EN_6 ,Port 1 Time Sync Message Type Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " P1_TS_MSG_TYPE_EN_5 ,Port 1 Time Sync Message Type Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " P1_TS_MSG_TYPE_EN_4 ,Port 1 Time Sync Message Type Enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " P1_TS_MSG_TYPE_EN_3 ,Port 1 Time Sync Message Type Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " P1_TS_MSG_TYPE_EN_2 ,Port 1 Time Sync Message Type Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " P1_TS_MSG_TYPE_EN_1 ,Port 1 Time Sync Message Type Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " P1_TS_MSG_TYPE_EN_0 ,Port 1 Time Sync Message Type Enable 0" "Disabled,Enabled" group.long 0x48++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP6,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6" bitfld.long 0x00 28.--30. " PRI55 ,Priority 55. A packet TOS of 0d55 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI54 ,Priority 54. A packet TOS of 0d54 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI53 ,Priority 53. A packet TOS of 0d53 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI52 ,Priority 52. A packet TOS of 0d52 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI51 ,Priority 51. A packet TOS of 0d51 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI50 ,Priority 50. A packet TOS of 0d50 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI49 ,Priority 49. A packet TOS of 0d49 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI48 ,Priority 48. A packet TOS of 0d48 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x230++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP0,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0" bitfld.long 0x00 28.--30. " PRI7 ,Priority 7. A packet TOS of 0d7 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6. A packet TOS of 0d6 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5. A packet TOS of 0d5 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4. A packet TOS of 0d4 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3. A packet TOS of 0d3 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2. A packet TOS of 0d2 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1. A packet TOS of 0d1 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0. A packet TOS of 0d0 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.long 0x00++0x03 line.long 0x00 "P0_CONTROL,CPSW PORT 0 CONTROL REGISTER" bitfld.long 0x00 28.--30. " P0_DLR_CPDMA_CH ,Port 0 DLR CPDMA Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. " P0_PASS_PRI_TAGGED ,Port 0 Pass Priority Tagged" "REPLACED,UNCHANGED" bitfld.long 0x00 21. " P0_VLAN_LTYPE2_EN ,Port 0 VLAN LTYPE 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " P0_VLAN_LTYPE1_EN ,Port 0 VLAN LTYPE 1 enable" "Disabled,Enabled" bitfld.long 0x00 16. " P0_DSCP_PRI_EN ,Port 0 DSCP Priority Enable" "Disabled,Enabled" group.long 0x128++0x03 line.long 0x00 "P1_SEND_PERCENT,CPSW PORT 1 TRANSMIT QUEUE SEND PERCENTAGES" hexmask.long.byte 0x00 16.--22. 1. " PRI3_SEND_PERCENT ,Priority 3 Transmit Percentage" hexmask.long.byte 0x00 8.--14. 1. " PRI2_SEND_PERCENT ,Priority 2 Transmit Percentage" hexmask.long.byte 0x00 0.--6. 1. " PRI1_SEND_PERCENT ,Priority 1 Transmit Percentage" rgroup.long 0x10C++0x03 line.long 0x00 "P1_BLK_CNT,CPSW PORT 1 FIFO BLOCK USAGE COUNT" bitfld.long 0x00 4.--8. " P1_TX_BLK_CNT ,Port 1 Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P1_RX_BLK_CNT ,Port 1 Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP2,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2" bitfld.long 0x00 28.--30. " PRI23 ,Priority 23. A packet TOS of 0d23 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI22 ,Priority 22. A packet TOS of 0d22 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI21 ,Priority 21. A packet TOS of 0d21 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI20 ,Priority 20. A packet TOS of 0d20 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI19 ,Priority 19. A packet TOS of 0d19 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI18 ,Priority 18. A packet TOS of 0d18 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI17 ,Priority 17. A packet TOS of 0d17 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI16 ,Priority 16. A packet TOS of 0d16 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" group.word 0x214++0x01 line.word 0x00 "P2_PORT_VLAN,CPSW PORT 2 VLAN REGISTER" bitfld.word 0x00 13.--15. " PORT_PRI ,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.word 0x00 12. " PORT_CFI ,Port CFI bit" "0,1" hexmask.word 0x00 0.--11. 1. " PORT_VID ,Port VLAN ID" group.long 0x114++0x03 line.long 0x00 "P1_PORT_VLAN,CPSW PORT 1 VLAN REGISTER" bitfld.long 0x00 13.--15. " PORT_PRI ,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12. " PORT_CFI ,Port CFI bit" "0,1" hexmask.long.word 0x00 0.--11. 1. " PORT_VID ,Port VLAN ID" group.long 0x104++0x03 line.long 0x00 "P1_TS_CTL2,CPSW_PORT_P1_TS_CTL2" hexmask.long.byte 0x00 16.--21. 1. " P1_DOMAIN_OFFSET ,Domain offset value" hexmask.long.word 0x00 0.--15. 1. " P1_TS_MCAST_TYPE_EN ,Multicast Type Enable" group.long 0x204++0x03 line.long 0x00 "P2_TS_CTL2,CPSW_PORT_P2_TS_CTL2" hexmask.long.byte 0x00 16.--21. 1. " P2_DOMAIN_OFFSET ,Domain offset value" hexmask.long.word 0x00 0.--15. 1. " P2_TS_MCAST_TYPE_EN ,Multicast Type Enable" width 11. tree.end tree "CPSW_SL Registers" tree "PORT 1" base ad:0x4A100D80 width 20. rgroup.long 0x00++0x03 line.long 0x00 "CPSW_SL_IDVER,CPGMAC_SL ID/VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " IDENT , Rx Identification Value" bitfld.long 0x00 11.--15. " Z , Rx Z value (X.Y.Z)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X , Rx X value (major)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " Y , Rx Y value (minor)" group.long 0x04++0x03 line.long 0x00 "CPSW_SL_MACCTRL,CPGMAC_SL MAC CONTROL REGISTER" bitfld.long 0x00 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable" "Disabled,Enabled" bitfld.long 0x00 23. " RX_CSF_EN ,RX Copy Short Frames Enable" "Disabled,Enabled" bitfld.long 0x00 22. " RX_CEF_EN ,RX Copy Error Frames Enable" "Disabled,Enabled" bitfld.long 0x00 21. " TX_SHORT_GAP_LIM_EN , Transmit Short Gap Limit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXT_EN , Control Enable" "Disabled,Enabled" bitfld.long 0x00 17. " GIG_FORCE , Gigabit Mode Force" "Mode on,Mode off" bitfld.long 0x00 16. " IFCTL_B ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps" bitfld.long 0x00 15. " IFCTL_A ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps" textline " " bitfld.long 0x00 12. " CRS_FLOW_EN ,Carrier Sense Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 11. " CMD_IDLE ,Command Idle" "Not commanded,Comanded" bitfld.long 0x00 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable" "Disabled,Enabled" bitfld.long 0x00 7. " GIG , Gigabit Mode(full duplex only)" "10/100 mode,Gigabit mode" textline " " bitfld.long 0x00 6. " TX_PACE ,Transmit Pacing Enable" "Disabled,Enabled" bitfld.long 0x00 5. " GMII_EN ,GMII Enable" "Disabled,Enabled" bitfld.long 0x00 4. " TX_FLOW_EN ,Transmit Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 3. " RX_FLOW_EN ,Receive Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " MTEST , Manufacturing Test mode" "Mode off,Mode on" bitfld.long 0x00 1. " LOOPBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 0. " FULLDUPLEX ,Full duplex mode" "Half duplex,Full duplex" rgroup.long 0x08++0x03 line.long 0x00 "CPSW_SL_MACSTS,CPGMAC_SL MAC STATUS REGISTER" bitfld.long 0x00 31. " en_2_0x1 ,CPGMAC_SL IDLE" "Not idle,Idle" bitfld.long 0x00 4. " EXT_GIG , External GIG" "0,1" bitfld.long 0x00 3. " EXT_FULLDUPLEX , External Fullduplex" "0,1" textline " " bitfld.long 0x00 1. " RX_FLOW_ACT , Receive Flow Control Active" "Not asserted,Asserted" bitfld.long 0x00 0. " TX_FLOW_ACT , Transmit Flow Control Active" "Not asserted,Asserted" group.long 0x0C++0x03 line.long 0x00 "CPSW_SL_SOFT_RESET,CPGMAC_SL SOFT RESET REGISTER" bitfld.long 0x00 0. " SOFT_RESET , Software reset" "Not reset,Reset" group.long 0x10++0x03 line.long 0x00 "CPSW_SL_RX_MAXLEN,CPGMAC_SL RX MAXIMUM LENGTH REGISTER" hexmask.long.word 0x00 0.--13. 1. " RX_MAXLEN , RX Maximum Frame Length" group.long 0x14++0x03 line.long 0x00 "CPSW_SL_BOFFTEST,CPGMAC_SL BACKOFF TEST REGISTER" bitfld.long 0x00 26.--30. " PACEVAL , Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " RNDNUM , Backoff Random Number Generator" rbitfld.long 0x00 12.--15. " COLL_COUNT , Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. " TX_BACKOFF , Backoff Count" rgroup.long 0x18++0x03 line.long 0x00 "CPSW_SL_RX_PAUSE,CPGMAC_SL RECEIVE PAUSE TIMER REGISTER" hexmask.long.word 0x00 0.--15. 1. " RX_PAUSETIMER , RX Pause Timer Value" group.long 0x1C++0x03 line.long 0x00 "CPSW_SL_TX_PAUSE,CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER" hexmask.long.word 0x00 0.--15. 1. " TX_PAUSETIMER , TX Pause Timer Value" group.long 0x20++0x03 line.long 0x00 "CPSW_SL_EMCTRL,CPGMAC_SL EMULATION CONTROL REGISTER" bitfld.long 0x00 1. " SOFT , Emulation Soft Bit" "0,1" bitfld.long 0x00 0. " FREE , Emulation Free Bit" "0,1" group.long 0x24++0x03 line.long 0x00 "CPSW_SL_RX_PRI_MAP,CPGMAC_SL RX PKT PRIORITY TO HEADER PRIORITY MAPPING REGISTER" bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet priority of 0x7 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet priority of 0x6 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet priority of 0x5 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet priority of 0x4 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet priority of 0x3 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet priority of 0x2 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet priority of 0x1 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet priority of 0x0 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" group.long 0x28++0x03 line.long 0x00 "CPSW_SL_TX_GAP,TRANSMIT INTER-PACKET GAP REGISTER" hexmask.long.word 0x00 0.--8. 1. " TX_GAP , Transmit Inter-Packet Gap" width 11. tree.end tree "PORT 2" base ad:0x4A100DC0 width 20. rgroup.long 0x00++0x03 line.long 0x00 "CPSW_SL_IDVER,CPGMAC_SL ID/VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " IDENT , Rx Identification Value" bitfld.long 0x00 11.--15. " Z , Rx Z value (X.Y.Z)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X , Rx X value (major)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " Y , Rx Y value (minor)" group.long 0x04++0x03 line.long 0x00 "CPSW_SL_MACCTRL,CPGMAC_SL MAC CONTROL REGISTER" bitfld.long 0x00 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable" "Disabled,Enabled" bitfld.long 0x00 23. " RX_CSF_EN ,RX Copy Short Frames Enable" "Disabled,Enabled" bitfld.long 0x00 22. " RX_CEF_EN ,RX Copy Error Frames Enable" "Disabled,Enabled" bitfld.long 0x00 21. " TX_SHORT_GAP_LIM_EN , Transmit Short Gap Limit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXT_EN , Control Enable" "Disabled,Enabled" bitfld.long 0x00 17. " GIG_FORCE , Gigabit Mode Force" "Mode on,Mode off" bitfld.long 0x00 16. " IFCTL_B ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps" bitfld.long 0x00 15. " IFCTL_A ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps" textline " " bitfld.long 0x00 12. " CRS_FLOW_EN ,Carrier Sense Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 11. " CMD_IDLE ,Command Idle" "Not commanded,Comanded" bitfld.long 0x00 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable" "Disabled,Enabled" bitfld.long 0x00 7. " GIG , Gigabit Mode(full duplex only)" "10/100 mode,Gigabit mode" textline " " bitfld.long 0x00 6. " TX_PACE ,Transmit Pacing Enable" "Disabled,Enabled" bitfld.long 0x00 5. " GMII_EN ,GMII Enable" "Disabled,Enabled" bitfld.long 0x00 4. " TX_FLOW_EN ,Transmit Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 3. " RX_FLOW_EN ,Receive Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " MTEST , Manufacturing Test mode" "Mode off,Mode on" bitfld.long 0x00 1. " LOOPBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 0. " FULLDUPLEX ,Full duplex mode" "Half duplex,Full duplex" rgroup.long 0x08++0x03 line.long 0x00 "CPSW_SL_MACSTS,CPGMAC_SL MAC STATUS REGISTER" bitfld.long 0x00 31. " en_2_0x1 ,CPGMAC_SL IDLE" "Not idle,Idle" bitfld.long 0x00 4. " EXT_GIG , External GIG" "0,1" bitfld.long 0x00 3. " EXT_FULLDUPLEX , External Fullduplex" "0,1" textline " " bitfld.long 0x00 1. " RX_FLOW_ACT , Receive Flow Control Active" "Not asserted,Asserted" bitfld.long 0x00 0. " TX_FLOW_ACT , Transmit Flow Control Active" "Not asserted,Asserted" group.long 0x0C++0x03 line.long 0x00 "CPSW_SL_SOFT_RESET,CPGMAC_SL SOFT RESET REGISTER" bitfld.long 0x00 0. " SOFT_RESET , Software reset" "Not reset,Reset" group.long 0x10++0x03 line.long 0x00 "CPSW_SL_RX_MAXLEN,CPGMAC_SL RX MAXIMUM LENGTH REGISTER" hexmask.long.word 0x00 0.--13. 1. " RX_MAXLEN , RX Maximum Frame Length" group.long 0x14++0x03 line.long 0x00 "CPSW_SL_BOFFTEST,CPGMAC_SL BACKOFF TEST REGISTER" bitfld.long 0x00 26.--30. " PACEVAL , Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " RNDNUM , Backoff Random Number Generator" rbitfld.long 0x00 12.--15. " COLL_COUNT , Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. " TX_BACKOFF , Backoff Count" rgroup.long 0x18++0x03 line.long 0x00 "CPSW_SL_RX_PAUSE,CPGMAC_SL RECEIVE PAUSE TIMER REGISTER" hexmask.long.word 0x00 0.--15. 1. " RX_PAUSETIMER , RX Pause Timer Value" group.long 0x1C++0x03 line.long 0x00 "CPSW_SL_TX_PAUSE,CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER" hexmask.long.word 0x00 0.--15. 1. " TX_PAUSETIMER , TX Pause Timer Value" group.long 0x20++0x03 line.long 0x00 "CPSW_SL_EMCTRL,CPGMAC_SL EMULATION CONTROL REGISTER" bitfld.long 0x00 1. " SOFT , Emulation Soft Bit" "0,1" bitfld.long 0x00 0. " FREE , Emulation Free Bit" "0,1" group.long 0x24++0x03 line.long 0x00 "CPSW_SL_RX_PRI_MAP,CPGMAC_SL RX PKT PRIORITY TO HEADER PRIORITY MAPPING REGISTER" bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet priority of 0x7 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet priority of 0x6 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet priority of 0x5 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet priority of 0x4 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet priority of 0x3 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet priority of 0x2 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet priority of 0x1 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet priority of 0x0 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" group.long 0x28++0x03 line.long 0x00 "CPSW_SL_TX_GAP,TRANSMIT INTER-PACKET GAP REGISTER" hexmask.long.word 0x00 0.--8. 1. " TX_GAP , Transmit Inter-Packet Gap" width 11. tree.end tree.end tree "CPSW_SS Registers" base ad:0x4A100000 width 22. rgroup.long 0x00++0x03 line.long 0x00 "CPSW_SS_ID_VER,ID VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " CPSW_3G_IDENT , 3G Identification Value" bitfld.long 0x00 11.--15. " CPSW_3G_RTL_VER , 3G RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " CPSW_3G_MAJ_VER , 3G Major Version Value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " CPSW_3G_MINOR_VER , 3G Minor Version Value" group.long 0x04++0x03 line.long 0x00 "CPSW_SS_CTRL,SWITCH CONTROL REGISTER" bitfld.long 0x00 3. " DLR_EN ,DLR enable" "Disabled,Enabled" bitfld.long 0x00 2. " RX_VLAN_ENCAP ,Port 0 VLAN Encapsulation" "Not encapsulated,Encapsulated" bitfld.long 0x00 1. " VLAN_AWARE ,VLAN Aware Mode" "Unaware mode,Aware mode" bitfld.long 0x00 0. " FIFO_LOOPBACK ,FIFO Loopback Mode" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "CPSW_SS_SOFT_RESET,SOFT RESET REGISTER" bitfld.long 0x00 0. " SOFT_RESET , Software reset" "Not reset,Reset" group.long 0x0C++0x03 line.long 0x00 "CPSW_SS_STAT_PORT_EN,STATISTICS PORT ENABLE REGISTER" bitfld.long 0x00 2. " P2_STAT_EN ,Port 2 Statistics Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1_STAT_EN , Port 1 Statistics Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0_STAT_EN ,Port 0 Statistics Enable" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "CPSW_SS_PTYPE,TRANSMIT PRIORITY TYPE REGISTER" bitfld.long 0x00 21. " P2_PRI3_SHAPE_EN , Port 2 Queue Priority 3 Transmit Shape Enable" "Disabled,Enabled" bitfld.long 0x00 20. " P2_PRI2_SHAPE_EN , Port 2 Queue Priority 2 Transmit Shape Enable" "Disabled,Enabled" bitfld.long 0x00 19. " P2_PRI1_SHAPE_EN , Port 2 Queue Priority 1 Transmit Shape Enable" "Disabled,Enabled" bitfld.long 0x00 18. " P1_PRI3_SHAPE_EN , Port 1 Queue Priority 3 Transmit Shape Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " P1_PRI2_SHAPE_EN , Port 1 Queue Priority 2 Transmit Shape Enable" "Disabled,Enabled" bitfld.long 0x00 16. " P1_PRI1_SHAPE_EN , Port 1 Queue Priority 1 Transmit Shape Enable" "Disabled,Enabled" bitfld.long 0x00 10. " P2_PTYPE_ESC ,Port 2 Priority Type Escalate" "Fixed,Not queue" bitfld.long 0x00 9. " P1_PTYPE_ESC ,Port 1 Priority Type Escalate" "Fixed,Not queue" textline " " bitfld.long 0x00 8. " P0_PTYPE_ESC ,Port 0 Priority Type Escalate" "Fixed,Not queue" bitfld.long 0x00 0.--4. " ESC_PRI_LD_VAL , Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14++0x03 line.long 0x00 "CPSW_SS_SOFT_IDLE,SOFTWARE IDLE" bitfld.long 0x00 0. " SOFT_IDLE , Software Idle" "Forwarding,Stop forwarding" group.long 0x18++0x03 line.long 0x00 "CPSW_SS_THRU_RATE,THROUGHPUT RATE" bitfld.long 0x00 12.--15. " SL_RX_THRU_RATE , CPGMAC_SL Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CPDMA_THRU_RATE , CPDMA Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "CPSW_SS_GAP_THRESH,CPGMAC_SL SHORT GAP THRESHOLD" bitfld.long 0x00 0.--4. " GAP_THRESH , CPGMAC_SL Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20++0x03 line.long 0x00 "CPSW_SS_TX_START_WDS,TRANSMIT START WORDS" hexmask.long.word 0x00 0.--10. 1. " TX_START_WDS , FIFO Packet Transmit (egress) Start Words" group.word 0x24++0x01 line.word 0x00 "CPSW_SS_FLOW_CTRL,FLOW CONTROL" bitfld.word 0x00 2. " P2_FLOW_EN , Port 2 Receive flow control enable" "Disabled,Enabled" bitfld.word 0x00 1. " P1_FLOW_EN , Port 1 Receive flow control enable" "Disabled,Enabled" bitfld.word 0x00 0. " P0_FLOW_EN , Port 0 Receive flow control enable" "Disabled,Enabled" group.long 0x28++0x03 line.long 0x00 "CPSW_SS_VLAN_LTYPE,LTYPE1 AND LTYPE 2 REGISTER" hexmask.long.word 0x00 16.--31. 1. " VLAN_LTYPE2 , Time Sync VLAN LTYPE2" hexmask.long.word 0x00 0.--15. 1. " VLAN_LTYPE1 , Time Sync VLAN LTYPE1" group.long 0x2C++0x03 line.long 0x00 "CPSW_SS_TS_LTYPE,VLAN_LTYPE1 AND VLAN_LTYPE2 REGISTER" hexmask.long.word 0x00 16.--31. 1. " TS_LTYPE2 , Time Sync LTYPE2" hexmask.long.word 0x00 0.--15. 1. " TS_LTYPE1 , Time Sync LTYPE1" group.word 0x30++0x01 line.word 0x00 "CPSW_SS_DLR_LTYPE,DLR LTYPE REGISTER" group.long 0x34++0x03 line.long 0x00 "CPSW_SS_STS," bitfld.long 0x00 22. " P0_FIF2_EMPTY ,The port 2 transmit FIFO is empty" "Not empty,Empty" bitfld.long 0x00 21. " P0_FIF1_EMPTY ,The port 1 transmit FIFO is empty" "Not empty,Empty" bitfld.long 0x00 20. " P0_FIFO_EMPTY ,The port 2 transmit FIFO is empty" "Not empty,Empty" width 11. tree.end tree "CPSW_WR Registers" base ad:0x4A101200 width 27. rgroup.long 0x00++0x03 line.long 0x00 "CPSW_WR_IDVER,SUBSYSTEM ID VERSION REGISTER" bitfld.long 0x00 30.--31. " SCHEME ,Scheme value" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNCTION ,Function value" bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor version" group.long 0x04++0x03 line.long 0x00 "CPSW_WR_SOFT_RESET,SUBSYSTEM SOFT RESET REGISTER" bitfld.long 0x00 0. " SOFT_RESET , Software reset" "Not reset,Reset" group.long 0x08++0x03 line.long 0x00 "CPSW_WR_CTRL,SUBSYSTEM CONTROL REGISTER" bitfld.long 0x00 2.--3. " MMR_STDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,2,3" bitfld.long 0x00 0.--1. " MMR_IDLEMODE ,Configuration of the local initiator state management mode" "Force-idle,No-idle,," group.long 0x0C++0x03 line.long 0x00 "CPSW_WR_INT_CTRL,SUBSYSTEM INTERRUPT CONTROL" bitfld.long 0x00 31. " INT_TEST , Interrupt Test" "0,1" hexmask.long.byte 0x00 16.--21. 1. " INT_PACE_EN , ARRAY(0x1b8eec0)" hexmask.long.word 0x00 0.--11. 1. " INT_PRESCALE , Interrupt Counter Prescaler" group.long 0x10++0x03 line.long 0x00 "CPSW_WR_C0_RX_THRESH_EN,SUBSYSTEM CORE 0 RECEIVE THRESHOLD INT ENABLE REGISTER" bitfld.long 0x00 7. " C0_RX_THRESH_EN_7 , Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C0_RX_THRESH_EN_6 , Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C0_RX_THRESH_EN_5 , Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 4. " C0_RX_THRESH_EN_4 , Core 0 Receive Threshold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " C0_RX_THRESH_EN_3 , Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C0_RX_THRESH_EN_2 , Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 1. " C0_RX_THRESH_EN_1 , Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C0_RX_THRESH_EN_0 , Core 0 Receive Threshold Enable" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "CPSW_WR_C0_RX_EN,SUBSYSTEM CORE 0 RECEIVE INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C0_RX_EN_7 , Core 0 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C0_RX_EN_6 , Core 0 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C0_RX_EN_5 , Core 0 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 4. " C0_RX_EN_4 , Core 0 Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " C0_RX_EN_3 , Core 0 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C0_RX_EN_2 , Core 0 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " C0_RX_EN_1 , Core 0 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C0_RX_EN_0 , Core 0 Receive Enable" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "CPSW_WR_C0_TX_EN,SUBSYSTEM CORE 0 TRANSMIT INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C0_TX_EN_7 , Core 0 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C0_TX_EN_6 , Core 0 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C0_TX_EN_5 , Core 0 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 4. " C0_TX_EN_4 , Core 0 Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " C0_TX_EN_3 , Core 0 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C0_TX_EN_2 , Core 0 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 1. " C0_TX_EN_1 , Core 0 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C0_TX_EN_0 , Core 0 Transmit Enable" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "CPSW_WR_C0_MISC_EN,SUBSYSTEM CORE 0 MISC INTERRUPT ENABLE REGISTER" bitfld.long 0x00 4. " C0_MISC_EN_4 , Core 0 Misc Enable(evnt_pend)" "Disabled,Enabled" bitfld.long 0x00 3. " C0_MISC_EN_3 , Core 0 Misc Enable(stat_pend)" "Disabled,Enabled" bitfld.long 0x00 2. " C0_MISC_EN_2 , Core 0 Misc Enable(host_pend)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C0_MISC_EN_1 , Core 0 Misc Enable(mdio_linkint)" "Disabled,Enabled" bitfld.long 0x00 0. " C0_MISC_EN_0 , Core 0 Misc Enable(mdio_userint)" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "CPSW_WR_C1_RX_THRESH_EN,SUBSYSTEM CORE 1 RECEIVE THRESHOLD INT ENABLE REGISTER" bitfld.long 0x00 7. " C1_RX_THRESH_EN_7 , Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C1_RX_THRESH_EN_6 , Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C1_RX_THRESH_EN_5 , Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 4. " C1_RX_THRESH_EN_4 , Core 1 Receive Threshold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " C1_RX_THRESH_EN_3 , Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C1_RX_THRESH_EN_2 , Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 1. " C1_RX_THRESH_EN_1 , Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C1_RX_THRESH_EN_0 , Core 1 Receive Threshold Enable" "Disabled,Enabled" group.long 0x24++0x03 line.long 0x00 "CPSW_WR_C1_RX_EN,SUBSYSTEM CORE 1 RECEIVE INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C1_RX_EN_7 , Core 1 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C1_RX_EN_6 , Core 1 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C1_RX_EN_5 , Core 1 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 4. " C1_RX_EN_4 , Core 1 Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " C1_RX_EN_3 , Core 1 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C1_RX_EN_2 , Core 1 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " C1_RX_EN_1 , Core 1 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C1_RX_EN_0 , Core 1 Receive Enable" "Disabled,Enabled" group.long 0x28++0x03 line.long 0x00 "CPSW_WR_C1_TX_EN,SUBSYSTEM CORE 1 TRANSMIT INTERRUPT ENABLE REGISTER" bitfld.long 0x00 6. " C1_TX_EN_7 , Core 1 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C1_TX_EN_6 , Core 1 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C1_TX_EN_5 , Core 1 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 4. " C1_TX_EN_4 , Core 1 Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " C1_TX_EN_3 , Core 1 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C1_TX_EN_2 , Core 1 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 1. " C1_TX_EN_1 , Core 1 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C1_TX_EN_0 , Core 1 Transmit Enable" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "CPSW_WR_C1_MISC_EN,SUBSYSTEM CORE 1 MISC INTERRUPT ENABLE REGISTER" bitfld.long 0x00 4. " C1_MISC_EN_4 , Core 1 Misc Enable(evnt_pend)" "Disabled,Enabled" bitfld.long 0x00 3. " C1_MISC_EN_3 , Core 1 Misc Enable(stat_pend)" "Disabled,Enabled" bitfld.long 0x00 2. " C1_MISC_EN_2 , Core 1 Misc Enable(host_pend)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C1_MISC_EN_1 , Core 1 Misc Enable(mdio_linkint)" "Disabled,Enabled" bitfld.long 0x00 0. " C1_MISC_EN_0 , Core 1 Misc Enable(mdio_userint)" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "CPSW_WR_C2_RX_THRESH_EN,SUBSYSTEM CORE 2 RECEIVE THRESHOLD INT ENABLE REGISTER" bitfld.long 0x00 7. " C2_RX_THRESH_EN_7 , Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C2_RX_THRESH_EN_6 , Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C2_RX_THRESH_EN_5 , Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 4. " C2_RX_THRESH_EN_4 , Core 2 Receive Threshold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " C2_RX_THRESH_EN_3 , Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C2_RX_THRESH_EN_2 , Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 1. " C2_RX_THRESH_EN_1 , Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C2_RX_THRESH_EN_0 , Core 2 Receive Threshold Enable" "Disabled,Enabled" group.long 0x34++0x03 line.long 0x00 "CPSW_WR_C2_RX_EN,SUBSYSTEM CORE 2 RECEIVE INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C2_RX_EN_7 , Core 2 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C2_RX_EN_6 , Core 2 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C2_RX_EN_5 , Core 2 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 4. " C2_RX_EN_4 , Core 2 Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " C2_RX_EN_3 , Core 2 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C2_RX_EN_2 , Core 2 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 1. " C2_RX_EN_1 , Core 2 Receive Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C2_RX_EN_0 , Core 2 Receive Enable" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "CPSW_WR_C2_TX_EN,SUBSYSTEM CORE 2 TRANSMIT INTERRUPT ENABLE REGISTER" bitfld.long 0x00 6. " C2_TX_EN_7 , Core 2 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C2_TX_EN_6 , Core 2 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C2_TX_EN_5 , Core 2 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 4. " C2_TX_EN_4 , Core 2 Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " C2_TX_EN_3 , Core 2 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C2_TX_EN_2 , Core 2 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 1. " C2_TX_EN_1 , Core 2 Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C2_TX_EN_0 , Core 2 Transmit Enable" "Disabled,Enabled" group.long 0x3C++0x03 line.long 0x00 "CPSW_WR_C2_MISC_EN,SUBSYSTEM CORE 2 MISC INTERRUPT ENABLE REGISTER" bitfld.long 0x00 4. " C2_MISC_EN_4 , Core 2 Misc Enable(evnt_pend)" "Disabled,Enabled" bitfld.long 0x00 3. " C2_MISC_EN_3 , Core 2 Misc Enable(stat_pend)" "Disabled,Enabled" bitfld.long 0x00 2. " C2_MISC_EN_2 , Core 2 Misc Enable(host_pend)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C2_MISC_EN_1 , Core 2 Misc Enable(mdio_linkint)" "Disabled,Enabled" bitfld.long 0x00 0. " C2_MISC_EN_0 , Core 2 Misc Enable(mdio_userint)" "Disabled,Enabled" rgroup.long 0x40++0x03 line.long 0x00 "CPSW_WR_C0_RX_THRESH_STAT,SUBSYSTEM CORE 0 RX THRESHOLD MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C0_RX_THRESH_STAT_7 , Core 0 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C0_RX_THRESH_STAT_6 , Core 0 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C0_RX_THRESH_STAT_5 , Core 0 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C0_RX_THRESH_STAT_4 , Core 0 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C0_RX_THRESH_STAT_3 , Core 0 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C0_RX_THRESH_STAT_2 , Core 0 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C0_RX_THRESH_STAT_1 , Core 0 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C0_RX_THRESH_STAT_0 , Core 0 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x44++0x03 line.long 0x00 "CPSW_WR_C0_RX_STAT,SUBSYSTEM CORE 0 RX INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C0_RX_STAT_7 , Core 0 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C0_RX_STAT_6 , Core 0 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C0_RX_STAT_5 , Core 0 Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C0_RX_STAT_4 , Core 0 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C0_RX_STAT_3 , Core 0 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C0_RX_STAT_2 , Core 0 Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C0_RX_STAT_1 , Core 0 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C0_RX_STAT_0 , Core 0 Receive Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x48++0x03 line.long 0x00 "CPSW_WR_C0_TX_STAT,SUBSYSTEM CORE 0 TX INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C0_TX_STAT_7 , Core 0 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C0_TX_STAT_6 , Core 0 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C0_TX_STAT_5 , Core 0 Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C0_TX_STAT_4 , Core 0 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C0_TX_STAT_3 , Core 0 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C0_TX_STAT_2 , Core 0 Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C0_TX_STAT_1 , Core 0 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C0_TX_STAT_0 , Core 0 Transmit Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x4C++0x03 line.long 0x00 "CPSW_WR_C0_MISC_STAT,SUBSYSTEM CORE 0 MISC INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 6. " C0_MISC_STAT_7 , Core 0 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C0_MISC_STAT_6 , Core 0 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 4. " C0_MISC_STAT_5 , Core 0 Misc Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " C0_MISC_STAT_4 , Core 0 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C0_MISC_STAT_3 , Core 0 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 1. " C0_MISC_STAT_2 , Core 0 Misc Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " C0_MISC_STAT_1 , Core 0 Misc Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x50++0x03 line.long 0x00 "CPSW_WR_C1_RX_THRESH_STAT,SUBSYSTEM CORE 1 RX THRESHOLD MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C1_RX_THRESH_STAT_7 , Core 1 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C1_RX_THRESH_STAT_6 , Core 1 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C1_RX_THRESH_STAT_5 , Core 1 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C1_RX_THRESH_STAT_4 , Core 1 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C1_RX_THRESH_STAT_3 , Core 1 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C1_RX_THRESH_STAT_2 , Core 1 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C1_RX_THRESH_STAT_1 , Core 1 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C1_RX_THRESH_STAT_0 , Core 1 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x54++0x03 line.long 0x00 "CPSW_WR_C1_RX_STAT,SUBSYSTEM CORE 1 RECEIVE MASKED INTERRUPT STATUS REGISTER" bitfld.long 0x00 7. " C1_RX_STAT_7 , Core 1 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C1_RX_STAT_6 , Core 1 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C1_RX_STAT_5 , Core 1 Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C1_RX_STAT_4 , Core 1 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C1_RX_STAT_3 , Core 1 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C1_RX_STAT_2 , Core 1 Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C1_RX_STAT_1 , Core 1 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C1_RX_STAT_0 , Core 1 Receive Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x58++0x03 line.long 0x00 "CPSW_WR_C1_TX_STAT,SUBSYSTEM CORE 1 TRANSMIT MASKED INTERRUPT STATUS REGISTER" bitfld.long 0x00 7. " C1_TX_STAT_7 , Core 1 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C1_TX_STAT_6 , Core 1 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C1_TX_STAT_5 , Core 1 Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C1_TX_STAT_4 , Core 1 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C1_TX_STAT_3 , Core 1 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C1_TX_STAT_2 , Core 1 Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C1_TX_STAT_1 , Core 1 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C1_TX_STAT_0 , Core 1 Transmit Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x5C++0x03 line.long 0x00 "CPSW_WR_C1_MISC_STAT,SUBSYSTEM CORE 1 MISC MASKED INTERRUPT STATUS REGISTER" bitfld.long 0x00 6. " C1_MISC_STAT_7 , Core 1 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C1_MISC_STAT_6 , Core 1 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 4. " C1_MISC_STAT_5 , Core 1 Misc Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " C1_MISC_STAT_4 , Core 1 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C1_MISC_STAT_3 , Core 1 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 1. " C1_MISC_STAT_2 , Core 1 Misc Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " C1_MISC_STAT_1 , Core 1 Misc Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x60++0x03 line.long 0x00 "CPSW_WR_C2_RX_THRESH_STAT,SUBSYSTEM CORE 2 RX THRESHOLD MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C2_RX_THRESH_STAT_7 , Core 2 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C2_RX_THRESH_STAT_6 , Core 2 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C2_RX_THRESH_STAT_5 , Core 2 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C2_RX_THRESH_STAT_4 , Core 2 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C2_RX_THRESH_STAT_3 , Core 2 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C2_RX_THRESH_STAT_2 , Core 2 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C2_RX_THRESH_STAT_1 , Core 2 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C2_RX_THRESH_STAT_0 , Core 2 Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x64++0x03 line.long 0x00 "CPSW_WR_C2_RX_STAT,SUBSYSTEM CORE 2 RECEIVE MASKED INTERRUPT STATUS REGISTER" bitfld.long 0x00 7. " C2_RX_STAT_7 , Core 2 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C2_RX_STAT_6 , Core 2 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C2_RX_STAT_5 , Core 2 Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C2_RX_STAT_4 , Core 2 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C2_RX_STAT_3 , Core 2 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C2_RX_STAT_2 , Core 2 Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C2_RX_STAT_1 , Core 2 Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C2_RX_STAT_0 , Core 2 Receive Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long ad:0x4A101268++0x03 line.long 0x00 "CPSW_WR_C2_TX_STAT,SUBSYSTEM CORE 2 TRANSMIT MASKED INTERRUPT STATUS REGISTER" bitfld.long 0x00 7. " C2_TX_STAT_7 , Core 2 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C2_TX_STAT_6 , Core 2 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C2_TX_STAT_5 , Core 2 Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C2_TX_STAT_4 , Core 2 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C2_TX_STAT_3 , Core 2 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C2_TX_STAT_2 , Core 2 Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C2_TX_STAT_1 , Core 2 Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C2_TX_STAT_0 , Core 2 Transmit Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x6C++0x03 line.long 0x00 "CPSW_WR_C2_MISC_STAT,SUBSYSTEM CORE 2 MISC MASKED INTERRUPT STATUS REGISTER" bitfld.long 0x00 6. " C2_MISC_STAT_6 , Core 2 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C2_MISC_STAT_5 , Core 2 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 4. " C2_MISC_STAT_4 , Core 2 Misc Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " C2_MISC_STAT_3 , Core 2 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C2_MISC_STAT_2 , Core 2 Misc Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 1. " C2_MISC_STAT_1 , Core 2 Misc Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " C2_MISC_STAT_0 , Core 2 Misc Masked Interrupt Status" "No interrupt,Interrupt" group.long 0x70++0x03 line.long 0x00 "CPSW_WR_C0_RX_IMAX,SUBSYSTEM CORE 0 RECEIVE INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C0_RX_IMAX , Core 0 Receive Interrupts per Millisecond" group.long 0x74++0x03 line.long 0x00 "CPSW_WR_C0_TX_IMAX,SUBSYSTEM CORE 0 TRANSMIT INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C0_TX_IMAX , Core 0 Transmit Interrupts per Millisecond" group.long 0x78++0x03 line.long 0x00 "CPSW_WR_C1_RX_IMAX,SUBSYSTEM CORE 1 RECEIVE INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C1_RX_IMAX , Core 1 Receive Interrupts per Millisecond" group.long 0x7C++0x03 line.long 0x00 "CPSW_WR_C1_TX_IMAX,SUBSYSTEM CORE 1 TRANSMIT INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C1_TX_IMAX , Core 1 Transmit Interrupts per Millisecond" group.long 0x80++0x03 line.long 0x00 "CPSW_WR_C2_RX_IMAX,SUBSYSTEM CORE 2 RECEIVE INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C2_RX_IMAX , Core 2 Receive Interrupts per Millisecond" group.long ad:0x4A101284++0x03 line.long 0x00 "CPSW_WR_C2_TX_IMAX,SUBSYSTEM CORE 2 TRANSMIT INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C2_TX_IMAX , Core 2 Transmit Interrupts per Millisecond" rgroup.long 0x88++0x03 line.long 0x00 "CPSW_WR_RGMII_CTL,RGMII CONTROL SIGNAL REGISTER" bitfld.long 0x00 7. " RGMII2_FULLDUPLEX ,RGMII2 Full duplex" "Half-duplex,Full-duplex" bitfld.long 0x00 5.--6. " RGMII2_SPEED ,RGMII2 Speed" "10Mbps,100Mbps,1000Mbps," bitfld.long 0x00 4. " RGMII2_LINK ,RGMII2 Link Indicator" "Down,Up" textline " " bitfld.long 0x00 3. " RGMII1_FULLDUPLEX ,RGMII1 Full duplex" "Half-duplex,Full-duplex" bitfld.long 0x00 1.--2. " RGMII1_SPEED ,RGMII1 Speed" "10Mbps,100Mbps,1000Mbps," bitfld.long 0x00 0. " RGMII1_LINK ,RGMII1 Link Indicator" "Down,Up" width 11. tree.end tree "MDIO Registers" base ad:0x4A101000 width 21. rgroup.long 0x000++0x03 line.long 0x00 "MDIO_VER,MDIO MDIO Version Register" hexmask.long.word 0x00 16.--31. 1. " MODID , Identifies type of peripheral" hexmask.long.byte 0x00 8.--15. 1. " REVMAJ , Management interface module major revision value" hexmask.long.byte 0x00 0.--7. 1. " REVMIN , Management interface module minor revision value" group.long 0x004++0x03 line.long 0x00 "MDIO_CTRL,MDIO Control Register" rbitfld.long 0x00 31. " IDLE ,MDIO state machine IDLE" "Not idle,Idle" bitfld.long 0x00 30. " EN ,Enable control" "Disabled,Enabled" rbitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL , Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "No,Yes" textline " " eventfld.long 0x00 19. " FAULT ,Fault indicator" "No failure,Fault" bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled" bitfld.long 0x00 17. " INTTESTENB ,Interrupt test enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " CLKDIV , Clock divider" group.long 0x008++0x03 line.long 0x00 "MDIO_ALIVE,PHY Alive Status Register" eventfld.long 0x00 31. " ALIVE_31 ,MDIO alive 31" "No effect,Clear" eventfld.long 0x00 30. " ALIVE_30 ,MDIO alive 30" "No effect,Clear" eventfld.long 0x00 29. " ALIVE_29 ,MDIO alive 29" "No effect,Clear" eventfld.long 0x00 28. " ALIVE_28 ,MDIO alive 28" "No effect,Clear" textline " " eventfld.long 0x00 27. " ALIVE_27 ,MDIO alive 27" "No effect,Clear" eventfld.long 0x00 26. " ALIVE_26 ,MDIO alive 26" "No effect,Clear" eventfld.long 0x00 25. " ALIVE_25 ,MDIO alive 25" "No effect,Clear" eventfld.long 0x00 24. " ALIVE_24 ,MDIO alive 24" "No effect,Clear" textline " " eventfld.long 0x00 23. " ALIVE_23 ,MDIO alive 23" "No effect,Clear" eventfld.long 0x00 22. " ALIVE_22 ,MDIO alive 22" "No effect,Clear" eventfld.long 0x00 21. " ALIVE_21 ,MDIO alive 21" "No effect,Clear" eventfld.long 0x00 20. " ALIVE_20 ,MDIO alive 20" "No effect,Clear" textline " " eventfld.long 0x00 19. " ALIVE_19 ,MDIO alive 19" "No effect,Clear" eventfld.long 0x00 18. " ALIVE_18 ,MDIO alive 18" "No effect,Clear" eventfld.long 0x00 17. " ALIVE_17 ,MDIO alive 17" "No effect,Clear" eventfld.long 0x00 16. " ALIVE_16 ,MDIO alive 16" "No effect,Clear" textline " " eventfld.long 0x00 15. " ALIVE_15 ,MDIO alive 15" "No effect,Clear" eventfld.long 0x00 14. " ALIVE_14 ,MDIO alive 14" "No effect,Clear" eventfld.long 0x00 13. " ALIVE_13 ,MDIO alive 13" "No effect,Clear" eventfld.long 0x00 12. " ALIVE_12 ,MDIO alive 12" "No effect,Clear" textline " " eventfld.long 0x00 11. " ALIVE_11 ,MDIO alive 11" "No effect,Clear" eventfld.long 0x00 10. " ALIVE_10 ,MDIO alive 10" "No effect,Clear" eventfld.long 0x00 9. " ALIVE_9 ,MDIO alive 9" "No effect,Clear" eventfld.long 0x00 8. " ALIVE_8 ,MDIO alive 8" "No effect,Clear" textline " " eventfld.long 0x00 7. " ALIVE_7 ,MDIO alive 7" "No effect,Clear" eventfld.long 0x00 6. " ALIVE_6 ,MDIO alive 6" "No effect,Clear" eventfld.long 0x00 5. " ALIVE_5 ,MDIO alive 5" "No effect,Clear" eventfld.long 0x00 4. " ALIVE_4 ,MDIO alive 4" "No effect,Clear" textline " " eventfld.long 0x00 3. " ALIVE_3 ,MDIO alive 3" "No effect,Clear" eventfld.long 0x00 2. " ALIVE_2 ,MDIO alive 2" "No effect,Clear" eventfld.long 0x00 1. " ALIVE_1 ,MDIO alive 1" "No effect,Clear" eventfld.long 0x00 0. " ALIVE_0 ,MDIO alive 0" "No effect,Clear" rgroup.long 0x00C++0x03 line.long 0x00 "MDIO_LINK,PHY Link Status Register" hexmask.long 0x00 0.--31. 1. " LINK , MDIO link state" group.long 0x010++0x03 line.long 0x00 "MDIO_LINKINTRAW,MDIO Link Status Change Interrupt Register" eventfld.long 0x00 1. " , MDIO link change event" "Not changed,Changed" eventfld.long 0x00 0. " LINKINTRAW_0 , MDIO link change event" "Not changed,Changed" group.long 0x014++0x03 line.long 0x00 "MDIO_LINKINTMASKED,MDIO Link Status Change Interrupt Register" eventfld.long 0x00 1. " LINKINTMASKED_0 , MDIO link change interrupt masked value" "Not masked,Masked" eventfld.long 0x00 0. " LINKINTMASKED_0 , MDIO link change interrupt masked value" "Not masked,Masked" group.long 0x020++0x03 line.long 0x00 "MDIO_USERINTRAW,MDIO User Command Complete Interrupt Register" eventfld.long 0x00 1. " USERINTRAW_1 , Raw value of MDIO user command complete event for MDIOUSERACCESS1" "Not scheduled,Scheduled" eventfld.long 0x00 0. " USERINTRAW_0 , Raw value of MDIO user command complete event for MDIOUSERACCESS0" "Not scheduled,Scheduled" group.long 0x024++0x03 line.long 0x00 "MDIO_USERINTMASKED,MDIO User Command Complete Interrupt Register" eventfld.long 0x00 1. " USERINTMASKED_1 , Masked value of MDIO user command complete interrupt for the MDIOUSERACCESS1" "Not masked,Masked" eventfld.long 0x00 0. " USERINTMASKED_0 , Masked value of MDIO user command complete interrupt for the MDIOUSERACCESS0" "Not masked,Masked" group.long 0x028++0x03 line.long 0x00 "MDIO_USERINTMASKSET,MDIO User Command Complete Interrupt Mask Set Register" eventfld.long 0x00 1. " USERINTMASKSET_1 ,Enable MDIO user command complete interrupts for MDIOUSERACCESS1" "Disabled,Enabled" eventfld.long 0x00 0. " USERINTMASKSET_0 ,Enable MDIO user command complete interrupts for MDIOUSERACCESS0" "Disabled,Enabled" group.long 0x02C++0x03 line.long 0x00 "MDIO_USERINTMASKCLR,MDIO User Interrupt Mask Clear Register" eventfld.long 0x00 1. " USERINTMASKCLR_1 ,Disable user command complete interrupts for MDIOUSERACCESS1" "No,Yes" eventfld.long 0x00 0. " USERINTMASKCLR_0 ,Disable user command complete interrupts for MDIOUSERACCESS0" "No,Yes" if (((d.l(ad:0x4A101000+0x04))&0x80000000)==0x80000000) group.long 0x080++0x03 line.long 0x00 "MDIO_USERACCESS0,MDIO User Access Register 0" bitfld.long 0x00 31. " GO , Go" "Not performed,Performed" bitfld.long 0x00 30. " WRITE , Write enable" "Read,Write" textline " " bitfld.long 0x00 29. " ACK , Acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 21.--25. " REGADR , Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PHYADR , PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " DATA , User data" else group.long 0x080++0x03 line.long 0x00 "MDIO_USERACCESS0,MDIO User Access Register 0" rbitfld.long 0x00 31. " GO , Go" "Not performed,Performed" bitfld.long 0x00 30. " WRITE , Write enable" "Read,Write" textline " " bitfld.long 0x00 29. " ACK , Acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 21.--25. " REGADR , Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PHYADR , PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " DATA , User data" endif group.long 0x084++0x03 line.long 0x00 "MDIO_USERPHYSEL0,MDIO User PHY Select Register 0" bitfld.long 0x00 7. " LINKSEL , Link status determination select" "MDIO,MLINK" bitfld.long 0x00 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " PHYADDRMON , PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((d.l(ad:0x4A101000+0x04))&0x80000000)==0x80000000) group.long 0x088++0x03 line.long 0x00 "MDIO_USERACCESS1,MDIO User Access Register 1" bitfld.long 0x00 31. " GO , Go" "Not performed,Performed" bitfld.long 0x00 30. " WRITE , Write enable" "Read,Write" textline " " bitfld.long 0x00 29. " ACK , Acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 21.--25. " REGADR , Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PHYADR , PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " DATA , User data" else group.long 0x088++0x03 line.long 0x00 "MDIO_USERACCESS1,MDIO User Access Register 1" rbitfld.long 0x00 31. " GO , Go" "Not performed,Performed" bitfld.long 0x00 30. " WRITE , Write enable" "Read,Write" textline " " bitfld.long 0x00 29. " ACK , Acknowledge" "Not acknowledged,Acknowledged" bitfld.long 0x00 21.--25. " REGADR , Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PHYADR , PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " DATA , User data" endif group.long 0x08C++0x03 line.long 0x00 "MDIO_USERPHYSEL1,MDIO User PHY Select Register 1" bitfld.long 0x00 7. " LINKSEL , Link status determination select" "MDIO,MLINK" bitfld.long 0x00 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " PHYADDRMON , PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 11. tree.end tree.end tree "MMC(Multimedia Card)" tree "MMCSD 0" base ad:0x48060000 width 14. group.long 0x0110++0x03 line.long 0x00 "SD_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power Management" "Force-standby,No-standby,Smart-standby,Smart-Standby wake-up-capable" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Int. and func. switched off,Int. maintained/Func. switched-off,Int. switched-off/Func. maintained,Int. and func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up," textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy" "Free-running,Gating strategy" rgroup.long 0x0114++0x03 line.long 0x00 "SD_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" group.long 0x0124++0x03 line.long 0x00 "SD_CSRE,This register enables the host controller to detect card status errors of response" if (((d.l(ad:0x48060000+0x0128))&0x8)==0x8) //this.DDIR== "Input" group.long 0x0128++0x03 line.long 0x00 "SD_SYSTEST,This register is used to control the signals that connect to I/O pins" bitfld.long 0x00 16. " OBI ,Out-of-band interrupt" "Low,High" textline " " bitfld.long 0x00 15. " SDCD ,Card detect input signal" "Low,High" bitfld.long 0x00 14. " SDWP ,Write protect input signal" "Low,High" bitfld.long 0x00 13. " WAKD ,Wake request output signal data value" "Low,High" bitfld.long 0x00 12. " SSB ,Set status bit" "Clear,Interrupt" textline " " bitfld.long 0x00 11. " D7D ,DAT7 input signal data value" "Low,High" bitfld.long 0x00 10. " D6D ,DAT6 input signal data value" "Low,High" bitfld.long 0x00 9. " D5D ,DAT5 input signal data value" "Low,High" bitfld.long 0x00 8. " D4D ,DAT4 input signal data value" "Low,High" textline " " bitfld.long 0x00 7. " D3D ,DAT3 input signal data value" "Low,High" bitfld.long 0x00 6. " D2D ,DAT2 input signal data value" "Low,High" bitfld.long 0x00 5. " D1D ,DAT1 input signal data value" "Low,High" bitfld.long 0x00 4. " D0D ,DAT0 input signal data value" "Low,High" textline " " bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value" "Low,High" bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction" "Output,Input" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value" "Low,High" else group.long 0x0128++0x03 line.long 0x00 "SD_SYSTEST,This register is used to control the signals that connect to I/O pins" bitfld.long 0x00 16. " OBI ,Out-of-band interrupt" "Low,High" textline " " bitfld.long 0x00 15. " SDCD ,Card detect input signal" "Low,High" bitfld.long 0x00 14. " SDWP ,Write protect input signal" "Low,High" bitfld.long 0x00 13. " WAKD ,Wake request output signal data value" "Low,High" bitfld.long 0x00 12. " SSB ,Set status bit" "Clear,Interrupt" textline " " bitfld.long 0x00 11. " D7D ,DAT7 output signal data value" "Low,High" bitfld.long 0x00 10. " D6D ,DAT6 output signal data value" "Low,High" bitfld.long 0x00 9. " D5D ,DAT5 output signal data value" "Low,High" bitfld.long 0x00 8. " D4D ,DAT4 output signal data value" "Low,High" textline " " bitfld.long 0x00 7. " D3D ,DAT3 output signal data value" "Low,High" bitfld.long 0x00 6. " D2D ,DAT2 output signal data value" "Low,High" bitfld.long 0x00 5. " D1D ,DAT1 output signal data value" "Low,High" bitfld.long 0x00 4. " D0D ,DAT0 output signal data value" "Low,High" textline " " bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value" "Low,High" bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction" "Output,Input" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value" "Low,High" endif group.long 0x012C++0x03 line.long 0x00 "SD_CON,SD_CON register" bitfld.long 0x00 21. " SDMA_LnE ,Slave DMA Level/Edge Request" "Edge,Level" bitfld.long 0x00 20. " DMA_MnS ,DMA Master or Slave selection" "Slave,Not available" bitfld.long 0x00 19. " DDR ,Dual Data Rate mode" "Single edge,Both edges" bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status Supported" "Not forced,Released" textline " " bitfld.long 0x00 17. " BOOT_ACK ,Book acknowledge received" "No received,Received" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained" bitfld.long 0x00 15. " PADEN ,Control power for MMC lines" "Not forced,Forced" bitfld.long 0x00 12. " CEATA ,CE-ATA control mode (MMC cards compliant with CE-ATA)" "MMC/SD/SDIO,CE-ATA" textline " " bitfld.long 0x00 11. " CTPL ,Control Power for mmc_dat[1] line (SD cards)" "Disabled,Except mmc_dat[1]" bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value (all cards)" "33 us,231 us,1 ms,8.4 ms" bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low" bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low" textline " " bitfld.long 0x00 6. " MIT ,MMC interrupt command (MMC cards only)" "Disabled,Enabled" bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select (MMC cards only)" "1-bit or 4-bit,8-bit" bitfld.long 0x00 4. " MODE ,Mode select (all cards)" "Functional,SYSTEST" bitfld.long 0x00 3. " STR , Stream command (MMC cards only)" "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cards only)" "Not generated,Generated" bitfld.long 0x00 1. " INIT ,Send initialization stream (all cards)" "Not send,Send" bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cards only)" "Disabled,Enabled" group.long 0x0130++0x03 line.long 0x00 "SD_PWCNT,Mmc counter to delay command transfers after activating the PAD power" hexmask.long.word 0x00 0.--15. 1. " PWRCNT ,Power counter register" rgroup.long 0x0200++0x03 line.long 0x00 "SD_SDMASA,Mmc counter to delay command transfers after activating the PAD power" if (((d.l(ad:0x48060000+0x020C))&0x2)==0x2)&&(((d.l(ad:0x48060000+0x020C))&0x20)==0x20) //SD_CMD.BCE== Enabled && SD_CMD.MSBS== "Multi block" group.long 0x0204++0x03 line.long 0x00 "SD_BLK,Block size and count register" hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" else group.long 0x0204++0x03 line.long 0x00 "SD_BLK,Block size and count register" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" endif group.long 0x0208++0x03 line.long 0x00 "SD_ARG,This register contains command argument specified as bit 39-8 of Command-Format" hexmask.long 0x00 0.--31. 1. " ARG , Command argument bits [31:0]" if (((d.l(ad:0x48060000+0x020C))&0x20)==0x20) group.long 0x020C++0x03 line.long 0x00 "SD_CMD,This register configures the data and command transfers" hexmask.long.byte 0x00 24.--29. 1. " INDX , Command index binary encoded value from 0 to 63 specifying the command number send to card (CMD0 or ACMD0 to CMD63 or ACMD63)." bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type" "Others,Bus Suspend,Function Select,I/O Abort" bitfld.long 0x00 21. " DP ,Data present select" "No transfer,Transfer" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCE ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select" "Single block,Multi block" bitfld.long 0x00 4. " DDIR ,Data transfer Direction" "Data Write,Data Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " BCE ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DE ,DMA Enable" "Disabled,Enabled" else group.long 0x020C++0x03 line.long 0x00 "SD_CMD,This register configures the data and command transfers" hexmask.long.byte 0x00 24.--29. 1. " INDX , Command index binary encoded value from 0 to 63 specifying the command number send to card (CMD0 or ACMD0 to CMD63 or ACMD63)." bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type" "Others,Bus Suspend,Function Select,I/O Abort" bitfld.long 0x00 21. " DP ,Data present select" "No transfer,Transfer" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCE ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select" "Single block,Multi block" bitfld.long 0x00 4. " DDIR ,Data transfer Direction" "Data Write,Data Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DE ,DMA Enable" "Disabled,Enabled" endif rgroup.long 0x0210++0x03 line.long 0x00 "SD_RSP10,This register holds bits positions [31:0] of command response type R1, R1b, R2, R3, R4, R5, R5b, or R6." hexmask.long.word 0x00 16.--31. 1. " RSP1 , Command Response [31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 , Command Response [15:0]" rgroup.long 0x0214++0x03 line.long 0x00 "SD_RSP32,This register holds bits positions [63:32] of command response type R2." hexmask.long.word 0x00 16.--31. 1. " RSP3 , Command Response [63:48]" hexmask.long.word 0x00 0.--15. 1. " RSP2 , Command Response [47:32]" rgroup.long 0x0218++0x03 line.long 0x00 "SD_RSP54,This register holds bits positions [95:64] of command response type R2." hexmask.long.word 0x00 16.--31. 1. " RSP5 , Command Response [95:80]" hexmask.long.word 0x00 0.--15. 1. " RSP4 , Command Response [79:64]" rgroup.long 0x021C++0x03 line.long 0x00 "SD_RSP76,This 32-bit register holds bits positions [127:96] of command response type R2." hexmask.long.word 0x00 16.--31. 1. " RSP7 , Command Response [127:112]" hexmask.long.word 0x00 0.--15. 1. " RSP6 , Command Response [111:96]" if (((d.l(ad:0x48060000+0x0224))&0x800)==0x800)&&(((d.l(ad:0x48060000+0x0224))&0x400)==0x400) group.long 0x0220++0x03 line.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" hexmask.long 0x00 0.--31. 1. " DATA , Data register [31:0]" elif (((d.l(ad:0x48060000+0x0224))&0x800)==0x0)&&(((d.l(ad:0x48060000+0x0224))&0x400)==0x400) wgroup.long 0x0220++0x03 line.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" hexmask.long 0x00 0.--31. 1. " DATA , Data register [31:0]" elif (((d.l(ad:0x48060000+0x0224))&0x800)==0x800)&&(((d.l(ad:0x48060000+0x0224))&0x400)==0x00) rgroup.long 0x0220++0x03 line.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" hexmask.long 0x00 0.--31. 1. " DATA , Data register [31:0]" else hgroup.long 0x0220++0x03 hide.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" endif if (((d.l(ad:0x48060000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x48060000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x48060000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x48060000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x48060000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x48060000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x48060000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x48060000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x48060000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x48060000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x48060000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x48060000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x48060000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x48060000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x48060000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x48060000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x48060000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x48060000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x48060000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x48060000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x48060000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x48060000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x48060000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x48060000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" endif if (((d.l(ad:0x48060000+0x0228))&0x80)==0x80) group.long 0x0228++0x03 line.long 0x00 "SD_HCTL,This register defines the host controls to set power,wake-up and transfer parameters" bitfld.long 0x00 27. " OBWE ,Wake-up event enable for 'out-of-band' Interrupt" "Disabled,Enabled" bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CR ,Continue request" "No affect,Transfer restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stop at block gap" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select (All cards)" ",,,,,1.8 V,3.0 V,3.3 V" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "SDCD#,Detect Test Level" bitfld.long 0x00 6. " CDTL , Card Detect Test Level" "No card,Card inserted" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select" ",,32-bit," bitfld.long 0x00 2. " HSPE ,High Speed Enable" "Normal,High" bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit" else group.long 0x0228++0x03 line.long 0x00 "SD_HCTL,This register defines the host controls to set power,wake-up and transfer parameters" bitfld.long 0x00 27. " OBWE ,Wake-up event enable for 'out-of-band' Interrupt" "Disabled,Enabled" bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CR ,Continue request" "No affect,Transfer restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stop at block gap" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select (All cards)" ",,,,,1.8 V,3.0 V,3.3 V" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "SDCD#,Detect Test Level" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select" ",,32-bit," bitfld.long 0x00 2. " HSPE ,High Speed Enable" "Normal,High" bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit" endif group.long 0x022C++0x03 line.long 0x00 "SD_SYSCTL,This register defines the system controls to set software resets, clock frequency management and data timeout" bitfld.long 0x00 26. " SRD ,Software reset for mmc_dat line" "No reset,Reset" bitfld.long 0x00 25. " SRC ,Software reset for mmc_cmd line" "No reset,Reset" textline " " bitfld.long 0x00 24. " SRA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCF x 2^13,TCF x 2^14,,,,,,,,,,,,,TCF x 2^27," hexmask.long.word 0x00 6.--15. 1. " CLKD ,Clock frequency select" textline " " bitfld.long 0x00 2. " CEN ,Clock enable" "Not provided,Provided" rbitfld.long 0x00 1. " ICS ,Internal clock stable" "Not stable,Stable" bitfld.long 0x00 0. " ICE ,Internal clock enable" "Stopped,Oscillates" group.long 0x0230++0x03 line.long 0x00 "SD_STAT,The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x00 29. " BADA ,Bad access to data space" "No interrupt,Bad access" bitfld.long 0x00 28. " CERR ,Card error" "No error,Error" textline " " bitfld.long 0x00 25. " ADMAE ,ADMA Error" "No error,Error" bitfld.long 0x00 24. " ACE ,Auto CMD12 error" "No error,Error" textline " " bitfld.long 0x00 22. " DEB ,Data End Bit error" "No error,Error" bitfld.long 0x00 21. " DCRC ,Data CRC Error" "No error,Error" bitfld.long 0x00 20. " DTO ,Data timeout error" "No error,Error" bitfld.long 0x00 19. " CIE ,Command index error" "No error,Error" textline " " bitfld.long 0x00 18. " CEB ,Command end bit error" "No error,Error" bitfld.long 0x00 17. " CCRC ,Command CRC error" "No error,Error" bitfld.long 0x00 16. " CTO ,Command timeout error" "No error,Error" rbitfld.long 0x00 15. " ERRI ,Error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " BSR ,Boot Status Received Interrupt(MMC cards)" "No interrupt,Interrupt" rbitfld.long 0x00 9. " OBI ,Out-of-band interrupt(MMC cards)" "No interrupt,Interrupt" rbitfld.long 0x00 8. " CIRQ ,Card interrupt(SD and SDIO cards)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " CREM ,Card Removal" "State stable or debouncing,Card Removed" bitfld.long 0x00 6. " CINS , Card Insertion" "Stable or debouncing,Card inserted" bitfld.long 0x00 5. " BRR ,Buffer read ready" "Not ready,Ready" bitfld.long 0x00 4. " BWR ,Buffer write ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " DMA ,DMA Interrupt" "Interrupt,No interrupt" bitfld.long 0x00 2. " BGE ,Block gap event" "No block,Blocked" bitfld.long 0x00 1. " TC ,Transfer completed" "Not completed,Completed" bitfld.long 0x00 0. " CC ,Command complete" "Not completed,Completed" group.long 0x0234++0x03 line.long 0x00 "SD_IE,This register allows to enable/disable the module to set status bits, on an event-by-event basis" bitfld.long 0x00 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled" bitfld.long 0x00 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 25. " ADMA_ENABLE ,ADMA error Interrupt Enable" "Masked,Enabled" bitfld.long 0x00 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled" bitfld.long 0x00 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled" bitfld.long 0x00 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled" bitfld.long 0x00 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled" bitfld.long 0x00 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled" bitfld.long 0x00 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled" rbitfld.long 0x00 15. " NULL ,The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "0,1" textline " " bitfld.long 0x00 10. " BSR_ENABLE ,Boot Status Interrupt Enable" "Masked,Enabled" bitfld.long 0x00 9. " OBI_ENABLE ,Out-of-band interrupt enable" "Masked,Enabled" bitfld.long 0x00 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 7. " CREM_ENABLE ,Card Removal interrupt Enable" "Masked,Enabled" bitfld.long 0x00 6. " CINS_ENABLE ,Card Insertion interrupt Enable" "Masked,Enabled" bitfld.long 0x00 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled" bitfld.long 0x00 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled" bitfld.long 0x00 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled" bitfld.long 0x00 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled" bitfld.long 0x00 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled" group.long 0x0238++0x03 line.long 0x00 "SD_ISE,Register allows you to enable/disable the module to set status bits, on an event-by-event basis" bitfld.long 0x00 29. " BADA_SIGEN ,Bad access to data space interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " CERR_SIGEN ,Card error interrupt signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled" bitfld.long 0x00 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled" bitfld.long 0x00 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled" bitfld.long 0x00 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled" bitfld.long 0x00 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled" bitfld.long 0x00 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled" bitfld.long 0x00 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled" rbitfld.long 0x00 15. " NULL , Fixed to 0" "0,1" textline " " bitfld.long 0x00 10. " BSR_SIGEN ,Boot Status signal status enable" "Disabled,Enabled" bitfld.long 0x00 9. " OBI_SIGEN ,Out-of-band interrupt signal status enable" "Disabled,Enabled" bitfld.long 0x00 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CREM_SIGEN ,Card Removal signal status enable" "Disabled,Enabled" bitfld.long 0x00 6. " CINS_SIGEN ,Card Insertion signal status enable" "Disabled,Enabled" bitfld.long 0x00 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled" bitfld.long 0x00 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled" bitfld.long 0x00 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled" bitfld.long 0x00 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled" bitfld.long 0x00 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled" if (((d.l(ad:0x48060000+0x020C))&0x4)==0x4)&&(((d.l(ad:0x48060000+0x0230))&0x1000000)==0x1000000) rgroup.long 0x023C++0x03 line.long 0x00 "SD_AC12,SD_AC12 register" bitfld.long 0x00 7. " CNI ,Command not issue by auto CMD12 error" "No error,Error" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error" textline " " bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 2. " ACCE , Auto CMD12 CRC error" "No error,Error" bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " ACNE , Auto CMD12 not executed" "Executed,Not executed" else hgroup.long 0x023C++0x03 hide.long 0x00 "SD_AC12,SD_AC12 register" endif group.long 0x0240++0x03 line.long 0x00 "SD_CAPA,This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x00 28. " BUS_64BIT ,64 Bit System Bus Support" "32-bit,64-bit" textline " " bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" textline " " rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "No,Yes" rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High-speed support" "Not supported,Supported" textline " " rbitfld.long 0x00 19. " AD2S ,This bit indicates whether the Host Controller is capable of using ADMA2" "Not supported,Supported" rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes," textline " " rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "KHz,MHz" group.long 0x0248++0x03 line.long 0x00 "SD_CUR_CAPA,This register indicates the maximum current capability for each voltage" hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V" hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V" hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V" wgroup.long 0x0250++0x03 line.long 0x00 "SD_FE,Address which the Error Interrupt Status register can be written" bitfld.long 0x00 29. " FE_BADA ,Force Event Bad access to data space" "No effect,Forced" textline " " bitfld.long 0x00 28. " FE_CERR ,Force Event Card error" "No effect,Forced" bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error." "No effect,Forced" bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error" "No effect,Forced" textline " " bitfld.long 0x00 22. " FE_DEB ,Force Event Data End Bit error" "No effect,Forced" bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error" "No effect,Forced" bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error" "No effect,Forced" textline " " bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error" "No effect,Forced" bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error" "No effect,Forced" bitfld.long 0x00 17. " FE_CCRC ,Force Event Comemand CRC error" "No effect,Forced" bitfld.long 0x00 16. " FE_CTO ,Force Event Command Timeout error" "No effect,Forced" textline " " bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error" "No effect,Forced" bitfld.long 0x00 4. " FE_ACIE ,Force Event Auto CMD12 index error" "No effect,Forced" textline " " bitfld.long 0x00 3. " FE_ACEB ,Force Event Auto CMD12 end bit error" "No effect,Forced" bitfld.long 0x00 2. " FE_ACCE ,Force Event Auto CMD12 CRC error" "No effect,Forced" bitfld.long 0x00 1. " FE_ACTO ,Force Event Auto CMD12 timeout error" "No effect,Forced" bitfld.long 0x00 0. " FE_ACNE ,Force Event Auto CMD12 not executed" "No effect,Forced" group.long 0x0254++0x03 line.long 0x00 "SD_ADMAES,SD_ADMAES register" bitfld.long 0x00 2. " LME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "ST_STOP(Contents),ST_STOP(Points),,ST_TFR" group.long 0x0258++0x03 line.long 0x00 "SD_ADMASAL,This register holds the byte address of the executing command of the Descriptor table" group.long 0x025C++0x03 line.long 0x00 "SD_ADMASAH,SD_ADMASAH" rgroup.long 0x02FC++0x03 line.long 0x00 "SD_REV,This register contains the hard coded RTL vendor revision number" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number" bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Deasserted,Asserted" width 11. tree.end tree "MMCSD 1" base ad:0x481D8000 width 14. group.long 0x0110++0x03 line.long 0x00 "SD_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power Management" "Force-standby,No-standby,Smart-standby,Smart-Standby wake-up-capable" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Int. and func. switched off,Int. maintained/Func. switched-off,Int. switched-off/Func. maintained,Int. and func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up," textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy" "Free-running,Gating strategy" rgroup.long 0x0114++0x03 line.long 0x00 "SD_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" group.long 0x0124++0x03 line.long 0x00 "SD_CSRE,This register enables the host controller to detect card status errors of response" if (((d.l(ad:0x481D8000+0x0128))&0x8)==0x8) //this.DDIR== "Input" group.long 0x0128++0x03 line.long 0x00 "SD_SYSTEST,This register is used to control the signals that connect to I/O pins" bitfld.long 0x00 16. " OBI ,Out-of-band interrupt" "Low,High" textline " " bitfld.long 0x00 15. " SDCD ,Card detect input signal" "Low,High" bitfld.long 0x00 14. " SDWP ,Write protect input signal" "Low,High" bitfld.long 0x00 13. " WAKD ,Wake request output signal data value" "Low,High" bitfld.long 0x00 12. " SSB ,Set status bit" "Clear,Interrupt" textline " " bitfld.long 0x00 11. " D7D ,DAT7 input signal data value" "Low,High" bitfld.long 0x00 10. " D6D ,DAT6 input signal data value" "Low,High" bitfld.long 0x00 9. " D5D ,DAT5 input signal data value" "Low,High" bitfld.long 0x00 8. " D4D ,DAT4 input signal data value" "Low,High" textline " " bitfld.long 0x00 7. " D3D ,DAT3 input signal data value" "Low,High" bitfld.long 0x00 6. " D2D ,DAT2 input signal data value" "Low,High" bitfld.long 0x00 5. " D1D ,DAT1 input signal data value" "Low,High" bitfld.long 0x00 4. " D0D ,DAT0 input signal data value" "Low,High" textline " " bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value" "Low,High" bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction" "Output,Input" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value" "Low,High" else group.long 0x0128++0x03 line.long 0x00 "SD_SYSTEST,This register is used to control the signals that connect to I/O pins" bitfld.long 0x00 16. " OBI ,Out-of-band interrupt" "Low,High" textline " " bitfld.long 0x00 15. " SDCD ,Card detect input signal" "Low,High" bitfld.long 0x00 14. " SDWP ,Write protect input signal" "Low,High" bitfld.long 0x00 13. " WAKD ,Wake request output signal data value" "Low,High" bitfld.long 0x00 12. " SSB ,Set status bit" "Clear,Interrupt" textline " " bitfld.long 0x00 11. " D7D ,DAT7 output signal data value" "Low,High" bitfld.long 0x00 10. " D6D ,DAT6 output signal data value" "Low,High" bitfld.long 0x00 9. " D5D ,DAT5 output signal data value" "Low,High" bitfld.long 0x00 8. " D4D ,DAT4 output signal data value" "Low,High" textline " " bitfld.long 0x00 7. " D3D ,DAT3 output signal data value" "Low,High" bitfld.long 0x00 6. " D2D ,DAT2 output signal data value" "Low,High" bitfld.long 0x00 5. " D1D ,DAT1 output signal data value" "Low,High" bitfld.long 0x00 4. " D0D ,DAT0 output signal data value" "Low,High" textline " " bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value" "Low,High" bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction" "Output,Input" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value" "Low,High" endif group.long 0x012C++0x03 line.long 0x00 "SD_CON,SD_CON register" bitfld.long 0x00 21. " SDMA_LnE ,Slave DMA Level/Edge Request" "Edge,Level" bitfld.long 0x00 20. " DMA_MnS ,DMA Master or Slave selection" "Slave,Not available" bitfld.long 0x00 19. " DDR ,Dual Data Rate mode" "Single edge,Both edges" bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status Supported" "Not forced,Released" textline " " bitfld.long 0x00 17. " BOOT_ACK ,Book acknowledge received" "No received,Received" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained" bitfld.long 0x00 15. " PADEN ,Control power for MMC lines" "Not forced,Forced" bitfld.long 0x00 12. " CEATA ,CE-ATA control mode (MMC cards compliant with CE-ATA)" "MMC/SD/SDIO,CE-ATA" textline " " bitfld.long 0x00 11. " CTPL ,Control Power for mmc_dat[1] line (SD cards)" "Disabled,Except mmc_dat[1]" bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value (all cards)" "33 us,231 us,1 ms,8.4 ms" bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low" bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low" textline " " bitfld.long 0x00 6. " MIT ,MMC interrupt command (MMC cards only)" "Disabled,Enabled" bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select (MMC cards only)" "1-bit or 4-bit,8-bit" bitfld.long 0x00 4. " MODE ,Mode select (all cards)" "Functional,SYSTEST" bitfld.long 0x00 3. " STR , Stream command (MMC cards only)" "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cards only)" "Not generated,Generated" bitfld.long 0x00 1. " INIT ,Send initialization stream (all cards)" "Not send,Send" bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cards only)" "Disabled,Enabled" group.long 0x0130++0x03 line.long 0x00 "SD_PWCNT,Mmc counter to delay command transfers after activating the PAD power" hexmask.long.word 0x00 0.--15. 1. " PWRCNT ,Power counter register" rgroup.long 0x0200++0x03 line.long 0x00 "SD_SDMASA,Mmc counter to delay command transfers after activating the PAD power" if (((d.l(ad:0x481D8000+0x020C))&0x2)==0x2)&&(((d.l(ad:0x481D8000+0x020C))&0x20)==0x20) //SD_CMD.BCE== Enabled && SD_CMD.MSBS== "Multi block" group.long 0x0204++0x03 line.long 0x00 "SD_BLK,Block size and count register" hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" else group.long 0x0204++0x03 line.long 0x00 "SD_BLK,Block size and count register" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" endif group.long 0x0208++0x03 line.long 0x00 "SD_ARG,This register contains command argument specified as bit 39-8 of Command-Format" hexmask.long 0x00 0.--31. 1. " ARG , Command argument bits [31:0]" if (((d.l(ad:0x481D8000+0x020C))&0x20)==0x20) group.long 0x020C++0x03 line.long 0x00 "SD_CMD,This register configures the data and command transfers" hexmask.long.byte 0x00 24.--29. 1. " INDX , Command index binary encoded value from 0 to 63 specifying the command number send to card (CMD0 or ACMD0 to CMD63 or ACMD63)." bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type" "Others,Bus Suspend,Function Select,I/O Abort" bitfld.long 0x00 21. " DP ,Data present select" "No transfer,Transfer" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCE ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select" "Single block,Multi block" bitfld.long 0x00 4. " DDIR ,Data transfer Direction" "Data Write,Data Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " BCE ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DE ,DMA Enable" "Disabled,Enabled" else group.long 0x020C++0x03 line.long 0x00 "SD_CMD,This register configures the data and command transfers" hexmask.long.byte 0x00 24.--29. 1. " INDX , Command index binary encoded value from 0 to 63 specifying the command number send to card (CMD0 or ACMD0 to CMD63 or ACMD63)." bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type" "Others,Bus Suspend,Function Select,I/O Abort" bitfld.long 0x00 21. " DP ,Data present select" "No transfer,Transfer" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCE ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select" "Single block,Multi block" bitfld.long 0x00 4. " DDIR ,Data transfer Direction" "Data Write,Data Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DE ,DMA Enable" "Disabled,Enabled" endif rgroup.long 0x0210++0x03 line.long 0x00 "SD_RSP10,This register holds bits positions [31:0] of command response type R1, R1b, R2, R3, R4, R5, R5b, or R6." hexmask.long.word 0x00 16.--31. 1. " RSP1 , Command Response [31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 , Command Response [15:0]" rgroup.long 0x0214++0x03 line.long 0x00 "SD_RSP32,This register holds bits positions [63:32] of command response type R2." hexmask.long.word 0x00 16.--31. 1. " RSP3 , Command Response [63:48]" hexmask.long.word 0x00 0.--15. 1. " RSP2 , Command Response [47:32]" rgroup.long 0x0218++0x03 line.long 0x00 "SD_RSP54,This register holds bits positions [95:64] of command response type R2." hexmask.long.word 0x00 16.--31. 1. " RSP5 , Command Response [95:80]" hexmask.long.word 0x00 0.--15. 1. " RSP4 , Command Response [79:64]" rgroup.long 0x021C++0x03 line.long 0x00 "SD_RSP76,This 32-bit register holds bits positions [127:96] of command response type R2." hexmask.long.word 0x00 16.--31. 1. " RSP7 , Command Response [127:112]" hexmask.long.word 0x00 0.--15. 1. " RSP6 , Command Response [111:96]" if (((d.l(ad:0x481D8000+0x0224))&0x800)==0x800)&&(((d.l(ad:0x481D8000+0x0224))&0x400)==0x400) group.long 0x0220++0x03 line.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" hexmask.long 0x00 0.--31. 1. " DATA , Data register [31:0]" elif (((d.l(ad:0x481D8000+0x0224))&0x800)==0x0)&&(((d.l(ad:0x481D8000+0x0224))&0x400)==0x400) wgroup.long 0x0220++0x03 line.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" hexmask.long 0x00 0.--31. 1. " DATA , Data register [31:0]" elif (((d.l(ad:0x481D8000+0x0224))&0x800)==0x800)&&(((d.l(ad:0x481D8000+0x0224))&0x400)==0x00) rgroup.long 0x0220++0x03 line.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" hexmask.long 0x00 0.--31. 1. " DATA , Data register [31:0]" else hgroup.long 0x0220++0x03 hide.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" endif if (((d.l(ad:0x481D8000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x481D8000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x481D8000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x481D8000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x481D8000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x481D8000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x481D8000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x481D8000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x481D8000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x481D8000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x481D8000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x481D8000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x481D8000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x481D8000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x481D8000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x481D8000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x481D8000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x481D8000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x481D8000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x481D8000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x481D8000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x481D8000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x481D8000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x481D8000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" endif if (((d.l(ad:0x481D8000+0x0228))&0x80)==0x80) group.long 0x0228++0x03 line.long 0x00 "SD_HCTL,This register defines the host controls to set power,wake-up and transfer parameters" bitfld.long 0x00 27. " OBWE ,Wake-up event enable for 'out-of-band' Interrupt" "Disabled,Enabled" bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CR ,Continue request" "No affect,Transfer restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stop at block gap" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select (All cards)" ",,,,,1.8 V,3.0 V,3.3 V" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "SDCD#,Detect Test Level" bitfld.long 0x00 6. " CDTL , Card Detect Test Level" "No card,Card inserted" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select" ",,32-bit," bitfld.long 0x00 2. " HSPE ,High Speed Enable" "Normal,High" bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit" else group.long 0x0228++0x03 line.long 0x00 "SD_HCTL,This register defines the host controls to set power,wake-up and transfer parameters" bitfld.long 0x00 27. " OBWE ,Wake-up event enable for 'out-of-band' Interrupt" "Disabled,Enabled" bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CR ,Continue request" "No affect,Transfer restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stop at block gap" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select (All cards)" ",,,,,1.8 V,3.0 V,3.3 V" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "SDCD#,Detect Test Level" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select" ",,32-bit," bitfld.long 0x00 2. " HSPE ,High Speed Enable" "Normal,High" bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit" endif group.long 0x022C++0x03 line.long 0x00 "SD_SYSCTL,This register defines the system controls to set software resets, clock frequency management and data timeout" bitfld.long 0x00 26. " SRD ,Software reset for mmc_dat line" "No reset,Reset" bitfld.long 0x00 25. " SRC ,Software reset for mmc_cmd line" "No reset,Reset" textline " " bitfld.long 0x00 24. " SRA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCF x 2^13,TCF x 2^14,,,,,,,,,,,,,TCF x 2^27," hexmask.long.word 0x00 6.--15. 1. " CLKD ,Clock frequency select" textline " " bitfld.long 0x00 2. " CEN ,Clock enable" "Not provided,Provided" rbitfld.long 0x00 1. " ICS ,Internal clock stable" "Not stable,Stable" bitfld.long 0x00 0. " ICE ,Internal clock enable" "Stopped,Oscillates" group.long 0x0230++0x03 line.long 0x00 "SD_STAT,The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x00 29. " BADA ,Bad access to data space" "No interrupt,Bad access" bitfld.long 0x00 28. " CERR ,Card error" "No error,Error" textline " " bitfld.long 0x00 25. " ADMAE ,ADMA Error" "No error,Error" bitfld.long 0x00 24. " ACE ,Auto CMD12 error" "No error,Error" textline " " bitfld.long 0x00 22. " DEB ,Data End Bit error" "No error,Error" bitfld.long 0x00 21. " DCRC ,Data CRC Error" "No error,Error" bitfld.long 0x00 20. " DTO ,Data timeout error" "No error,Error" bitfld.long 0x00 19. " CIE ,Command index error" "No error,Error" textline " " bitfld.long 0x00 18. " CEB ,Command end bit error" "No error,Error" bitfld.long 0x00 17. " CCRC ,Command CRC error" "No error,Error" bitfld.long 0x00 16. " CTO ,Command timeout error" "No error,Error" rbitfld.long 0x00 15. " ERRI ,Error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " BSR ,Boot Status Received Interrupt(MMC cards)" "No interrupt,Interrupt" rbitfld.long 0x00 9. " OBI ,Out-of-band interrupt(MMC cards)" "No interrupt,Interrupt" rbitfld.long 0x00 8. " CIRQ ,Card interrupt(SD and SDIO cards)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " CREM ,Card Removal" "State stable or debouncing,Card Removed" bitfld.long 0x00 6. " CINS , Card Insertion" "Stable or debouncing,Card inserted" bitfld.long 0x00 5. " BRR ,Buffer read ready" "Not ready,Ready" bitfld.long 0x00 4. " BWR ,Buffer write ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " DMA ,DMA Interrupt" "Interrupt,No interrupt" bitfld.long 0x00 2. " BGE ,Block gap event" "No block,Blocked" bitfld.long 0x00 1. " TC ,Transfer completed" "Not completed,Completed" bitfld.long 0x00 0. " CC ,Command complete" "Not completed,Completed" group.long 0x0234++0x03 line.long 0x00 "SD_IE,This register allows to enable/disable the module to set status bits, on an event-by-event basis" bitfld.long 0x00 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled" bitfld.long 0x00 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 25. " ADMA_ENABLE ,ADMA error Interrupt Enable" "Masked,Enabled" bitfld.long 0x00 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled" bitfld.long 0x00 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled" bitfld.long 0x00 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled" bitfld.long 0x00 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled" bitfld.long 0x00 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled" bitfld.long 0x00 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled" rbitfld.long 0x00 15. " NULL ,The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "0,1" textline " " bitfld.long 0x00 10. " BSR_ENABLE ,Boot Status Interrupt Enable" "Masked,Enabled" bitfld.long 0x00 9. " OBI_ENABLE ,Out-of-band interrupt enable" "Masked,Enabled" bitfld.long 0x00 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 7. " CREM_ENABLE ,Card Removal interrupt Enable" "Masked,Enabled" bitfld.long 0x00 6. " CINS_ENABLE ,Card Insertion interrupt Enable" "Masked,Enabled" bitfld.long 0x00 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled" bitfld.long 0x00 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled" bitfld.long 0x00 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled" bitfld.long 0x00 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled" bitfld.long 0x00 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled" group.long 0x0238++0x03 line.long 0x00 "SD_ISE,Register allows you to enable/disable the module to set status bits, on an event-by-event basis" bitfld.long 0x00 29. " BADA_SIGEN ,Bad access to data space interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " CERR_SIGEN ,Card error interrupt signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled" bitfld.long 0x00 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled" bitfld.long 0x00 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled" bitfld.long 0x00 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled" bitfld.long 0x00 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled" bitfld.long 0x00 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled" bitfld.long 0x00 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled" rbitfld.long 0x00 15. " NULL , Fixed to 0" "0,1" textline " " bitfld.long 0x00 10. " BSR_SIGEN ,Boot Status signal status enable" "Disabled,Enabled" bitfld.long 0x00 9. " OBI_SIGEN ,Out-of-band interrupt signal status enable" "Disabled,Enabled" bitfld.long 0x00 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CREM_SIGEN ,Card Removal signal status enable" "Disabled,Enabled" bitfld.long 0x00 6. " CINS_SIGEN ,Card Insertion signal status enable" "Disabled,Enabled" bitfld.long 0x00 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled" bitfld.long 0x00 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled" bitfld.long 0x00 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled" bitfld.long 0x00 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled" bitfld.long 0x00 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled" if (((d.l(ad:0x481D8000+0x020C))&0x4)==0x4)&&(((d.l(ad:0x481D8000+0x0230))&0x1000000)==0x1000000) rgroup.long 0x023C++0x03 line.long 0x00 "SD_AC12,SD_AC12 register" bitfld.long 0x00 7. " CNI ,Command not issue by auto CMD12 error" "No error,Error" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error" textline " " bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 2. " ACCE , Auto CMD12 CRC error" "No error,Error" bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " ACNE , Auto CMD12 not executed" "Executed,Not executed" else hgroup.long 0x023C++0x03 hide.long 0x00 "SD_AC12,SD_AC12 register" endif group.long 0x0240++0x03 line.long 0x00 "SD_CAPA,This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x00 28. " BUS_64BIT ,64 Bit System Bus Support" "32-bit,64-bit" textline " " bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" textline " " rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "No,Yes" rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High-speed support" "Not supported,Supported" textline " " rbitfld.long 0x00 19. " AD2S ,This bit indicates whether the Host Controller is capable of using ADMA2" "Not supported,Supported" rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes," textline " " rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "KHz,MHz" group.long 0x0248++0x03 line.long 0x00 "SD_CUR_CAPA,This register indicates the maximum current capability for each voltage" hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V" hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V" hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V" wgroup.long 0x0250++0x03 line.long 0x00 "SD_FE,Address which the Error Interrupt Status register can be written" bitfld.long 0x00 29. " FE_BADA ,Force Event Bad access to data space" "No effect,Forced" textline " " bitfld.long 0x00 28. " FE_CERR ,Force Event Card error" "No effect,Forced" bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error." "No effect,Forced" bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error" "No effect,Forced" textline " " bitfld.long 0x00 22. " FE_DEB ,Force Event Data End Bit error" "No effect,Forced" bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error" "No effect,Forced" bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error" "No effect,Forced" textline " " bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error" "No effect,Forced" bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error" "No effect,Forced" bitfld.long 0x00 17. " FE_CCRC ,Force Event Comemand CRC error" "No effect,Forced" bitfld.long 0x00 16. " FE_CTO ,Force Event Command Timeout error" "No effect,Forced" textline " " bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error" "No effect,Forced" bitfld.long 0x00 4. " FE_ACIE ,Force Event Auto CMD12 index error" "No effect,Forced" textline " " bitfld.long 0x00 3. " FE_ACEB ,Force Event Auto CMD12 end bit error" "No effect,Forced" bitfld.long 0x00 2. " FE_ACCE ,Force Event Auto CMD12 CRC error" "No effect,Forced" bitfld.long 0x00 1. " FE_ACTO ,Force Event Auto CMD12 timeout error" "No effect,Forced" bitfld.long 0x00 0. " FE_ACNE ,Force Event Auto CMD12 not executed" "No effect,Forced" group.long 0x0254++0x03 line.long 0x00 "SD_ADMAES,SD_ADMAES register" bitfld.long 0x00 2. " LME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "ST_STOP(Contents),ST_STOP(Points),,ST_TFR" group.long 0x0258++0x03 line.long 0x00 "SD_ADMASAL,This register holds the byte address of the executing command of the Descriptor table" group.long 0x025C++0x03 line.long 0x00 "SD_ADMASAH,SD_ADMASAH" rgroup.long 0x02FC++0x03 line.long 0x00 "SD_REV,This register contains the hard coded RTL vendor revision number" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number" bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Deasserted,Asserted" width 11. tree.end tree "MMCSD 1" base ad:0x47810000 width 14. group.long 0x0110++0x03 line.long 0x00 "SD_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power Management" "Force-standby,No-standby,Smart-standby,Smart-Standby wake-up-capable" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Int. and func. switched off,Int. maintained/Func. switched-off,Int. switched-off/Func. maintained,Int. and func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up," textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy" "Free-running,Gating strategy" rgroup.long 0x0114++0x03 line.long 0x00 "SD_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" group.long 0x0124++0x03 line.long 0x00 "SD_CSRE,This register enables the host controller to detect card status errors of response" if (((d.l(ad:0x47810000+0x0128))&0x8)==0x8) //this.DDIR== "Input" group.long 0x0128++0x03 line.long 0x00 "SD_SYSTEST,This register is used to control the signals that connect to I/O pins" bitfld.long 0x00 16. " OBI ,Out-of-band interrupt" "Low,High" textline " " bitfld.long 0x00 15. " SDCD ,Card detect input signal" "Low,High" bitfld.long 0x00 14. " SDWP ,Write protect input signal" "Low,High" bitfld.long 0x00 13. " WAKD ,Wake request output signal data value" "Low,High" bitfld.long 0x00 12. " SSB ,Set status bit" "Clear,Interrupt" textline " " bitfld.long 0x00 11. " D7D ,DAT7 input signal data value" "Low,High" bitfld.long 0x00 10. " D6D ,DAT6 input signal data value" "Low,High" bitfld.long 0x00 9. " D5D ,DAT5 input signal data value" "Low,High" bitfld.long 0x00 8. " D4D ,DAT4 input signal data value" "Low,High" textline " " bitfld.long 0x00 7. " D3D ,DAT3 input signal data value" "Low,High" bitfld.long 0x00 6. " D2D ,DAT2 input signal data value" "Low,High" bitfld.long 0x00 5. " D1D ,DAT1 input signal data value" "Low,High" bitfld.long 0x00 4. " D0D ,DAT0 input signal data value" "Low,High" textline " " bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value" "Low,High" bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction" "Output,Input" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value" "Low,High" else group.long 0x0128++0x03 line.long 0x00 "SD_SYSTEST,This register is used to control the signals that connect to I/O pins" bitfld.long 0x00 16. " OBI ,Out-of-band interrupt" "Low,High" textline " " bitfld.long 0x00 15. " SDCD ,Card detect input signal" "Low,High" bitfld.long 0x00 14. " SDWP ,Write protect input signal" "Low,High" bitfld.long 0x00 13. " WAKD ,Wake request output signal data value" "Low,High" bitfld.long 0x00 12. " SSB ,Set status bit" "Clear,Interrupt" textline " " bitfld.long 0x00 11. " D7D ,DAT7 output signal data value" "Low,High" bitfld.long 0x00 10. " D6D ,DAT6 output signal data value" "Low,High" bitfld.long 0x00 9. " D5D ,DAT5 output signal data value" "Low,High" bitfld.long 0x00 8. " D4D ,DAT4 output signal data value" "Low,High" textline " " bitfld.long 0x00 7. " D3D ,DAT3 output signal data value" "Low,High" bitfld.long 0x00 6. " D2D ,DAT2 output signal data value" "Low,High" bitfld.long 0x00 5. " D1D ,DAT1 output signal data value" "Low,High" bitfld.long 0x00 4. " D0D ,DAT0 output signal data value" "Low,High" textline " " bitfld.long 0x00 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input" bitfld.long 0x00 2. " CDAT ,CMD input/output signal data value" "Low,High" bitfld.long 0x00 1. " CDIR ,Control of the CMD pin direction" "Output,Input" bitfld.long 0x00 0. " MCKD ,MMC clock output signal data value" "Low,High" endif group.long 0x012C++0x03 line.long 0x00 "SD_CON,SD_CON register" bitfld.long 0x00 21. " SDMA_LnE ,Slave DMA Level/Edge Request" "Edge,Level" bitfld.long 0x00 20. " DMA_MnS ,DMA Master or Slave selection" "Slave,Not available" bitfld.long 0x00 19. " DDR ,Dual Data Rate mode" "Single edge,Both edges" bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status Supported" "Not forced,Released" textline " " bitfld.long 0x00 17. " BOOT_ACK ,Book acknowledge received" "No received,Received" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained" bitfld.long 0x00 15. " PADEN ,Control power for MMC lines" "Not forced,Forced" bitfld.long 0x00 12. " CEATA ,CE-ATA control mode (MMC cards compliant with CE-ATA)" "MMC/SD/SDIO,CE-ATA" textline " " bitfld.long 0x00 11. " CTPL ,Control Power for mmc_dat[1] line (SD cards)" "Disabled,Except mmc_dat[1]" bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value (all cards)" "33 us,231 us,1 ms,8.4 ms" bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low" bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low" textline " " bitfld.long 0x00 6. " MIT ,MMC interrupt command (MMC cards only)" "Disabled,Enabled" bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select (MMC cards only)" "1-bit or 4-bit,8-bit" bitfld.long 0x00 4. " MODE ,Mode select (all cards)" "Functional,SYSTEST" bitfld.long 0x00 3. " STR , Stream command (MMC cards only)" "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cards only)" "Not generated,Generated" bitfld.long 0x00 1. " INIT ,Send initialization stream (all cards)" "Not send,Send" bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cards only)" "Disabled,Enabled" group.long 0x0130++0x03 line.long 0x00 "SD_PWCNT,Mmc counter to delay command transfers after activating the PAD power" hexmask.long.word 0x00 0.--15. 1. " PWRCNT ,Power counter register" rgroup.long 0x0200++0x03 line.long 0x00 "SD_SDMASA,Mmc counter to delay command transfers after activating the PAD power" if (((d.l(ad:0x47810000+0x020C))&0x2)==0x2)&&(((d.l(ad:0x47810000+0x020C))&0x20)==0x20) //SD_CMD.BCE== Enabled && SD_CMD.MSBS== "Multi block" group.long 0x0204++0x03 line.long 0x00 "SD_BLK,Block size and count register" hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" else group.long 0x0204++0x03 line.long 0x00 "SD_BLK,Block size and count register" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" endif group.long 0x0208++0x03 line.long 0x00 "SD_ARG,This register contains command argument specified as bit 39-8 of Command-Format" hexmask.long 0x00 0.--31. 1. " ARG , Command argument bits [31:0]" if (((d.l(ad:0x47810000+0x020C))&0x20)==0x20) group.long 0x020C++0x03 line.long 0x00 "SD_CMD,This register configures the data and command transfers" hexmask.long.byte 0x00 24.--29. 1. " INDX , Command index binary encoded value from 0 to 63 specifying the command number send to card (CMD0 or ACMD0 to CMD63 or ACMD63)." bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type" "Others,Bus Suspend,Function Select,I/O Abort" bitfld.long 0x00 21. " DP ,Data present select" "No transfer,Transfer" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCE ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select" "Single block,Multi block" bitfld.long 0x00 4. " DDIR ,Data transfer Direction" "Data Write,Data Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " BCE ,Block Count Enable" "Disabled,Enabled" bitfld.long 0x00 0. " DE ,DMA Enable" "Disabled,Enabled" else group.long 0x020C++0x03 line.long 0x00 "SD_CMD,This register configures the data and command transfers" hexmask.long.byte 0x00 24.--29. 1. " INDX , Command index binary encoded value from 0 to 63 specifying the command number send to card (CMD0 or ACMD0 to CMD63 or ACMD63)." bitfld.long 0x00 22.--23. " CMD_TYPE ,Command type" "Others,Bus Suspend,Function Select,I/O Abort" bitfld.long 0x00 21. " DP ,Data present select" "No transfer,Transfer" textline " " bitfld.long 0x00 20. " CICE ,Command Index check enable" "Disabled,Enabled" bitfld.long 0x00 19. " CCCE ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x00 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy" textline " " bitfld.long 0x00 5. " MSBS ,Multi/Single block select" "Single block,Multi block" bitfld.long 0x00 4. " DDIR ,Data transfer Direction" "Data Write,Data Read" bitfld.long 0x00 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DE ,DMA Enable" "Disabled,Enabled" endif rgroup.long 0x0210++0x03 line.long 0x00 "SD_RSP10,This register holds bits positions [31:0] of command response type R1, R1b, R2, R3, R4, R5, R5b, or R6." hexmask.long.word 0x00 16.--31. 1. " RSP1 , Command Response [31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 , Command Response [15:0]" rgroup.long 0x0214++0x03 line.long 0x00 "SD_RSP32,This register holds bits positions [63:32] of command response type R2." hexmask.long.word 0x00 16.--31. 1. " RSP3 , Command Response [63:48]" hexmask.long.word 0x00 0.--15. 1. " RSP2 , Command Response [47:32]" rgroup.long 0x0218++0x03 line.long 0x00 "SD_RSP54,This register holds bits positions [95:64] of command response type R2." hexmask.long.word 0x00 16.--31. 1. " RSP5 , Command Response [95:80]" hexmask.long.word 0x00 0.--15. 1. " RSP4 , Command Response [79:64]" rgroup.long 0x021C++0x03 line.long 0x00 "SD_RSP76,This 32-bit register holds bits positions [127:96] of command response type R2." hexmask.long.word 0x00 16.--31. 1. " RSP7 , Command Response [127:112]" hexmask.long.word 0x00 0.--15. 1. " RSP6 , Command Response [111:96]" if (((d.l(ad:0x47810000+0x0224))&0x800)==0x800)&&(((d.l(ad:0x47810000+0x0224))&0x400)==0x400) group.long 0x0220++0x03 line.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" hexmask.long 0x00 0.--31. 1. " DATA , Data register [31:0]" elif (((d.l(ad:0x47810000+0x0224))&0x800)==0x0)&&(((d.l(ad:0x47810000+0x0224))&0x400)==0x400) wgroup.long 0x0220++0x03 line.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" hexmask.long 0x00 0.--31. 1. " DATA , Data register [31:0]" elif (((d.l(ad:0x47810000+0x0224))&0x800)==0x800)&&(((d.l(ad:0x47810000+0x0224))&0x400)==0x00) rgroup.long 0x0220++0x03 line.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" hexmask.long 0x00 0.--31. 1. " DATA , Data register [31:0]" else hgroup.long 0x0220++0x03 hide.long 0x00 "SD_DATA,This register is the 32-bit entry point of the buffer for read or write data transfers" endif if (((d.l(ad:0x47810000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x47810000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x47810000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x47810000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x47810000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x47810000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x47810000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x47810000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x47810000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x47810000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x47810000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x47810000+0x012C))&0x80)==0x80) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "Yes,No" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x47810000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x47810000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x47810000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x47810000+0x0224))&0x20000)==0x20000)&&(((d.l(ad:0x47810000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x47810000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "1,0" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x47810000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x47810000+0x012C))&0x100)==0x100)&&(((d.l(ad:0x47810000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Not protected,Protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" elif (((d.l(ad:0x47810000+0x0224))&0x20000)==0x00)&&(((d.l(ad:0x47810000+0x012C))&0x100)==0x00)&&(((d.l(ad:0x47810000+0x012C))&0x80)==0x0) group.long 0x0224++0x03 line.long 0x00 "SD_PSTATE,The Host can get the status of the Host controller from this register" bitfld.long 0x00 24. " CLEV ,Mmc_cmd line signal level" "0,1" bitfld.long 0x00 20.--23. " DLEV ,Mmc_dat[3:0] " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " WP ,Write Protect" "Protected,Not protected" textline " " bitfld.long 0x00 17. " CSS ,Card State Stable" "No,Stable" bitfld.long 0x00 16. " CINS ,Card inserted" "No,Yes" bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer Write enable" "Not enough,Enough" textline " " bitfld.long 0x00 9. " RTA ,Read transfer active" "No valid data,Read data" bitfld.long 0x00 8. " WTA ,Write transfer active" "No valid data,Write data" bitfld.long 0x00 1. " DATI ,Command inhibit (mmc_dat)" "Allowed,Not allowed" bitfld.long 0x00 2. " DLA ,Mmc_dat line active" "Inactive,Active" textline " " bitfld.long 0x00 0. " CMDI ,Command inhibit(mmc_cmd)" "Allowed,Not allowed" endif if (((d.l(ad:0x47810000+0x0228))&0x80)==0x80) group.long 0x0228++0x03 line.long 0x00 "SD_HCTL,This register defines the host controls to set power,wake-up and transfer parameters" bitfld.long 0x00 27. " OBWE ,Wake-up event enable for 'out-of-band' Interrupt" "Disabled,Enabled" bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CR ,Continue request" "No affect,Transfer restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stop at block gap" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select (All cards)" ",,,,,1.8 V,3.0 V,3.3 V" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "SDCD#,Detect Test Level" bitfld.long 0x00 6. " CDTL , Card Detect Test Level" "No card,Card inserted" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select" ",,32-bit," bitfld.long 0x00 2. " HSPE ,High Speed Enable" "Normal,High" bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit" else group.long 0x0228++0x03 line.long 0x00 "SD_HCTL,This register defines the host controls to set power,wake-up and transfer parameters" bitfld.long 0x00 27. " OBWE ,Wake-up event enable for 'out-of-band' Interrupt" "Disabled,Enabled" bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CR ,Continue request" "No affect,Transfer restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stop at block gap" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select (All cards)" ",,,,,1.8 V,3.0 V,3.3 V" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On" bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "SDCD#,Detect Test Level" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select" ",,32-bit," bitfld.long 0x00 2. " HSPE ,High Speed Enable" "Normal,High" bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit" endif group.long 0x022C++0x03 line.long 0x00 "SD_SYSCTL,This register defines the system controls to set software resets, clock frequency management and data timeout" bitfld.long 0x00 26. " SRD ,Software reset for mmc_dat line" "No reset,Reset" bitfld.long 0x00 25. " SRC ,Software reset for mmc_cmd line" "No reset,Reset" textline " " bitfld.long 0x00 24. " SRA ,Software reset for all" "No reset,Reset" bitfld.long 0x00 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCF x 2^13,TCF x 2^14,,,,,,,,,,,,,TCF x 2^27," hexmask.long.word 0x00 6.--15. 1. " CLKD ,Clock frequency select" textline " " bitfld.long 0x00 2. " CEN ,Clock enable" "Not provided,Provided" rbitfld.long 0x00 1. " ICS ,Internal clock stable" "Not stable,Stable" bitfld.long 0x00 0. " ICE ,Internal clock enable" "Stopped,Oscillates" group.long 0x0230++0x03 line.long 0x00 "SD_STAT,The interrupt status regroups all the status of the module internal events that can generate an interrupt" bitfld.long 0x00 29. " BADA ,Bad access to data space" "No interrupt,Bad access" bitfld.long 0x00 28. " CERR ,Card error" "No error,Error" textline " " bitfld.long 0x00 25. " ADMAE ,ADMA Error" "No error,Error" bitfld.long 0x00 24. " ACE ,Auto CMD12 error" "No error,Error" textline " " bitfld.long 0x00 22. " DEB ,Data End Bit error" "No error,Error" bitfld.long 0x00 21. " DCRC ,Data CRC Error" "No error,Error" bitfld.long 0x00 20. " DTO ,Data timeout error" "No error,Error" bitfld.long 0x00 19. " CIE ,Command index error" "No error,Error" textline " " bitfld.long 0x00 18. " CEB ,Command end bit error" "No error,Error" bitfld.long 0x00 17. " CCRC ,Command CRC error" "No error,Error" bitfld.long 0x00 16. " CTO ,Command timeout error" "No error,Error" rbitfld.long 0x00 15. " ERRI ,Error interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " BSR ,Boot Status Received Interrupt(MMC cards)" "No interrupt,Interrupt" rbitfld.long 0x00 9. " OBI ,Out-of-band interrupt(MMC cards)" "No interrupt,Interrupt" rbitfld.long 0x00 8. " CIRQ ,Card interrupt(SD and SDIO cards)" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " CREM ,Card Removal" "State stable or debouncing,Card Removed" bitfld.long 0x00 6. " CINS , Card Insertion" "Stable or debouncing,Card inserted" bitfld.long 0x00 5. " BRR ,Buffer read ready" "Not ready,Ready" bitfld.long 0x00 4. " BWR ,Buffer write ready" "Not ready,Ready" textline " " bitfld.long 0x00 3. " DMA ,DMA Interrupt" "Interrupt,No interrupt" bitfld.long 0x00 2. " BGE ,Block gap event" "No block,Blocked" bitfld.long 0x00 1. " TC ,Transfer completed" "Not completed,Completed" bitfld.long 0x00 0. " CC ,Command complete" "Not completed,Completed" group.long 0x0234++0x03 line.long 0x00 "SD_IE,This register allows to enable/disable the module to set status bits, on an event-by-event basis" bitfld.long 0x00 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled" bitfld.long 0x00 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 25. " ADMA_ENABLE ,ADMA error Interrupt Enable" "Masked,Enabled" bitfld.long 0x00 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled" bitfld.long 0x00 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled" bitfld.long 0x00 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled" bitfld.long 0x00 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled" bitfld.long 0x00 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled" bitfld.long 0x00 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled" rbitfld.long 0x00 15. " NULL ,The host driver shall control error interrupts using the Error Interrupt Signal Enable register" "0,1" textline " " bitfld.long 0x00 10. " BSR_ENABLE ,Boot Status Interrupt Enable" "Masked,Enabled" bitfld.long 0x00 9. " OBI_ENABLE ,Out-of-band interrupt enable" "Masked,Enabled" bitfld.long 0x00 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 7. " CREM_ENABLE ,Card Removal interrupt Enable" "Masked,Enabled" bitfld.long 0x00 6. " CINS_ENABLE ,Card Insertion interrupt Enable" "Masked,Enabled" bitfld.long 0x00 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled" bitfld.long 0x00 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x00 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled" bitfld.long 0x00 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled" bitfld.long 0x00 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled" bitfld.long 0x00 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled" group.long 0x0238++0x03 line.long 0x00 "SD_ISE,Register allows you to enable/disable the module to set status bits, on an event-by-event basis" bitfld.long 0x00 29. " BADA_SIGEN ,Bad access to data space interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " CERR_SIGEN ,Card error interrupt signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled" bitfld.long 0x00 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled" bitfld.long 0x00 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled" bitfld.long 0x00 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled" bitfld.long 0x00 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled" bitfld.long 0x00 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled" bitfld.long 0x00 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled" rbitfld.long 0x00 15. " NULL , Fixed to 0" "0,1" textline " " bitfld.long 0x00 10. " BSR_SIGEN ,Boot Status signal status enable" "Disabled,Enabled" bitfld.long 0x00 9. " OBI_SIGEN ,Out-of-band interrupt signal status enable" "Disabled,Enabled" bitfld.long 0x00 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CREM_SIGEN ,Card Removal signal status enable" "Disabled,Enabled" bitfld.long 0x00 6. " CINS_SIGEN ,Card Insertion signal status enable" "Disabled,Enabled" bitfld.long 0x00 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled" bitfld.long 0x00 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled" bitfld.long 0x00 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled" bitfld.long 0x00 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled" bitfld.long 0x00 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled" if (((d.l(ad:0x47810000+0x020C))&0x4)==0x4)&&(((d.l(ad:0x47810000+0x0230))&0x1000000)==0x1000000) rgroup.long 0x023C++0x03 line.long 0x00 "SD_AC12,SD_AC12 register" bitfld.long 0x00 7. " CNI ,Command not issue by auto CMD12 error" "No error,Error" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error" textline " " bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 2. " ACCE , Auto CMD12 CRC error" "No error,Error" bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " ACNE , Auto CMD12 not executed" "Executed,Not executed" else hgroup.long 0x023C++0x03 hide.long 0x00 "SD_AC12,SD_AC12 register" endif group.long 0x0240++0x03 line.long 0x00 "SD_CAPA,This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x00 28. " BUS_64BIT ,64 Bit System Bus Support" "32-bit,64-bit" textline " " bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported" textline " " rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "No,Yes" rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported" rbitfld.long 0x00 21. " HSS ,High-speed support" "Not supported,Supported" textline " " rbitfld.long 0x00 19. " AD2S ,This bit indicates whether the Host Controller is capable of using ADMA2" "Not supported,Supported" rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes," textline " " rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "KHz,MHz" group.long 0x0248++0x03 line.long 0x00 "SD_CUR_CAPA,This register indicates the maximum current capability for each voltage" hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V" hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V" hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V" wgroup.long 0x0250++0x03 line.long 0x00 "SD_FE,Address which the Error Interrupt Status register can be written" bitfld.long 0x00 29. " FE_BADA ,Force Event Bad access to data space" "No effect,Forced" textline " " bitfld.long 0x00 28. " FE_CERR ,Force Event Card error" "No effect,Forced" bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error." "No effect,Forced" bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error" "No effect,Forced" textline " " bitfld.long 0x00 22. " FE_DEB ,Force Event Data End Bit error" "No effect,Forced" bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error" "No effect,Forced" bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error" "No effect,Forced" textline " " bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error" "No effect,Forced" bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error" "No effect,Forced" bitfld.long 0x00 17. " FE_CCRC ,Force Event Comemand CRC error" "No effect,Forced" bitfld.long 0x00 16. " FE_CTO ,Force Event Command Timeout error" "No effect,Forced" textline " " bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error" "No effect,Forced" bitfld.long 0x00 4. " FE_ACIE ,Force Event Auto CMD12 index error" "No effect,Forced" textline " " bitfld.long 0x00 3. " FE_ACEB ,Force Event Auto CMD12 end bit error" "No effect,Forced" bitfld.long 0x00 2. " FE_ACCE ,Force Event Auto CMD12 CRC error" "No effect,Forced" bitfld.long 0x00 1. " FE_ACTO ,Force Event Auto CMD12 timeout error" "No effect,Forced" bitfld.long 0x00 0. " FE_ACNE ,Force Event Auto CMD12 not executed" "No effect,Forced" group.long 0x0254++0x03 line.long 0x00 "SD_ADMAES,SD_ADMAES register" bitfld.long 0x00 2. " LME ,ADMA Length Mismatch Error" "No error,Error" bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "ST_STOP(Contents),ST_STOP(Points),,ST_TFR" group.long 0x0258++0x03 line.long 0x00 "SD_ADMASAL,This register holds the byte address of the executing command of the Descriptor table" group.long 0x025C++0x03 line.long 0x00 "SD_ADMASAH,SD_ADMASAH" rgroup.long 0x02FC++0x03 line.long 0x00 "SD_REV,This register contains the hard coded RTL vendor revision number" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number" bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Deasserted,Asserted" width 11. tree.end tree.end tree "IC(Interprocessor Communication)" tree "Mailbox" width 18. rgroup.long 0x000++0x03 line.long 0x00 "MLB_REVISION,This register contains the IP revision code" bitfld.long 0x00 30.--31. " SCHEME , Not defined yet" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC , Not defined yet" bitfld.long 0x00 11.--15. " RTL , Not defined yet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR , IP-Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Not Defined Yet" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , IP-Minor Revision" group.long 0x010++0x03 line.long 0x00 "MLB_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x00 2.--3. " SIDLEMODE ,SIDLEMODE" "0,1,2,3" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x040++0x03 line.long 0x00 "MLB_MESSAGE_0,The message register stores the next to be read message of the mailbox" group.long 0x044++0x03 line.long 0x00 "MLB_MESSAGE_1,The message register stores the next to be read message of the mailbox" group.long 0x048++0x03 line.long 0x00 "MLB_MESSAGE_2,The message register stores the next to be read message of the mailbox" group.long 0x04C++0x03 line.long 0x00 "MLB_MESSAGE_3,The message register stores the next to be read message of the mailbox" group.long 0x050++0x03 line.long 0x00 "MLB_MESSAGE_4,The message register stores the next to be read message of the mailbox" group.long 0x054++0x03 line.long 0x00 "MLB_MESSAGE_5,The message register stores the next to be read message of the mailbox" group.long 0x058++0x03 line.long 0x00 "MLB_MESSAGE_6,The message register stores the next to be read message of the mailbox" group.long 0x05C++0x03 line.long 0x00 "MLB_MESSAGE_7,The message register stores the next to be read message of the mailbox" group.long 0x080++0x03 line.long 0x00 "MLB_FIFOSTS_0,The message register stores the next to be read message of the mailbox" hexmask.long 0x00 1.--31. 1. " MESSAGEVALUEMBM , Message in Mailbox" rbitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox" "Not full,Full" group.long 0x084++0x03 line.long 0x00 "MLB_FIFOSTS_1,The message register stores the next to be read message of the mailbox" hexmask.long 0x00 1.--31. 1. " MESSAGEVALUEMBM , Message in Mailbox" rbitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox" "Not full,Full" group.long 0x088++0x03 line.long 0x00 "MLB_FIFOSTS_2,The message register stores the next to be read message of the mailbox" hexmask.long 0x00 1.--31. 1. " MESSAGEVALUEMBM , Message in Mailbox" rbitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox" "Not full,Full" group.long 0x08C++0x03 line.long 0x00 "MLB_FIFOSTS_3,The message register stores the next to be read message of the mailbox" hexmask.long 0x00 1.--31. 1. " MESSAGEVALUEMBM , Message in Mailbox" rbitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox" "Not full,Full" group.long 0x090++0x03 line.long 0x00 "MLB_FIFOSTS_4,The message register stores the next to be read message of the mailbox" hexmask.long 0x00 1.--31. 1. " MESSAGEVALUEMBM , Message in Mailbox" rbitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox" "Not full,Full" group.long 0x094++0x03 line.long 0x00 "MLB_FIFOSTS_5,The message register stores the next to be read message of the mailbox" hexmask.long 0x00 1.--31. 1. " MESSAGEVALUEMBM , Message in Mailbox" rbitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox" "Not full,Full" group.long 0x098++0x03 line.long 0x00 "MLB_FIFOSTS_6,The message register stores the next to be read message of the mailbox" hexmask.long 0x00 1.--31. 1. " MESSAGEVALUEMBM , Message in Mailbox" rbitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox" "Not full,Full" group.long 0x09C++0x03 line.long 0x00 "MLB_FIFOSTS_7,The message register stores the next to be read message of the mailbox" hexmask.long 0x00 1.--31. 1. " MESSAGEVALUEMBM , Message in Mailbox" rbitfld.long 0x00 0. " FIFOFULLMBM ,Full flag for Mailbox" "Not full,Full" rgroup.long 0x0C0++0x03 line.long 0x00 "MLB_MSGSTS_0,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. " NBOFMSGMBM , Number of unread messages in Mailbox" "0,1,2,3,4,,," rgroup.long 0x0C4++0x03 line.long 0x00 "MLB_MSGSTS_1,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. " NBOFMSGMBM , Number of unread messages in Mailbox" "0,1,2,3,4,,," rgroup.long 0x0C8++0x03 line.long 0x00 "MLB_MSGSTS_2,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. " NBOFMSGMBM , Number of unread messages in Mailbox" "0,1,2,3,4,,," rgroup.long 0x0CC++0x03 line.long 0x00 "MLB_MSGSTS_3,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. " NBOFMSGMBM , Number of unread messages in Mailbox" "0,1,2,3,4,,," rgroup.long 0x0D0++0x03 line.long 0x00 "MLB_MSGSTS_4,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. " NBOFMSGMBM , Number of unread messages in Mailbox" "0,1,2,3,4,,," rgroup.long 0x0D4++0x03 line.long 0x00 "MLB_MSGSTS_5,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. " NBOFMSGMBM , Number of unread messages in Mailbox" "0,1,2,3,4,,," rgroup.long 0x0D8++0x03 line.long 0x00 "MLB_MSGSTS_6,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. " NBOFMSGMBM , Number of unread messages in Mailbox" "0,1,2,3,4,,," rgroup.long 0x0DC++0x03 line.long 0x00 "MLB_MSGSTS_7,The message status register has the status of the messages in the mailbox" bitfld.long 0x00 0.--2. " NBOFMSGMBM , Number of unread messages in Mailbox" "0,1,2,3,4,,," group.long 0x100++0x03 line.long 0x00 "MLB_IRQSTS_RAW_0,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x104++0x03 line.long 0x00 "MLB_IRQSTS_CLR_0,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x108++0x03 line.long 0x00 "MLB_IRQEN_SET_0,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x10C++0x03 line.long 0x00 "MLB_IRQEN_CLR_0,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" textline "" group.long 0x110++0x03 line.long 0x00 "MLB_IRQSTS_RAW_1,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x114++0x03 line.long 0x00 "MLB_IRQSTS_CLR_1,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x118++0x03 line.long 0x00 "MLB_IRQEN_SET_1,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x11C++0x03 line.long 0x00 "MLB_IRQEN_CLR_1,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" textline "" group.long 0x120++0x03 line.long 0x00 "MLB_IRQSTS_RAW_2,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x124++0x03 line.long 0x00 "MLB_IRQSTS_CLR_2,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x128++0x03 line.long 0x00 "MLB_IRQEN_SET_2,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x12C++0x03 line.long 0x00 "MLB_IRQEN_CLR_2,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" textline "" group.long 0x130++0x03 line.long 0x00 "MLB_IRQSTS_RAW_3,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x134++0x03 line.long 0x00 "MLB_IRQSTS_CLR_3,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x138++0x03 line.long 0x00 "MLB_IRQEN_SET_3,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" group.long 0x13C++0x03 line.long 0x00 "MLB_IRQEN_CLR_3,The interrupt status register" bitfld.long 0x00 15. " NOTFULLSTSUUMB7 ,Not Full Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 14. " NEWMSGSTSUUMB7 ,New Message Status bit for User u, Mailbox 7" "No action,Set" bitfld.long 0x00 13. " NOTFULLSTSUUMB6 ,Not Full Status bit for User u, Mailbox 6" "No action,Set" bitfld.long 0x00 12. " NEWMSGSTSUUMB6 ,New Message Status bit for User u, Mailbox 6" "No action,Set" textline " " bitfld.long 0x00 11. " NOTFULLSTSUUMB5 ,Not Full Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 10. " NEWMSGSTSUUMB5 ,New Message Status bit for User u, Mailbox 5" "No action,Set" bitfld.long 0x00 9. " NOTFULLSTSUUMB4 ,Not Full Status bit for User u, Mailbox 4" "No action,Set" bitfld.long 0x00 8. " NEWMSGSTSUUMB4 ,New Message Status bit for User u, Mailbox 4" "No action,Set" textline " " bitfld.long 0x00 7. " NOTFULLSTSUUMB3 ,Not Full Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 6. " NEWMSGSTSUUMB3 ,New Message Status bit for User u, Mailbox 3" "No action,Set" bitfld.long 0x00 5. " NOTFULLSTSUUMB2 ,Not Full Status bit for User u, Mailbox 2" "No action,Set" bitfld.long 0x00 4. " NEWMSGSTSUUMB2 ,New Message Status bit for User u, Mailbox 2" "No action,Set" textline " " bitfld.long 0x00 3. " NOTFULLSTSUUMB1 ,Not Full Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 2. " NEWMSGSTSUUMB1 ,New Message Status bit for User u, Mailbox 1" "No action,Set" bitfld.long 0x00 1. " NOTFULLSTSUUMB0 ,Not Full Status bit for User u, Mailbox 0" "No action,Set" bitfld.long 0x00 0. " NEWMSGSTSUUMB0 ,New Message Status bit for User u, Mailbox 0" "No action,Set" tree.end tree "Spinlock" base ad:0x480CA000 width 20. rgroup.long 0x000++0x03 line.long 0x00 "SPINLOCK_REV,IP revision identifier" group.long 0x010++0x03 line.long 0x00 "SPINLOCK_SYSCONFIG,This register controls the various parameters of the OCP interface" rbitfld.long 0x00 8. " CLOCKACTIVITY ,Indicates whether the module requires the OCP when in IDLE mode" "Off,On" rbitfld.long 0x00 3.--4. " SIDLEMODE ,Control of the slave interface power management IDLE request acknowledgement" "Immediately,Never,Internal module," rbitfld.long 0x00 2. " ENWAKEUP ,Asynchronous wakeup gereration" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Module software reset" "No reset,Reset" rbitfld.long 0x00 0. " AUTOGATING ,Internal OCP clock gating strategy" "Not gated,Gating" rgroup.long 0x014++0x03 line.long 0x00 "SPINLOCK_SYSTS,This register provides status information about this instance of the Spin Lock module." hexmask.long.byte 0x00 24.--31. 1. " NUMLOCKS ,NUMLOCKS" bitfld.long 0x00 15. " IU7 ,In-Use flag 7" "No locked,Locked" bitfld.long 0x00 14. " IU6 ,In-Use flag 6" "No locked,Locked" textline " " bitfld.long 0x00 13. " IU5 ,In-Use flag 5" "No locked,Locked" bitfld.long 0x00 12. " IU4 ,In-Use flag 4" "No locked,Locked" bitfld.long 0x00 11. " IU3 ,In-Use flag 3" "No locked,Locked" bitfld.long 0x00 10. " IU2 ,In-Use flag 2" "No locked,Locked" textline " " bitfld.long 0x00 9. " IU1 , In-Use flag 1" "No locked,Locked" bitfld.long 0x00 8. " IU0 , In-Use flag 0" "No locked,Locked" bitfld.long 0x00 0. " RESETDONE ,Reset status" "In progress,Completed" group.long 0x800++0x03 line.long 0x00 "SPINLOCK_REG_0,SPINLOCK_REG_0" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x804++0x03 line.long 0x00 "SPINLOCK_REG_1,SPINLOCK_REG_1" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x808++0x03 line.long 0x00 "SPINLOCK_REG_2,SPINLOCK_REG_2" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x80C++0x03 line.long 0x00 "SPINLOCK_REG_3,SPINLOCK_REG_3" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x810++0x03 line.long 0x00 "SPINLOCK_REG_4,SPINLOCK_REG_4" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x814++0x03 line.long 0x00 "SPINLOCK_REG_5,SPINLOCK_REG_5" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x818++0x03 line.long 0x00 "SPINLOCK_REG_6,SPINLOCK_REG_6" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x81C++0x03 line.long 0x00 "SPINLOCK_REG_7,SPINLOCK_REG_7" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x820++0x03 line.long 0x00 "SPINLOCK_REG_8,SPINLOCK_REG_8" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x824++0x03 line.long 0x00 "SPINLOCK_REG_9,SPINLOCK_REG_9" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x828++0x03 line.long 0x00 "SPINLOCK_REG_10,SPINLOCK_REG_10" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x82C++0x03 line.long 0x00 "SPINLOCK_REG_11,SPINLOCK_REG_11" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x830++0x03 line.long 0x00 "SPINLOCK_REG_12,SPINLOCK_REG_12" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x834++0x03 line.long 0x00 "SPINLOCK_REG_13,SPINLOCK_REG_13" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x838++0x03 line.long 0x00 "SPINLOCK_REG_14,SPINLOCK_REG_14" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x83C++0x03 line.long 0x00 "SPINLOCK_REG_15,SPINLOCK_REG_15" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x840++0x03 line.long 0x00 "SPINLOCK_REG_16,SPINLOCK_REG_16" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x844++0x03 line.long 0x00 "SPINLOCK_REG_17,SPINLOCK_REG_17" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x848++0x03 line.long 0x00 "SPINLOCK_REG_18,SPINLOCK_REG_18" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x84C++0x03 line.long 0x00 "SPINLOCK_REG_19,SPINLOCK_REG_19" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x850++0x03 line.long 0x00 "SPINLOCK_REG_20,SPINLOCK_REG_20" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x854++0x03 line.long 0x00 "SPINLOCK_REG_21,SPINLOCK_REG_21" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x858++0x03 line.long 0x00 "SPINLOCK_REG_22,SPINLOCK_REG_22" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x85C++0x03 line.long 0x00 "SPINLOCK_REG_23,SPINLOCK_REG_23" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x860++0x03 line.long 0x00 "SPINLOCK_REG_24,SPINLOCK_REG_24" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x864++0x03 line.long 0x00 "SPINLOCK_REG_25,SPINLOCK_REG_25" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x868++0x03 line.long 0x00 "SPINLOCK_REG_26,SPINLOCK_REG_26" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x86C++0x03 line.long 0x00 "SPINLOCK_REG_27,SPINLOCK_REG_27" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x870++0x03 line.long 0x00 "SPINLOCK_REG_28,SPINLOCK_REG_28" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x874++0x03 line.long 0x00 "SPINLOCK_REG_29,SPINLOCK_REG_29" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x878++0x03 line.long 0x00 "SPINLOCK_REG_30,SPINLOCK_REG_30" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" group.long 0x87C++0x03 line.long 0x00 "SPINLOCK_REG_31,SPINLOCK_REG_31" bitfld.long 0x00 0. " TAKEN ,TAKEN" "Not taken,Taken" width 11. tree.end tree.end tree "TIMERS" tree "DMTIMER" tree "DMTIMER 0" base ad:0x44E05000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 1MS" base ad:0x44E31000 width 23. rgroup.long 0x000++0x03 line.long 0x00 "DMTIMER_1MS_TIDR,This register contains the IP revision code" hexmask.long.byte 0x00 0.--7. 1. " TID_REV , IP revision" group.long 0x010++0x03 line.long 0x00 "DMTIMER_1MS_TIOCP_CFG,This register controls the various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,CLOCKACTIVITY" "0,1,2,3" bitfld.long 0x00 5. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Free-running" bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management req/ack control" "Force-idle,No-idle,Smart-idle," textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "No wakeup,Wakeup" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Free-running,Gating strategy" rgroup.long 0x014++0x03 line.long 0x00 "DMTIMER_1MS_TISTAT,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed" group.long 0x018++0x03 line.long 0x00 "DMTIMER_1MS_TISR,The Timer Status Register is used to determine which of the timer events requested an interrupt." bitfld.long 0x00 2. " TCAR_IT_FLAG ,Indicates when an external pulse transition of the correct polarity is detected on the external pin PIEVENTCAPT" "No capture,Capture" bitfld.long 0x00 1. " OVF_IT_FLAG ,TCRR overflow" "No overflow,Overflow" bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare result of TCRR and TMAR " "No compare,Compare" group.long 0x01C++0x03 line.long 0x00 "DMTIMER_1MS_TIER,This register controls (enable/disable) the interrupt events" bitfld.long 0x00 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled" group.long 0x020++0x03 line.long 0x00 "DMTIMER_1MS_TWER,This register controls (enable/disable) the wakeup feature on specific interrupt events" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled" group.long 0x024++0x03 line.long 0x00 "DMTIMER_1MS_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 14. " GPO_CFG ,GPO_CFG" "0,1" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "First,Second" bitfld.long 0x00 12. " PT ,Pulse or Toggle select bit" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger Output Mode" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode" "No capture,Rising edges,Falling edges,Booth edges" bitfld.long 0x00 7. " SCPWM ,Pulse Width Modulation output pin default value" "0,1" textline " " bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV , Trigger Output Mode" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x028++0x03 line.long 0x00 "DMTIMER_1MS_TCRR,This register holds the value of the internal counter" group.long 0x02C++0x03 line.long 0x00 "DMTIMER_1MS_TLDR,This register holds the timer's load value" group.long 0x030++0x03 line.long 0x00 "DMTIMER_1MS_TTGR,This register triggers a counter reload of timer by writing any value in it." rgroup.long 0x034++0x03 line.long 0x00 "DMTIMER_1MS_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 9. " W_PEND_TOWR ,Write pending for register TOWR" "No Overflow,Overflow" bitfld.long 0x00 8. " W_PEND_TOCR ,Write pending for register TOCR" "No Overflow,Overflow" bitfld.long 0x00 7. " W_PEND_TCVR ,Write pending for register TCVR" "No,Yes" textline " " bitfld.long 0x00 6. " W_PEND_TNIR ,Write pending for register TNIR" "No Negativ,Negativ" bitfld.long 0x00 5. " W_PEND_TPIR ,Write pending for register TPIR" "No Positive,Positive" bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "No Match,Match" textline " " bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "No Trigger,Trigger" bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "No Load,Load" bitfld.long 0x00 1. " W_PEND_TCRR ,Counter Register write pending" "0,1" textline " " bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "No control,Control" group.long 0x038++0x03 line.long 0x00 "DMTIMER_1MS_TMAR,This register holds the match value to be compared with the counter's value" rgroup.long 0x03C++0x03 line.long 0x00 "DMTIMER_1MS_TCAR1,This register holds the value of the first counter register capture" group.long 0x040++0x03 line.long 0x00 "DMTIMER_1MS_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,PIFREQRATIO" "Inactive,Active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x044++0x03 line.long 0x00 "DMTIMER_1MS_TCAR2,This register holds the value of the second counter register capture" group.long 0x048++0x03 line.long 0x00 "DMTIMER_1MS_TPIR,The TPIR register holds the value of the positive increment" group.long 0x04C++0x03 line.long 0x00 "DMTIMER_1MS_TNIR,The TNIR register holds the value of the negative increment" group.long 0x050++0x03 line.long 0x00 "DMTIMER_1MS_TCVR,The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value" group.long 0x054++0x03 line.long 0x00 "DMTIMER_1MS_TOCR,This register is used to mask the tick interrupt for a selected number of ticks" hexmask.long.tbyte 0x00 0.--23. 1. " OVF_CTR_VALUE , The number of overflow events" group.long 0x058++0x03 line.long 0x00 "DMTIMER_1MS_TOWR,This register holds the number of masked overflow interrupts" hexmask.long.tbyte 0x00 0.--23. 1. " OVF_WRAPPING_VALUE , The number of masked interrupts" width 11. tree.end tree "DMTIMER 2" base ad:0x48040000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 3" base ad:0x48042000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 4" base ad:0x48044000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 5" base ad:0x48046000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 6" base ad:0x48048000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 7" base ad:0x4804A000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 8" base ad:0x481C1000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 9" base ad:0x4833D000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 10" base ad:0x4833F000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree "DMTIMER 11" base ad:0x48341000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "DMTIMER_TIDR,Revision number of the module" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "DMTIMER_TIOCP_CFG,Various parameters of the OCP interface" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management req/ack control" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" bitfld.long 0x00 1. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Runs free" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Done,Initiate" group.long 0x20++0x03 line.long 0x00 "DMTIMER_IRQ_EOI,Software End-Of-Interrupt" bitfld.long 0x00 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it" "SW EOI,No action" group.long 0x24++0x03 line.long 0x00 "DMTIMER_IRQSTS_RAW,Component interrupt request status" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Set" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Set" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Set" group.long 0x28++0x03 line.long 0x00 "DMTIMER_IRQSTS,Component interrupt request status Write 1 to clear" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No action,Clear" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No action,Clear" group.long 0x2C++0x03 line.long 0x00 "DMTIMER_IRQEN_SET,Component interrupt request enable" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Enabled" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Enabled" group.long 0x30++0x03 line.long 0x00 "DMTIMER_IRQEN_CLR,Component interrupt request enable Write 1 to clear" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "No action,Clear" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "No action,Clear" bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "No action,Clear" group.long 0x34++0x03 line.long 0x00 "DMTIMER_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "DMTIMER_TCLR,This register controls optional features specific to the timer functionality" bitfld.long 0x00 15. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 14. " IODIRECTION ,Drives the direction for TriState buffers" "Output,Input" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select bit (first/second)" "Single capture,Second event" bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" textline " " bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,Overflow,Overflow and match," bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,Low to high transition,Both edge transition,Booth edges of PIEVETCAPT" bitfld.long 0x00 7. " SCPWM ,This bit should be set or clear while the timer is stopped or the trigger is off" "Clear,Set" bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot timer,Auto-reload timer" bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stop,Start" group.long 0x3C++0x03 line.long 0x00 "DMTIMER_TCRR,This register holds the value of the internal counter" group.long 0x40++0x03 line.long 0x00 "DMTIMER_TLDR,This register holds the timer's load value" group.long 0x44++0x03 line.long 0x00 "DMTIMER_TTGR,DMTIMER_TTGR register" rgroup.long 0x48++0x03 line.long 0x00 "DMTIMER_TWPS,This register contains the write posting bits for all writ-able functional registers" bitfld.long 0x00 4. " W_PEND_TMAR ,Pending to the TMAR register" "Not pended,Pended" bitfld.long 0x00 3. " W_PEND_TTGR ,Pending to the TTGR register" "Not pended,Pended" bitfld.long 0x00 2. " W_PEND_TLDR ,Pending to the TLDR register" "Not pended,Pended" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Pending to the TCRR register" "Not pended,Pended" bitfld.long 0x00 0. " W_PEND_TCLR ,Pending to the TCLR register" "Not pended,Pended" rgroup.long 0x4C++0x03 line.long 0x00 "DMTIMER_TMAR,The compare logic consists of a 32-bit wide, read/write data TMAR register and logic to compare counter" rgroup.long 0x50++0x03 line.long 0x00 "DMTIMER_TCAR1,Timer counter value captured on an external event trigger" group.long 0x54++0x03 line.long 0x00 "DMTIMER_TSICR,Timer Synchronous Interface Control Register" bitfld.long 0x00 2. " POSTED ,Reset value of POSTED depends on hardware integration module at design time" "Mode inactive,Mode active" bitfld.long 0x00 1. " SFT ,This bit reset all the functional part of the module" "Disabled,Enabled" rgroup.long 0x58++0x03 line.long 0x00 "DMTIMER_TCAR2,Timer counter value captured on an external event trigger" width 11. tree.end tree.end tree "Sync Timer" base ad:0x44E86000 width 25. rgroup.long 0x00++0x03 line.long 0x00 "SYNCTIMER32K_SYNCNT_REV," hexmask.long.byte 0x00 0.--7. 1. " CID_REV , Revision number" group.long 0x04++0x03 line.long 0x00 "SYNCTIMER32K_SYSCONFIG," bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management Req/Ack Control" "Force idle,No-idle,," rgroup.long 0x10++0x03 line.long 0x00 "SYNCTIMER32K_CR," hexmask.long.word 0x00 16.--31. 1. " CTR_HI , Read counter high" hexmask.long.word 0x00 0.--15. 1. " CTR_LO , Read counter low" width 11. tree.end tree "RTC(Real-Time Clock)" base ad:0x44E3E000 width 26. group.long 0x000++0x03 line.long 0x00 "RTCSS_SECONDS_REG,SECONDS_REG is used to program the required seconds value of the current time" bitfld.long 0x00 4.--6. " SEC1 ,2nd digit of seconds" "0,1,2,3,4,5,," bitfld.long 0x00 0.--3. " SEC0 ,1st digit of seconds" "0,1,2,3,4,5,6,7,8,9,,,,,," group.long 0x004++0x03 line.long 0x00 "RTCSS_MINUTES_REG,MINUTES_REG is used to program the minutes value of the current time" bitfld.long 0x00 4.--6. " MIN1 ,2nd digit of minutes" "0,1,2,3,4,5,," bitfld.long 0x00 0.--3. " MIN0 ,1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,,,,,," if (((d.l(ad:0x44E3E000+0x008))&0x30)==0x20) //this.HOUR1== "2" group.long 0x008++0x03 line.long 0x00 "RTCSS_HOURS_REG,HOURS_REG is used to program the hours value of the current time" bitfld.long 0x00 7. " PM_NAM ,Only used in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR1 ,2nd digit of hours" "0,1,2," bitfld.long 0x00 0.--3. " HOUR0 ,1st digit of hours" "0,1,2,3,4,,,,,,,,,,," elif (((d.l(ad:0x44E3E000+0x008))&0x30)==0x10)||(((d.l(ad:0x44E3E000+0x008))&0x30)==0x00) //this.HOUR1== "1" || "0" group.long 0x008++0x03 line.long 0x00 "RTCSS_HOURS_REG,HOURS_REG is used to program the hours value of the current time" bitfld.long 0x00 7. " PM_NAM ,Only used in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR1 ,2nd digit of hours" "0,1,2," bitfld.long 0x00 0.--3. " HOUR0 ,1st digit of hours" "0,1,2,3,4,5,6,7,8,9,,,,,," else group.long 0x008++0x03 line.long 0x00 "RTCSS_HOURS_REG,HOURS_REG is used to program the hours value of the current time" bitfld.long 0x00 7. " PM_NAM ,Only used in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR1 ,2nd digit of hours" "0,1,2," endif if (((d.l(ad:0x44E3E000+0x00C))&0x30)==0x30) //this.DAY1== "3" group.long 0x00C++0x03 line.long 0x00 "RTCSS_DAYS_REG,DAYS_REG is used to program the day of the month value of the current date" bitfld.long 0x00 4.--5. " DAY1 , 2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. " DAY0 , 1st digit of days" "0,1,,,,,,,,,,,,,," else group.long 0x00C++0x03 line.long 0x00 "RTCSS_DAYS_REG,DAYS_REG is used to program the day of the month value of the current date" bitfld.long 0x00 4.--5. " DAY1 , 2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. " DAY0 , 1st digit of days" "0,1,2,3,4,5,6,7,8,9,,,,,," endif group.long 0x010++0x03 line.long 0x00 "RTCSS_MONTHS_REG,MONTHS_REG is used to set the month in the year value of the current date" bitfld.long 0x00 0.--4. " MONTH0 ,Months" "January,February,March,April,May,June,July,August,September,October,November,November,December,,,..." group.long 0x014++0x03 line.long 0x00 "RTCSS_YEARS_REG,YEARS_REG is used to program the year value of the current date" bitfld.long 0x00 4.--7. " YEAR1 , 2nd digit of years" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " YEAR0 , 1st digit of years" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x018++0x03 line.long 0x00 "RTCSS_WEEKS_REG,WEEKS_REG is used to program the day of the week value of the current date" bitfld.long 0x00 0.--2. " WEEK , 1st digit of days in a week" "Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday," group.long 0x020++0x03 line.long 0x00 "RTCSS_ALARM_SECONDS_REG,ALARM_SECONDS_REG is used to program the second value for the alarm interrupt" bitfld.long 0x00 4.--6. " ALARMSEC1 , 2nd digit of seconds" "0,1,2,3,4,5,," bitfld.long 0x00 0.--3. " ALARMSEC0 , 1st digit of seconds" "0,1,2,3,4,5,6,7,8,9,,,,,," group.long 0x024++0x03 line.long 0x00 "RTCSS_ALARM_MINUTES_REG,ALARM_MINUTES_REG is used to program the minute value for the alarm interrupt" bitfld.long 0x00 4.--6. " ALARM_MIN1 , 2nd digit of minutes" "0,1,2,3,4,5,," bitfld.long 0x00 0.--3. " ALARM_MIN0 , 1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,,,,,," if (((d.l(ad:0x44E3E000+0x028))&0x30)==0x20) //this.ALARM_HOUR1== "2" group.long 0x028++0x03 line.long 0x00 "RTCSS_ALARM_HOURS_REG,ALARM_HOURS_REG is used to program the hour value for the alarm interrupt" bitfld.long 0x00 7. " ALARM_PM_NAM ,Only used in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " ALARM_HOUR1 , 2nd digit of hours" "0,1,2," bitfld.long 0x00 0.--3. " ALARM_HOUR0 , 1st digit of hours" "0,1,2,3,4,,,,,,,,,,," elif (((d.l(ad:0x44E3E000+0x028))&0x30)==0x10)||(((d.l(ad:0x44E3E000+0x028))&0x30)==0x00) //this.ALARM_HOUR1== "1" || "0" group.long 0x028++0x03 line.long 0x00 "RTCSS_ALARM_HOURS_REG,ALARM_HOURS_REG is used to program the hour value for the alarm interrupt" bitfld.long 0x00 7. " ALARM_PM_NAM ,Only used in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " ALARM_HOUR1 , 2nd digit of hours" "0,1,2," bitfld.long 0x00 0.--3. " ALARM_HOUR0 , 1st digit of hours" "0,1,2,3,4,5,6,7,8,9,,,,,," else group.long 0x028++0x03 line.long 0x00 "RTCSS_ALARM_HOURS_REG,ALARM_HOURS_REG is used to program the hour value for the alarm interrupt" bitfld.long 0x00 7. " ALARM_PM_NAM ,Only used in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " ALARM_HOUR1 , 2nd digit of hours" "0,1,2," endif if (((d.l(ad:0x44E3E000+0x02C))&0x30)==0x30) //this.ALARM_DAY1== "3" group.long 0x02C++0x03 line.long 0x00 "RTCSS_ALARM_DAYS_REG,ALARM_DAYS_REG is used to program the day of the month value for the alarm interrupt" bitfld.long 0x00 4.--5. " ALARM_DAY1 , 2nd digit for days" "0,1,2,3" bitfld.long 0x00 0.--3. " ALARM_DAY0 , 1st digit for days" "0,1,,,,,,,,,,,,,," else group.long 0x02C++0x03 line.long 0x00 "RTCSS_ALARM_DAYS_REG,ALARM_DAYS_REG is used to program the day of the month value for the alarm interrupt" bitfld.long 0x00 4.--5. " ALARM_DAY1 , 2nd digit for days" "0,1,2,3" bitfld.long 0x00 0.--3. " ALARM_DAY0 , 1st digit for days" "0,1,2,3,4,5,6,7,8,9,,,,,," endif group.long 0x030++0x03 line.long 0x00 "RTCSS_ALARM_MONTHS_REG,ALARM_MONTHS_REG is used to program the month in the year value for the alarm interrupt" bitfld.long 0x00 0.--4. " ALARM_MONTH0 ,Months" "January,February,March,April,May,June,July,August,September,October,November,November,December,,,..." group.long 0x034++0x03 line.long 0x00 "RTCSS_ALARM_YEARS_REG,The ALARM_YEARS_REG is used to program the year for the alarm interrupt" bitfld.long 0x00 4.--7. " ALARM_YEAR1 , 2nd digit of years" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALARM_YEAR0 , 1st digit of years" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x040++0x03 line.long 0x00 "RTCSS_CTRL_REG,RTC_CTRL_REG register" bitfld.long 0x00 6. " RTC_DISABLE ,Disable RTC module and gate 32-kHz reference clock" "No,Yes" bitfld.long 0x00 5. " SET_32_CTR ,Set the 32-kHz counter" "No action,Set" bitfld.long 0x00 4. " TEST_MODE ,Test mode" "Functional mode,Test mode" textline " " bitfld.long 0x00 3. " MODE_12_24 ,Enable 12-hour mode for HOURS and ALARMHOURS registers" "24-hr mode,12-hour mode" bitfld.long 0x00 2. " AUTO_COMP ,Enable oscillator compensation mode" "No compensation,Enabled" bitfld.long 0x00 1. " ROUND_30S ,Enable one-time rounding to nearest minute on next time register read" "No update,Rounded" textline " " bitfld.long 0x00 0. " STOP_RTC ,Stop the RTC 32-kHz counter" "Frozen,Running" group.long 0x044++0x03 line.long 0x00 "RTCSS_STS_REG,RTC_STATUS_REG register" bitfld.long 0x00 7. " ALARM2 , Indicates that an alarm2 interrupt has been generated" "Not generated,Generated" bitfld.long 0x00 6. " ALARM , Indicates that an alarm interrupt has been generated" "Not generated,Generated" rbitfld.long 0x00 5. " 1D_EVT , One day has occurred" "Not occurred,Occurred" textline " " rbitfld.long 0x00 4. " 1H_EVT , One hour has occurred" "Not occurred,Occurred" rbitfld.long 0x00 3. " 1M_EVT , One minute has occurred" "Not occurred,Occurred" rbitfld.long 0x00 2. " 1S_EVT , One second has occurred" "Not occurred,Occurred" textline " " rbitfld.long 0x00 1. " RUN ,RTC is frozen or is running" "Frozen,Running" rbitfld.long 0x00 0. " BUSY ,Status of RTC module" "15 s,Updating" group.long 0x048++0x03 line.long 0x00 "RTCSS_INTRS_REG,RTC_INTERRUPTS_REG register" bitfld.long 0x00 4. " IT_ALARM2 ,Enable one interrupt when the alarm value is reached (TC ALARM2 registers) by the TC registers" "Disabled,Enabled" bitfld.long 0x00 3. " IT_ALARM ,Enable one interrupt when the alarm value is reached (TC ALARM registers) by the TC registers" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " IT_TIMER ,Enable periodic interrupt" "Disabled,Enabled" bitfld.long 0x00 0.--1. " EVERY ,Interrupt period" "Second,Minute,Hour,Day" group.long 0x04C++0x03 line.long 0x00 "RTCSS_COMP_LSB_REG,COMP_LSB_REG register" hexmask.long.byte 0x00 0.--7. 1. " RTC_COMP_LSB ,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour" group.long 0x050++0x03 line.long 0x00 "RTCSS_COMP_MSB_REG,COMP_MSB_REG register" hexmask.long.byte 0x00 0.--7. 1. " RTC_COMP_MSB ,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour" group.long 0x054++0x03 line.long 0x00 "RTCSS_OSC_REG,RTCSS_OSC_REG" bitfld.long 0x00 6. " 32KCLK_EN ,32-kHz clock enable post clock mux of rtc_32k_clk_rtc_32k_aux_clk and rtc_32k_clk_rtc_32k_clk" "Disabled,Enabled" bitfld.long 0x00 4. " OSC32K_GZ ,Disable the oscillator and apply high impedance to the output" "Yes,No" bitfld.long 0x00 3. " 32KCLK_SEL ,32-kHz clock source select" "Internal,External" textline " " bitfld.long 0x00 2. " RES_SELECT ,External feedback resistor" "Internal,External" bitfld.long 0x00 1. " SW2 , Inverter size adjustment" "0,1" bitfld.long 0x00 0. " SW1 , Inverter size adjustment" "0,1" group.long 0x060++0x03 line.long 0x00 "RTCSS_SCRATCH0_REG,RTC_SCRATCH0_REG is used to hold some required values for the RTC register." group.long 0x064++0x03 line.long 0x00 "RTCSS_SCRATCH1_REG,RTC_SCRATCH1_REG is used to hold some required values for the RTC register." group.long 0x068++0x03 line.long 0x00 "RTCSS_SCRATCH2_REG,RTC_SCRATCH2_REG is used to hold some required values for the RTC register." group.long 0x06C++0x03 line.long 0x00 "RTCSS_KICK0R,Kick registers (KICKnR) are used to enable and disable write protection on the RTC registers" group.long 0x070++0x03 line.long 0x00 "RTCSS_KICK1R,Kick registers (KICKnR) are used to enable and disable write protection on the RTC registers" rgroup.long 0x074++0x03 line.long 0x00 "RTCSS_REVISION,RTCSS_REVISION" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision (Y)" group.long 0x078++0x03 line.long 0x00 "RTCSS_SYSCONFIG,RTCSS_SYSCONFIG" bitfld.long 0x00 0.--1. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode" group.long 0x07C++0x03 line.long 0x00 "RTCSS_IRQWAKEEN,RTCSS_IRQWAKEEN" bitfld.long 0x00 1. " ALARM_WAKEEN ,Wakeup generation for event Alarm" "Disabled,Enabled" bitfld.long 0x00 0. " TIMER_WAKEEN ,Wakeup generation for event Timer" "Disabled,Enabled" group.long 0x080++0x03 line.long 0x00 "RTCSS_ALARM2_SECONDS_REG,The ALARM2_SECONDS_REG is used to program the second value for the alarm2 time" bitfld.long 0x00 4.--6. " ALARM2_SEC1 , 2nd digit of seconds" "0,1,2,3,4,5,," bitfld.long 0x00 0.--3. " ALARM2_SEC0 , 1st digit of seconds" "0,1,2,3,4,5,6,7,8,9,,,,,," group.long 0x084++0x03 line.long 0x00 "RTCSS_ALARM2_MINUTES_REG,The ALARM2_MINUTES_REG is used to program the minute value for the alarm2 time" bitfld.long 0x00 4.--6. " ALARM2_MIN1 , 2nd digit of minutes" "0,1,2,3,4,5,," bitfld.long 0x00 0.--3. " ALARM2_MIN0 , 1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,,,,,," if (((d.l(ad:0x44E3E000+0x088))&0x30)==0x20) //this.ALARM2_HOUR1== "2" group.long 0x088++0x03 line.long 0x00 "RTCSS_ALARM2_HOURS_REG,The ALARM2_HOURS_REG is used to program the hour value for the alarm2 time" bitfld.long 0x00 7. " ALARM2_PM_NAM ,Only used in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " ALARM2_HOUR1 , 2nd digit of hours" "0,1,2," bitfld.long 0x00 0.--3. " ALARM2_HOUR0 , 1st digit of hours" "0,1,2,3,4,,,,,,,,,,," elif (((d.l(ad:0x44E3E000+0x088))&0x30)==0x10)||(((d.l(ad:0x44E3E000+0x088))&0x30)==0x00) //this.ALARM2_HOUR1== "1" || "0" group.long 0x088++0x03 line.long 0x00 "RTCSS_ALARM2_HOURS_REG,The ALARM2_HOURS_REG is used to program the hour value for the alarm2 time" bitfld.long 0x00 7. " ALARM2_PM_NAM ,Only used in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " ALARM2_HOUR1 , 2nd digit of hours" "0,1,2," bitfld.long 0x00 0.--3. " ALARM2_HOUR0 , 1st digit of hours" "0,1,2,3,4,5,6,7,8,9,,,,,," else group.long 0x088++0x03 line.long 0x00 "RTCSS_ALARM2_HOURS_REG,The ALARM2_HOURS_REG is used to program the hour value for the alarm2 time" bitfld.long 0x00 7. " ALARM2_PM_NAM ,Only used in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " ALARM2_HOUR1 , 2nd digit of hours" "0,1,2," endif if (((d.l(ad:0x44E3E000+0x08C))&0x30)==0x30) //this.ALARM2_DAY1== "3" group.long 0x08C++0x03 line.long 0x00 "RTCSS_ALARM2_DAYS_REG,The ALARM2_DAYS_REG is used to program the day of the month value for the alarm2 date" bitfld.long 0x00 4.--5. " ALARM2_DAY1 , 2nd digit for days" "0,1,2,3" bitfld.long 0x00 0.--3. " ALARM2_DAY0 , 1st digit for days" "0,1,,,,,,,,,,,,,," else group.long 0x08C++0x03 line.long 0x00 "RTCSS_ALARM2_DAYS_REG,The ALARM2_DAYS_REG is used to program the day of the month value for the alarm2 date" bitfld.long 0x00 4.--5. " ALARM2_DAY1 , 2nd digit for days" "0,1,2,3" bitfld.long 0x00 0.--3. " ALARM2_DAY0 , 1st digit for days" "0,1,2,3,4,5,6,7,8,9,,,,,," endif group.long 0x090++0x03 line.long 0x00 "RTCSS_ALARM2_MONTHS_REG,The ALARM2_MONTHS_REG is used to program the month in the year value for the alarm2 date" bitfld.long 0x00 0.--4. " ALARM2_MONTH ,Months" "January,February,March,April,May,June,July,August,September,October,November,November,December,,,..." group.long 0x094++0x03 line.long 0x00 "RTCSS_ALARM2_YEARS_REG,The ALARM2_YEARS_REG is used to program the year for the alarm2 date" bitfld.long 0x00 4.--7. " ALARM2_YEAR1 , 2nd digit of years" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALARM2_YEAR0 , 1st digit of years" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x098++0x03 line.long 0x00 "RTCSS_PMIC,RTCSS_PMIC" bitfld.long 0x00 17.--18. " PWR_EN_SM ,Power state machine state" "Idle,Shutdown,Time-based wakeup,Ext.-ev.-based wakeup" bitfld.long 0x00 16. " PWR_EN ,Enable for PMIC_POWER_EN signal" "Disabled,Enabled" textline " " eventfld.long 0x00 15. " EXT_WAKEUP_STS[3] ,External wakeup status" "Not occurred,Occurred" eventfld.long 0x00 14. " EXT_WAKEUP_STS[2] ,External wakeup status" "Not occurred,Occurred" textline " " eventfld.long 0x00 13. " EXT_WAKEUP_STS[1] ,External wakeup status" "Not occurred,Occurred" eventfld.long 0x00 12. " EXT_WAKEUP_STS[0] ,External wakeup status" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " EXT_WAKEUP_DB_EN[3] ,External wakeup debounce enabled" "Disabled,Enabled" bitfld.long 0x00 10. " EXT_WAKEUP_DB_EN[2] ,External wakeup debounce enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EXT_WAKEUP_DB_EN[1] ,External wakeup debounce enabled" "Disabled,Enabled" bitfld.long 0x00 8. " EXT_WAKEUP_DB_EN[0] ,External wakeup debounce enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " EXT_WAKEUP_POL[3] ,External wakeup input polarity" "Active high,Active low" bitfld.long 0x00 6. " EXT_WAKEUP_POL[2] ,External wakeup input polarity" "Active high,Active low" textline " " bitfld.long 0x00 5. " EXT_WAKEUP_POL[1] ,External wakeup input polarity" "Active high,Active low" bitfld.long 0x00 4. " EXT_WAKEUP_POL[0] ,External wakeup input polarity" "Active high,Active low" textline " " bitfld.long 0x00 3. " EXT_WAKEUP_EN[3] ,Enable external wakeup input" "Disabled,Enabled" bitfld.long 0x00 2. " EXT_WAKEUP_EN[2] ,Enable external wakeup input" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " EXT_WAKEUP_EN[1] ,Enable external wakeup input" "Disabled,Enabled" bitfld.long 0x00 0. " EXT_WAKEUP_EN[0] ,Enable external wakeup input" "Disabled,Enabled" group.long 0x09C++0x03 line.long 0x00 "RTCSS_DEBOUNCE,RTCSS_DEBOUNCE register" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCE_REG ,Debounce time" width 11. tree.end tree "WDT(WATCHDOG)" base ad:0x44E35000 width 17. rgroup.long 0x000++0x03 line.long 0x00 "WDT_WIDR,Watchdog Identification Register" hexmask.long 0x00 0.--31. 1. " REVISION , IP Revision" group.long 0x010++0x03 line.long 0x00 "WDT_WDSC,The Watchdog System Control Register controls the various parameters of the L4 interface" bitfld.long 0x00 5. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Free-running" bitfld.long 0x00 3.--4. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No action,Reset" rgroup.long 0x014++0x03 line.long 0x00 "WDT_WDST,The Watchdog Status Register provides status information about the module" bitfld.long 0x00 0. " RESETDONE ,Internal module reset monitoring" "Ongoing,Completed" group.long 0x018++0x03 line.long 0x00 "WDT_WISR,The Watchdog Interrupt Status Register shows which interrupt events are pending inside the module" bitfld.long 0x00 1. " DLY_IT_FLAG ,Pending delay interrupt status" "No delay,Delay" bitfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "No overflow,Overflow" group.long 0x01C++0x03 line.long 0x00 "WDT_WIER,The Watchdog Interrupt Enable Register controls (enable/disable) the interrupt events" bitfld.long 0x00 1. " DLY_IT_ENA ,Delay interrupt enable/disable" "Disabled,Enabled" bitfld.long 0x00 0. " OVF_IT_ENA ,Overflow interrupt enable/disable" "Disabled,Enabled" group.long 0x024++0x03 line.long 0x00 "WDT_WCLR,The Watchdog Control Register controls the prescaler stage of the counter" bitfld.long 0x00 5. " PRE ,Prescaler enable/disable configuration" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV , Prescaler value" "0,1,2,3,4,5,6,7" group.long 0x028++0x03 line.long 0x00 "WDT_WCRR,The Watchdog Counter Register holds the value of the internal counter" group.long 0x02C++0x03 line.long 0x00 "WDT_WLDR,The Watchdog Load Register holds the timer load value" group.long 0x030++0x03 line.long 0x00 "WDT_WTGR,Writing a different value than the one already written in the Watchdog Trigger Register does a watchdog counter reload" rgroup.long 0x034++0x03 line.long 0x00 "WDT_WWPS,The Watchdog Write Posting Bits Register contains the write posting bits for all writeable functional registers" bitfld.long 0x00 5. " W_PEND_WDLY ,Write pending for register WDLY" "No,Yes" bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "No,Yes" bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "No,Yes" textline " " bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "No,Yes" bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "No,Yes" bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "No,Yes" group.long 0x044++0x03 line.long 0x00 "WDT_WDLY,The Watchdog Delay Configuration Register holds the delay value that controls the internal pre-overflow event detection" group.long 0x048++0x03 line.long 0x00 "WDT_WSPR,The Watchdog Start/Stop Register holds the start-stop value that controls the internal start-stop FSM" group.long 0x054++0x03 line.long 0x00 "WDT_WIRQSTATRAW,WDT_WIRQSTATRAW register" bitfld.long 0x00 1. " EVT_DLY ,Settable raw status for delay event" "No pending,Pending" bitfld.long 0x00 0. " EVT_OVF ,Settable raw status for overflow event" "No pending,Pending" group.long 0x058++0x03 line.long 0x00 "WDT_WIRQSTAT,WDT_WIRQSTAT register" eventfld.long 0x00 1. " EVT_DLY ,Clearable enabled status for delay event" "No action,Clear" eventfld.long 0x00 0. " EVT_OVF ,Clearable enabled status for overflow event" "No action,Clear" group.long 0x05C++0x03 line.long 0x00 "WDT_WIRQENSET,WDT_WIRQENSET register" bitfld.long 0x00 1. " EN_DLY ,Enable for delay event" "Disabled,Enabled" bitfld.long 0x00 0. " EN_OVF ,Enable for overflow event" "Disabled,Enabled" group.long 0x060++0x03 line.long 0x00 "WDT_WIRQENCLR,WDT_WIRQENCLR register" bitfld.long 0x00 1. " EN_DLY ,Enable for delay event" "Disabled,Enabled" bitfld.long 0x00 0. " EN_OVF ,Enable for overflow event" "Disabled,Enabled" width 11. tree.end tree.end tree "PWMSS(Pulse-Width Modulation Subsystem)" tree "PWMSS0" tree "PWMSS0 Configuration Registers" width 11. base ad:0x48300000 rgroup.long 0x00++0x03 line.long 0x00 "IDVER,The IP revision register is used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" ",,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "SYSCONFIG,The system configuration register is used for clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode," bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x08++0x03 line.long 0x00 "CLKCONFIG,The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control" bitfld.long 0x00 9. " EPWMCLKSTOP_REQ ,This bit controls the clkstop_req input to the ePWM module" "0,1" bitfld.long 0x00 8. " EPWMCLK_EN ,This bit controls the clk_en input to the ePWM module" "0,1" bitfld.long 0x00 5. " EQEPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEPCLK_EN ,This bit controls the clk_en input to the eQEP module" "0,1" bitfld.long 0x00 1. " ECAPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eCAP module" "0,1" bitfld.long 0x00 0. " ECAPCLK_EN ,This bit controls the clk_en input to the eCAP module" "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "CLKSTATUS,The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status" bitfld.long 0x00 9. " EPWM_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM module" "0,1" bitfld.long 0x00 8. " EPWM_CLK_EN_ACK ,This bit is the clk_en status output of the ePWM module" "0,1" bitfld.long 0x00 5. " EQEP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEP_CLK_EN_ACK ,This bit is the clk_en status output of the eQEP module" "0,1" bitfld.long 0x00 1. " ECAP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eCAP module" "0,1" bitfld.long 0x00 0. " ECAP_CLK_EN_ACK ,This bit is the clk_en status output of the eCAP module" "0,1" width 11. tree.end tree "PWMSS eCAP0 Registers" base ad:0x48300100 width 8. group.long 0x00++0x03 line.long 0x00 "TSCTR,Active 32 bit counter register that is used as the capture time-base" group.long 0x04++0x03 line.long 0x00 "CTRPHS,Counter phase value register" group.long 0x08++0x03 line.long 0x00 "CAP1,CAP1" group.long 0x0C++0x03 line.long 0x00 "CAP2,CAP2" group.long 0x10++0x03 line.long 0x00 "CAP3,Time-stamp capture register" group.long 0x14++0x03 line.long 0x00 "CAP4,Time-stamp capture register" group.word 0x28++0x01 line.word 0x00 "ECCTL1,ECCTL1" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Control" "Stops immediately,Runs until = 0,Run Free,Run Free" bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale select" "1,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.word 0x00 8. " CAPLDEN ,Enable Loading of CAP1 to CAP4 registers on a capture event" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "Not reset,Reset" bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "Rising edge,Falling edge" bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "Not reset,Reset" bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "Not reset,Reset" bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "Rising edge,Falling edge" bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "Not reset,Reset" bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "Rising edge,Falling edge" if (((d.l(ad:0x48300100+0x2A))&0x200)==0x200) //this.CAP_APWM== "APWM" group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECCTL2" bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "Active high,Active low" bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "No effect,Forces a TSCTR" textline " " bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-in,PRDEQ,Disabled,Disabled" bitfld.word 0x00 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " REARM , One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "1,2,3,4" bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control(capture mode)" "Continuous mode,One-shot mode" else group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECCTL2" bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "No effect,Forces a TSCTR" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-in,PRDEQ,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running" bitfld.word 0x00 3. " REARM , One-Shot Re-Arming Control" "No effect,One-shot sequence" textline " " bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "1,2,3,4" bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control(capture mode)" "Continuous mode,One-shot mode" endif group.word 0x2C++0x01 line.word 0x00 "ECEINT,The interrupt enable bits (CEVTn) block any of the selected events from generating an interrupt" bitfld.word 0x00 7. " CMPEQ ,Counter Equal Compare Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 6. " PRDEQ ,Counter Equal Period Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "Disabled,Enabled" if (((d.l(ad:0x48300100+0x2A))&0x200)==0x200) //this.CAP_APWM== "APWM" rgroup.word 0x2E++0x01 line.word 0x00 "ECFLG,ECFLG" bitfld.word 0x00 7. " CMPEQ ,Compare Equal Compare Status Flag" "No occurred,Occurred" bitfld.word 0x00 6. " PRDEQ ,Counter Equal Period Status Flag" "No occurred,Occurred" textline " " bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Status Flag" "No occurred,Occurred" bitfld.word 0x00 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt" else rgroup.word 0x2E++0x01 line.word 0x00 "ECFLG,ECFLG" bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Status Flag" "No occurred,Occurred" bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Flag" "No occurred,Occurred" bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Flag" "No occurred,Occurred" textline " " bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Flag" "No occurred,Occurred" bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Flag" "No occurred,Occurred" bitfld.word 0x00 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt" endif group.word 0x30++0x01 line.word 0x00 "ECCLR,ECCLR" bitfld.word 0x00 7. " CMPEQ ,Counter Equal Compare Status Flag" "No effect,Clear" bitfld.word 0x00 6. " PRDEQ ,Counter Equal Period Status Flag" "No effect,Clear" bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Status Flag" "No effect,Clear" bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Flag" "No effect,Clear" textline " " bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Flag" "No effect,Clear" bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Flag" "No effect,Clear" bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Flag" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Clear" group.word 0x32++0x01 line.word 0x00 "ECFRC,ECFRC" bitfld.word 0x00 7. " CMPEQ ,Force Counter Equal Compare Interrupt" "No effect,Set" bitfld.word 0x00 6. " PRDEQ ,Force Counter Equal Period Interrupt" "No effect,Set" bitfld.word 0x00 5. " CNTOVF ,Force Counter Overflow" "No effect,Set" bitfld.word 0x00 4. " CEVT4 ,Force Capture Event 4" "No effect,Set" textline " " bitfld.word 0x00 3. " CEVT3 ,Force Capture Event 3" "No effect,Set" bitfld.word 0x00 2. " CEVT2 ,Force Capture Event 2" "No effect,Set" bitfld.word 0x00 1. " CEVT1 ,Force Capture Event 1" "No effect,Set" rgroup.long 0x5C++0x03 line.long 0x00 "REVID,REVID" width 11. tree.end tree "PWMSS eQEP0 Registers" base ad:0x48300180 width 10. group.long 0x000++0x03 line.long 0x00 "QPOSCNT,This 32 bit position counter register counts up/down on every eQEP pulse based on direction input" group.long 0x004++0x03 line.long 0x00 "QPOSINIT,This register contains the position value that is used to initialize the position counter based on external strobe or index event" group.long 0x008++0x03 line.long 0x00 "QPOSMAX,This register contains the maximum position counter value" group.long 0x00C++0x03 line.long 0x00 "QPOSCMP,Generate sync output and/or interrupt on compare match" rgroup.long 0x010++0x03 line.long 0x00 "QPOSILAT,The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits" rgroup.long 0x014++0x03 line.long 0x00 "QPOSSLAT,The position-counter value is latched into this register on strobe event as defined by the QEPCTL[SEL] bits" rgroup.long 0x018++0x03 line.long 0x00 "QPOSLAT,The position-counter value is latched into this register on unit time out event" group.long 0x01C++0x03 line.long 0x00 "QUTMR,This register acts as time base for unit time event generation" group.long 0x020++0x03 line.long 0x00 "QUPRD,This register contains the period count" group.word 0x024++0x01 line.word 0x00 "QWDTMR,This register acts as time base for watch dog to detect motor stalls" group.word 0x026++0x01 line.word 0x00 "QWDPRD,This register contains the time-out count for the eQEP peripheral watch dog timer" group.word 0x028++0x01 line.word 0x00 "QDECCTL,QDECCTL" bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature,Direction,UP,DOWN" bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,1" bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index,Strobe" textline " " bitfld.word 0x00 11. " XCR ,External clock rate" "Rising/falling,Rising" bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disabled,Gated" bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates" textline " " bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates" bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates" bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates" group.word 0x02A++0x01 line.word 0x00 "QEPCTL,QEPCTL" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Control Bits" "Stops immediately,Until rollover,Disabled,Disabled" bitfld.word 0x00 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" bitfld.word 0x00 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising edge,Clockwise Direction" bitfld.word 0x00 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising edge,Falling edge" textline " " eventfld.word 0x00 7. " SWI ,Software initialization of position counter" "Disabled,Initialize" bitfld.word 0x00 6. " SEL ,Strobe event latch of position counter" "0,1" bitfld.word 0x00 4.--5. " IEL ,Index event latch of position counter (software index marker)" ",Rising edge,Falling edge,Software index marker" bitfld.word 0x00 3. " PHEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x00 2. " QCLM ,EQEP capture latch mode" "CPU,Time out" bitfld.word 0x00 1. " UTE ,EQEP unit timer enable" "Disabled,Enabled" bitfld.word 0x00 0. " WDE ,EQEP watchdog enable" "Disabled,Enabled" group.word 0x02C++0x01 line.word 0x00 "QCAPCTL,QCAPCTL" bitfld.word 0x00 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x00 4.--6. " CCPS ,EQEP capture timer clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 0.--3. " UPPS ,Unit position event prescaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,,,," group.word 0x02E++0x01 line.word 0x00 "QPOSCTL,QPOSCTL" bitfld.word 0x00 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x00 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP" bitfld.word 0x00 13. " PCPOL ,Polarity of sync output" "Active HIGH,Active LOW" textline " " bitfld.word 0x00 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" hexmask.word 0x00 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" group.word 0x030++0x01 line.word 0x00 "QEINT,QEINT" bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "Disabled,Enabled" rgroup.word 0x032++0x01 line.word 0x00 "QFLG,QFLG" bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 8. " PCM ,EQEP compare match event interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 4. " WTO ,Watchdog timeout interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x034++0x01 line.word 0x00 "QCLR,QCLR" bitfld.word 0x00 11. " UTO ,Clear unit time out interrupt flag" "No effect,Clear" bitfld.word 0x00 10. " IEL ,Clear index event latch interrupt flag" "No effect,Clear" bitfld.word 0x00 9. " SEL ,Clear strobe event latch interrupt flag" "No effect,Clear" bitfld.word 0x00 8. " PCM ,Clear eQEP compare match event interrupt flag" "No effect,Clear" textline " " bitfld.word 0x00 7. " PCR ,Clear position-compare ready interrupt flag" "No effect,Clear" bitfld.word 0x00 6. " PCO ,Clear position counter overflow interrupt flag" "No effect,Clear" bitfld.word 0x00 5. " PCU ,Clear position counter underflow interrupt flag" "No effect,Clear" bitfld.word 0x00 4. " WTO ,Clear watchdog timeout interrupt flag" "No effect,Clear" textline " " bitfld.word 0x00 3. " QDC ,Clear quadrature direction change interrupt flag" "No effect,Clear" bitfld.word 0x00 2. " PHE ,Clear quadrature phase error interrupt flag" "No effect,Clear" bitfld.word 0x00 1. " PCE ,Clear position counter error interrupt flag" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear" group.word 0x036++0x01 line.word 0x00 "QFRC,QFRC" bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Force" bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Force" bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Force" bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Force" textline " " bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Force" bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Force" bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Force" bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Force" textline " " bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Force" bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Force" bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Force" group.word 0x038++0x01 line.word 0x00 "QEPSTS,QEPSTS" bitfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" rbitfld.word 0x00 6. " FDF ,Direction on the first index marker" "Reverse,Forward" rbitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Reverse,Forward" rbitfld.word 0x00 4. " QDLF ,EQEP direction latch flag" "Reverse,Forward" textline " " eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred" eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred" eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not set,Set by first" rbitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error" group.word 0x03A++0x01 line.word 0x00 "QCTMR,This register provides time base for edge capture unit" group.word 0x03C++0x01 line.word 0x00 "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x03E++0x01 line.word 0x00 "QCTMRLAT,QCTMRLAT" group.word 0x040++0x01 line.word 0x00 "QCPRDLAT,QCPRDLAT" rgroup.long 0x05C++0x03 line.long 0x00 "REVID,EQEP revision ID" width 11. tree.end tree "PWMSS ePWM0 Registers" base ad:0x48300200 width 9. group.word 0x00++0x01 line.word 0x00 "TBCTL,TBCTL" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "Stop after next,Complete stops,Free run,Free run" bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale Bits" "/1,/2,/4,/6,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced" bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled" textline " " bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Shadow,Without shadow" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze" group.word 0x02++0x01 line.word 0x00 "TBSTS,TBSTS" eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit" "Not reached,Reached" eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit" "Not occurred,Occurred" rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" group.word 0x04++0x01 line.word 0x00 "TBPHSHR,TBPHSHR" hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution bits" group.word 0x06++0x01 line.word 0x00 "TBPHS,time-base counter phase of the selected ePWM" group.word 0x08++0x01 line.word 0x00 "TBCNT,Current time-base counter value" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Period of the time-base counter" group.word 0x0E++0x01 line.word 0x00 "CMPCTL,CMPCTL Register" rbitfld.word 0x00 9. " SHDWBFULL , Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full" rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow mode,Immediate mode" textline " " bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow mode,Immediate mode" bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode." "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" group.word 0x10++0x01 line.word 0x00 "CMPAHR,CMPAHR Register" hexmask.word.byte 0x00 8.--15. 1. " CMPAHR , Compare A High-Resolution register bits for MEP step control" group.word 0x12++0x01 line.word 0x00 "CMPA,CMPA Register" group.word 0x14++0x01 line.word 0x00 "CMPB,CMPB Register" group.word 0x16++0x01 line.word 0x00 "AQCTLA,AQCTLA Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggle" group.word 0x18++0x01 line.word 0x00 "AQCTLB,AQCTLB Register" bitfld.word 0x00 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,,Set,Toggle" group.word 0x1A++0x01 line.word 0x00 "AQSFRC,AQSFRC Register" bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Load immediately" bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Initiate" bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Initiate" bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggle" group.word 0x1C++0x01 line.word 0x00 "AQCSFRC,AQCSFRC Register" bitfld.word 0x00 2.--3. " CSFB ,Software forcing is disabled and has no effect" "Disabled,Low,High,Disabled" bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A In immediate mode" "Disabled,Low,High,Disabled" group.word 0x1E++0x01 line.word 0x00 "DBCTL,DBCTL Register" bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "Both,Rising-edge,Fising-edge,Both" bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Bypassed,Rising-edge,Falling-edge,Enabled" group.word 0x20++0x01 line.word 0x00 "DBRED,DBRED Register" hexmask.word 0x00 0.--9. 1. " DEL , Rising Edge Delay Count" group.word 0x22++0x01 line.word 0x00 "DBFED,DBFED Register" hexmask.word 0x00 0.--9. 1. " DEL , Falling Edge Delay Count" group.word 0x24++0x01 line.word 0x00 "TZSEL,TZSEL Register" bitfld.word 0x00 15. " OSHT7 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 14. " OSHT6 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT5 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 12. " OSHT4 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " OSHT3 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 10. " OSHT2 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT1 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT0 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CBC7 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 6. " CBC6 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 5. " CBC5 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 4. " CBC4 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CBC3 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 2. " CBC2 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 0. " CBC0 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,TZCTL Register" bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High impedance,High state,Low state,No action" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High impedance,High state,Low state,No action" group.word 0x2A++0x01 line.word 0x00 "TZEINT,TZEINT Register" bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled" rgroup.word 0x2C++0x01 line.word 0x00 "TZFLG,TZFLG Register" bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred" bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred" bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x2E++0x01 line.word 0x00 "TZCLR,TZCLR Register" bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Clear" bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Clear" group.word 0x30++0x01 line.word 0x00 "TZFRC,TZFRC Register" bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x32++0x01 line.word 0x00 "ETSEL,ETSEL Register" bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,EPWM Interrupt (EPWMx_INT) Selection Options" ",TBCNT =0,TBCNT=TBPRD,,CMPA when incrementing,CMPA when decrementing,CMPB when incrementing,CMPB when decrementing" group.word 0x34++0x01 line.word 0x00 "ETPS,ETPS Register" rbitfld.word 0x00 2.--3. " INTCNT ,EPWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x00 0.--1. " INTPRD ,EPWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event" rgroup.word 0x36++0x01 line.word 0x00 "ETFLG,ETFLG Register" bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "Not occurred,Occurred" rgroup.word 0x38++0x01 line.word 0x00 "ETCLR,ETCLR Register" bitfld.word 0x00 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "No effect,Clear" rgroup.word 0x3A++0x01 line.word 0x00 "ETFRC,ETFRC Register" bitfld.word 0x00 0. " INT ,INT Force Bit" "No interrupt,Interrupt" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PCCTL Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%)," bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "1,2,3,4,5,6,7,8" bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" group.word 0xC0++0x01 line.word 0x00 "HRCNFG,HRCNFG" bitfld.word 0x00 3. " HRLOAD ,Shadow mode bit" "CNT_zero pulse,PRD_eq pulse" bitfld.word 0x00 2. " CTLMODE ,Control Mode Bits" "CMPAHR,TBPHSHR" bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode Bits" "Disabled,Rising edge,Falling edge,Both edges" width 11. tree.end tree.end tree "PWMSS1" tree "PWMSS1 Configuration Registers" width 11. base ad:0x48302000 rgroup.long 0x00++0x03 line.long 0x00 "IDVER,The IP revision register is used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" ",,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "SYSCONFIG,The system configuration register is used for clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode," bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x08++0x03 line.long 0x00 "CLKCONFIG,The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control" bitfld.long 0x00 9. " EPWMCLKSTOP_REQ ,This bit controls the clkstop_req input to the ePWM module" "0,1" bitfld.long 0x00 8. " EPWMCLK_EN ,This bit controls the clk_en input to the ePWM module" "0,1" bitfld.long 0x00 5. " EQEPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEPCLK_EN ,This bit controls the clk_en input to the eQEP module" "0,1" bitfld.long 0x00 1. " ECAPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eCAP module" "0,1" bitfld.long 0x00 0. " ECAPCLK_EN ,This bit controls the clk_en input to the eCAP module" "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "CLKSTATUS,The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status" bitfld.long 0x00 9. " EPWM_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM module" "0,1" bitfld.long 0x00 8. " EPWM_CLK_EN_ACK ,This bit is the clk_en status output of the ePWM module" "0,1" bitfld.long 0x00 5. " EQEP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEP_CLK_EN_ACK ,This bit is the clk_en status output of the eQEP module" "0,1" bitfld.long 0x00 1. " ECAP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eCAP module" "0,1" bitfld.long 0x00 0. " ECAP_CLK_EN_ACK ,This bit is the clk_en status output of the eCAP module" "0,1" width 11. tree.end tree "PWMSS eCAP1 Registers" base ad:0x48302100 width 8. group.long 0x00++0x03 line.long 0x00 "TSCTR,Active 32 bit counter register that is used as the capture time-base" group.long 0x04++0x03 line.long 0x00 "CTRPHS,Counter phase value register" group.long 0x08++0x03 line.long 0x00 "CAP1,CAP1" group.long 0x0C++0x03 line.long 0x00 "CAP2,CAP2" group.long 0x10++0x03 line.long 0x00 "CAP3,Time-stamp capture register" group.long 0x14++0x03 line.long 0x00 "CAP4,Time-stamp capture register" group.word 0x28++0x01 line.word 0x00 "ECCTL1,ECCTL1" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Control" "Stops immediately,Runs until = 0,Run Free,Run Free" bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale select" "1,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.word 0x00 8. " CAPLDEN ,Enable Loading of CAP1 to CAP4 registers on a capture event" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "Not reset,Reset" bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "Rising edge,Falling edge" bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "Not reset,Reset" bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "Not reset,Reset" bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "Rising edge,Falling edge" bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "Not reset,Reset" bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "Rising edge,Falling edge" if (((d.l(ad:0x48302100+0x2A))&0x200)==0x200) //this.CAP_APWM== "APWM" group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECCTL2" bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "Active high,Active low" bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "No effect,Forces a TSCTR" textline " " bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-in,PRDEQ,Disabled,Disabled" bitfld.word 0x00 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " REARM , One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "1,2,3,4" bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control(capture mode)" "Continuous mode,One-shot mode" else group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECCTL2" bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "No effect,Forces a TSCTR" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-in,PRDEQ,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running" bitfld.word 0x00 3. " REARM , One-Shot Re-Arming Control" "No effect,One-shot sequence" textline " " bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "1,2,3,4" bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control(capture mode)" "Continuous mode,One-shot mode" endif group.word 0x2C++0x01 line.word 0x00 "ECEINT,The interrupt enable bits (CEVTn) block any of the selected events from generating an interrupt" bitfld.word 0x00 7. " CMPEQ ,Counter Equal Compare Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 6. " PRDEQ ,Counter Equal Period Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "Disabled,Enabled" if (((d.l(ad:0x48302100+0x2A))&0x200)==0x200) //this.CAP_APWM== "APWM" rgroup.word 0x2E++0x01 line.word 0x00 "ECFLG,ECFLG" bitfld.word 0x00 7. " CMPEQ ,Compare Equal Compare Status Flag" "No occurred,Occurred" bitfld.word 0x00 6. " PRDEQ ,Counter Equal Period Status Flag" "No occurred,Occurred" textline " " bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Status Flag" "No occurred,Occurred" bitfld.word 0x00 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt" else rgroup.word 0x2E++0x01 line.word 0x00 "ECFLG,ECFLG" bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Status Flag" "No occurred,Occurred" bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Flag" "No occurred,Occurred" bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Flag" "No occurred,Occurred" textline " " bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Flag" "No occurred,Occurred" bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Flag" "No occurred,Occurred" bitfld.word 0x00 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt" endif group.word 0x30++0x01 line.word 0x00 "ECCLR,ECCLR" bitfld.word 0x00 7. " CMPEQ ,Counter Equal Compare Status Flag" "No effect,Clear" bitfld.word 0x00 6. " PRDEQ ,Counter Equal Period Status Flag" "No effect,Clear" bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Status Flag" "No effect,Clear" bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Flag" "No effect,Clear" textline " " bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Flag" "No effect,Clear" bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Flag" "No effect,Clear" bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Flag" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Clear" group.word 0x32++0x01 line.word 0x00 "ECFRC,ECFRC" bitfld.word 0x00 7. " CMPEQ ,Force Counter Equal Compare Interrupt" "No effect,Set" bitfld.word 0x00 6. " PRDEQ ,Force Counter Equal Period Interrupt" "No effect,Set" bitfld.word 0x00 5. " CNTOVF ,Force Counter Overflow" "No effect,Set" bitfld.word 0x00 4. " CEVT4 ,Force Capture Event 4" "No effect,Set" textline " " bitfld.word 0x00 3. " CEVT3 ,Force Capture Event 3" "No effect,Set" bitfld.word 0x00 2. " CEVT2 ,Force Capture Event 2" "No effect,Set" bitfld.word 0x00 1. " CEVT1 ,Force Capture Event 1" "No effect,Set" rgroup.long 0x5C++0x03 line.long 0x00 "REVID,REVID" width 11. tree.end tree "PWMSS eQEP1 Registers" base ad:0x48302180 width 10. group.long 0x000++0x03 line.long 0x00 "QPOSCNT,This 32 bit position counter register counts up/down on every eQEP pulse based on direction input" group.long 0x004++0x03 line.long 0x00 "QPOSINIT,This register contains the position value that is used to initialize the position counter based on external strobe or index event" group.long 0x008++0x03 line.long 0x00 "QPOSMAX,This register contains the maximum position counter value" group.long 0x00C++0x03 line.long 0x00 "QPOSCMP,Generate sync output and/or interrupt on compare match" rgroup.long 0x010++0x03 line.long 0x00 "QPOSILAT,The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits" rgroup.long 0x014++0x03 line.long 0x00 "QPOSSLAT,The position-counter value is latched into this register on strobe event as defined by the QEPCTL[SEL] bits" rgroup.long 0x018++0x03 line.long 0x00 "QPOSLAT,The position-counter value is latched into this register on unit time out event" group.long 0x01C++0x03 line.long 0x00 "QUTMR,This register acts as time base for unit time event generation" group.long 0x020++0x03 line.long 0x00 "QUPRD,This register contains the period count" group.word 0x024++0x01 line.word 0x00 "QWDTMR,This register acts as time base for watch dog to detect motor stalls" group.word 0x026++0x01 line.word 0x00 "QWDPRD,This register contains the time-out count for the eQEP peripheral watch dog timer" group.word 0x028++0x01 line.word 0x00 "QDECCTL,QDECCTL" bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature,Direction,UP,DOWN" bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,1" bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index,Strobe" textline " " bitfld.word 0x00 11. " XCR ,External clock rate" "Rising/falling,Rising" bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disabled,Gated" bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates" textline " " bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates" bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates" bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates" group.word 0x02A++0x01 line.word 0x00 "QEPCTL,QEPCTL" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Control Bits" "Stops immediately,Until rollover,Disabled,Disabled" bitfld.word 0x00 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" bitfld.word 0x00 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising edge,Clockwise Direction" bitfld.word 0x00 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising edge,Falling edge" textline " " eventfld.word 0x00 7. " SWI ,Software initialization of position counter" "Disabled,Initialize" bitfld.word 0x00 6. " SEL ,Strobe event latch of position counter" "0,1" bitfld.word 0x00 4.--5. " IEL ,Index event latch of position counter (software index marker)" ",Rising edge,Falling edge,Software index marker" bitfld.word 0x00 3. " PHEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x00 2. " QCLM ,EQEP capture latch mode" "CPU,Time out" bitfld.word 0x00 1. " UTE ,EQEP unit timer enable" "Disabled,Enabled" bitfld.word 0x00 0. " WDE ,EQEP watchdog enable" "Disabled,Enabled" group.word 0x02C++0x01 line.word 0x00 "QCAPCTL,QCAPCTL" bitfld.word 0x00 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x00 4.--6. " CCPS ,EQEP capture timer clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 0.--3. " UPPS ,Unit position event prescaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,,,," group.word 0x02E++0x01 line.word 0x00 "QPOSCTL,QPOSCTL" bitfld.word 0x00 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x00 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP" bitfld.word 0x00 13. " PCPOL ,Polarity of sync output" "Active HIGH,Active LOW" textline " " bitfld.word 0x00 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" hexmask.word 0x00 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" group.word 0x030++0x01 line.word 0x00 "QEINT,QEINT" bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "Disabled,Enabled" rgroup.word 0x032++0x01 line.word 0x00 "QFLG,QFLG" bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 8. " PCM ,EQEP compare match event interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 4. " WTO ,Watchdog timeout interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x034++0x01 line.word 0x00 "QCLR,QCLR" bitfld.word 0x00 11. " UTO ,Clear unit time out interrupt flag" "No effect,Clear" bitfld.word 0x00 10. " IEL ,Clear index event latch interrupt flag" "No effect,Clear" bitfld.word 0x00 9. " SEL ,Clear strobe event latch interrupt flag" "No effect,Clear" bitfld.word 0x00 8. " PCM ,Clear eQEP compare match event interrupt flag" "No effect,Clear" textline " " bitfld.word 0x00 7. " PCR ,Clear position-compare ready interrupt flag" "No effect,Clear" bitfld.word 0x00 6. " PCO ,Clear position counter overflow interrupt flag" "No effect,Clear" bitfld.word 0x00 5. " PCU ,Clear position counter underflow interrupt flag" "No effect,Clear" bitfld.word 0x00 4. " WTO ,Clear watchdog timeout interrupt flag" "No effect,Clear" textline " " bitfld.word 0x00 3. " QDC ,Clear quadrature direction change interrupt flag" "No effect,Clear" bitfld.word 0x00 2. " PHE ,Clear quadrature phase error interrupt flag" "No effect,Clear" bitfld.word 0x00 1. " PCE ,Clear position counter error interrupt flag" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear" group.word 0x036++0x01 line.word 0x00 "QFRC,QFRC" bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Force" bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Force" bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Force" bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Force" textline " " bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Force" bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Force" bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Force" bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Force" textline " " bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Force" bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Force" bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Force" group.word 0x038++0x01 line.word 0x00 "QEPSTS,QEPSTS" bitfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" rbitfld.word 0x00 6. " FDF ,Direction on the first index marker" "Reverse,Forward" rbitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Reverse,Forward" rbitfld.word 0x00 4. " QDLF ,EQEP direction latch flag" "Reverse,Forward" textline " " eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred" eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred" eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not set,Set by first" rbitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error" group.word 0x03A++0x01 line.word 0x00 "QCTMR,This register provides time base for edge capture unit" group.word 0x03C++0x01 line.word 0x00 "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x03E++0x01 line.word 0x00 "QCTMRLAT,QCTMRLAT" group.word 0x040++0x01 line.word 0x00 "QCPRDLAT,QCPRDLAT" rgroup.long 0x05C++0x03 line.long 0x00 "REVID,EQEP revision ID" width 11. tree.end tree "PWMSS ePWM1 Registers" base ad:0x48302200 width 9. group.word 0x00++0x01 line.word 0x00 "TBCTL,TBCTL" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "Stop after next,Complete stops,Free run,Free run" bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale Bits" "/1,/2,/4,/6,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced" bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled" textline " " bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Shadow,Without shadow" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze" group.word 0x02++0x01 line.word 0x00 "TBSTS,TBSTS" eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit" "Not reached,Reached" eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit" "Not occurred,Occurred" rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" group.word 0x04++0x01 line.word 0x00 "TBPHSHR,TBPHSHR" hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution bits" group.word 0x06++0x01 line.word 0x00 "TBPHS,time-base counter phase of the selected ePWM" group.word 0x08++0x01 line.word 0x00 "TBCNT,Current time-base counter value" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Period of the time-base counter" group.word 0x0E++0x01 line.word 0x00 "CMPCTL,CMPCTL Register" rbitfld.word 0x00 9. " SHDWBFULL , Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full" rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow mode,Immediate mode" textline " " bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow mode,Immediate mode" bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode." "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" group.word 0x10++0x01 line.word 0x00 "CMPAHR,CMPAHR Register" hexmask.word.byte 0x00 8.--15. 1. " CMPAHR , Compare A High-Resolution register bits for MEP step control" group.word 0x12++0x01 line.word 0x00 "CMPA,CMPA Register" group.word 0x14++0x01 line.word 0x00 "CMPB,CMPB Register" group.word 0x16++0x01 line.word 0x00 "AQCTLA,AQCTLA Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggle" group.word 0x18++0x01 line.word 0x00 "AQCTLB,AQCTLB Register" bitfld.word 0x00 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,,Set,Toggle" group.word 0x1A++0x01 line.word 0x00 "AQSFRC,AQSFRC Register" bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Load immediately" bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Initiate" bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Initiate" bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggle" group.word 0x1C++0x01 line.word 0x00 "AQCSFRC,AQCSFRC Register" bitfld.word 0x00 2.--3. " CSFB ,Software forcing is disabled and has no effect" "Disabled,Low,High,Disabled" bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A In immediate mode" "Disabled,Low,High,Disabled" group.word 0x1E++0x01 line.word 0x00 "DBCTL,DBCTL Register" bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "Both,Rising-edge,Fising-edge,Both" bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Bypassed,Rising-edge,Falling-edge,Enabled" group.word 0x20++0x01 line.word 0x00 "DBRED,DBRED Register" hexmask.word 0x00 0.--9. 1. " DEL , Rising Edge Delay Count" group.word 0x22++0x01 line.word 0x00 "DBFED,DBFED Register" hexmask.word 0x00 0.--9. 1. " DEL , Falling Edge Delay Count" group.word 0x24++0x01 line.word 0x00 "TZSEL,TZSEL Register" bitfld.word 0x00 15. " OSHT7 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 14. " OSHT6 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT5 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 12. " OSHT4 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " OSHT3 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 10. " OSHT2 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT1 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT0 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CBC7 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 6. " CBC6 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 5. " CBC5 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 4. " CBC4 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CBC3 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 2. " CBC2 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 0. " CBC0 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,TZCTL Register" bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High impedance,High state,Low state,No action" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High impedance,High state,Low state,No action" group.word 0x2A++0x01 line.word 0x00 "TZEINT,TZEINT Register" bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled" rgroup.word 0x2C++0x01 line.word 0x00 "TZFLG,TZFLG Register" bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred" bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred" bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x2E++0x01 line.word 0x00 "TZCLR,TZCLR Register" bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Clear" bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Clear" group.word 0x30++0x01 line.word 0x00 "TZFRC,TZFRC Register" bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x32++0x01 line.word 0x00 "ETSEL,ETSEL Register" bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,EPWM Interrupt (EPWMx_INT) Selection Options" ",TBCNT =0,TBCNT=TBPRD,,CMPA when incrementing,CMPA when decrementing,CMPB when incrementing,CMPB when decrementing" group.word 0x34++0x01 line.word 0x00 "ETPS,ETPS Register" rbitfld.word 0x00 2.--3. " INTCNT ,EPWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x00 0.--1. " INTPRD ,EPWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event" rgroup.word 0x36++0x01 line.word 0x00 "ETFLG,ETFLG Register" bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "Not occurred,Occurred" rgroup.word 0x38++0x01 line.word 0x00 "ETCLR,ETCLR Register" bitfld.word 0x00 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "No effect,Clear" rgroup.word 0x3A++0x01 line.word 0x00 "ETFRC,ETFRC Register" bitfld.word 0x00 0. " INT ,INT Force Bit" "No interrupt,Interrupt" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PCCTL Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%)," bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "1,2,3,4,5,6,7,8" bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" group.word 0xC0++0x01 line.word 0x00 "HRCNFG,HRCNFG" bitfld.word 0x00 3. " HRLOAD ,Shadow mode bit" "CNT_zero pulse,PRD_eq pulse" bitfld.word 0x00 2. " CTLMODE ,Control Mode Bits" "CMPAHR,TBPHSHR" bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode Bits" "Disabled,Rising edge,Falling edge,Both edges" width 11. tree.end tree.end tree "PWMSS2" tree "PWMSS2 Configuration Registers" width 11. base ad:0x48304000 rgroup.long 0x00++0x03 line.long 0x00 "IDVER,The IP revision register is used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" ",,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "SYSCONFIG,The system configuration register is used for clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode," bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x08++0x03 line.long 0x00 "CLKCONFIG,The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control" bitfld.long 0x00 9. " EPWMCLKSTOP_REQ ,This bit controls the clkstop_req input to the ePWM module" "0,1" bitfld.long 0x00 8. " EPWMCLK_EN ,This bit controls the clk_en input to the ePWM module" "0,1" bitfld.long 0x00 5. " EQEPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEPCLK_EN ,This bit controls the clk_en input to the eQEP module" "0,1" bitfld.long 0x00 1. " ECAPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eCAP module" "0,1" bitfld.long 0x00 0. " ECAPCLK_EN ,This bit controls the clk_en input to the eCAP module" "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "CLKSTATUS,The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status" bitfld.long 0x00 9. " EPWM_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM module" "0,1" bitfld.long 0x00 8. " EPWM_CLK_EN_ACK ,This bit is the clk_en status output of the ePWM module" "0,1" bitfld.long 0x00 5. " EQEP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEP_CLK_EN_ACK ,This bit is the clk_en status output of the eQEP module" "0,1" bitfld.long 0x00 1. " ECAP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eCAP module" "0,1" bitfld.long 0x00 0. " ECAP_CLK_EN_ACK ,This bit is the clk_en status output of the eCAP module" "0,1" width 11. tree.end tree "PWMSS eCAP2 Registers" base ad:0x48304100 width 8. group.long 0x00++0x03 line.long 0x00 "TSCTR,Active 32 bit counter register that is used as the capture time-base" group.long 0x04++0x03 line.long 0x00 "CTRPHS,Counter phase value register" group.long 0x08++0x03 line.long 0x00 "CAP1,CAP1" group.long 0x0C++0x03 line.long 0x00 "CAP2,CAP2" group.long 0x10++0x03 line.long 0x00 "CAP3,Time-stamp capture register" group.long 0x14++0x03 line.long 0x00 "CAP4,Time-stamp capture register" group.word 0x28++0x01 line.word 0x00 "ECCTL1,ECCTL1" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Control" "Stops immediately,Runs until = 0,Run Free,Run Free" bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale select" "1,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62" bitfld.word 0x00 8. " CAPLDEN ,Enable Loading of CAP1 to CAP4 registers on a capture event" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "Not reset,Reset" bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "Rising edge,Falling edge" bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "Not reset,Reset" bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "Not reset,Reset" bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "Rising edge,Falling edge" bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "Not reset,Reset" bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "Rising edge,Falling edge" if (((d.l(ad:0x48304100+0x2A))&0x200)==0x200) //this.CAP_APWM== "APWM" group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECCTL2" bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "Active high,Active low" bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "No effect,Forces a TSCTR" textline " " bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-in,PRDEQ,Disabled,Disabled" bitfld.word 0x00 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " REARM , One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "1,2,3,4" bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control(capture mode)" "Continuous mode,One-shot mode" else group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECCTL2" bitfld.word 0x00 9. " CAP_APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "No effect,Forces a TSCTR" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-in,PRDEQ,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running" bitfld.word 0x00 3. " REARM , One-Shot Re-Arming Control" "No effect,One-shot sequence" textline " " bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "1,2,3,4" bitfld.word 0x00 0. " CONT_ONESHT ,Continuous or one-shot mode control(capture mode)" "Continuous mode,One-shot mode" endif group.word 0x2C++0x01 line.word 0x00 "ECEINT,The interrupt enable bits (CEVTn) block any of the selected events from generating an interrupt" bitfld.word 0x00 7. " CMPEQ ,Counter Equal Compare Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 6. " PRDEQ ,Counter Equal Period Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "Disabled,Enabled" if (((d.l(ad:0x48304100+0x2A))&0x200)==0x200) //this.CAP_APWM== "APWM" rgroup.word 0x2E++0x01 line.word 0x00 "ECFLG,ECFLG" bitfld.word 0x00 7. " CMPEQ ,Compare Equal Compare Status Flag" "No occurred,Occurred" bitfld.word 0x00 6. " PRDEQ ,Counter Equal Period Status Flag" "No occurred,Occurred" textline " " bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Status Flag" "No occurred,Occurred" bitfld.word 0x00 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt" else rgroup.word 0x2E++0x01 line.word 0x00 "ECFLG,ECFLG" bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Status Flag" "No occurred,Occurred" bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Flag" "No occurred,Occurred" bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Flag" "No occurred,Occurred" textline " " bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Flag" "No occurred,Occurred" bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Flag" "No occurred,Occurred" bitfld.word 0x00 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt" endif group.word 0x30++0x01 line.word 0x00 "ECCLR,ECCLR" bitfld.word 0x00 7. " CMPEQ ,Counter Equal Compare Status Flag" "No effect,Clear" bitfld.word 0x00 6. " PRDEQ ,Counter Equal Period Status Flag" "No effect,Clear" bitfld.word 0x00 5. " CNTOVF ,Counter Overflow Status Flag" "No effect,Clear" bitfld.word 0x00 4. " CEVT4 ,Capture Event 4 Status Flag" "No effect,Clear" textline " " bitfld.word 0x00 3. " CEVT3 ,Capture Event 3 Status Flag" "No effect,Clear" bitfld.word 0x00 2. " CEVT2 ,Capture Event 2 Status Flag" "No effect,Clear" bitfld.word 0x00 1. " CEVT1 ,Capture Event 1 Status Flag" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Clear" group.word 0x32++0x01 line.word 0x00 "ECFRC,ECFRC" bitfld.word 0x00 7. " CMPEQ ,Force Counter Equal Compare Interrupt" "No effect,Set" bitfld.word 0x00 6. " PRDEQ ,Force Counter Equal Period Interrupt" "No effect,Set" bitfld.word 0x00 5. " CNTOVF ,Force Counter Overflow" "No effect,Set" bitfld.word 0x00 4. " CEVT4 ,Force Capture Event 4" "No effect,Set" textline " " bitfld.word 0x00 3. " CEVT3 ,Force Capture Event 3" "No effect,Set" bitfld.word 0x00 2. " CEVT2 ,Force Capture Event 2" "No effect,Set" bitfld.word 0x00 1. " CEVT1 ,Force Capture Event 1" "No effect,Set" rgroup.long 0x5C++0x03 line.long 0x00 "REVID,REVID" width 11. tree.end tree "PWMSS eQEP2 Registers" base ad:0x48304180 width 10. group.long 0x000++0x03 line.long 0x00 "QPOSCNT,This 32 bit position counter register counts up/down on every eQEP pulse based on direction input" group.long 0x004++0x03 line.long 0x00 "QPOSINIT,This register contains the position value that is used to initialize the position counter based on external strobe or index event" group.long 0x008++0x03 line.long 0x00 "QPOSMAX,This register contains the maximum position counter value" group.long 0x00C++0x03 line.long 0x00 "QPOSCMP,Generate sync output and/or interrupt on compare match" rgroup.long 0x010++0x03 line.long 0x00 "QPOSILAT,The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits" rgroup.long 0x014++0x03 line.long 0x00 "QPOSSLAT,The position-counter value is latched into this register on strobe event as defined by the QEPCTL[SEL] bits" rgroup.long 0x018++0x03 line.long 0x00 "QPOSLAT,The position-counter value is latched into this register on unit time out event" group.long 0x01C++0x03 line.long 0x00 "QUTMR,This register acts as time base for unit time event generation" group.long 0x020++0x03 line.long 0x00 "QUPRD,This register contains the period count" group.word 0x024++0x01 line.word 0x00 "QWDTMR,This register acts as time base for watch dog to detect motor stalls" group.word 0x026++0x01 line.word 0x00 "QWDPRD,This register contains the time-out count for the eQEP peripheral watch dog timer" group.word 0x028++0x01 line.word 0x00 "QDECCTL,QDECCTL" bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature,Direction,UP,DOWN" bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,1" bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index,Strobe" textline " " bitfld.word 0x00 11. " XCR ,External clock rate" "Rising/falling,Rising" bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disabled,Gated" bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates" textline " " bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates" bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates" bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates" group.word 0x02A++0x01 line.word 0x00 "QEPCTL,QEPCTL" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Control Bits" "Stops immediately,Until rollover,Disabled,Disabled" bitfld.word 0x00 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" bitfld.word 0x00 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising edge,Clockwise Direction" bitfld.word 0x00 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising edge,Falling edge" textline " " eventfld.word 0x00 7. " SWI ,Software initialization of position counter" "Disabled,Initialize" bitfld.word 0x00 6. " SEL ,Strobe event latch of position counter" "0,1" bitfld.word 0x00 4.--5. " IEL ,Index event latch of position counter (software index marker)" ",Rising edge,Falling edge,Software index marker" bitfld.word 0x00 3. " PHEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x00 2. " QCLM ,EQEP capture latch mode" "CPU,Time out" bitfld.word 0x00 1. " UTE ,EQEP unit timer enable" "Disabled,Enabled" bitfld.word 0x00 0. " WDE ,EQEP watchdog enable" "Disabled,Enabled" group.word 0x02C++0x01 line.word 0x00 "QCAPCTL,QCAPCTL" bitfld.word 0x00 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x00 4.--6. " CCPS ,EQEP capture timer clock prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.word 0x00 0.--3. " UPPS ,Unit position event prescaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,,,," group.word 0x02E++0x01 line.word 0x00 "QPOSCTL,QPOSCTL" bitfld.word 0x00 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x00 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP" bitfld.word 0x00 13. " PCPOL ,Polarity of sync output" "Active HIGH,Active LOW" textline " " bitfld.word 0x00 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" hexmask.word 0x00 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" group.word 0x030++0x01 line.word 0x00 "QEINT,QEINT" bitfld.word 0x00 11. " UTO ,Unit time out interrupt enable" "Disabled,Enabled" bitfld.word 0x00 10. " IEL ,Index event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x00 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " PCE ,Position counter error interrupt enable" "Disabled,Enabled" rgroup.word 0x032++0x01 line.word 0x00 "QFLG,QFLG" bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 8. " PCM ,EQEP compare match event interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 4. " WTO ,Watchdog timeout interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x034++0x01 line.word 0x00 "QCLR,QCLR" bitfld.word 0x00 11. " UTO ,Clear unit time out interrupt flag" "No effect,Clear" bitfld.word 0x00 10. " IEL ,Clear index event latch interrupt flag" "No effect,Clear" bitfld.word 0x00 9. " SEL ,Clear strobe event latch interrupt flag" "No effect,Clear" bitfld.word 0x00 8. " PCM ,Clear eQEP compare match event interrupt flag" "No effect,Clear" textline " " bitfld.word 0x00 7. " PCR ,Clear position-compare ready interrupt flag" "No effect,Clear" bitfld.word 0x00 6. " PCO ,Clear position counter overflow interrupt flag" "No effect,Clear" bitfld.word 0x00 5. " PCU ,Clear position counter underflow interrupt flag" "No effect,Clear" bitfld.word 0x00 4. " WTO ,Clear watchdog timeout interrupt flag" "No effect,Clear" textline " " bitfld.word 0x00 3. " QDC ,Clear quadrature direction change interrupt flag" "No effect,Clear" bitfld.word 0x00 2. " PHE ,Clear quadrature phase error interrupt flag" "No effect,Clear" bitfld.word 0x00 1. " PCE ,Clear position counter error interrupt flag" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Clear" group.word 0x036++0x01 line.word 0x00 "QFRC,QFRC" bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Force" bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Force" bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Force" bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Force" textline " " bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Force" bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Force" bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Force" bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Force" textline " " bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Force" bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Force" bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Force" group.word 0x038++0x01 line.word 0x00 "QEPSTS,QEPSTS" bitfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" rbitfld.word 0x00 6. " FDF ,Direction on the first index marker" "Reverse,Forward" rbitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Reverse,Forward" rbitfld.word 0x00 4. " QDLF ,EQEP direction latch flag" "Reverse,Forward" textline " " eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred" eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred" eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not set,Set by first" rbitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error" group.word 0x03A++0x01 line.word 0x00 "QCTMR,This register provides time base for edge capture unit" group.word 0x03C++0x01 line.word 0x00 "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x03E++0x01 line.word 0x00 "QCTMRLAT,QCTMRLAT" group.word 0x040++0x01 line.word 0x00 "QCPRDLAT,QCPRDLAT" rgroup.long 0x05C++0x03 line.long 0x00 "REVID,EQEP revision ID" width 11. tree.end tree "PWMSS ePWM2 Registers" base ad:0x48304200 width 9. group.word 0x00++0x01 line.word 0x00 "TBCTL,TBCTL" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "Stop after next,Complete stops,Free run,Free run" bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale Bits" "/1,/2,/4,/6,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced" bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled" textline " " bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Shadow,Without shadow" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze" group.word 0x02++0x01 line.word 0x00 "TBSTS,TBSTS" eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit" "Not reached,Reached" eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit" "Not occurred,Occurred" rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" group.word 0x04++0x01 line.word 0x00 "TBPHSHR,TBPHSHR" hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution bits" group.word 0x06++0x01 line.word 0x00 "TBPHS,time-base counter phase of the selected ePWM" group.word 0x08++0x01 line.word 0x00 "TBCNT,Current time-base counter value" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Period of the time-base counter" group.word 0x0E++0x01 line.word 0x00 "CMPCTL,CMPCTL Register" rbitfld.word 0x00 9. " SHDWBFULL , Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full" rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow mode,Immediate mode" textline " " bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow mode,Immediate mode" bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode." "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" group.word 0x10++0x01 line.word 0x00 "CMPAHR,CMPAHR Register" hexmask.word.byte 0x00 8.--15. 1. " CMPAHR , Compare A High-Resolution register bits for MEP step control" group.word 0x12++0x01 line.word 0x00 "CMPA,CMPA Register" group.word 0x14++0x01 line.word 0x00 "CMPB,CMPB Register" group.word 0x16++0x01 line.word 0x00 "AQCTLA,AQCTLA Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggle" group.word 0x18++0x01 line.word 0x00 "AQCTLB,AQCTLB Register" bitfld.word 0x00 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,,Set,Toggle" group.word 0x1A++0x01 line.word 0x00 "AQSFRC,AQSFRC Register" bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Load immediately" bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Initiate" bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Initiate" bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggle" group.word 0x1C++0x01 line.word 0x00 "AQCSFRC,AQCSFRC Register" bitfld.word 0x00 2.--3. " CSFB ,Software forcing is disabled and has no effect" "Disabled,Low,High,Disabled" bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A In immediate mode" "Disabled,Low,High,Disabled" group.word 0x1E++0x01 line.word 0x00 "DBCTL,DBCTL Register" bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "Both,Rising-edge,Fising-edge,Both" bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Bypassed,Rising-edge,Falling-edge,Enabled" group.word 0x20++0x01 line.word 0x00 "DBRED,DBRED Register" hexmask.word 0x00 0.--9. 1. " DEL , Rising Edge Delay Count" group.word 0x22++0x01 line.word 0x00 "DBFED,DBFED Register" hexmask.word 0x00 0.--9. 1. " DEL , Falling Edge Delay Count" group.word 0x24++0x01 line.word 0x00 "TZSEL,TZSEL Register" bitfld.word 0x00 15. " OSHT7 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 14. " OSHT6 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT5 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 12. " OSHT4 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " OSHT3 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 10. " OSHT2 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT1 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT0 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CBC7 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 6. " CBC6 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 5. " CBC5 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 4. " CBC4 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CBC3 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 2. " CBC2 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 0. " CBC0 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,TZCTL Register" bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High impedance,High state,Low state,No action" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High impedance,High state,Low state,No action" group.word 0x2A++0x01 line.word 0x00 "TZEINT,TZEINT Register" bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled" rgroup.word 0x2C++0x01 line.word 0x00 "TZFLG,TZFLG Register" bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred" bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred" bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x2E++0x01 line.word 0x00 "TZCLR,TZCLR Register" bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Clear" bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Clear" group.word 0x30++0x01 line.word 0x00 "TZFRC,TZFRC Register" bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x32++0x01 line.word 0x00 "ETSEL,ETSEL Register" bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,EPWM Interrupt (EPWMx_INT) Selection Options" ",TBCNT =0,TBCNT=TBPRD,,CMPA when incrementing,CMPA when decrementing,CMPB when incrementing,CMPB when decrementing" group.word 0x34++0x01 line.word 0x00 "ETPS,ETPS Register" rbitfld.word 0x00 2.--3. " INTCNT ,EPWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x00 0.--1. " INTPRD ,EPWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event" rgroup.word 0x36++0x01 line.word 0x00 "ETFLG,ETFLG Register" bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "Not occurred,Occurred" rgroup.word 0x38++0x01 line.word 0x00 "ETCLR,ETCLR Register" bitfld.word 0x00 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "No effect,Clear" rgroup.word 0x3A++0x01 line.word 0x00 "ETFRC,ETFRC Register" bitfld.word 0x00 0. " INT ,INT Force Bit" "No interrupt,Interrupt" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PCCTL Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%)," bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "1,2,3,4,5,6,7,8" bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" group.word 0xC0++0x01 line.word 0x00 "HRCNFG,HRCNFG" bitfld.word 0x00 3. " HRLOAD ,Shadow mode bit" "CNT_zero pulse,PRD_eq pulse" bitfld.word 0x00 2. " CTLMODE ,Control Mode Bits" "CMPAHR,TBPHSHR" bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode Bits" "Disabled,Rising edge,Falling edge,Both edges" width 11. tree.end tree.end tree "PWMSS3" tree "PWMSS3 Configuration Registers" width 11. base ad:0x48306000 rgroup.long 0x00++0x03 line.long 0x00 "IDVER,The IP revision register is used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" ",,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "SYSCONFIG,The system configuration register is used for clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode," bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x08++0x03 line.long 0x00 "CLKCONFIG,The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control" bitfld.long 0x00 9. " EPWMCLKSTOP_REQ ,This bit controls the clkstop_req input to the ePWM module" "0,1" bitfld.long 0x00 8. " EPWMCLK_EN ,This bit controls the clk_en input to the ePWM module" "0,1" bitfld.long 0x00 5. " EQEPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEPCLK_EN ,This bit controls the clk_en input to the eQEP module" "0,1" bitfld.long 0x00 1. " ECAPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eCAP module" "0,1" bitfld.long 0x00 0. " ECAPCLK_EN ,This bit controls the clk_en input to the eCAP module" "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "CLKSTATUS,The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status" bitfld.long 0x00 9. " EPWM_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM module" "0,1" bitfld.long 0x00 8. " EPWM_CLK_EN_ACK ,This bit is the clk_en status output of the ePWM module" "0,1" bitfld.long 0x00 5. " EQEP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEP_CLK_EN_ACK ,This bit is the clk_en status output of the eQEP module" "0,1" bitfld.long 0x00 1. " ECAP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eCAP module" "0,1" bitfld.long 0x00 0. " ECAP_CLK_EN_ACK ,This bit is the clk_en status output of the eCAP module" "0,1" width 11. tree.end tree "PWMSS ePWM3 Registers" base ad:0x48306200 width 9. group.word 0x00++0x01 line.word 0x00 "TBCTL,TBCTL" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "Stop after next,Complete stops,Free run,Free run" bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale Bits" "/1,/2,/4,/6,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced" bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled" textline " " bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Shadow,Without shadow" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze" group.word 0x02++0x01 line.word 0x00 "TBSTS,TBSTS" eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit" "Not reached,Reached" eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit" "Not occurred,Occurred" rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" group.word 0x04++0x01 line.word 0x00 "TBPHSHR,TBPHSHR" hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution bits" group.word 0x06++0x01 line.word 0x00 "TBPHS,time-base counter phase of the selected ePWM" group.word 0x08++0x01 line.word 0x00 "TBCNT,Current time-base counter value" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Period of the time-base counter" group.word 0x0E++0x01 line.word 0x00 "CMPCTL,CMPCTL Register" rbitfld.word 0x00 9. " SHDWBFULL , Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full" rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow mode,Immediate mode" textline " " bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow mode,Immediate mode" bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode." "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" group.word 0x10++0x01 line.word 0x00 "CMPAHR,CMPAHR Register" hexmask.word.byte 0x00 8.--15. 1. " CMPAHR , Compare A High-Resolution register bits for MEP step control" group.word 0x12++0x01 line.word 0x00 "CMPA,CMPA Register" group.word 0x14++0x01 line.word 0x00 "CMPB,CMPB Register" group.word 0x16++0x01 line.word 0x00 "AQCTLA,AQCTLA Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggle" group.word 0x18++0x01 line.word 0x00 "AQCTLB,AQCTLB Register" bitfld.word 0x00 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,,Set,Toggle" group.word 0x1A++0x01 line.word 0x00 "AQSFRC,AQSFRC Register" bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Load immediately" bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Initiate" bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Initiate" bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggle" group.word 0x1C++0x01 line.word 0x00 "AQCSFRC,AQCSFRC Register" bitfld.word 0x00 2.--3. " CSFB ,Software forcing is disabled and has no effect" "Disabled,Low,High,Disabled" bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A In immediate mode" "Disabled,Low,High,Disabled" group.word 0x1E++0x01 line.word 0x00 "DBCTL,DBCTL Register" bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "Both,Rising-edge,Fising-edge,Both" bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Bypassed,Rising-edge,Falling-edge,Enabled" group.word 0x20++0x01 line.word 0x00 "DBRED,DBRED Register" hexmask.word 0x00 0.--9. 1. " DEL , Rising Edge Delay Count" group.word 0x22++0x01 line.word 0x00 "DBFED,DBFED Register" hexmask.word 0x00 0.--9. 1. " DEL , Falling Edge Delay Count" group.word 0x24++0x01 line.word 0x00 "TZSEL,TZSEL Register" bitfld.word 0x00 15. " OSHT7 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 14. " OSHT6 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT5 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 12. " OSHT4 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " OSHT3 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 10. " OSHT2 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT1 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT0 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CBC7 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 6. " CBC6 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 5. " CBC5 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 4. " CBC4 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CBC3 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 2. " CBC2 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 0. " CBC0 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,TZCTL Register" bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High impedance,High state,Low state,No action" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High impedance,High state,Low state,No action" group.word 0x2A++0x01 line.word 0x00 "TZEINT,TZEINT Register" bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled" rgroup.word 0x2C++0x01 line.word 0x00 "TZFLG,TZFLG Register" bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred" bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred" bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x2E++0x01 line.word 0x00 "TZCLR,TZCLR Register" bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Clear" bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Clear" group.word 0x30++0x01 line.word 0x00 "TZFRC,TZFRC Register" bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x32++0x01 line.word 0x00 "ETSEL,ETSEL Register" bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,EPWM Interrupt (EPWMx_INT) Selection Options" ",TBCNT =0,TBCNT=TBPRD,,CMPA when incrementing,CMPA when decrementing,CMPB when incrementing,CMPB when decrementing" group.word 0x34++0x01 line.word 0x00 "ETPS,ETPS Register" rbitfld.word 0x00 2.--3. " INTCNT ,EPWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x00 0.--1. " INTPRD ,EPWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event" rgroup.word 0x36++0x01 line.word 0x00 "ETFLG,ETFLG Register" bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "Not occurred,Occurred" rgroup.word 0x38++0x01 line.word 0x00 "ETCLR,ETCLR Register" bitfld.word 0x00 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "No effect,Clear" rgroup.word 0x3A++0x01 line.word 0x00 "ETFRC,ETFRC Register" bitfld.word 0x00 0. " INT ,INT Force Bit" "No interrupt,Interrupt" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PCCTL Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%)," bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "1,2,3,4,5,6,7,8" bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" group.word 0xC0++0x01 line.word 0x00 "HRCNFG,HRCNFG" bitfld.word 0x00 3. " HRLOAD ,Shadow mode bit" "CNT_zero pulse,PRD_eq pulse" bitfld.word 0x00 2. " CTLMODE ,Control Mode Bits" "CMPAHR,TBPHSHR" bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode Bits" "Disabled,Rising edge,Falling edge,Both edges" width 11. tree.end tree.end tree "PWMSS4" tree "PWMSS4 Configuration Registers" width 11. base ad:0x48308000 rgroup.long 0x00++0x03 line.long 0x00 "IDVER,The IP revision register is used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" ",,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "SYSCONFIG,The system configuration register is used for clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode," bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x08++0x03 line.long 0x00 "CLKCONFIG,The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control" bitfld.long 0x00 9. " EPWMCLKSTOP_REQ ,This bit controls the clkstop_req input to the ePWM module" "0,1" bitfld.long 0x00 8. " EPWMCLK_EN ,This bit controls the clk_en input to the ePWM module" "0,1" bitfld.long 0x00 5. " EQEPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEPCLK_EN ,This bit controls the clk_en input to the eQEP module" "0,1" bitfld.long 0x00 1. " ECAPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eCAP module" "0,1" bitfld.long 0x00 0. " ECAPCLK_EN ,This bit controls the clk_en input to the eCAP module" "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "CLKSTATUS,The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status" bitfld.long 0x00 9. " EPWM_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM module" "0,1" bitfld.long 0x00 8. " EPWM_CLK_EN_ACK ,This bit is the clk_en status output of the ePWM module" "0,1" bitfld.long 0x00 5. " EQEP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEP_CLK_EN_ACK ,This bit is the clk_en status output of the eQEP module" "0,1" bitfld.long 0x00 1. " ECAP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eCAP module" "0,1" bitfld.long 0x00 0. " ECAP_CLK_EN_ACK ,This bit is the clk_en status output of the eCAP module" "0,1" width 11. tree.end tree "PWMSS ePWM4 Registers" base ad:0x48308200 width 17. rgroup.long 0x000++0x03 line.long 0x00 "WDT_WIDR,Watchdog Identification Register" hexmask.long 0x00 0.--31. 1. " REVISION , IP Revision" group.long 0x010++0x03 line.long 0x00 "WDT_WDSC,The Watchdog System Control Register controls the various parameters of the L4 interface" bitfld.long 0x00 5. " EMUFREE ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Frozen,Free-running" bitfld.long 0x00 3.--4. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No action,Reset" rgroup.long 0x014++0x03 line.long 0x00 "WDT_WDST,The Watchdog Status Register provides status information about the module" bitfld.long 0x00 0. " RESETDONE ,Internal module reset monitoring" "Ongoing,Completed" group.long 0x018++0x03 line.long 0x00 "WDT_WISR,The Watchdog Interrupt Status Register shows which interrupt events are pending inside the module" bitfld.long 0x00 1. " DLY_IT_FLAG ,Pending delay interrupt status" "No delay,Delay" bitfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "No overflow,Overflow" group.long 0x01C++0x03 line.long 0x00 "WDT_WIER,The Watchdog Interrupt Enable Register controls (enable/disable) the interrupt events" bitfld.long 0x00 1. " DLY_IT_ENA ,Delay interrupt enable/disable" "Disabled,Enabled" bitfld.long 0x00 0. " OVF_IT_ENA ,Overflow interrupt enable/disable" "Disabled,Enabled" group.long 0x024++0x03 line.long 0x00 "WDT_WCLR,The Watchdog Control Register controls the prescaler stage of the counter" bitfld.long 0x00 5. " PRE ,Prescaler enable/disable configuration" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV , Prescaler value" "0,1,2,3,4,5,6,7" group.long 0x028++0x03 line.long 0x00 "WDT_WCRR,The Watchdog Counter Register holds the value of the internal counter" group.long 0x02C++0x03 line.long 0x00 "WDT_WLDR,The Watchdog Load Register holds the timer load value" group.long 0x030++0x03 line.long 0x00 "WDT_WTGR,Writing a different value than the one already written in the Watchdog Trigger Register does a watchdog counter reload" rgroup.long 0x034++0x03 line.long 0x00 "WDT_WWPS,The Watchdog Write Posting Bits Register contains the write posting bits for all writeable functional registers" bitfld.long 0x00 5. " W_PEND_WDLY ,Write pending for register WDLY" "No,Yes" bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "No,Yes" bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "No,Yes" textline " " bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "No,Yes" bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "No,Yes" bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "No,Yes" group.long 0x044++0x03 line.long 0x00 "WDT_WDLY,The Watchdog Delay Configuration Register holds the delay value that controls the internal pre-overflow event detection" group.long 0x048++0x03 line.long 0x00 "WDT_WSPR,The Watchdog Start/Stop Register holds the start-stop value that controls the internal start-stop FSM" group.long 0x054++0x03 line.long 0x00 "WDT_WIRQSTATRAW,WDT_WIRQSTATRAW register" bitfld.long 0x00 1. " EVT_DLY ,Settable raw status for delay event" "No pending,Pending" bitfld.long 0x00 0. " EVT_OVF ,Settable raw status for overflow event" "No pending,Pending" group.long 0x058++0x03 line.long 0x00 "WDT_WIRQSTAT,WDT_WIRQSTAT register" eventfld.long 0x00 1. " EVT_DLY ,Clearable enabled status for delay event" "No action,Clear" eventfld.long 0x00 0. " EVT_OVF ,Clearable enabled status for overflow event" "No action,Clear" group.long 0x05C++0x03 line.long 0x00 "WDT_WIRQENSET,WDT_WIRQENSET register" bitfld.long 0x00 1. " EN_DLY ,Enable for delay event" "Disabled,Enabled" bitfld.long 0x00 0. " EN_OVF ,Enable for overflow event" "Disabled,Enabled" group.long 0x060++0x03 line.long 0x00 "WDT_WIRQENCLR,WDT_WIRQENCLR register" bitfld.long 0x00 1. " EN_DLY ,Enable for delay event" "Disabled,Enabled" bitfld.long 0x00 0. " EN_OVF ,Enable for overflow event" "Disabled,Enabled" width 11. tree.end tree.end tree "PWMSS5" tree "PWMSS5 Configuration Registers" width 11. base ad:0x4830A000 rgroup.long 0x00++0x03 line.long 0x00 "IDVER,The IP revision register is used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" ",,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x04++0x03 line.long 0x00 "SYSCONFIG,The system configuration register is used for clock management configuration" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby," bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode," bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend event from Debug Subsystem" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x08++0x03 line.long 0x00 "CLKCONFIG,The clock configuration register is used in the PWMSS submodule for clkstop req and clk_en control" bitfld.long 0x00 9. " EPWMCLKSTOP_REQ ,This bit controls the clkstop_req input to the ePWM module" "0,1" bitfld.long 0x00 8. " EPWMCLK_EN ,This bit controls the clk_en input to the ePWM module" "0,1" bitfld.long 0x00 5. " EQEPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEPCLK_EN ,This bit controls the clk_en input to the eQEP module" "0,1" bitfld.long 0x00 1. " ECAPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eCAP module" "0,1" bitfld.long 0x00 0. " ECAPCLK_EN ,This bit controls the clk_en input to the eCAP module" "0,1" rgroup.long 0x0C++0x03 line.long 0x00 "CLKSTATUS,The clock status register is used in the PWMSS submodule for clkstop ack and clk_en ack status" bitfld.long 0x00 9. " EPWM_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM module" "0,1" bitfld.long 0x00 8. " EPWM_CLK_EN_ACK ,This bit is the clk_en status output of the ePWM module" "0,1" bitfld.long 0x00 5. " EQEP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module" "0,1" textline " " bitfld.long 0x00 4. " EQEP_CLK_EN_ACK ,This bit is the clk_en status output of the eQEP module" "0,1" bitfld.long 0x00 1. " ECAP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eCAP module" "0,1" bitfld.long 0x00 0. " ECAP_CLK_EN_ACK ,This bit is the clk_en status output of the eCAP module" "0,1" width 11. tree.end tree "PWMSS ePWM5 Registers" base ad:0x4830A200 width 9. group.word 0x00++0x01 line.word 0x00 "TBCTL,TBCTL" bitfld.word 0x00 14.--15. " FREE_SOFT ,Emulation Mode Bits" "Stop after next,Complete stops,Free run,Free run" bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale Bits" "/1,/2,/4,/6,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced" bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled" textline " " bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Shadow,Without shadow" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze" group.word 0x02++0x01 line.word 0x00 "TBSTS,TBSTS" eventfld.word 0x00 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit" "Not reached,Reached" eventfld.word 0x00 1. " SYNCI ,Input Synchronization Latched Status Bit" "Not occurred,Occurred" rbitfld.word 0x00 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" group.word 0x04++0x01 line.word 0x00 "TBPHSHR,TBPHSHR" hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution bits" group.word 0x06++0x01 line.word 0x00 "TBPHS,time-base counter phase of the selected ePWM" group.word 0x08++0x01 line.word 0x00 "TBCNT,Current time-base counter value" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Period of the time-base counter" group.word 0x0E++0x01 line.word 0x00 "CMPCTL,CMPCTL Register" rbitfld.word 0x00 9. " SHDWBFULL , Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full" rbitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow mode,Immediate mode" textline " " bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow mode,Immediate mode" bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode." "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR = 0,CTR = PRD,CTR = 0 or CTR = PRD,Freeze" group.word 0x10++0x01 line.word 0x00 "CMPAHR,CMPAHR Register" hexmask.word.byte 0x00 8.--15. 1. " CMPAHR , Compare A High-Resolution register bits for MEP step control" group.word 0x12++0x01 line.word 0x00 "CMPA,CMPA Register" group.word 0x14++0x01 line.word 0x00 "CMPB,CMPB Register" group.word 0x16++0x01 line.word 0x00 "AQCTLA,AQCTLA Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggle" group.word 0x18++0x01 line.word 0x00 "AQCTLB,AQCTLB Register" bitfld.word 0x00 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,,Set,Toggle" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,,Set,Toggle" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,,Set,Toggle" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,,Set,Toggle" group.word 0x1A++0x01 line.word 0x00 "AQSFRC,AQSFRC Register" bitfld.word 0x00 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Load immediately" bitfld.word 0x00 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Initiate" bitfld.word 0x00 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggle" textline " " bitfld.word 0x00 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Initiate" bitfld.word 0x00 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggle" group.word 0x1C++0x01 line.word 0x00 "AQCSFRC,AQCSFRC Register" bitfld.word 0x00 2.--3. " CSFB ,Software forcing is disabled and has no effect" "Disabled,Low,High,Disabled" bitfld.word 0x00 0.--1. " CSFA ,Continuous Software Force on Output A In immediate mode" "Disabled,Low,High,Disabled" group.word 0x1E++0x01 line.word 0x00 "DBCTL,DBCTL Register" bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "Both,Rising-edge,Fising-edge,Both" bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Bypassed,Rising-edge,Falling-edge,Enabled" group.word 0x20++0x01 line.word 0x00 "DBRED,DBRED Register" hexmask.word 0x00 0.--9. 1. " DEL , Rising Edge Delay Count" group.word 0x22++0x01 line.word 0x00 "DBFED,DBFED Register" hexmask.word 0x00 0.--9. 1. " DEL , Falling Edge Delay Count" group.word 0x24++0x01 line.word 0x00 "TZSEL,TZSEL Register" bitfld.word 0x00 15. " OSHT7 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 14. " OSHT6 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT5 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 12. " OSHT4 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " OSHT3 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 10. " OSHT2 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT1 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT0 ,One-Shot (OSHT) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " CBC7 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 6. " CBC6 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 5. " CBC5 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 4. " CBC4 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CBC3 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 2. " CBC2 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" bitfld.word 0x00 0. " CBC0 ,Cycle-by-Cycle (CBC) trip-zone enable/disable" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,TZCTL Register" bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High impedance,High state,Low state,No action" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High impedance,High state,Low state,No action" group.word 0x2A++0x01 line.word 0x00 "TZEINT,TZEINT Register" bitfld.word 0x00 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled" bitfld.word 0x00 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled" rgroup.word 0x2C++0x01 line.word 0x00 "TZFLG,TZFLG Register" bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred" bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred" bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x2E++0x01 line.word 0x00 "TZCLR,TZCLR Register" bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Clear" bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Clear" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Clear" group.word 0x30++0x01 line.word 0x00 "TZFRC,TZFRC Register" bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x32++0x01 line.word 0x00 "ETSEL,ETSEL Register" bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,EPWM Interrupt (EPWMx_INT) Selection Options" ",TBCNT =0,TBCNT=TBPRD,,CMPA when incrementing,CMPA when decrementing,CMPB when incrementing,CMPB when decrementing" group.word 0x34++0x01 line.word 0x00 "ETPS,ETPS Register" rbitfld.word 0x00 2.--3. " INTCNT ,EPWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x00 0.--1. " INTPRD ,EPWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event" rgroup.word 0x36++0x01 line.word 0x00 "ETFLG,ETFLG Register" bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "Not occurred,Occurred" rgroup.word 0x38++0x01 line.word 0x00 "ETCLR,ETCLR Register" bitfld.word 0x00 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear Bit" "No effect,Clear" rgroup.word 0x3A++0x01 line.word 0x00 "ETFRC,ETFRC Register" bitfld.word 0x00 0. " INT ,INT Force Bit" "No interrupt,Interrupt" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PCCTL Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%)," bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "1,2,3,4,5,6,7,8" bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" group.word 0xC0++0x01 line.word 0x00 "HRCNFG,HRCNFG" bitfld.word 0x00 3. " HRLOAD ,Shadow mode bit" "CNT_zero pulse,PRD_eq pulse" bitfld.word 0x00 2. " CTLMODE ,Control Mode Bits" "CMPAHR,TBPHSHR" bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode Bits" "Disabled,Rising edge,Falling edge,Both edges" width 11. tree.end tree.end tree.end tree "UART(Universal Asynchronous Receiver/Transmitter)" tree "UART 0" base ad:0x44E09000 width 18. if (((d.w(ad:0x44E09000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x06) wgroup.word 0x00++0x01 line.word 0x00 "THR,Transmit holding register " hexmask.word.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.word 0x04++0x01 line.word 0x00 "IER_CIR,Following interrupt enable register" bitfld.word 0x00 5. " TXSTATUSIT ,TXSTATUSIT" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,RXOVERRUNIT" "Disabled,Enabled" bitfld.word 0x00 2. " RXSTOPIT ,RXSTOPIT" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,THRIT" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,RHRIT" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x44E09000+0x08))&0x10)==0x00)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x44E09000+0x08))&0x10)==0x01)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x44E09000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x05)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x04)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x01) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_IRDA,Following interrupt enable register (IER) description is for IrDA mode" bitfld.word 0x00 7. " EOFIT ,Enable/Disable the received EOF interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " LINESTSIT ,Enable/Disable the receiver line status interrupt" "Disabled,Enabled" bitfld.word 0x00 5. " TXSTATUSIT ,Enable/Disable the TX status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " STSFIFOTRIGIT ,Enable/Disable status FIFO trigger level interrupt" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,Enable/Disable the RX overrun interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LASTRXBYTEIT ,Enable/Disable the last byte of frame in RX FIFO interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Enable/Disable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Enable/Disable the RHR interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_IRDA,IIR_IRDA" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt active/active" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x44E09000+0x08))&0x10)==0x00)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x44E09000+0x08))&0x10)==0x01)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x38++0x01 line.word 0x00 "BLR,The BOF control register" bitfld.word 0x00 7. " STSFIFORESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOFTYPE ,SIR xBOF select" "FF,C0" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x44E09000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x00)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x02)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x03) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_UART,The following interrupt enable register (IER) description is for UART mode" bitfld.word 0x00 7. " CTSIT ,Disable/Enable the CTS (active-low) interrupt" "0,1" bitfld.word 0x00 6. " RTSIT ,Disable/Enable the RTS (active-low) interrupt" "0,1" bitfld.word 0x00 5. " XOFFIT ,Disable/Enable the XOFF interrupt" "0,1" textline " " bitfld.word 0x00 4. " SLEEPMODE ,Disable/Enable sleep mode" "Disabled,Enabled" bitfld.word 0x00 3. " MODEMSTSIT ,Disables/Enabled the modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LINESTSIT ,Disable/Enable the receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Disable/Enable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Disable/Enable the RHR interrupt and time out interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x44E09000+0x08))&0x10)==0x00)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x44E09000+0x08))&0x10)==0x01)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x01)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x04)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x00)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x02)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "XOFF1,The XOFF1" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,Stores the 8 bit XOFF1 character in UART modes" if (((d.w(ad:0x44E09000+0x08))&0x10)==0x01)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x44E09000+0x08))&0x10)==0x00)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "XOFF2,The XOFF2 register is selected with a register bit setting of LCR[7]=BF" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,Stores the 8 bit XOFF2 character in UART modes" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x44E09000+0x08))&0x10)==0x01)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x44E09000+0x08))&0x10)==0x00)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x00)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x02)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x44E09000+0x08))&0x10)==0x01)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x44E09000+0x08))&0x10)==0x00)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x01)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x04)||(((d.w(ad:0x44E09000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x44E09000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x44E09000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x44E09000+0x08))&0x10)==0x01)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x44E09000+0x08))&0x10)==0x00)&&(((d.w(ad:0x44E09000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" else hgroup.word 0x00++0x01 hide.word 0x00 "DLL,The divisor latches low register " hgroup.word 0x04++0x01 hide.word 0x00 "DLH,The divisor latches high register" hgroup.word 0x08++0x01 hide.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" hgroup.word 0x08++0x01 hide.word 0x00 "FCR,The FIFO control register" hgroup.word 0x0C++0x01 hide.word 0x00 "LCR,Line control register" hgroup.word 0x14++0x01 hide.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" hgroup.word 0x18++0x01 hide.word 0x00 "TCR,Transmission control register" hgroup.word 0x18++0x01 hide.word 0x00 "MSR,The modem status register" hgroup.word 0x1C++0x01 hide.word 0x00 "TLR,The trigger level register" hgroup.word 0x1C++0x01 hide.word 0x00 "SPR,Scratchpad register" hgroup.word 0x20++0x01 hide.word 0x00 "MDR1,Mode definition register 1" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode definition register 2" hgroup.word 0x28++0x01 hide.word 0x00 "SFLSR,The status FIFO line status register" hgroup.word 0x28++0x01 hide.word 0x00 "TXFLL,Transmit frame length low register" hgroup.word 0x2C++0x01 hide.word 0x00 "RESUME,The RESUME register " hgroup.word 0x2C++0x01 hide.word 0x00 "TXFLH,The transmit frame length high register" hgroup.word 0x30++0x01 hide.word 0x00 "SFREGL,The status FIFO register low" hgroup.word 0x30++0x01 hide.word 0x00 "RXFLL,Received frame length low register" hgroup.word 0x34++0x01 hide.word 0x00 "SFREGH,Status FIFO register high" hgroup.word 0x34++0x01 hide.word 0x00 "RXFLH,The received frame length high register" hgroup.word 0x40++0x01 hide.word 0x00 "SCR,The supplementary control register " hgroup.word 0x44++0x01 hide.word 0x00 "SSR,The supplementary status register " hgroup.word 0x50++0x01 hide.word 0x00 "MVR,The module version register" hgroup.word 0x54++0x01 hide.word 0x00 "SYSC,The system configuration register " hgroup.word 0x64++0x01 hide.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hgroup.word 0x68++0x01 hide.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hgroup.word 0x6C++0x01 hide.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" hgroup.word 0x70++0x01 hide.word 0x00 "ISR2,Interrupt status register 2" hgroup.word 0x74++0x01 hide.word 0x00 "FREQ_SEL,FREQ_SEL" hgroup.word 0x80++0x01 hide.word 0x00 "MDR3,Mode definition register 3" hgroup.word 0x84++0x01 hide.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " endif width 11. tree.end tree "UART 1" base ad:0x48022000 width 18. if (((d.w(ad:0x48022000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x06) wgroup.word 0x00++0x01 line.word 0x00 "THR,Transmit holding register " hexmask.word.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.word 0x04++0x01 line.word 0x00 "IER_CIR,Following interrupt enable register" bitfld.word 0x00 5. " TXSTATUSIT ,TXSTATUSIT" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,RXOVERRUNIT" "Disabled,Enabled" bitfld.word 0x00 2. " RXSTOPIT ,RXSTOPIT" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,THRIT" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,RHRIT" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48022000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48022000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48022000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x05)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x04)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x01) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_IRDA,Following interrupt enable register (IER) description is for IrDA mode" bitfld.word 0x00 7. " EOFIT ,Enable/Disable the received EOF interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " LINESTSIT ,Enable/Disable the receiver line status interrupt" "Disabled,Enabled" bitfld.word 0x00 5. " TXSTATUSIT ,Enable/Disable the TX status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " STSFIFOTRIGIT ,Enable/Disable status FIFO trigger level interrupt" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,Enable/Disable the RX overrun interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LASTRXBYTEIT ,Enable/Disable the last byte of frame in RX FIFO interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Enable/Disable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Enable/Disable the RHR interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_IRDA,IIR_IRDA" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt active/active" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48022000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48022000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x38++0x01 line.word 0x00 "BLR,The BOF control register" bitfld.word 0x00 7. " STSFIFORESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOFTYPE ,SIR xBOF select" "FF,C0" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48022000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x00)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x02)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x03) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_UART,The following interrupt enable register (IER) description is for UART mode" bitfld.word 0x00 7. " CTSIT ,Disable/Enable the CTS (active-low) interrupt" "0,1" bitfld.word 0x00 6. " RTSIT ,Disable/Enable the RTS (active-low) interrupt" "0,1" bitfld.word 0x00 5. " XOFFIT ,Disable/Enable the XOFF interrupt" "0,1" textline " " bitfld.word 0x00 4. " SLEEPMODE ,Disable/Enable sleep mode" "Disabled,Enabled" bitfld.word 0x00 3. " MODEMSTSIT ,Disables/Enabled the modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LINESTSIT ,Disable/Enable the receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Disable/Enable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Disable/Enable the RHR interrupt and time out interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48022000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48022000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x01)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x04)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x00)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x02)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "XOFF1,The XOFF1" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,Stores the 8 bit XOFF1 character in UART modes" if (((d.w(ad:0x48022000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48022000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "XOFF2,The XOFF2 register is selected with a register bit setting of LCR[7]=BF" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,Stores the 8 bit XOFF2 character in UART modes" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48022000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48022000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x00)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x02)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48022000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48022000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x01)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x04)||(((d.w(ad:0x48022000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48022000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48022000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48022000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48022000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48022000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" else hgroup.word 0x00++0x01 hide.word 0x00 "DLL,The divisor latches low register " hgroup.word 0x04++0x01 hide.word 0x00 "DLH,The divisor latches high register" hgroup.word 0x08++0x01 hide.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" hgroup.word 0x08++0x01 hide.word 0x00 "FCR,The FIFO control register" hgroup.word 0x0C++0x01 hide.word 0x00 "LCR,Line control register" hgroup.word 0x14++0x01 hide.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" hgroup.word 0x18++0x01 hide.word 0x00 "TCR,Transmission control register" hgroup.word 0x18++0x01 hide.word 0x00 "MSR,The modem status register" hgroup.word 0x1C++0x01 hide.word 0x00 "TLR,The trigger level register" hgroup.word 0x1C++0x01 hide.word 0x00 "SPR,Scratchpad register" hgroup.word 0x20++0x01 hide.word 0x00 "MDR1,Mode definition register 1" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode definition register 2" hgroup.word 0x28++0x01 hide.word 0x00 "SFLSR,The status FIFO line status register" hgroup.word 0x28++0x01 hide.word 0x00 "TXFLL,Transmit frame length low register" hgroup.word 0x2C++0x01 hide.word 0x00 "RESUME,The RESUME register " hgroup.word 0x2C++0x01 hide.word 0x00 "TXFLH,The transmit frame length high register" hgroup.word 0x30++0x01 hide.word 0x00 "SFREGL,The status FIFO register low" hgroup.word 0x30++0x01 hide.word 0x00 "RXFLL,Received frame length low register" hgroup.word 0x34++0x01 hide.word 0x00 "SFREGH,Status FIFO register high" hgroup.word 0x34++0x01 hide.word 0x00 "RXFLH,The received frame length high register" hgroup.word 0x40++0x01 hide.word 0x00 "SCR,The supplementary control register " hgroup.word 0x44++0x01 hide.word 0x00 "SSR,The supplementary status register " hgroup.word 0x50++0x01 hide.word 0x00 "MVR,The module version register" hgroup.word 0x54++0x01 hide.word 0x00 "SYSC,The system configuration register " hgroup.word 0x64++0x01 hide.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hgroup.word 0x68++0x01 hide.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hgroup.word 0x6C++0x01 hide.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" hgroup.word 0x70++0x01 hide.word 0x00 "ISR2,Interrupt status register 2" hgroup.word 0x74++0x01 hide.word 0x00 "FREQ_SEL,FREQ_SEL" hgroup.word 0x80++0x01 hide.word 0x00 "MDR3,Mode definition register 3" hgroup.word 0x84++0x01 hide.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " endif width 11. tree.end tree "UART 2" base ad:0x48024000 width 18. if (((d.w(ad:0x48024000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x06) wgroup.word 0x00++0x01 line.word 0x00 "THR,Transmit holding register " hexmask.word.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.word 0x04++0x01 line.word 0x00 "IER_CIR,Following interrupt enable register" bitfld.word 0x00 5. " TXSTATUSIT ,TXSTATUSIT" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,RXOVERRUNIT" "Disabled,Enabled" bitfld.word 0x00 2. " RXSTOPIT ,RXSTOPIT" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,THRIT" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,RHRIT" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48024000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48024000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48024000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x05)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x04)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x01) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_IRDA,Following interrupt enable register (IER) description is for IrDA mode" bitfld.word 0x00 7. " EOFIT ,Enable/Disable the received EOF interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " LINESTSIT ,Enable/Disable the receiver line status interrupt" "Disabled,Enabled" bitfld.word 0x00 5. " TXSTATUSIT ,Enable/Disable the TX status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " STSFIFOTRIGIT ,Enable/Disable status FIFO trigger level interrupt" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,Enable/Disable the RX overrun interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LASTRXBYTEIT ,Enable/Disable the last byte of frame in RX FIFO interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Enable/Disable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Enable/Disable the RHR interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_IRDA,IIR_IRDA" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt active/active" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48024000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48024000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x38++0x01 line.word 0x00 "BLR,The BOF control register" bitfld.word 0x00 7. " STSFIFORESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOFTYPE ,SIR xBOF select" "FF,C0" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48024000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x00)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x02)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x03) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_UART,The following interrupt enable register (IER) description is for UART mode" bitfld.word 0x00 7. " CTSIT ,Disable/Enable the CTS (active-low) interrupt" "0,1" bitfld.word 0x00 6. " RTSIT ,Disable/Enable the RTS (active-low) interrupt" "0,1" bitfld.word 0x00 5. " XOFFIT ,Disable/Enable the XOFF interrupt" "0,1" textline " " bitfld.word 0x00 4. " SLEEPMODE ,Disable/Enable sleep mode" "Disabled,Enabled" bitfld.word 0x00 3. " MODEMSTSIT ,Disables/Enabled the modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LINESTSIT ,Disable/Enable the receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Disable/Enable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Disable/Enable the RHR interrupt and time out interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48024000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48024000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x01)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x04)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x00)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x02)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "XOFF1,The XOFF1" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,Stores the 8 bit XOFF1 character in UART modes" if (((d.w(ad:0x48024000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48024000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "XOFF2,The XOFF2 register is selected with a register bit setting of LCR[7]=BF" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,Stores the 8 bit XOFF2 character in UART modes" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48024000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48024000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x00)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x02)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48024000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48024000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x01)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x04)||(((d.w(ad:0x48024000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x48024000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x48024000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x48024000+0x08))&0x10)==0x01)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x48024000+0x08))&0x10)==0x00)&&(((d.w(ad:0x48024000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" else hgroup.word 0x00++0x01 hide.word 0x00 "DLL,The divisor latches low register " hgroup.word 0x04++0x01 hide.word 0x00 "DLH,The divisor latches high register" hgroup.word 0x08++0x01 hide.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" hgroup.word 0x08++0x01 hide.word 0x00 "FCR,The FIFO control register" hgroup.word 0x0C++0x01 hide.word 0x00 "LCR,Line control register" hgroup.word 0x14++0x01 hide.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" hgroup.word 0x18++0x01 hide.word 0x00 "TCR,Transmission control register" hgroup.word 0x18++0x01 hide.word 0x00 "MSR,The modem status register" hgroup.word 0x1C++0x01 hide.word 0x00 "TLR,The trigger level register" hgroup.word 0x1C++0x01 hide.word 0x00 "SPR,Scratchpad register" hgroup.word 0x20++0x01 hide.word 0x00 "MDR1,Mode definition register 1" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode definition register 2" hgroup.word 0x28++0x01 hide.word 0x00 "SFLSR,The status FIFO line status register" hgroup.word 0x28++0x01 hide.word 0x00 "TXFLL,Transmit frame length low register" hgroup.word 0x2C++0x01 hide.word 0x00 "RESUME,The RESUME register " hgroup.word 0x2C++0x01 hide.word 0x00 "TXFLH,The transmit frame length high register" hgroup.word 0x30++0x01 hide.word 0x00 "SFREGL,The status FIFO register low" hgroup.word 0x30++0x01 hide.word 0x00 "RXFLL,Received frame length low register" hgroup.word 0x34++0x01 hide.word 0x00 "SFREGH,Status FIFO register high" hgroup.word 0x34++0x01 hide.word 0x00 "RXFLH,The received frame length high register" hgroup.word 0x40++0x01 hide.word 0x00 "SCR,The supplementary control register " hgroup.word 0x44++0x01 hide.word 0x00 "SSR,The supplementary status register " hgroup.word 0x50++0x01 hide.word 0x00 "MVR,The module version register" hgroup.word 0x54++0x01 hide.word 0x00 "SYSC,The system configuration register " hgroup.word 0x64++0x01 hide.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hgroup.word 0x68++0x01 hide.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hgroup.word 0x6C++0x01 hide.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" hgroup.word 0x70++0x01 hide.word 0x00 "ISR2,Interrupt status register 2" hgroup.word 0x74++0x01 hide.word 0x00 "FREQ_SEL,FREQ_SEL" hgroup.word 0x80++0x01 hide.word 0x00 "MDR3,Mode definition register 3" hgroup.word 0x84++0x01 hide.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " endif width 11. tree.end tree "UART 3" base ad:0x481A6000 width 18. if (((d.w(ad:0x481A6000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x06) wgroup.word 0x00++0x01 line.word 0x00 "THR,Transmit holding register " hexmask.word.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.word 0x04++0x01 line.word 0x00 "IER_CIR,Following interrupt enable register" bitfld.word 0x00 5. " TXSTATUSIT ,TXSTATUSIT" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,RXOVERRUNIT" "Disabled,Enabled" bitfld.word 0x00 2. " RXSTOPIT ,RXSTOPIT" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,THRIT" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,RHRIT" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A6000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A6000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A6000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x05)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x04)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x01) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_IRDA,Following interrupt enable register (IER) description is for IrDA mode" bitfld.word 0x00 7. " EOFIT ,Enable/Disable the received EOF interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " LINESTSIT ,Enable/Disable the receiver line status interrupt" "Disabled,Enabled" bitfld.word 0x00 5. " TXSTATUSIT ,Enable/Disable the TX status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " STSFIFOTRIGIT ,Enable/Disable status FIFO trigger level interrupt" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,Enable/Disable the RX overrun interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LASTRXBYTEIT ,Enable/Disable the last byte of frame in RX FIFO interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Enable/Disable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Enable/Disable the RHR interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_IRDA,IIR_IRDA" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt active/active" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A6000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A6000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x38++0x01 line.word 0x00 "BLR,The BOF control register" bitfld.word 0x00 7. " STSFIFORESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOFTYPE ,SIR xBOF select" "FF,C0" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A6000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x00)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x02)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x03) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_UART,The following interrupt enable register (IER) description is for UART mode" bitfld.word 0x00 7. " CTSIT ,Disable/Enable the CTS (active-low) interrupt" "0,1" bitfld.word 0x00 6. " RTSIT ,Disable/Enable the RTS (active-low) interrupt" "0,1" bitfld.word 0x00 5. " XOFFIT ,Disable/Enable the XOFF interrupt" "0,1" textline " " bitfld.word 0x00 4. " SLEEPMODE ,Disable/Enable sleep mode" "Disabled,Enabled" bitfld.word 0x00 3. " MODEMSTSIT ,Disables/Enabled the modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LINESTSIT ,Disable/Enable the receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Disable/Enable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Disable/Enable the RHR interrupt and time out interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A6000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A6000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x01)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x04)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x00)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x02)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "XOFF1,The XOFF1" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,Stores the 8 bit XOFF1 character in UART modes" if (((d.w(ad:0x481A6000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A6000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "XOFF2,The XOFF2 register is selected with a register bit setting of LCR[7]=BF" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,Stores the 8 bit XOFF2 character in UART modes" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A6000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A6000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x00)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x02)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A6000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A6000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x01)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x04)||(((d.w(ad:0x481A6000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A6000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A6000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A6000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A6000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A6000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" else hgroup.word 0x00++0x01 hide.word 0x00 "DLL,The divisor latches low register " hgroup.word 0x04++0x01 hide.word 0x00 "DLH,The divisor latches high register" hgroup.word 0x08++0x01 hide.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" hgroup.word 0x08++0x01 hide.word 0x00 "FCR,The FIFO control register" hgroup.word 0x0C++0x01 hide.word 0x00 "LCR,Line control register" hgroup.word 0x14++0x01 hide.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" hgroup.word 0x18++0x01 hide.word 0x00 "TCR,Transmission control register" hgroup.word 0x18++0x01 hide.word 0x00 "MSR,The modem status register" hgroup.word 0x1C++0x01 hide.word 0x00 "TLR,The trigger level register" hgroup.word 0x1C++0x01 hide.word 0x00 "SPR,Scratchpad register" hgroup.word 0x20++0x01 hide.word 0x00 "MDR1,Mode definition register 1" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode definition register 2" hgroup.word 0x28++0x01 hide.word 0x00 "SFLSR,The status FIFO line status register" hgroup.word 0x28++0x01 hide.word 0x00 "TXFLL,Transmit frame length low register" hgroup.word 0x2C++0x01 hide.word 0x00 "RESUME,The RESUME register " hgroup.word 0x2C++0x01 hide.word 0x00 "TXFLH,The transmit frame length high register" hgroup.word 0x30++0x01 hide.word 0x00 "SFREGL,The status FIFO register low" hgroup.word 0x30++0x01 hide.word 0x00 "RXFLL,Received frame length low register" hgroup.word 0x34++0x01 hide.word 0x00 "SFREGH,Status FIFO register high" hgroup.word 0x34++0x01 hide.word 0x00 "RXFLH,The received frame length high register" hgroup.word 0x40++0x01 hide.word 0x00 "SCR,The supplementary control register " hgroup.word 0x44++0x01 hide.word 0x00 "SSR,The supplementary status register " hgroup.word 0x50++0x01 hide.word 0x00 "MVR,The module version register" hgroup.word 0x54++0x01 hide.word 0x00 "SYSC,The system configuration register " hgroup.word 0x64++0x01 hide.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hgroup.word 0x68++0x01 hide.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hgroup.word 0x6C++0x01 hide.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" hgroup.word 0x70++0x01 hide.word 0x00 "ISR2,Interrupt status register 2" hgroup.word 0x74++0x01 hide.word 0x00 "FREQ_SEL,FREQ_SEL" hgroup.word 0x80++0x01 hide.word 0x00 "MDR3,Mode definition register 3" hgroup.word 0x84++0x01 hide.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " endif width 11. tree.end tree "UART 4" base ad:0x481A8000 width 18. if (((d.w(ad:0x481A8000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x06) wgroup.word 0x00++0x01 line.word 0x00 "THR,Transmit holding register " hexmask.word.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.word 0x04++0x01 line.word 0x00 "IER_CIR,Following interrupt enable register" bitfld.word 0x00 5. " TXSTATUSIT ,TXSTATUSIT" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,RXOVERRUNIT" "Disabled,Enabled" bitfld.word 0x00 2. " RXSTOPIT ,RXSTOPIT" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,THRIT" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,RHRIT" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A8000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A8000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A8000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x05)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x04)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x01) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_IRDA,Following interrupt enable register (IER) description is for IrDA mode" bitfld.word 0x00 7. " EOFIT ,Enable/Disable the received EOF interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " LINESTSIT ,Enable/Disable the receiver line status interrupt" "Disabled,Enabled" bitfld.word 0x00 5. " TXSTATUSIT ,Enable/Disable the TX status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " STSFIFOTRIGIT ,Enable/Disable status FIFO trigger level interrupt" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,Enable/Disable the RX overrun interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LASTRXBYTEIT ,Enable/Disable the last byte of frame in RX FIFO interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Enable/Disable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Enable/Disable the RHR interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_IRDA,IIR_IRDA" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt active/active" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A8000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A8000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x38++0x01 line.word 0x00 "BLR,The BOF control register" bitfld.word 0x00 7. " STSFIFORESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOFTYPE ,SIR xBOF select" "FF,C0" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A8000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x00)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x02)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x03) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_UART,The following interrupt enable register (IER) description is for UART mode" bitfld.word 0x00 7. " CTSIT ,Disable/Enable the CTS (active-low) interrupt" "0,1" bitfld.word 0x00 6. " RTSIT ,Disable/Enable the RTS (active-low) interrupt" "0,1" bitfld.word 0x00 5. " XOFFIT ,Disable/Enable the XOFF interrupt" "0,1" textline " " bitfld.word 0x00 4. " SLEEPMODE ,Disable/Enable sleep mode" "Disabled,Enabled" bitfld.word 0x00 3. " MODEMSTSIT ,Disables/Enabled the modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LINESTSIT ,Disable/Enable the receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Disable/Enable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Disable/Enable the RHR interrupt and time out interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A8000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A8000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x01)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x04)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x00)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x02)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "XOFF1,The XOFF1" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,Stores the 8 bit XOFF1 character in UART modes" if (((d.w(ad:0x481A8000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A8000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "XOFF2,The XOFF2 register is selected with a register bit setting of LCR[7]=BF" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,Stores the 8 bit XOFF2 character in UART modes" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A8000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A8000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x00)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x02)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A8000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A8000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x01)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x04)||(((d.w(ad:0x481A8000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481A8000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481A8000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481A8000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481A8000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481A8000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" else hgroup.word 0x00++0x01 hide.word 0x00 "DLL,The divisor latches low register " hgroup.word 0x04++0x01 hide.word 0x00 "DLH,The divisor latches high register" hgroup.word 0x08++0x01 hide.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" hgroup.word 0x08++0x01 hide.word 0x00 "FCR,The FIFO control register" hgroup.word 0x0C++0x01 hide.word 0x00 "LCR,Line control register" hgroup.word 0x14++0x01 hide.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" hgroup.word 0x18++0x01 hide.word 0x00 "TCR,Transmission control register" hgroup.word 0x18++0x01 hide.word 0x00 "MSR,The modem status register" hgroup.word 0x1C++0x01 hide.word 0x00 "TLR,The trigger level register" hgroup.word 0x1C++0x01 hide.word 0x00 "SPR,Scratchpad register" hgroup.word 0x20++0x01 hide.word 0x00 "MDR1,Mode definition register 1" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode definition register 2" hgroup.word 0x28++0x01 hide.word 0x00 "SFLSR,The status FIFO line status register" hgroup.word 0x28++0x01 hide.word 0x00 "TXFLL,Transmit frame length low register" hgroup.word 0x2C++0x01 hide.word 0x00 "RESUME,The RESUME register " hgroup.word 0x2C++0x01 hide.word 0x00 "TXFLH,The transmit frame length high register" hgroup.word 0x30++0x01 hide.word 0x00 "SFREGL,The status FIFO register low" hgroup.word 0x30++0x01 hide.word 0x00 "RXFLL,Received frame length low register" hgroup.word 0x34++0x01 hide.word 0x00 "SFREGH,Status FIFO register high" hgroup.word 0x34++0x01 hide.word 0x00 "RXFLH,The received frame length high register" hgroup.word 0x40++0x01 hide.word 0x00 "SCR,The supplementary control register " hgroup.word 0x44++0x01 hide.word 0x00 "SSR,The supplementary status register " hgroup.word 0x50++0x01 hide.word 0x00 "MVR,The module version register" hgroup.word 0x54++0x01 hide.word 0x00 "SYSC,The system configuration register " hgroup.word 0x64++0x01 hide.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hgroup.word 0x68++0x01 hide.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hgroup.word 0x6C++0x01 hide.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" hgroup.word 0x70++0x01 hide.word 0x00 "ISR2,Interrupt status register 2" hgroup.word 0x74++0x01 hide.word 0x00 "FREQ_SEL,FREQ_SEL" hgroup.word 0x80++0x01 hide.word 0x00 "MDR3,Mode definition register 3" hgroup.word 0x84++0x01 hide.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " endif width 11. tree.end tree "UART 5" base ad:0x481AA000 width 18. if (((d.w(ad:0x481AA000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x06) wgroup.word 0x00++0x01 line.word 0x00 "THR,Transmit holding register " hexmask.word.byte 0x00 0.--7. 1. " THR ,Transmit holding register" group.word 0x04++0x01 line.word 0x00 "IER_CIR,Following interrupt enable register" bitfld.word 0x00 5. " TXSTATUSIT ,TXSTATUSIT" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,RXOVERRUNIT" "Disabled,Enabled" bitfld.word 0x00 2. " RXSTOPIT ,RXSTOPIT" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,THRIT" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,RHRIT" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481AA000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481AA000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481AA000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x05)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x04)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x01) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_IRDA,Following interrupt enable register (IER) description is for IrDA mode" bitfld.word 0x00 7. " EOFIT ,Enable/Disable the received EOF interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " LINESTSIT ,Enable/Disable the receiver line status interrupt" "Disabled,Enabled" bitfld.word 0x00 5. " TXSTATUSIT ,Enable/Disable the TX status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " STSFIFOTRIGIT ,Enable/Disable status FIFO trigger level interrupt" "Disabled,Enabled" bitfld.word 0x00 3. " RXOVERRUNIT ,Enable/Disable the RX overrun interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LASTRXBYTEIT ,Enable/Disable the last byte of frame in RX FIFO interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Enable/Disable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Enable/Disable the RHR interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_IRDA,IIR_IRDA" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt active/active" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481AA000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481AA000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x38++0x01 line.word 0x00 "BLR,The BOF control register" bitfld.word 0x00 7. " STSFIFORESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOFTYPE ,SIR xBOF select" "FF,C0" group.word 0x3C++0x01 line.word 0x00 "ACREG,The auxiliary control register" bitfld.word 0x00 7. " PULSETYPE ,SIR pulse-width select" "3/16 baud-rate,1.6 microseconds" bitfld.word 0x00 6. " SDMOD ,SD pin is set to low/high" "High,Low" bitfld.word 0x00 5. " DISIRRX ,Disable RX input" "No,Yes" textline " " bitfld.word 0x00 4. " DISTXUNDERRUN ,Disable/Enable TX underrun" "Enabled,Disabled" bitfld.word 0x00 3. " SENDSIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP)" "No action,Send" bitfld.word 0x00 2. " SCTXEN ,Store and control TX start" "No action,Starts" textline " " bitfld.word 0x00 1. " ABORTEN ,Frame abort" "Not aborted,Aborted" bitfld.word 0x00 0. " EOTEN ,EOT (end-of-transmission) bit" "0,1" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" group.word 0x48++0x01 line.word 0x00 "EBLR,The BOF length register" hexmask.word.byte 0x00 0.--7. 1. " GEN_RXSTOP_INT_255 ,Generate RXSTOP interrupt after receiving 255 zero bits." rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481AA000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x00)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x02)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x00)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x03) hgroup.word 0x00++0x03 hide.long 0x00 "RHR/THR,Receive/Transmit Holding Register" in group.word 0x04++0x01 line.word 0x00 "IER_UART,The following interrupt enable register (IER) description is for UART mode" bitfld.word 0x00 7. " CTSIT ,Disable/Enable the CTS (active-low) interrupt" "0,1" bitfld.word 0x00 6. " RTSIT ,Disable/Enable the RTS (active-low) interrupt" "0,1" bitfld.word 0x00 5. " XOFFIT ,Disable/Enable the XOFF interrupt" "0,1" textline " " bitfld.word 0x00 4. " SLEEPMODE ,Disable/Enable sleep mode" "Disabled,Enabled" bitfld.word 0x00 3. " MODEMSTSIT ,Disables/Enabled the modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 2. " LINESTSIT ,Disable/Enable the receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THRIT ,Disable/Enable the THR interrupt" "Disabled,Enabled" bitfld.word 0x00 0. " RHRIT ,Disable/Enable the RHR interrupt and time out interrupt" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481AA000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481AA000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x40) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 7. " FRAMEENDMODE ,IrDA mode only" "Frame-length,EOT bit" bitfld.word 0x00 6. " SIPMODE ,MIR/FIR modes only" "Manual,Automatic" bitfld.word 0x00 5. " SCT ,Store and control the transmission" "START_WITH_THR_WRITE,START_WITH_CTRL_OF_ACREG_2" textline " " bitfld.word 0x00 4. " SETTXIR ,Used to configure the infrared transceiver" "No action,Force" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x01)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x04)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "TCR,Transmission control register" bitfld.word 0x00 4.--7. " RXFIFOTRIGSTART ,RX FIFO trigger level to RESTORE transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXFIFOTRIGHALT ,RX FIFO trigger level to HALT transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x00)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x02)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)==0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes." group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,Stores the 8 bit XON2 character in UART modes and ADDR2 address 2 in IrDA modes" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,8 bit XON2 character" group.word 0x18++0x01 line.word 0x00 "XOFF1,The XOFF1" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,Stores the 8 bit XOFF1 character in UART modes" if (((d.w(ad:0x481AA000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481AA000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "XOFF2,The XOFF2 register is selected with a register bit setting of LCR[7]=BF" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,Stores the 8 bit XOFF2 character in UART modes" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x06) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced feature register enables or disables enhanced features" bitfld.word 0x00 4. " ENHANCEDEN ,Enhanced functions write enable bit" "Disabled,Enabled" bitfld.word 0x00 0.--3. " SWFLOWCONTROL ,Combinations of software flow control can be selected by programming this bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481AA000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481AA000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier frequency prescaler register " hexmask.word.byte 0x00 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple)" rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x00)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x02)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x03) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" rgroup.word 0x08++0x01 line.word 0x00 "IIR_UART,Following interrupt identification register " bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Seven possible interrupts in UART mode. Other combinations never occur" "Modem,THR,RHR,Line status,res,res,Rx timeout,res,Xoff,res,CTS,,,,,,,,,,,,,,,,,,,,," bitfld.word 0x00 0. " IT_PENDING ,No interrupt is pending" "Pending,Not pending" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" group.word 0x10++0x01 line.word 0x00 "MCR,Modem control register" bitfld.word 0x00 6. " TCRTLR ,TCRTLR" "Disabled,Enabled" bitfld.word 0x00 5. " XONEN ,XONEN" "Disabled,Enabled" bitfld.word 0x00 4. " LOOPBACKEN ,Loopback mode enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " CDSTSCH ,CDSTSCH" "Input_high,Input_low" bitfld.word 0x00 2. " RISTSCH ,RISTSCH" "Inactive,Avtive" bitfld.word 0x00 1. " RTS ,RTS" "Inactive,Avtive" textline " " bitfld.word 0x00 0. " DTR ,DTR" "Inactive,Avtive" rgroup.word 0x14++0x01 line.word 0x00 "LSR_UART,Line status register " bitfld.word 0x00 7. " RXFIFOSTS ,RXFIFOSTS" "Normal,One error" bitfld.word 0x00 6. " TXSRE ,Transmitter hold (TX FIFO) and shift registers are not empty/empty" "Not empty,Empty" bitfld.word 0x00 5. " TXFIFOE ,Transmit hold register (TX FIFO) is not empty/empty" "Not empty,Empty" textline " " bitfld.word 0x00 4. " RXBI ,Break condition detect" "Not detected,Detected" bitfld.word 0x00 3. " RXFE ,Framing error" "Not occurred,Occurred" bitfld.word 0x00 2. " RXPE ,Parity error" "Not occurred,Occurred" textline " " bitfld.word 0x00 1. " RXOE ,Overrun error" "Not occurred,Occurred" bitfld.word 0x00 0. " RXFIFOE ,Data in the receive FIFO" "No data,One data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481AA000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481AA000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x38++0x01 line.word 0x00 "UASR,The UART autobauding status register " bitfld.word 0x00 6.--7. " PARITYTYPE ,Type of the parity in UART autobauding mode" "No parity,Parity space,Even parity,Odd parity" bitfld.word 0x00 5. " BITBYCHAR ,Number of bits by characters" "7-bit,8-bit" bitfld.word 0x00 0.--4. " SPEED ,Speed" "No speed identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9600 baud,4800 baud,2400 baud,1200 baud,,,,,,,,,,,,,,,,,,,,," group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x58++0x01 line.word 0x00 "SYSS,The system status register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete" group.word 0x5C++0x01 line.word 0x00 "WER,The wake-up enable register" bitfld.word 0x00 7. " TXWAKEUPEN ,Wake-up interrupt" "Disabled,Enabled" bitfld.word 0x00 6. " RLS_INTERRUPT ,RLS_INTERRUPT" "Disabled,Enabled" bitfld.word 0x00 5. " RHR_INTERRUPT ,RHR_INTERRUPT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RX_ACTIVITY ,RX_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 3. " DCD_ACTIVITY ,DCD_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 2. " RI_ACTIVITY ,RI_ACTIVITY" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " DSR_ACTIVITY ,DSR_ACTIVITY" "Disabled,Enabled" bitfld.word 0x00 0. " CTS_ACTIVITY ,CTS__ACTIVITY" "Disabled,Enabled" group.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" group.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" elif (((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x01)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x04)||(((d.w(ad:0x481AA000+0x0C))&0x80)==0x80)&&(((d.w(ad:0x481AA000+0x0C))&0xFF)!=0xBF)&&(((d.w(ad:0x481AA000+0x20))&0x07)==0x05) group.word 0x00++0x01 line.word 0x00 "DLL,The divisor latches low register " hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,Divisor latches low. Stores the 8 LSB divisor value" group.word 0x04++0x01 line.word 0x00 "DLH,The divisor latches high register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,Divisor latches high. Stores the 6 MSB divisor value" rgroup.word 0x08++0x01 line.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" bitfld.word 0x00 5. " TXSTATUSIT ,TX status interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 3. " RXOEIT ,RX overrun interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 2. " RXSTOPIT ,Receive stop interrupt is inactive/active" "Inactive,Active" textline " " bitfld.word 0x00 1. " THRIT ,THR interrupt inactive/active" "Inactive,Active" bitfld.word 0x00 0. " RHRIT ,RHR interrupt inactive/active" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,The FIFO control register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO" "8 characters,16 characters,32 characters,56 characters" bitfld.word 0x00 3. " DMA_MODE ,Select DMA Mode" "No DMA,UART_NDMA_REQ" textline " " bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Clears the transmit FIFO" "Not clear,Clear" bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Clears the receive FIFO" "Not clear,Clear" bitfld.word 0x00 0. " FIFO_EN ,Disable/Enable the transmit and receive FIFOs" "Disabled,Enabled" group.word 0x0C++0x01 line.word 0x00 "LCR,Line control register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control bit" "Normal,Force output" bitfld.word 0x00 5. " PARITY_TYPE2 ,If LCR[3] = 1" "0,1" textline " " bitfld.word 0x00 4. " PARITY_TYPE1 ,If LCR[3] = 1" "Odd,Even" bitfld.word 0x00 3. " PARITY_EN ,Parity bit" "Not generated,Generated" bitfld.word 0x00 2. " NB_STOP ,Specifies the number of stop bits" "1 stop bit,1.5 stop bits" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "5 bits,6 bits,7 bits,8 bit" rgroup.word 0x14++0x01 line.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" bitfld.word 0x00 7. " THR_EMPTY ,Transmit holding register (TX FIFO) is (not empty/empty)" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO is full" "Not full,Full" bitfld.word 0x00 5. " RX_LAST_BYTE ,The RX FIFO (RHR) does (not contain/contains) the last byte of the frame to be read" "No last byte,Last byte" textline " " bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame-too-long error" "No error,Error" bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in frame" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO not empty/empty" "No empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,Data in the receive FIFO" "One data,No data" rgroup.word 0x18++0x01 line.word 0x00 "MSR,The modem status register" bitfld.word 0x00 7. " NCD_STS ,This bit is the complement of the DCD (active-low) input. In loopback mode, it is equivalent to MCR[3]." "0,1" bitfld.word 0x00 6. " NRI_STS ,This bit is the complement of the RI (active-low) input. In loopback mode, it is equivalent to MCR[2]." "0,1" bitfld.word 0x00 5. " NDSR_STS ,This bit is the complement of the DSR (active-low) input. In loopback mode, it is equivalent to MCR[0]." "0,1" textline " " bitfld.word 0x00 4. " NCTS_STS ,NCTS_STS" "0,1" bitfld.word 0x00 3. " DCD_STS ,DCD_STS" "No change,Change" bitfld.word 0x00 2. " RI_STS ,RI_STS" "No change,Change" textline " " bitfld.word 0x00 1. " DSR_STS ,DSR_STS" "No change,Change" bitfld.word 0x00 0. " CTS_STS ,CTS_STS" "No change,Change" if (((d.w(ad:0x481AA000+0x08))&0x10)==0x01)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "TLR,The trigger level register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.w(ad:0x481AA000+0x08))&0x10)==0x00)&&(((d.w(ad:0x481AA000+0x08))&0x40)==0x00) group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,SPR_WORD" endif group.word 0x20++0x01 line.word 0x00 "MDR1,Mode definition register 1" bitfld.word 0x00 3. " IRSLEEP ,IrDA/CIR sleep mode" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODESELECT ,UART/IrDA/CIR mode selection" "UART 16x,SIR mode,UART 16x auto-baud,UART 13x,MIR mode,FIR mode,CIR mode,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode definition register 2" bitfld.word 0x00 7. " SETTXIRALT ,Provides alternate functionality for MDR1[4]" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,Only for IR mode (IrDA and CIR) Invert RX pin in the module before the voting or sampling system logic of the infrared block" "Inverted,Not inverted" bitfld.word 0x00 4.--5. " CIRPULSEMODE ,CIR pulse modulation definition" "Width 3,Width 4,Width 5,Width 6" textline " " bitfld.word 0x00 3. " UARTPULSE ,UART mode only. Used to allow pulse shaping in UART mode" "Normal mode,Pulse shaping" bitfld.word 0x00 1.--2. " STSFIFOTRIG ,Only for IrDA mode. Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" rbitfld.word 0x00 0. " IRTXUNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,The status FIFO line status register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error in RX FIFO" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detected" "No error,Error" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit frame length low register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,LSB register used to specify the frame length." rgroup.word 0x2C++0x01 line.word 0x00 "RESUME,The RESUME register " hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2C++0x01 line.word 0x00 "TXFLH,The transmit frame length high register" bitfld.word 0x00 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,The status FIFO register low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received frame length low register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO register high" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,The received frame length high register" bitfld.word 0x00 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x40++0x01 line.word 0x00 "SCR,The supplementary control register " bitfld.word 0x00 7. " RXTRIGGRANU1 ,RXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 6. " TXTRIGGRANU1 ,TXTRIGGRANU1" "Disabled,Enabled" bitfld.word 0x00 5. " DSRIT ,DSRIT" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " RXCTSDSRWAKEUPENABLE ,RX CTS wake-up enable" "Disabled,Enabled" bitfld.word 0x00 3. " TXEMPTYCTLIT ,TXEMPTYCTLIT" "Normal mode,Interrupt" bitfld.word 0x00 1.--2. " DMAMODE2 ,Specifies the DMA mode valid if SCR[0] = 1" "No DMA,UARTnDMAREQ[0] in TX | UARTnDMAREQ[1] in RX,UARTnDMAREQ[0] in RX,UARTnDMAREQ[0] in TX" textline " " bitfld.word 0x00 0. " TXFIFOFULL ,DMAMODECTL" "FCR_3,SCR_2_1" group.word 0x44++0x01 line.word 0x00 "SSR,The supplementary status register " bitfld.word 0x00 2. " DMACOUNTERRST ,DMACOUNTERRST" "No reset,Reset" rbitfld.word 0x00 1. " RXCTSDSRWAKEUPSTS ,Pin falling edge detection" "Not occurred,Occurred" rbitfld.word 0x00 0. " TXFIFOFULL ,TXFIFOFULL" "Not full,Full" rgroup.word 0x50++0x01 line.word 0x00 "MVR,The module version register" bitfld.word 0x00 4.--7. " MAJORREV ,Major revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " MINORREV_ ,Minor revision number of the module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0x54++0x01 line.word 0x00 "SYSC,The system configuration register " bitfld.word 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Force idle,No-idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal interface clock-gating strategy" "Running," rgroup.word 0x64++0x01 line.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " RXFIFO_LVL ,Level of the RX FIFO" rgroup.word 0x68++0x01 line.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hexmask.word.byte 0x00 0.--7. 1. " TXFIFO_LVL ,Level of the TX FIFO" group.word 0x6C++0x01 line.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" bitfld.word 0x00 1. " EN_TXFIFO_EMPTY ,EN_TXFIFO_EMPTY" "Disabled,Enabled" bitfld.word 0x00 0. " EN_RXFIFO_EMPTY ,Number of bits by characters" "Disabled,Enabled" group.word 0x70++0x01 line.word 0x00 "ISR2,Interrupt status register 2" bitfld.word 0x00 1. " TXFIFO_EMPTY_STS ,TXFIFO_EMPTY_STS" "No pending,Pending" bitfld.word 0x00 0. " RXFIFO_EMPTY_STS ,RXFIFO_EMPTY_STS" "No pending,Pending" group.word 0x74++0x01 line.word 0x00 "FREQ_SEL,FREQ_SEL" hexmask.word.byte 0x00 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if non default frequency is used" group.word 0x80++0x01 line.word 0x00 "MDR3,Mode definition register 3" bitfld.word 0x00 2. " SET_DMA_TX_THRESHOLD ,Disable/Enable use of TX DMA Threshold register" "Disabled,Enabled" bitfld.word 0x00 1. " NONDEFAULT_FREQ ,Disable/Enable using NONDEFAULT fclk frequencies" "Disabled,Enabled" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable/Enable CIR RX demodulation" "Enabled,Disabled" group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" else hgroup.word 0x00++0x01 hide.word 0x00 "DLL,The divisor latches low register " hgroup.word 0x04++0x01 hide.word 0x00 "DLH,The divisor latches high register" hgroup.word 0x08++0x01 hide.word 0x00 "IIR_CIR,The following interrupt identification register (IIR) description is for CIR mode" hgroup.word 0x08++0x01 hide.word 0x00 "FCR,The FIFO control register" hgroup.word 0x0C++0x01 hide.word 0x00 "LCR,Line control register" hgroup.word 0x14++0x01 hide.word 0x00 "LSR_IRDA,The following line status register (LSR) description is for IrDA mode" hgroup.word 0x18++0x01 hide.word 0x00 "TCR,Transmission control register" hgroup.word 0x18++0x01 hide.word 0x00 "MSR,The modem status register" hgroup.word 0x1C++0x01 hide.word 0x00 "TLR,The trigger level register" hgroup.word 0x1C++0x01 hide.word 0x00 "SPR,Scratchpad register" hgroup.word 0x20++0x01 hide.word 0x00 "MDR1,Mode definition register 1" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode definition register 2" hgroup.word 0x28++0x01 hide.word 0x00 "SFLSR,The status FIFO line status register" hgroup.word 0x28++0x01 hide.word 0x00 "TXFLL,Transmit frame length low register" hgroup.word 0x2C++0x01 hide.word 0x00 "RESUME,The RESUME register " hgroup.word 0x2C++0x01 hide.word 0x00 "TXFLH,The transmit frame length high register" hgroup.word 0x30++0x01 hide.word 0x00 "SFREGL,The status FIFO register low" hgroup.word 0x30++0x01 hide.word 0x00 "RXFLL,Received frame length low register" hgroup.word 0x34++0x01 hide.word 0x00 "SFREGH,Status FIFO register high" hgroup.word 0x34++0x01 hide.word 0x00 "RXFLH,The received frame length high register" hgroup.word 0x40++0x01 hide.word 0x00 "SCR,The supplementary control register " hgroup.word 0x44++0x01 hide.word 0x00 "SSR,The supplementary status register " hgroup.word 0x50++0x01 hide.word 0x00 "MVR,The module version register" hgroup.word 0x54++0x01 hide.word 0x00 "SYSC,The system configuration register " hgroup.word 0x64++0x01 hide.word 0x00 "RXFIFO_LVL,RXFIFO_LVL" hgroup.word 0x68++0x01 hide.word 0x00 "TXFIFO_LVL,TXFIFO_LVL" hgroup.word 0x6C++0x01 hide.word 0x00 "IER2,IER2 enables RX/TX FIFOs empty corresponding interrupts" hgroup.word 0x70++0x01 hide.word 0x00 "ISR2,Interrupt status register 2" hgroup.word 0x74++0x01 hide.word 0x00 "FREQ_SEL,FREQ_SEL" hgroup.word 0x80++0x01 hide.word 0x00 "MDR3,Mode definition register 3" hgroup.word 0x84++0x01 hide.word 0x00 "TX_DMA_THRESHOLD,TX DMA threshold register " endif width 11. tree.end tree.end tree "I2C" tree "I2C 0" base ad:0x44E0B000 width 18. rgroup.long 0x00++0x03 line.long 0x00 "I2C_REVNB_LO,Register contains the hard-coded revision number of the module" bitfld.long 0x00 11.--15. " RTL , RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR , Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision" rgroup.long 0x04++0x03 line.long 0x00 "I2C_REVNB_HI,I2C_REVNB_HI register" bitfld.long 0x00 14.--15. " SCHEME , Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " FUNC ,Indicates a software compatible module family" group.long 0x10++0x03 line.long 0x00 "I2C_SYSC,This register allows controlling various parameters of the peripheral interface." bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both clocks off,Interface/OCP active|system clock off,System clock active|Interface/OCP off,Both active" textline " " bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No Idle,Smart Idle,Smart-idle wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled" bitfld.long 0x00 1. " SRST ,SoftReset bit" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled" textline " " if (((d.l(ad:0x44E0B000+0xA4))&0x400)==0x400)&&(((d.l(ad:0x44E0B000+0xA4))&0x200)==0x200) //I2C_CON.MST== "Master" &&I 2C_CON.TRX== "Transmitter" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status(I2C Master Transmit mode only)" "Disabled,Enabled" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" bitfld.long 0x00 10. " XUDF ,Transmit underflow status(I2C transmit mode only)" "Normal,Underflow" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" textline " " eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status(I2C mode)" "On-going,Ready" bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" elif (((d.l(ad:0x44E0B000+0xA4))&0x400)==0x400)&&(((d.l(ad:0x44E0B000+0xA4))&0x200)==0x00) //I2C_CON.MST== "Master" &&I 2C_CON.TRX== "Receiver" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" bitfld.long 0x00 13. " RDR ,Receive draining IRQ status(I2C Receive mode only)" "Disabled,Enabled" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" rbitfld.long 0x00 11. " ROVR ,Receive overrun status(I2C receive mode only)" "Normal,Overrun" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" textline " " bitfld.long 0x00 3. " RRDY ,RX FIFO level is above the configured threshold status(I2C mode)" "Not reached,Reached" bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" elif (((d.l(ad:0x44E0B000+0xA4))&0x400)==0x00)&&(((d.l(ad:0x44E0B000+0xA4))&0x200)==0x00) //I2C_CON.MST== "Slave" &&I 2C_CON.TRX== "Receiver" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" bitfld.long 0x00 13. " RDR ,Receive draining IRQ status(I2C Receive mode only)" "Disabled,Enabled" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" rbitfld.long 0x00 11. " ROVR ,Receive overrun status(I2C receive mode only)" "Normal,Overrun" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" textline " " bitfld.long 0x00 3. " RRDY ,RX FIFO level is above the configured threshold status(I2C mode)" "Not reached,Reached" bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" elif (((d.l(ad:0x44E0B000+0xA4))&0x400)==0x00)&&(((d.l(ad:0x44E0B000+0xA4))&0x200)==0x200) //I2C_CON.MST== "Slave" &&I 2C_CON.TRX== "Transmitter" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "Normal,Underflow" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" textline " " bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status(I2C mode)" "On-going,Ready" textline " " bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" endif group.long 0x28++0x03 line.long 0x00 "I2C_IRQSTS,This register provides core status information for interrupt handling, showing all active and enabled events and masking the others" eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled" eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled" eventfld.long 0x00 12. " BB ,Bus busy enabled status" "Free,Occupied" textline " " eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,overrun" eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "Normal,underflow" eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Address recognized" eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free" textline " " eventfld.long 0x00 7. " AERR , Access Error IRQ enabled status" "No action,Error" eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected" eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "On-going,Ready" textline " " eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "No available,Available" eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Module busy,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ enabled status" "Normal,Detected" eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected" group.long 0x2C++0x03 line.long 0x00 "I2C_IRQEN_SET,All 1-bit fields enable a specific interrupt event to trigger an interrupt request" bitfld.long 0x00 14. " XDR_IE ,Transmit draining interrupt enable set" "No effect,Enabled" bitfld.long 0x00 13. " RDR_IE ,Receive draining interrupt enable set" "No effect,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun enable set" "No effect,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow enable set" "No effect,Enabled" bitfld.long 0x00 9. " AAS_IE ,Addressed as slave interrupt enable set" "No effect,Enabled" bitfld.long 0x00 8. " BF_IE ,Bus free interrupt enable set" "No effect,Enabled" textline " " bitfld.long 0x00 7. " AERR_IE ,Access error interrupt enabled set" "No effect,Enabled" bitfld.long 0x00 6. " STC_IE ,Start condition interrupt enable set" "No effect,Enabled" bitfld.long 0x00 5. " GC_IE ,General call interrupt enable set" "No effect,Enabled" bitfld.long 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable set" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RRDY_IE ,Receive data ready interrupt enable set" "No effect,Enabled" bitfld.long 0x00 2. " ARDY_IE ,Register access ready interrupt enable set" "No effect,Enabled" bitfld.long 0x00 1. " NACK_IE ,No acknowledgment interrupt enable set" "No effect,Enabled" bitfld.long 0x00 0. " AL_IE ,Arbitration lost interrupt enable set" "No effect,Enabled" group.long 0x30++0x03 line.long 0x00 "I2C_IRQEN_CLR,All 1-bit fields clear a specific interrupt event" bitfld.long 0x00 14. " XDR_IE ,Transmit draining interrupt enable clear" "No effect,Clear" bitfld.long 0x00 13. " RDR_IE ,Receive draining interrupt enable clear" "No effect,Clear" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun enable clear" "No effect,Clear" bitfld.long 0x00 10. " XUDF ,Transmit underflow enable clear" "No effect,Clear" bitfld.long 0x00 9. " AAS_IE ,Addressed as slave interrupt enable clear" "No effect,Clear" bitfld.long 0x00 8. " BF_IE ,Bus free interrupt enable clear" "No effect,Clear" textline " " bitfld.long 0x00 7. " AERR_IE ,Access error interrupt enabled clear" "No effect,Clear" bitfld.long 0x00 6. " STC_IE ,Start condition interrupt enable clear" "No effect,Clear" bitfld.long 0x00 5. " GC_IE ,General call interrupt enable clear" "No effect,Clear" bitfld.long 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " RRDY_IE ,Receive data ready interrupt enable clear" "No effect,Clear" bitfld.long 0x00 2. " ARDY_IE ,Register access ready interrupt enable clear" "No effect,Clear" bitfld.long 0x00 1. " NACK_IE ,No acknowledgment interrupt enable clear" "No effect,Clear" bitfld.long 0x00 0. " AL_IE ,Arbitration lost interrupt enable clear" "No effect,Clear" group.long 0x34++0x03 line.long 0x00 "I2C_WE,Every 1-bit field in the I2C_WE register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup" bitfld.long 0x00 14. " XDR_WE ,Transmit draining wakeup enable" "Disabled,Enabled" bitfld.long 0x00 13. " RDR_WE ,Receive draining wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR_WE ,Receive overrun wakeup enable" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF_WE ,Transmit underflow wakeup enable" "Disabled,Enabled" bitfld.long 0x00 9. " AAS_WE ,Address as slave IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 8. " BF_WE ,Bus free IRQ wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC_WE ,Start condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC_WE ,General call IRQ wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY_WE ,Receive/Transmit data ready IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY_WE ,Register access ready IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 1. " NACK_WE ,No acknowledgment IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 0. " AL_WE ,Arbitration lost IRQ wakeup enable" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "I2C_DMARXEN_SET,The 1-bit field enables a receive DMA request" bitfld.long 0x00 0. " DMARX_EN_SET , Receive DMA channel enable set" "No effect,Enabled" group.long 0x3C++0x03 line.long 0x00 "I2C_DMATXEN_SET,The 1-bit field enables a transmit DMA request" bitfld.long 0x00 0. " DMATX_TRANSMIT_SET , Transmit DMA channel enable set" "No effect,Enabled" group.long 0x40++0x03 line.long 0x00 "I2C_DMARXEN_CLR,The 1-bit field disables a receive DMA request" eventfld.long 0x00 0. " DMARX_EN_CLR , Receive DMA channel enable clear." "No effect,Clear" group.long 0x44++0x03 line.long 0x00 "I2C_DMATXEN_CLR,The 1-bit field disables a transmit DMA request" eventfld.long 0x00 0. " DMATX_EN_CLR , Transmit DMA channel enable clear" "No effect,Clear" group.long 0x48++0x03 line.long 0x00 "I2C_DMARXWAKE_EN,All 1-bit fields enable a specific (synchronous) DMA request source to generate an asynchronous wakeup" bitfld.long 0x00 14. " XDR ,Transmit draining wakeup set" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 8. " BF ,Bus free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC ,Start condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY ,Receive/transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" group.long 0x4C++0x03 line.long 0x00 "I2C_DMATXWAKE_EN,All 1-bit fields enable a specific (synchronous) DMA request source to generate an asynchronous wakeup" bitfld.long 0x00 14. " XDR ,Transmit draining wakeup set" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 8. " BF ,Bus free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC ,Start condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY ,Receive/transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" group.long 0x90++0x03 line.long 0x00 "I2C_SYSS,I2C_SYSS" bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed" group.long 0x94++0x03 line.long 0x00 "I2C_BUF,Register enables DMA transfers and allows the configuration of FIFO thresholds for the FIFO management" bitfld.long 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset" textline " " bitfld.long 0x00 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset" bitfld.long 0x00 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" if (((d.l(ad:0x44E0B000+0xA4))&0x400)==0x400) //I2C_CON.MST== "Master" group.long 0x98++0x03 line.long 0x00 "I2C_CNT,I2C_CNT" hexmask.long.word 0x00 0.--15. 1. " DCOUNT ,Data count(I2C Master Mode only)" else hgroup.long 0x98++0x03 hide.long 0x00 "I2C_CNT,I2C_CNT" endif hgroup.long 0x9C++0x03 hide.long 0x00 "I2C_DATA,This register is the entry point for the local host to read data from or write data to the FIFO buffer." in if (((d.l(ad:0x44E0B000+0xA4))&0x400)==0x400) //I2C_CON.MST== "Master" group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C_CON" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard mode,,," bitfld.long 0x00 11. " STB ,Start byte mode(I2C master mode only)" "Normal,Start" bitfld.long 0x00 10. " MST ,Master/slave mode(I2C mode only)" "Slave,Master" textline " " bitfld.long 0x00 9. " TRX ,Transmitter/receiver mode (i2C master mode only)" "Receiver,Transmitter" bitfld.long 0x00 8. " XSA ,Expand slave address(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 7. " XOA0 ,Expand own address 0(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand own address 1(I2C mode only)" "7-bit,10-bit" textline " " bitfld.long 0x00 5. " XOA2 ,Expand own address 2(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand own address 3" "7-bit,10-bit" bitfld.long 0x00 1. " STP ,Stop condition (I2C master mode only)" "No action,Stop condition" bitfld.long 0x00 0. " STT ,Start condition (I2C master mode only)" "No action,Start condition" else group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C_CON" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard mode,,," bitfld.long 0x00 10. " MST ,Master/slave mode(I2C mode only)" "Slave,Master" bitfld.long 0x00 8. " XSA ,Expand slave address(I2C mode only)" "7-bit,10-bit" textline " " bitfld.long 0x00 7. " XOA0 ,Expand own address 0(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand own address 1(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 5. " XOA2 ,Expand own address 2(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand own address 3" "7-bit,10-bit" endif if (((d.l(ad:0x44E0B000+0xA4))&0x80)==0x80) //I2C_CON.XOA0== "10-bit" group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C_OA" hexmask.long.word 0x00 0.--9. 1. " OA , Own address" else group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C_OA" hexmask.long.word 0x00 0.--7. 1. " OA , Own address" endif if (((d.l(ad:0x44E0B000+0xA4))&0x100)==0x100) //I2C_CON.XSA== "10-bit" group.long 0xAC++0x03 line.long 0x00 "I2C_SA,I2C_SA" hexmask.long.word 0x00 0.--9. 1. " SA , Slave address" else group.long 0xAC++0x03 line.long 0x00 "I2C_SA,I2C_SA" hexmask.long.word 0x00 0.--7. 1. " SA , Slave address" endif group.long 0xB0++0x03 line.long 0x00 "I2C_PSC,I2C_PSC" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value" if (((d.l(ad:0x44E0B000+0xA4))&0x400)==0x400) //I2C_CON.MST== "Master" group.long 0xB4++0x03 line.long 0x00 "I2C_SCLL,I2C_SCLL" hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time" group.long 0xB8++0x03 line.long 0x00 "I2C_SCLH,I2C_SCLH" hexmask.long.byte 0x00 0.--7. 1. " SCLH , Fast/Standard mode SCL high time" else hgroup.long 0xB4++0x03 hide.long 0x00 "I2C_SCLL,I2C_SCLL" hgroup.long 0xB8++0x03 hide.long 0x00 "I2C_SCLH,I2C_SCLH" endif if (((d.l(ad:0x44E0B000+0xBC))&0x8000)==0x8000)||(((d.l(ad:0x44E0B000+0xBC))&0x3000)==0x2000) group.long 0xBC++0x03 line.long 0x00 "I2C_SYSTEST,I2C_SYSTEST" bitfld.long 0x00 15. " ST_EN ,System test enable" "Normal,System test" bitfld.long 0x00 14. " FREE ,Free running mode" "Stop mode,Free running" bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional mode,,Test of SCL counters,Loop back mode+SDA/SCL IO" bitfld.long 0x00 11. " SSB ,Set status bits" "No action,Set" textline " " bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "0,1" bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "0,1" bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "0,1" bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "0,1" textline " " bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "0,1" bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low level forced,High-impedance" bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "0,1" bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low level forced,High-impedance" else group.long 0xBC++0x03 line.long 0x00 "I2C_SYSTEST,I2C_SYSTEST" bitfld.long 0x00 15. " ST_EN ,System test enable" "Normal,System test" bitfld.long 0x00 14. " FREE ,Free running mode" "Stop mode,Free running" bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional mode,,Test of SCL counters,Loop back mode+SDA/SCL IO" textline " " bitfld.long 0x00 11. " SSB ,Set status bits" "No action,Set" bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "0,1" bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "0,1" bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "0,1" bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "0,1" endif rgroup.long 0xC0++0x03 line.long 0x00 "I2C_BUFSTAT,Status of the internal buffers for the FIFO management" bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.long 0x00 8.--13. " RXSTAT , RX buffer status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TXSTAT ,TX buffer status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((d.l(ad:0x44E0B000+0xA4))&0x40)==0x40) //I2C_CON.XOA1== "10-bit" group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C_OA1" hexmask.long.word 0x00 0.--9. 1. " OA1 , Own address 1" else group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C_OA1" hexmask.long.word 0x00 0.--7. 1. " OA1 , Own address 1" endif if (((d.l(ad:0x44E0B000+0xA4))&0x20)==0x20) //I2C_CON.XOA2== "10-bit" group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C_OA2" hexmask.long.word 0x00 0.--9. 1. " OA2 , Own address 2" else group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C_OA2" hexmask.long.word 0x00 0.--7. 1. " OA2 , Own address 2" endif if (((d.l(ad:0x44E0B000+0xA4))&0x10)==0x10) //I2C_CON.XOA2== "10-bit" group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C_OA3" hexmask.long.word 0x00 0.--9. 1. " OA3 , Own address 3" else group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C_OA3" hexmask.long.word 0x00 0.--7. 1. " OA3 , Own address 3" endif rgroup.long 0xD0++0x03 line.long 0x00 "I2C_ACTOA,Register is used to indicate which one of the module four own addresses the external master used when addressing the module" bitfld.long 0x00 3. " OA3_ACT ,Own address 3 active" "Inactive,Active" bitfld.long 0x00 2. " OA2_ACT ,Own address 2 active" "Inactive,Active" bitfld.long 0x00 1. " OA1_ACT ,Own address 1 active" "Inactive,Active" bitfld.long 0x00 0. " OA0_ACT ,Own address 0 active" "Inactive,Active" group.long 0xD4++0x03 line.long 0x00 "I2C_SBLOCK,Register controls the automatic blocking of I2C clock feature in slave mode" bitfld.long 0x00 3. " OA3_EN ,Enable I2C clock blocking for own address 3" "Released,Blocked" bitfld.long 0x00 2. " OA2_EN ,Enable I2C clock blocking for own address 2" "Released,Blocked" bitfld.long 0x00 1. " OA1_EN ,Enable I2C clock blocking for own address 1" "Released,Blocked" bitfld.long 0x00 0. " OA0_EN ,Enable I2C clock blocking for own address 0" "Released,Blocked" width 11. tree.end tree "I2C 1" base ad:0x4802A000 width 18. rgroup.long 0x00++0x03 line.long 0x00 "I2C_REVNB_LO,Register contains the hard-coded revision number of the module" bitfld.long 0x00 11.--15. " RTL , RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR , Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision" rgroup.long 0x04++0x03 line.long 0x00 "I2C_REVNB_HI,I2C_REVNB_HI register" bitfld.long 0x00 14.--15. " SCHEME , Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " FUNC ,Indicates a software compatible module family" group.long 0x10++0x03 line.long 0x00 "I2C_SYSC,This register allows controlling various parameters of the peripheral interface." bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both clocks off,Interface/OCP active|system clock off,System clock active|Interface/OCP off,Both active" textline " " bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No Idle,Smart Idle,Smart-idle wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled" bitfld.long 0x00 1. " SRST ,SoftReset bit" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled" textline " " if (((d.l(ad:0x4802A000+0xA4))&0x400)==0x400)&&(((d.l(ad:0x4802A000+0xA4))&0x200)==0x200) //I2C_CON.MST== "Master" &&I 2C_CON.TRX== "Transmitter" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status(I2C Master Transmit mode only)" "Disabled,Enabled" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" bitfld.long 0x00 10. " XUDF ,Transmit underflow status(I2C transmit mode only)" "Normal,Underflow" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" textline " " eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status(I2C mode)" "On-going,Ready" bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" elif (((d.l(ad:0x4802A000+0xA4))&0x400)==0x400)&&(((d.l(ad:0x4802A000+0xA4))&0x200)==0x00) //I2C_CON.MST== "Master" &&I 2C_CON.TRX== "Receiver" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" bitfld.long 0x00 13. " RDR ,Receive draining IRQ status(I2C Receive mode only)" "Disabled,Enabled" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" rbitfld.long 0x00 11. " ROVR ,Receive overrun status(I2C receive mode only)" "Normal,Overrun" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" textline " " bitfld.long 0x00 3. " RRDY ,RX FIFO level is above the configured threshold status(I2C mode)" "Not reached,Reached" bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" elif (((d.l(ad:0x4802A000+0xA4))&0x400)==0x00)&&(((d.l(ad:0x4802A000+0xA4))&0x200)==0x00) //I2C_CON.MST== "Slave" &&I 2C_CON.TRX== "Receiver" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" bitfld.long 0x00 13. " RDR ,Receive draining IRQ status(I2C Receive mode only)" "Disabled,Enabled" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" rbitfld.long 0x00 11. " ROVR ,Receive overrun status(I2C receive mode only)" "Normal,Overrun" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" textline " " bitfld.long 0x00 3. " RRDY ,RX FIFO level is above the configured threshold status(I2C mode)" "Not reached,Reached" bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" elif (((d.l(ad:0x4802A000+0xA4))&0x400)==0x00)&&(((d.l(ad:0x4802A000+0xA4))&0x200)==0x200) //I2C_CON.MST== "Slave" &&I 2C_CON.TRX== "Transmitter" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "Normal,Underflow" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" textline " " bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status(I2C mode)" "On-going,Ready" textline " " bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" endif group.long 0x28++0x03 line.long 0x00 "I2C_IRQSTS,This register provides core status information for interrupt handling, showing all active and enabled events and masking the others" eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled" eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled" eventfld.long 0x00 12. " BB ,Bus busy enabled status" "Free,Occupied" textline " " eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,overrun" eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "Normal,underflow" eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Address recognized" eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free" textline " " eventfld.long 0x00 7. " AERR , Access Error IRQ enabled status" "No action,Error" eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected" eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "On-going,Ready" textline " " eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "No available,Available" eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Module busy,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ enabled status" "Normal,Detected" eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected" group.long 0x2C++0x03 line.long 0x00 "I2C_IRQEN_SET,All 1-bit fields enable a specific interrupt event to trigger an interrupt request" bitfld.long 0x00 14. " XDR_IE ,Transmit draining interrupt enable set" "No effect,Enabled" bitfld.long 0x00 13. " RDR_IE ,Receive draining interrupt enable set" "No effect,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun enable set" "No effect,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow enable set" "No effect,Enabled" bitfld.long 0x00 9. " AAS_IE ,Addressed as slave interrupt enable set" "No effect,Enabled" bitfld.long 0x00 8. " BF_IE ,Bus free interrupt enable set" "No effect,Enabled" textline " " bitfld.long 0x00 7. " AERR_IE ,Access error interrupt enabled set" "No effect,Enabled" bitfld.long 0x00 6. " STC_IE ,Start condition interrupt enable set" "No effect,Enabled" bitfld.long 0x00 5. " GC_IE ,General call interrupt enable set" "No effect,Enabled" bitfld.long 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable set" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RRDY_IE ,Receive data ready interrupt enable set" "No effect,Enabled" bitfld.long 0x00 2. " ARDY_IE ,Register access ready interrupt enable set" "No effect,Enabled" bitfld.long 0x00 1. " NACK_IE ,No acknowledgment interrupt enable set" "No effect,Enabled" bitfld.long 0x00 0. " AL_IE ,Arbitration lost interrupt enable set" "No effect,Enabled" group.long 0x30++0x03 line.long 0x00 "I2C_IRQEN_CLR,All 1-bit fields clear a specific interrupt event" bitfld.long 0x00 14. " XDR_IE ,Transmit draining interrupt enable clear" "No effect,Clear" bitfld.long 0x00 13. " RDR_IE ,Receive draining interrupt enable clear" "No effect,Clear" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun enable clear" "No effect,Clear" bitfld.long 0x00 10. " XUDF ,Transmit underflow enable clear" "No effect,Clear" bitfld.long 0x00 9. " AAS_IE ,Addressed as slave interrupt enable clear" "No effect,Clear" bitfld.long 0x00 8. " BF_IE ,Bus free interrupt enable clear" "No effect,Clear" textline " " bitfld.long 0x00 7. " AERR_IE ,Access error interrupt enabled clear" "No effect,Clear" bitfld.long 0x00 6. " STC_IE ,Start condition interrupt enable clear" "No effect,Clear" bitfld.long 0x00 5. " GC_IE ,General call interrupt enable clear" "No effect,Clear" bitfld.long 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " RRDY_IE ,Receive data ready interrupt enable clear" "No effect,Clear" bitfld.long 0x00 2. " ARDY_IE ,Register access ready interrupt enable clear" "No effect,Clear" bitfld.long 0x00 1. " NACK_IE ,No acknowledgment interrupt enable clear" "No effect,Clear" bitfld.long 0x00 0. " AL_IE ,Arbitration lost interrupt enable clear" "No effect,Clear" group.long 0x34++0x03 line.long 0x00 "I2C_WE,Every 1-bit field in the I2C_WE register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup" bitfld.long 0x00 14. " XDR_WE ,Transmit draining wakeup enable" "Disabled,Enabled" bitfld.long 0x00 13. " RDR_WE ,Receive draining wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR_WE ,Receive overrun wakeup enable" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF_WE ,Transmit underflow wakeup enable" "Disabled,Enabled" bitfld.long 0x00 9. " AAS_WE ,Address as slave IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 8. " BF_WE ,Bus free IRQ wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC_WE ,Start condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC_WE ,General call IRQ wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY_WE ,Receive/Transmit data ready IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY_WE ,Register access ready IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 1. " NACK_WE ,No acknowledgment IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 0. " AL_WE ,Arbitration lost IRQ wakeup enable" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "I2C_DMARXEN_SET,The 1-bit field enables a receive DMA request" bitfld.long 0x00 0. " DMARX_EN_SET , Receive DMA channel enable set" "No effect,Enabled" group.long 0x3C++0x03 line.long 0x00 "I2C_DMATXEN_SET,The 1-bit field enables a transmit DMA request" bitfld.long 0x00 0. " DMATX_TRANSMIT_SET , Transmit DMA channel enable set" "No effect,Enabled" group.long 0x40++0x03 line.long 0x00 "I2C_DMARXEN_CLR,The 1-bit field disables a receive DMA request" eventfld.long 0x00 0. " DMARX_EN_CLR , Receive DMA channel enable clear." "No effect,Clear" group.long 0x44++0x03 line.long 0x00 "I2C_DMATXEN_CLR,The 1-bit field disables a transmit DMA request" eventfld.long 0x00 0. " DMATX_EN_CLR , Transmit DMA channel enable clear" "No effect,Clear" group.long 0x48++0x03 line.long 0x00 "I2C_DMARXWAKE_EN,All 1-bit fields enable a specific (synchronous) DMA request source to generate an asynchronous wakeup" bitfld.long 0x00 14. " XDR ,Transmit draining wakeup set" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 8. " BF ,Bus free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC ,Start condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY ,Receive/transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" group.long 0x4C++0x03 line.long 0x00 "I2C_DMATXWAKE_EN,All 1-bit fields enable a specific (synchronous) DMA request source to generate an asynchronous wakeup" bitfld.long 0x00 14. " XDR ,Transmit draining wakeup set" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 8. " BF ,Bus free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC ,Start condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY ,Receive/transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" group.long 0x90++0x03 line.long 0x00 "I2C_SYSS,I2C_SYSS" bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed" group.long 0x94++0x03 line.long 0x00 "I2C_BUF,Register enables DMA transfers and allows the configuration of FIFO thresholds for the FIFO management" bitfld.long 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset" textline " " bitfld.long 0x00 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset" bitfld.long 0x00 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" if (((d.l(ad:0x4802A000+0xA4))&0x400)==0x400) //I2C_CON.MST== "Master" group.long 0x98++0x03 line.long 0x00 "I2C_CNT,I2C_CNT" hexmask.long.word 0x00 0.--15. 1. " DCOUNT ,Data count(I2C Master Mode only)" else hgroup.long 0x98++0x03 hide.long 0x00 "I2C_CNT,I2C_CNT" endif hgroup.long 0x9C++0x03 hide.long 0x00 "I2C_DATA,This register is the entry point for the local host to read data from or write data to the FIFO buffer." in if (((d.l(ad:0x4802A000+0xA4))&0x400)==0x400) //I2C_CON.MST== "Master" group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C_CON" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard mode,,," bitfld.long 0x00 11. " STB ,Start byte mode(I2C master mode only)" "Normal,Start" bitfld.long 0x00 10. " MST ,Master/slave mode(I2C mode only)" "Slave,Master" textline " " bitfld.long 0x00 9. " TRX ,Transmitter/receiver mode (i2C master mode only)" "Receiver,Transmitter" bitfld.long 0x00 8. " XSA ,Expand slave address(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 7. " XOA0 ,Expand own address 0(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand own address 1(I2C mode only)" "7-bit,10-bit" textline " " bitfld.long 0x00 5. " XOA2 ,Expand own address 2(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand own address 3" "7-bit,10-bit" bitfld.long 0x00 1. " STP ,Stop condition (I2C master mode only)" "No action,Stop condition" bitfld.long 0x00 0. " STT ,Start condition (I2C master mode only)" "No action,Start condition" else group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C_CON" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard mode,,," bitfld.long 0x00 10. " MST ,Master/slave mode(I2C mode only)" "Slave,Master" bitfld.long 0x00 8. " XSA ,Expand slave address(I2C mode only)" "7-bit,10-bit" textline " " bitfld.long 0x00 7. " XOA0 ,Expand own address 0(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand own address 1(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 5. " XOA2 ,Expand own address 2(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand own address 3" "7-bit,10-bit" endif if (((d.l(ad:0x4802A000+0xA4))&0x80)==0x80) //I2C_CON.XOA0== "10-bit" group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C_OA" hexmask.long.word 0x00 0.--9. 1. " OA , Own address" else group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C_OA" hexmask.long.word 0x00 0.--7. 1. " OA , Own address" endif if (((d.l(ad:0x4802A000+0xA4))&0x100)==0x100) //I2C_CON.XSA== "10-bit" group.long 0xAC++0x03 line.long 0x00 "I2C_SA,I2C_SA" hexmask.long.word 0x00 0.--9. 1. " SA , Slave address" else group.long 0xAC++0x03 line.long 0x00 "I2C_SA,I2C_SA" hexmask.long.word 0x00 0.--7. 1. " SA , Slave address" endif group.long 0xB0++0x03 line.long 0x00 "I2C_PSC,I2C_PSC" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value" if (((d.l(ad:0x4802A000+0xA4))&0x400)==0x400) //I2C_CON.MST== "Master" group.long 0xB4++0x03 line.long 0x00 "I2C_SCLL,I2C_SCLL" hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time" group.long 0xB8++0x03 line.long 0x00 "I2C_SCLH,I2C_SCLH" hexmask.long.byte 0x00 0.--7. 1. " SCLH , Fast/Standard mode SCL high time" else hgroup.long 0xB4++0x03 hide.long 0x00 "I2C_SCLL,I2C_SCLL" hgroup.long 0xB8++0x03 hide.long 0x00 "I2C_SCLH,I2C_SCLH" endif if (((d.l(ad:0x4802A000+0xBC))&0x8000)==0x8000)||(((d.l(ad:0x4802A000+0xBC))&0x3000)==0x2000) group.long 0xBC++0x03 line.long 0x00 "I2C_SYSTEST,I2C_SYSTEST" bitfld.long 0x00 15. " ST_EN ,System test enable" "Normal,System test" bitfld.long 0x00 14. " FREE ,Free running mode" "Stop mode,Free running" bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional mode,,Test of SCL counters,Loop back mode+SDA/SCL IO" bitfld.long 0x00 11. " SSB ,Set status bits" "No action,Set" textline " " bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "0,1" bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "0,1" bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "0,1" bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "0,1" textline " " bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "0,1" bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low level forced,High-impedance" bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "0,1" bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low level forced,High-impedance" else group.long 0xBC++0x03 line.long 0x00 "I2C_SYSTEST,I2C_SYSTEST" bitfld.long 0x00 15. " ST_EN ,System test enable" "Normal,System test" bitfld.long 0x00 14. " FREE ,Free running mode" "Stop mode,Free running" bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional mode,,Test of SCL counters,Loop back mode+SDA/SCL IO" textline " " bitfld.long 0x00 11. " SSB ,Set status bits" "No action,Set" bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "0,1" bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "0,1" bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "0,1" bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "0,1" endif rgroup.long 0xC0++0x03 line.long 0x00 "I2C_BUFSTAT,Status of the internal buffers for the FIFO management" bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.long 0x00 8.--13. " RXSTAT , RX buffer status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TXSTAT ,TX buffer status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((d.l(ad:0x4802A000+0xA4))&0x40)==0x40) //I2C_CON.XOA1== "10-bit" group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C_OA1" hexmask.long.word 0x00 0.--9. 1. " OA1 , Own address 1" else group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C_OA1" hexmask.long.word 0x00 0.--7. 1. " OA1 , Own address 1" endif if (((d.l(ad:0x4802A000+0xA4))&0x20)==0x20) //I2C_CON.XOA2== "10-bit" group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C_OA2" hexmask.long.word 0x00 0.--9. 1. " OA2 , Own address 2" else group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C_OA2" hexmask.long.word 0x00 0.--7. 1. " OA2 , Own address 2" endif if (((d.l(ad:0x4802A000+0xA4))&0x10)==0x10) //I2C_CON.XOA2== "10-bit" group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C_OA3" hexmask.long.word 0x00 0.--9. 1. " OA3 , Own address 3" else group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C_OA3" hexmask.long.word 0x00 0.--7. 1. " OA3 , Own address 3" endif rgroup.long 0xD0++0x03 line.long 0x00 "I2C_ACTOA,Register is used to indicate which one of the module four own addresses the external master used when addressing the module" bitfld.long 0x00 3. " OA3_ACT ,Own address 3 active" "Inactive,Active" bitfld.long 0x00 2. " OA2_ACT ,Own address 2 active" "Inactive,Active" bitfld.long 0x00 1. " OA1_ACT ,Own address 1 active" "Inactive,Active" bitfld.long 0x00 0. " OA0_ACT ,Own address 0 active" "Inactive,Active" group.long 0xD4++0x03 line.long 0x00 "I2C_SBLOCK,Register controls the automatic blocking of I2C clock feature in slave mode" bitfld.long 0x00 3. " OA3_EN ,Enable I2C clock blocking for own address 3" "Released,Blocked" bitfld.long 0x00 2. " OA2_EN ,Enable I2C clock blocking for own address 2" "Released,Blocked" bitfld.long 0x00 1. " OA1_EN ,Enable I2C clock blocking for own address 1" "Released,Blocked" bitfld.long 0x00 0. " OA0_EN ,Enable I2C clock blocking for own address 0" "Released,Blocked" width 11. tree.end tree "I2C 2" base ad:0x4819C000 width 18. rgroup.long 0x00++0x03 line.long 0x00 "I2C_REVNB_LO,Register contains the hard-coded revision number of the module" bitfld.long 0x00 11.--15. " RTL , RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR , Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision" rgroup.long 0x04++0x03 line.long 0x00 "I2C_REVNB_HI,I2C_REVNB_HI register" bitfld.long 0x00 14.--15. " SCHEME , Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " FUNC ,Indicates a software compatible module family" group.long 0x10++0x03 line.long 0x00 "I2C_SYSC,This register allows controlling various parameters of the peripheral interface." bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both clocks off,Interface/OCP active|system clock off,System clock active|Interface/OCP off,Both active" textline " " bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No Idle,Smart Idle,Smart-idle wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled" bitfld.long 0x00 1. " SRST ,SoftReset bit" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled" textline " " if (((d.l(ad:0x4819C000+0xA4))&0x400)==0x400)&&(((d.l(ad:0x4819C000+0xA4))&0x200)==0x200) //I2C_CON.MST== "Master" &&I 2C_CON.TRX== "Transmitter" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status(I2C Master Transmit mode only)" "Disabled,Enabled" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" bitfld.long 0x00 10. " XUDF ,Transmit underflow status(I2C transmit mode only)" "Normal,Underflow" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" textline " " eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status(I2C mode)" "On-going,Ready" bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" elif (((d.l(ad:0x4819C000+0xA4))&0x400)==0x400)&&(((d.l(ad:0x4819C000+0xA4))&0x200)==0x00) //I2C_CON.MST== "Master" &&I 2C_CON.TRX== "Receiver" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" bitfld.long 0x00 13. " RDR ,Receive draining IRQ status(I2C Receive mode only)" "Disabled,Enabled" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" rbitfld.long 0x00 11. " ROVR ,Receive overrun status(I2C receive mode only)" "Normal,Overrun" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" textline " " bitfld.long 0x00 3. " RRDY ,RX FIFO level is above the configured threshold status(I2C mode)" "Not reached,Reached" bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" elif (((d.l(ad:0x4819C000+0xA4))&0x400)==0x00)&&(((d.l(ad:0x4819C000+0xA4))&0x200)==0x00) //I2C_CON.MST== "Slave" &&I 2C_CON.TRX== "Receiver" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" bitfld.long 0x00 13. " RDR ,Receive draining IRQ status(I2C Receive mode only)" "Disabled,Enabled" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" rbitfld.long 0x00 11. " ROVR ,Receive overrun status(I2C receive mode only)" "Normal,Overrun" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" textline " " bitfld.long 0x00 3. " RRDY ,RX FIFO level is above the configured threshold status(I2C mode)" "Not reached,Reached" bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" elif (((d.l(ad:0x4819C000+0xA4))&0x400)==0x00)&&(((d.l(ad:0x4819C000+0xA4))&0x200)==0x200) //I2C_CON.MST== "Slave" &&I 2C_CON.TRX== "Transmitter" group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTS_RAW,This register provides core status information for interrupt handling, showing all active events" rbitfld.long 0x00 12. " BB ,State of the serial bus" "Free,Occupied" bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "Normal,Underflow" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status(I2C mode)" "No action,Recognized" bitfld.long 0x00 8. " BF ,Bus I2C Free(I2C mode)" "No action,Status" textline " " bitfld.long 0x00 7. " AERR ,Access Error IRQ status(I2C mode)" "No action,Access Error" bitfld.long 0x00 6. " STC ,Start Condition IRQ status(I2C mode)" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status(I2C mode)" "Not detected,Detected" eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status(I2C mode)" "On-going,Ready" textline " " bitfld.long 0x00 2. " ARDY ,Access ready IRQ status(I2C mode)" "No action,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ status(I2C mode)" "Normal,Detected" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status(I2C mode)" "Normal,Detected" endif group.long 0x28++0x03 line.long 0x00 "I2C_IRQSTS,This register provides core status information for interrupt handling, showing all active and enabled events and masking the others" eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled" eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled" eventfld.long 0x00 12. " BB ,Bus busy enabled status" "Free,Occupied" textline " " eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,overrun" eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "Normal,underflow" eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Address recognized" eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free" textline " " eventfld.long 0x00 7. " AERR , Access Error IRQ enabled status" "No action,Error" eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected" eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "On-going,Ready" textline " " eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "No available,Available" eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Module busy,Access ready" eventfld.long 0x00 1. " NACK ,No acknowledgment IRQ enabled status" "Normal,Detected" eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected" group.long 0x2C++0x03 line.long 0x00 "I2C_IRQEN_SET,All 1-bit fields enable a specific interrupt event to trigger an interrupt request" bitfld.long 0x00 14. " XDR_IE ,Transmit draining interrupt enable set" "No effect,Enabled" bitfld.long 0x00 13. " RDR_IE ,Receive draining interrupt enable set" "No effect,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun enable set" "No effect,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow enable set" "No effect,Enabled" bitfld.long 0x00 9. " AAS_IE ,Addressed as slave interrupt enable set" "No effect,Enabled" bitfld.long 0x00 8. " BF_IE ,Bus free interrupt enable set" "No effect,Enabled" textline " " bitfld.long 0x00 7. " AERR_IE ,Access error interrupt enabled set" "No effect,Enabled" bitfld.long 0x00 6. " STC_IE ,Start condition interrupt enable set" "No effect,Enabled" bitfld.long 0x00 5. " GC_IE ,General call interrupt enable set" "No effect,Enabled" bitfld.long 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable set" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RRDY_IE ,Receive data ready interrupt enable set" "No effect,Enabled" bitfld.long 0x00 2. " ARDY_IE ,Register access ready interrupt enable set" "No effect,Enabled" bitfld.long 0x00 1. " NACK_IE ,No acknowledgment interrupt enable set" "No effect,Enabled" bitfld.long 0x00 0. " AL_IE ,Arbitration lost interrupt enable set" "No effect,Enabled" group.long 0x30++0x03 line.long 0x00 "I2C_IRQEN_CLR,All 1-bit fields clear a specific interrupt event" bitfld.long 0x00 14. " XDR_IE ,Transmit draining interrupt enable clear" "No effect,Clear" bitfld.long 0x00 13. " RDR_IE ,Receive draining interrupt enable clear" "No effect,Clear" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun enable clear" "No effect,Clear" bitfld.long 0x00 10. " XUDF ,Transmit underflow enable clear" "No effect,Clear" bitfld.long 0x00 9. " AAS_IE ,Addressed as slave interrupt enable clear" "No effect,Clear" bitfld.long 0x00 8. " BF_IE ,Bus free interrupt enable clear" "No effect,Clear" textline " " bitfld.long 0x00 7. " AERR_IE ,Access error interrupt enabled clear" "No effect,Clear" bitfld.long 0x00 6. " STC_IE ,Start condition interrupt enable clear" "No effect,Clear" bitfld.long 0x00 5. " GC_IE ,General call interrupt enable clear" "No effect,Clear" bitfld.long 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " RRDY_IE ,Receive data ready interrupt enable clear" "No effect,Clear" bitfld.long 0x00 2. " ARDY_IE ,Register access ready interrupt enable clear" "No effect,Clear" bitfld.long 0x00 1. " NACK_IE ,No acknowledgment interrupt enable clear" "No effect,Clear" bitfld.long 0x00 0. " AL_IE ,Arbitration lost interrupt enable clear" "No effect,Clear" group.long 0x34++0x03 line.long 0x00 "I2C_WE,Every 1-bit field in the I2C_WE register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup" bitfld.long 0x00 14. " XDR_WE ,Transmit draining wakeup enable" "Disabled,Enabled" bitfld.long 0x00 13. " RDR_WE ,Receive draining wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR_WE ,Receive overrun wakeup enable" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF_WE ,Transmit underflow wakeup enable" "Disabled,Enabled" bitfld.long 0x00 9. " AAS_WE ,Address as slave IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 8. " BF_WE ,Bus free IRQ wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC_WE ,Start condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC_WE ,General call IRQ wakeup enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY_WE ,Receive/Transmit data ready IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY_WE ,Register access ready IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 1. " NACK_WE ,No acknowledgment IRQ wakeup enable" "Disabled,Enabled" bitfld.long 0x00 0. " AL_WE ,Arbitration lost IRQ wakeup enable" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "I2C_DMARXEN_SET,The 1-bit field enables a receive DMA request" bitfld.long 0x00 0. " DMARX_EN_SET , Receive DMA channel enable set" "No effect,Enabled" group.long 0x3C++0x03 line.long 0x00 "I2C_DMATXEN_SET,The 1-bit field enables a transmit DMA request" bitfld.long 0x00 0. " DMATX_TRANSMIT_SET , Transmit DMA channel enable set" "No effect,Enabled" group.long 0x40++0x03 line.long 0x00 "I2C_DMARXEN_CLR,The 1-bit field disables a receive DMA request" eventfld.long 0x00 0. " DMARX_EN_CLR , Receive DMA channel enable clear." "No effect,Clear" group.long 0x44++0x03 line.long 0x00 "I2C_DMATXEN_CLR,The 1-bit field disables a transmit DMA request" eventfld.long 0x00 0. " DMATX_EN_CLR , Transmit DMA channel enable clear" "No effect,Clear" group.long 0x48++0x03 line.long 0x00 "I2C_DMARXWAKE_EN,All 1-bit fields enable a specific (synchronous) DMA request source to generate an asynchronous wakeup" bitfld.long 0x00 14. " XDR ,Transmit draining wakeup set" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 8. " BF ,Bus free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC ,Start condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY ,Receive/transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" group.long 0x4C++0x03 line.long 0x00 "I2C_DMATXWAKE_EN,All 1-bit fields enable a specific (synchronous) DMA request source to generate an asynchronous wakeup" bitfld.long 0x00 14. " XDR ,Transmit draining wakeup set" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 8. " BF ,Bus free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC ,Start condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY ,Receive/transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" group.long 0x90++0x03 line.long 0x00 "I2C_SYSS,I2C_SYSS" bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed" group.long 0x94++0x03 line.long 0x00 "I2C_BUF,Register enables DMA transfers and allows the configuration of FIFO thresholds for the FIFO management" bitfld.long 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled" bitfld.long 0x00 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset" textline " " bitfld.long 0x00 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled" bitfld.long 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset" bitfld.long 0x00 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" if (((d.l(ad:0x4819C000+0xA4))&0x400)==0x400) //I2C_CON.MST== "Master" group.long 0x98++0x03 line.long 0x00 "I2C_CNT,I2C_CNT" hexmask.long.word 0x00 0.--15. 1. " DCOUNT ,Data count(I2C Master Mode only)" else hgroup.long 0x98++0x03 hide.long 0x00 "I2C_CNT,I2C_CNT" endif hgroup.long 0x9C++0x03 hide.long 0x00 "I2C_DATA,This register is the entry point for the local host to read data from or write data to the FIFO buffer." in if (((d.l(ad:0x4819C000+0xA4))&0x400)==0x400) //I2C_CON.MST== "Master" group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C_CON" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard mode,,," bitfld.long 0x00 11. " STB ,Start byte mode(I2C master mode only)" "Normal,Start" bitfld.long 0x00 10. " MST ,Master/slave mode(I2C mode only)" "Slave,Master" textline " " bitfld.long 0x00 9. " TRX ,Transmitter/receiver mode (i2C master mode only)" "Receiver,Transmitter" bitfld.long 0x00 8. " XSA ,Expand slave address(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 7. " XOA0 ,Expand own address 0(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand own address 1(I2C mode only)" "7-bit,10-bit" textline " " bitfld.long 0x00 5. " XOA2 ,Expand own address 2(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand own address 3" "7-bit,10-bit" bitfld.long 0x00 1. " STP ,Stop condition (I2C master mode only)" "No action,Stop condition" bitfld.long 0x00 0. " STT ,Start condition (I2C master mode only)" "No action,Start condition" else group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C_CON" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard mode,,," bitfld.long 0x00 10. " MST ,Master/slave mode(I2C mode only)" "Slave,Master" bitfld.long 0x00 8. " XSA ,Expand slave address(I2C mode only)" "7-bit,10-bit" textline " " bitfld.long 0x00 7. " XOA0 ,Expand own address 0(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand own address 1(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 5. " XOA2 ,Expand own address 2(I2C mode only)" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand own address 3" "7-bit,10-bit" endif if (((d.l(ad:0x4819C000+0xA4))&0x80)==0x80) //I2C_CON.XOA0== "10-bit" group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C_OA" hexmask.long.word 0x00 0.--9. 1. " OA , Own address" else group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C_OA" hexmask.long.word 0x00 0.--7. 1. " OA , Own address" endif if (((d.l(ad:0x4819C000+0xA4))&0x100)==0x100) //I2C_CON.XSA== "10-bit" group.long 0xAC++0x03 line.long 0x00 "I2C_SA,I2C_SA" hexmask.long.word 0x00 0.--9. 1. " SA , Slave address" else group.long 0xAC++0x03 line.long 0x00 "I2C_SA,I2C_SA" hexmask.long.word 0x00 0.--7. 1. " SA , Slave address" endif group.long 0xB0++0x03 line.long 0x00 "I2C_PSC,I2C_PSC" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value" if (((d.l(ad:0x4819C000+0xA4))&0x400)==0x400) //I2C_CON.MST== "Master" group.long 0xB4++0x03 line.long 0x00 "I2C_SCLL,I2C_SCLL" hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time" group.long 0xB8++0x03 line.long 0x00 "I2C_SCLH,I2C_SCLH" hexmask.long.byte 0x00 0.--7. 1. " SCLH , Fast/Standard mode SCL high time" else hgroup.long 0xB4++0x03 hide.long 0x00 "I2C_SCLL,I2C_SCLL" hgroup.long 0xB8++0x03 hide.long 0x00 "I2C_SCLH,I2C_SCLH" endif if (((d.l(ad:0x4819C000+0xBC))&0x8000)==0x8000)||(((d.l(ad:0x4819C000+0xBC))&0x3000)==0x2000) group.long 0xBC++0x03 line.long 0x00 "I2C_SYSTEST,I2C_SYSTEST" bitfld.long 0x00 15. " ST_EN ,System test enable" "Normal,System test" bitfld.long 0x00 14. " FREE ,Free running mode" "Stop mode,Free running" bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional mode,,Test of SCL counters,Loop back mode+SDA/SCL IO" bitfld.long 0x00 11. " SSB ,Set status bits" "No action,Set" textline " " bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "0,1" bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "0,1" bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "0,1" bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "0,1" textline " " bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "0,1" bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low level forced,High-impedance" bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "0,1" bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low level forced,High-impedance" else group.long 0xBC++0x03 line.long 0x00 "I2C_SYSTEST,I2C_SYSTEST" bitfld.long 0x00 15. " ST_EN ,System test enable" "Normal,System test" bitfld.long 0x00 14. " FREE ,Free running mode" "Stop mode,Free running" bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional mode,,Test of SCL counters,Loop back mode+SDA/SCL IO" textline " " bitfld.long 0x00 11. " SSB ,Set status bits" "No action,Set" bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "0,1" bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "0,1" bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "0,1" bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "0,1" endif rgroup.long 0xC0++0x03 line.long 0x00 "I2C_BUFSTAT,Status of the internal buffers for the FIFO management" bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.long 0x00 8.--13. " RXSTAT , RX buffer status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " TXSTAT ,TX buffer status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((d.l(ad:0x4819C000+0xA4))&0x40)==0x40) //I2C_CON.XOA1== "10-bit" group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C_OA1" hexmask.long.word 0x00 0.--9. 1. " OA1 , Own address 1" else group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C_OA1" hexmask.long.word 0x00 0.--7. 1. " OA1 , Own address 1" endif if (((d.l(ad:0x4819C000+0xA4))&0x20)==0x20) //I2C_CON.XOA2== "10-bit" group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C_OA2" hexmask.long.word 0x00 0.--9. 1. " OA2 , Own address 2" else group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C_OA2" hexmask.long.word 0x00 0.--7. 1. " OA2 , Own address 2" endif if (((d.l(ad:0x4819C000+0xA4))&0x10)==0x10) //I2C_CON.XOA2== "10-bit" group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C_OA3" hexmask.long.word 0x00 0.--9. 1. " OA3 , Own address 3" else group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C_OA3" hexmask.long.word 0x00 0.--7. 1. " OA3 , Own address 3" endif rgroup.long 0xD0++0x03 line.long 0x00 "I2C_ACTOA,Register is used to indicate which one of the module four own addresses the external master used when addressing the module" bitfld.long 0x00 3. " OA3_ACT ,Own address 3 active" "Inactive,Active" bitfld.long 0x00 2. " OA2_ACT ,Own address 2 active" "Inactive,Active" bitfld.long 0x00 1. " OA1_ACT ,Own address 1 active" "Inactive,Active" bitfld.long 0x00 0. " OA0_ACT ,Own address 0 active" "Inactive,Active" group.long 0xD4++0x03 line.long 0x00 "I2C_SBLOCK,Register controls the automatic blocking of I2C clock feature in slave mode" bitfld.long 0x00 3. " OA3_EN ,Enable I2C clock blocking for own address 3" "Released,Blocked" bitfld.long 0x00 2. " OA2_EN ,Enable I2C clock blocking for own address 2" "Released,Blocked" bitfld.long 0x00 1. " OA1_EN ,Enable I2C clock blocking for own address 1" "Released,Blocked" bitfld.long 0x00 0. " OA0_EN ,Enable I2C clock blocking for own address 0" "Released,Blocked" width 11. tree.end tree.end tree "HDQ/1-Wire Interface" base ad:0x4819C000 width 17. rgroup.long 0x00++0x03 line.long 0x00 "HDQ1W_REVISION,This register contains the IP revision code" hexmask.long.byte 0x00 0.--7. 1. " REV , IP revision" group.long 0x04++0x03 line.long 0x00 "HDQ1W_TX_DATA,This register contains the data to be transmitted" hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data" rgroup.long 0x08++0x03 line.long 0x00 "HDQ1W_RX_DATA,This register contains the data to be received" hexmask.long.byte 0x00 0.--7. 1. " RX_DATA , receive data" group.long 0x0C++0x03 line.long 0x00 "HDQ1W_CTRL_STS,This register provides status information about the module." bitfld.long 0x00 8.--10. " BITFSM_DELAY , BITFSM delay value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7. " ONE_WIRE_SINGLE_BIT ,ONE_WIRE_SINGLE_BIT" "0,1" bitfld.long 0x00 6. " INTRMASK ,INTRMASK" "0,1" textline " " bitfld.long 0x00 5. " CLOCKEN ,CLOCKEN" "0,1" bitfld.long 0x00 4. " GO ,GO" "0,1" rbitfld.long 0x00 3. " PRESENCEDETECT ,PRESENCEDETECT" "0,1" textline " " bitfld.long 0x00 2. " INITIALIZATION ,INITIALIZATION" "0,1" bitfld.long 0x00 1. " DIR ,DIR" "0,1" bitfld.long 0x00 0. " MODE ,MODE" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "HDQ1W_INT_STS,This register controls interrupts status" bitfld.long 0x00 2. " TXCOMPLETE ,Txcomplete" "0,1" bitfld.long 0x00 1. " RXCOMPLETE ,Rxcomplete" "0,1" bitfld.long 0x00 0. " TIMEOUT ,Timeout" "0,1" group.long 0x14++0x03 line.long 0x00 "HDQ1W_SYSCONFIG,This register controls various bits" bitfld.long 0x00 1. " SOFTRESET ,Soft reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,OCP idle" "0,1" rgroup.long 0x18++0x03 line.long 0x00 "HDQ1W_SYSSTS,This register monitors the reset sequence" bitfld.long 0x00 0. " RESETDONE ,Reset done" "0,1" width 11. tree.end tree "McASP(Multichannel Audio Serial Port)" tree "MCASP0" base ad:0x48038000 width 24. rgroup.long 0x000++0x03 line.long 0x00 "MCASP_REV,Revision Identification Register" hexmask.long 0x00 0.--31. 1. " REV , Identifies revision of peripheral." group.long 0x004++0x03 line.long 0x00 "MCASP_PWRIDLESYSCONFIG,Power Idle SYSCONFIG Register" bitfld.long 0x00 0.--1. " IDLEMODE ,Power management Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle," group.long 0x010++0x03 line.long 0x00 "MCASP_PFUNC,Pin Function Register" bitfld.long 0x00 31. " AFSR ,Determines if AFSR pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 30. " AHCLKR ,Determines if AHCLKR pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 29. " ACLKR ,Determines if ACLKR pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 28. " AFSX ,Determines if AFSX pin functions as McASP or GPIO" "McASP,GPIO" textline " " bitfld.long 0x00 27. " AHCLKX ,Determines if AHCLKX pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 26. " ACLKX ,Determines if ACLKX pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 25. " AMUTE ,Determines if AMUTE pin functions as McASP or GPIO" "McASP,GPIO" textline " " bitfld.long 0x00 3. " AXR_3 ,Determines if AXR3 pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 2. " AXR_2 ,Determines if AXR2 pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 1. " AXR_1 ,Determines if AXR1 pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 0. " AXR_0 ,Determines if AXR0 pin functions as McASP or GPIO" "McASP,GPIO" group.long 0x014++0x03 line.long 0x00 "MCASP_PDIR,Pin Direction Register" bitfld.long 0x00 31. " AFSR ,Determines if AFSR pin functions as an input or output" "Input,Output" bitfld.long 0x00 30. " AHCLKR ,Determines if AHCLKR pin functions as an input or output" "Input,Output" bitfld.long 0x00 29. " ACLKR ,Determines if ACLKR pin functions as an input or output" "Input,Output" bitfld.long 0x00 28. " AFSX ,Determines if AFSX pin functions as an input or output" "Input,Output" textline " " bitfld.long 0x00 27. " AHCLKX ,Determines if AHCLKX pin functions as an input or output" "Input,Output" bitfld.long 0x00 26. " ACLKX ,Determines if ACLKX pin functions as an input or output" "Input,Output" bitfld.long 0x00 25. " AMUTE ,Determines if AMUTE pin functions as an input or output" "Input,Output" textline " " bitfld.long 0x00 3. " AXR_3 ,Determines if AXR3 pin functions as an input or output" "Input,Output" bitfld.long 0x00 2. " AXR_2 ,Determines if AXR2 pin functions as an input or output" "Input,Output" bitfld.long 0x00 1. " AXR_1 ,Determines if AXR1 pin functions as an input or output" "Input,Output" bitfld.long 0x00 0. " AXR_0 ,Determines if AXRn pin functions as an input or output" "Input,Output" group.long 0x018++0x03 line.long 0x00 "MCASP_PDOUT,Pin Data Output Register" bitfld.long 0x00 31. " AFSR ,Determines drive on AFSR output pin" "Low,High" bitfld.long 0x00 30. " AHCLKR ,Determines drive on AHCLKR output pin" "Low,High" bitfld.long 0x00 29. " ACLKR ,Determines drive on ACLKR output pin" "Low,High" bitfld.long 0x00 28. " AFSX ,Determines drive on AFSX output pin" "Low,High" textline " " bitfld.long 0x00 27. " AHCLKX ,Determines drive on AHCLKX output pin" "Low,High" bitfld.long 0x00 26. " ACLKX ,Determines drive on ACLKX output pin" "Low,High" bitfld.long 0x00 25. " AMUTE ,Determines drive on AMUTE output pin" "Low,High" textline " " bitfld.long 0x00 3. " AXR_3 ,Determines drive on AXR3 output pin" "Low,High" bitfld.long 0x00 2. " AXR_2 ,Determines drive on AXR2 output pin" "Low,High" bitfld.long 0x00 1. " AXR_1 ,Determines drive on AXR1 output pin" "Low,High" bitfld.long 0x00 0. " AXR_0 ,Determines drive on AXR0 output pin" "Low,High" group.long 0x01C++0x03 line.long 0x00 "MCASP_PDIN,Pin Data Input Register" bitfld.long 0x00 31. " AFSR ,Logic level on AFSR pin" "Low,High" bitfld.long 0x00 30. " AHCLKR ,Logic level on AHCLKR pin" "Low,High" bitfld.long 0x00 29. " ACLKR ,Logic level on ACLKR pin" "Low,High" bitfld.long 0x00 28. " AFSX ,Logic level on AFSX pin" "Low,High" textline " " bitfld.long 0x00 27. " AHCLKX ,Logic level on AHCLKX pin" "Low,High" bitfld.long 0x00 26. " ACLKX ,Logic level on ACLKX pin" "Low,High" bitfld.long 0x00 25. " AMUTE ,Logic level on AMUTE pin" "Low,High" textline " " bitfld.long 0x00 3. " AXR_3 ,Logic level on AXR3 pin" "Low,High" bitfld.long 0x00 2. " AXR_2 ,Logic level on AXR2 pin" "Low,High" bitfld.long 0x00 1. " AXR_1 ,Logic level on AXR1 pin" "Low,High" bitfld.long 0x00 0. " AXR_0 ,Logic level on AXR0 pin" "Low,High" group.long 0x020++0x03 line.long 0x00 "MCASP_PDCLR,Pin Data Clear Register" bitfld.long 0x00 31. " AFSR ,Clear AFSR pin" "No effect,Clear" bitfld.long 0x00 30. " AHCLKR ,Clear AHCLKR pin" "No effect,Clear" bitfld.long 0x00 29. " ACLKR ,Clear ACLKR pin" "No effect,Clear" bitfld.long 0x00 28. " AFSX ,Clear AFSX pin" "No effect,Clear" textline " " bitfld.long 0x00 27. " AHCLKX ,Clear AHCLKX pin" "No effect,Clear" bitfld.long 0x00 26. " ACLKX ,Clear ACLKX pin" "No effect,Clear" bitfld.long 0x00 25. " AMUTE ,Clear AMUTE pin" "No effect,Clear" textline " " bitfld.long 0x00 3. " AXR_3 ,Clear AXR3 pin" "No effect,Clear" bitfld.long 0x00 2. " AXR_2 ,Clear AXR2 pin" "No effect,Clear" bitfld.long 0x00 1. " AXR_1 ,Clear AXR1 pin" "No effect,Clear" bitfld.long 0x00 0. " AXR_0 ,Clear AXR0 pin" "No effect,Clear" group.long 0x044++0x03 line.long 0x00 "MCASP_GBLCTL,Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable bit" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable bit" "Reset,No reset" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable bit" "Cleared,Active" bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "Reset,Running" textline " " bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable bit" "Reset,Running" bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable bit" "Reset,Active" bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable bit" "Reset,No reset" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable bit" "Cleared,Active" textline " " bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit" "Reset,Running" bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable bit" "Reset,Running" group.long 0x048++0x03 line.long 0x00 "MCASP_AMUTE,Audio Mute Control Register" bitfld.long 0x00 12. " XDMAERR ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 11. " RDMAERR ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 10. " XCKFAIL ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 9. " RCKFAIL ,Drive AMUTE active enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " XSYNCERR ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 7. " RSYNCERR ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " XUNDRN ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 5. " ROVRN ,Drive AMUTE active enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " INSTAT ,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "Inactive,Active" bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled" bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select bit" "Active high,Active low" bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable bit" "Disabled,High,Low," if (((d.l(ad:0x48038000+0x04C))&0x01)==0x01) //this.DLBEN== "YES" group.long 0x04C++0x03 line.long 0x00 "MCASP_DLBCTL,Digital Loopback Control Register" bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode bits" "Default,Both sections,," bitfld.long 0x00 1. " ORD ,Loopback order bit" "Odd,Even" bitfld.long 0x00 0. " DLBEN ,Loopback mode enable bit" "Disabled,Enabled" else group.long 0x04C++0x03 line.long 0x00 "MCASP_DLBCTL,Digital Loopback Control Register" bitfld.long 0x00 0. " DLBEN ,Loopback mode enable bit" "Disabled,Enabled" endif group.long 0x050++0x03 line.long 0x00 "MCASP_DITCTL,DIT Mode Control Register" bitfld.long 0x00 3. " VB ,Valid bit for odd time slots (DIT right subframe)" "0,1" bitfld.long 0x00 2. " VA ,Valid bit for even time slots (DIT left subframe)" "0,1" bitfld.long 0x00 0. " DITEN ,DIT mode enable bit" "Disabled,Enabled" group.long 0x060++0x03 line.long 0x00 "MCASP_RGBLCTL,Receiver Global Control Register" rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable bit" "Disabled,Enabled" rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "Disabled,Enabled" textline " " rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable bit" "Reset,Active" bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable bit" "Reset,No reset" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable bit" "Cleared,Active" textline " " bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit" "Reset,Running" bitfld.long 0x00 0. " RCLKRST ,Receive clock divider reset enable bit" "Reset,Running" group.long 0x064++0x03 line.long 0x00 "MCASP_RMASK,Receive Format Unit Bit Mask Register" bitfld.long 0x00 31. " RMASK_31 ,Receive data mask 31 enable bit" "Masked,Returned" bitfld.long 0x00 30. " RMASK_30 ,Receive data mask 30 enable bit" "Masked,Returned" bitfld.long 0x00 29. " RMASK_29 ,Receive data mask 29 enable bit" "Masked,Returned" bitfld.long 0x00 28. " RMASK_28 ,Receive data mask 28 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 27. " RMASK_27 ,Receive data mask 27 enable bit" "Masked,Returned" bitfld.long 0x00 26. " RMASK_26 ,Receive data mask 26 enable bit" "Masked,Returned" bitfld.long 0x00 25. " RMASK_25 ,Receive data mask 25 enable bit" "Masked,Returned" bitfld.long 0x00 24. " RMASK_24 ,Receive data mask 24 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 23. " RMASK_23 ,Receive data mask 23 enable bit" "Masked,Returned" bitfld.long 0x00 22. " RMASK_22 ,Receive data mask 22 enable bit" "Masked,Returned" bitfld.long 0x00 21. " RMASK_21 ,Receive data mask 21 enable bit" "Masked,Returned" bitfld.long 0x00 20. " RMASK_20 ,Receive data mask 20 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 19. " RMASK_19 ,Receive data mask 19 enable bit" "Masked,Returned" bitfld.long 0x00 18. " RMASK_18 ,Receive data mask 18 enable bit" "Masked,Returned" bitfld.long 0x00 17. " RMASK_17 ,Receive data mask 17 enable bit" "Masked,Returned" bitfld.long 0x00 16. " RMASK_16 ,Receive data mask 16 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 15. " RMASK_15 ,Receive data mask 15 enable bit" "Masked,Returned" bitfld.long 0x00 14. " RMASK_14 ,Receive data mask 14 enable bit" "Masked,Returned" bitfld.long 0x00 13. " RMASK_13 ,Receive data mask 13 enable bit" "Masked,Returned" bitfld.long 0x00 12. " RMASK_12 ,Receive data mask 12 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 11. " RMASK_11 ,Receive data mask 11 enable bit" "Masked,Returned" bitfld.long 0x00 10. " RMASK_10 ,Receive data mask 10 enable bit" "Masked,Returned" bitfld.long 0x00 9. " RMASK_9 ,Receive data mask 9 enable bit" "Masked,Returned" bitfld.long 0x00 8. " RMASK_8 ,Receive data mask 8 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 7. " RMASK_7 ,Receive data mask 7 enable bit" "Masked,Returned" bitfld.long 0x00 6. " RMASK_6 ,Receive data mask 6 enable bit" "Masked,Returned" bitfld.long 0x00 5. " RMASK_5 ,Receive data mask 5 enable bit" "Masked,Returned" bitfld.long 0x00 4. " RMASK_4 ,Receive data mask 4 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 3. " RMASK_3 ,Receive data mask 3 enable bit" "Masked,Returned" bitfld.long 0x00 2. " RMASK_2 ,Receive data mask 2 enable bit" "Masked,Returned" bitfld.long 0x00 1. " RMASK_1 ,Receive data mask 1 enable bit" "Masked,Returned" bitfld.long 0x00 0. " RMASK_0 ,Receive data mask 0 enable bit" "Masked,Returned" group.long 0x068++0x03 line.long 0x00 "MCASP_RFMT,Receive Bit Stream Format Register" bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit," bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " RPAD , Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT," bitfld.long 0x00 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU or DMA from RBUF[n]) is used to pad the extra bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" ",,,8,,12,,16,,20,,24,,28,,32" bitfld.long 0x00 3. " RBUSEL ,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "Data port,Conf. bus" bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0,4,8,12,16,20,24,28" group.long 0x06C++0x03 line.long 0x00 "MCASP_AFSRCTL,Receive Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select bits" bitfld.long 0x00 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "Single bit,Single word" bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select bit" "Externally-generated,Internally-generated" bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select bit" "Rising edge,Failing edge" group.long 0x070++0x03 line.long 0x00 "MCASP_ACLKRCTL,Receive Clock Control Register" bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select bit" "Failing edge,Rising edge" bitfld.long 0x00 5. " CLKRM ,Receive bit clock source bit" "External,Internal" bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x074++0x03 line.long 0x00 "MCASP_AHCLKRCTL,Receive High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source bit" "External,Internal" bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0x078++0x03 line.long 0x00 "MCASP_RTDM,Receive TDM Time Slot 0-31 Register" bitfld.long 0x00 31. " RTDMS_31 ,Receiver mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " RTDMS_30 ,Receiver mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " RTDMS_29 ,Receiver mode during TDM time slot 29" "Inactive,Active" bitfld.long 0x00 28. " RTDMS_28 ,Receiver mode during TDM time slot 28" "Inactive,Active" textline " " bitfld.long 0x00 27. " RTDMS_27 ,Receiver mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " RTDMS_26 ,Receiver mode during TDM time slot 26" "Inactive,Active" bitfld.long 0x00 25. " RTDMS_25 ,Receiver mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " RTDMS_24 ,Receiver mode during TDM time slot 24" "Inactive,Active" textline " " bitfld.long 0x00 23. " RTDMS_23 ,Receiver mode during TDM time slot 23" "Inactive,Active" bitfld.long 0x00 22. " RTDMS_22 ,Receiver mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " RTDMS_21 ,Receiver mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " RTDMS_20 ,Receiver mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " RTDMS_19 ,Receiver mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " RTDMS_18 ,Receiver mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " RTDMS_17 ,Receiver mode during TDM time slot 17" "Inactive,Active" bitfld.long 0x00 16. " RTDMS_16 ,Receiver mode during TDM time slot 16" "Inactive,Active" textline " " bitfld.long 0x00 15. " RTDMS_15 ,Receiver mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " RTDMS_14 ,Receiver mode during TDM time slot 14" "Inactive,Active" bitfld.long 0x00 13. " RTDMS_13 ,Receiver mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " RTDMS_12 ,Receiver mode during TDM time slot 12" "Inactive,Active" textline " " bitfld.long 0x00 11. " RTDMS_11 ,Receiver mode during TDM time slot 11" "Inactive,Active" bitfld.long 0x00 10. " RTDMS_10 ,Receiver mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " RTDMS_9 ,Receiver mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " RTDMS_8 ,Receiver mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " RTDMS_7 ,Receiver mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " RTDMS_6 ,Receiver mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " RTDMS_5 ,Receiver mode during TDM time slot 5" "Inactive,Active" bitfld.long 0x00 4. " RTDMS_4 ,Receiver mode during TDM time slot 4" "Inactive,Active" textline " " bitfld.long 0x00 3. " RTDMS_3 ,Receiver mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " RTDMS_2 ,Receiver mode during TDM time slot 2" "Inactive,Active" bitfld.long 0x00 1. " RTDMS_1 ,Receiver mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " RTDMS_0 ,Receiver mode during TDM time slot 0" "Inactive,Active" group.long 0x07C++0x03 line.long 0x00 "MCASP_RINTCTL,Receiver Interrupt Control Register" bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable bit" "Disabled,Enabled" group.long 0x080++0x03 line.long 0x00 "MCASP_RSTAT,Receiver Status Register" bitfld.long 0x00 8. " RERR ,Logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "Not occurred,Occurred" eventfld.long 0x00 7. " RDMAERR ,Receive DMA error flag" "Not occurred,Occurred" eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "No new frame,New frame" eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No new data,Data transfered" textline " " eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last" rbitfld.long 0x00 3. " RTDMSLOT ,Returns the LSB of RSLOT" "Odd,Even" eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure flag" "Not occurred,Occurred" eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " ROVRN ,Receiver overrun flag" "Not occurred,Occurred" rgroup.long 0x084++0x03 line.long 0x00 "MCASP_RSLOT,Current Receive TDM Time Slot Register" hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count" group.long 0x088++0x03 line.long 0x00 "MCASP_RCLKCHK,Receive Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary" hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary" bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,,,,,,," group.long 0x08C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA Event Control Register" bitfld.long 0x00 0. " RDATDMA ,Receive data DMA request enable bit" "Enabled," group.long 0x0A0++0x03 line.long 0x00 "MCASP_XGBLCTL,Transmitter Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable bit" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable bit" "Reset,No reset" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable bit" "Cleared,Active" bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "Reset,Running" textline " " bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable bit" "Reset,Running" rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable bit" "Disabled,Enabled" textline " " rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " RCLKRST ,Receive clock divider reset enable bit" "Disabled,Enabled" group.long 0x0A4++0x03 line.long 0x00 "MCASP_XMASK,Transmit Format Unit Bit Mask Register" bitfld.long 0x00 31. " XMASK_31 ,Transmit data mask n enable bit_31" "Masked,Transmitted" bitfld.long 0x00 30. " XMASK_30 ,Transmit data mask n enable bit_30" "Masked,Transmitted" bitfld.long 0x00 29. " XMASK_29 ,Transmit data mask n enable bit_29" "Masked,Transmitted" bitfld.long 0x00 28. " XMASK_28 ,Transmit data mask n enable bit_28" "Masked,Transmitted" textline " " bitfld.long 0x00 27. " XMASK_27 ,Transmit data mask n enable bit_27" "Masked,Transmitted" bitfld.long 0x00 26. " XMASK_26 ,Transmit data mask n enable bit_26" "Masked,Transmitted" bitfld.long 0x00 25. " XMASK_25 ,Transmit data mask n enable bit_25" "Masked,Transmitted" bitfld.long 0x00 24. " XMASK_24 ,Transmit data mask n enable bit_24" "Masked,Transmitted" textline " " bitfld.long 0x00 23. " XMASK_23 ,Transmit data mask n enable bit_23" "Masked,Transmitted" bitfld.long 0x00 22. " XMASK_22 ,Transmit data mask n enable bit_22" "Masked,Transmitted" bitfld.long 0x00 21. " XMASK_21 ,Transmit data mask n enable bit_21" "Masked,Transmitted" bitfld.long 0x00 20. " XMASK_20 ,Transmit data mask n enable bit_20" "Masked,Transmitted" textline " " bitfld.long 0x00 19. " XMASK_19 ,Transmit data mask n enable bit_19" "Masked,Transmitted" bitfld.long 0x00 18. " XMASK_18 ,Transmit data mask n enable bit_18" "Masked,Transmitted" bitfld.long 0x00 17. " XMASK_17 ,Transmit data mask n enable bit_17" "Masked,Transmitted" bitfld.long 0x00 16. " XMASK_16 ,Transmit data mask n enable bit_16" "Masked,Transmitted" textline " " bitfld.long 0x00 15. " XMASK_15 ,Transmit data mask n enable bit_15" "Masked,Transmitted" bitfld.long 0x00 14. " XMASK_14 ,Transmit data mask n enable bit_14" "Masked,Transmitted" bitfld.long 0x00 13. " XMASK_13 ,Transmit data mask n enable bit_13" "Masked,Transmitted" bitfld.long 0x00 12. " XMASK_12 ,Transmit data mask n enable bit_12" "Masked,Transmitted" textline " " bitfld.long 0x00 11. " XMASK_11 ,Transmit data mask n enable bit_11" "Masked,Transmitted" bitfld.long 0x00 10. " XMASK_10 ,Transmit data mask n enable bit_10" "Masked,Transmitted" bitfld.long 0x00 9. " XMASK_9 ,Transmit data mask n enable bit_9" "Masked,Transmitted" bitfld.long 0x00 8. " XMASK_8 ,Transmit data mask n enable bit_8" "Masked,Transmitted" textline " " bitfld.long 0x00 7. " XMASK_7 ,Transmit data mask n enable bit_7" "Masked,Transmitted" bitfld.long 0x00 6. " XMASK_6 ,Transmit data mask n enable bit_6" "Masked,Transmitted" bitfld.long 0x00 5. " XMASK_5 ,Transmit data mask n enable bit_5" "Masked,Transmitted" bitfld.long 0x00 4. " XMASK_4 ,Transmit data mask n enable bit_4" "Masked,Transmitted" textline " " bitfld.long 0x00 3. " XMASK_3 ,Transmit data mask n enable bit_3" "Masked,Transmitted" bitfld.long 0x00 2. " XMASK_2 ,Transmit data mask n enable bit_2" "Masked,Transmitted" bitfld.long 0x00 1. " XMASK_1 ,Transmit data mask n enable bit_1" "Masked,Transmitted" bitfld.long 0x00 0. " XMASK_0 ,Transmit data mask n enable bit_0" "Masked,Transmitted" group.long 0x0A8++0x03 line.long 0x00 "MCASP_XFMT,Transmit Bit Stream Format Register" bitfld.long 0x00 16.--17. " XDATDLY ,Transmit sync bit delay" "0-bit,1-bit,2-bit," bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK" "0,1,XPBIT," bitfld.long 0x00 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" ",,,8,,12,,16,,20,,24,,28,,32" bitfld.long 0x00 3. " XBUSEL ,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "Data port,Conf. bus" bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,4,8,12,16,20,24,28" group.long 0x0AC++0x03 line.long 0x00 "MCASP_AFSXCTL,Transmit Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select bits" bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period" "Single bit,Single word" bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select bit" "Externally,Internally" bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select bit" "Rising edge,Failing edge" group.long 0x0B0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit Clock Control Register" bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select bit" "Rising edge,Falling edge" bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable bit" "Synchronous,Asynchronous" bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source bit" "External,Internal" bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x0B4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,Transmit High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source bit" "External,Internal" bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX" group.long 0x0B8++0x03 line.long 0x00 "MCASP_XTDM,Transmit TDM Time Slot 0-31 Register" bitfld.long 0x00 31. " XTDMS_31 ,Transmitter mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " XTDMS_30 ,Transmitter mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " XTDMS_29 ,Transmitter mode during TDM time slot 29" "Inactive,Active" bitfld.long 0x00 28. " XTDMS_28 ,Transmitter mode during TDM time slot 28" "Inactive,Active" textline " " bitfld.long 0x00 27. " XTDMS_27 ,Transmitter mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " XTDMS_26 ,Transmitter mode during TDM time slot 26" "Inactive,Active" bitfld.long 0x00 25. " XTDMS_25 ,Transmitter mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " XTDMS_24 ,Transmitter mode during TDM time slot 24" "Inactive,Active" textline " " bitfld.long 0x00 23. " XTDMS_23 ,Transmitter mode during TDM time slot 23" "Inactive,Active" bitfld.long 0x00 22. " XTDMS_22 ,Transmitter mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " XTDMS_21 ,Transmitter mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " XTDMS_20 ,Transmitter mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " XTDMS_19 ,Transmitter mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " XTDMS_18 ,Transmitter mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " XTDMS_17 ,Transmitter mode during TDM time slot 17" "Inactive,Active" bitfld.long 0x00 16. " XTDMS_16 ,Transmitter mode during TDM time slot 16" "Inactive,Active" textline " " bitfld.long 0x00 15. " XTDMS_15 ,Transmitter mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " XTDMS_14 ,Transmitter mode during TDM time slot 14" "Inactive,Active" bitfld.long 0x00 13. " XTDMS_13 ,Transmitter mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " XTDMS_12 ,Transmitter mode during TDM time slot 12" "Inactive,Active" textline " " bitfld.long 0x00 11. " XTDMS_11 ,Transmitter mode during TDM time slot 11" "Inactive,Active" bitfld.long 0x00 10. " XTDMS_10 ,Transmitter mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " XTDMS_9 ,Transmitter mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " XTDMS_8 ,Transmitter mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " XTDMS_7 ,Transmitter mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " XTDMS_6 ,Transmitter mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " XTDMS_5 ,Transmitter mode during TDM time slot 5" "Inactive,Active" bitfld.long 0x00 4. " XTDMS_4 ,Transmitter mode during TDM time slot 4" "Inactive,Active" textline " " bitfld.long 0x00 3. " XTDMS_3 ,Transmitter mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " XTDMS_2 ,Transmitter mode during TDM time slot 2" "Inactive,Active" bitfld.long 0x00 1. " XTDMS_1 ,Transmitter mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " XTDMS_0 ,Transmitter mode during TDM time slot 0" "Inactive,Active" group.long 0x0BC++0x03 line.long 0x00 "MCASP_XINTCTL,Transmitter Interrupt Control Register" bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "Disabled,Enabled" group.long 0x0C0++0x03 line.long 0x00 "MCASP_XSTAT,Transmitter Status Register" bitfld.long 0x00 8. " XERR ,Logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "Not occurred,Occurred" eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error flag" "Not occurred,Occurred" eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "No new frame,New fame" eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "Not ready,Ready" textline " " eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last" rbitfld.long 0x00 3. " XTDMSLOT ,Returns the LSB of XSLOT" "Odd,Even" eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure flag" "Not occurred,Occurred" eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun flag" "Not occurred,Occurred" rgroup.long 0x0C4++0x03 line.long 0x00 "MCASP_XSLOT,Current Transmit TDM Time Slot Register" hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count" group.long 0x0C8++0x03 line.long 0x00 "MCASP_XCLKCHK,Transmit Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " XCNT , Transmit clock count value" hexmask.long.byte 0x00 16.--23. 1. " XMAX , Transmit clock maximum boundary" hexmask.long.byte 0x00 8.--15. 1. " XMIN , Transmit clock minimum boundary" bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,,,,,,," group.long 0x0CC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA Event Control Register" bitfld.long 0x00 0. " XDATDMA ,Transmit data DMA request enable bit" "Enabled," width 18. tree "MCASP_DITCSRA - array[6]" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRA[0],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRA[1],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRA[2],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRA[3],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRA[4],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRA[5],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." tree.end tree "MCASP_DITCSRB - array[6]" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRB[0],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRB[1],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRB[2],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRB[3],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRB[4],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRB[5],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." tree.end tree "MCASP_DITUDRA - array[6]" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRA[0],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRA[1],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRA[2],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRA[3],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRA[4],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRA[5],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." tree.end tree "MCASP_DITUDRB - array[6]" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRB[0],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRB[1],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRB[2],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRB[3],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRB[4],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRB[5],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." tree.end width 16. tree "MCASP_SRCTL - array[6]" group.long 0x180++0x03 line.long 0x00 "MCASP_SRCTL[0],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x184++0x03 line.long 0x00 "MCASP_SRCTL[1],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x188++0x03 line.long 0x00 "MCASP_SRCTL[2],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x18C++0x03 line.long 0x00 "MCASP_SRCTL[3],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x190++0x03 line.long 0x00 "MCASP_SRCTL[4],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x194++0x03 line.long 0x00 "MCASP_SRCTL[5],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," tree.end width 15. tree "MCASP_XBUF - array[6]" group.long 0x200++0x03 line.long 0x00 "MCASP_XBUF[0],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x204++0x03 line.long 0x00 "MCASP_XBUF[1],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x208++0x03 line.long 0x00 "MCASP_XBUF[2],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x20C++0x03 line.long 0x00 "MCASP_XBUF[3],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x210++0x03 line.long 0x00 "MCASP_XBUF[4],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x214++0x03 line.long 0x00 "MCASP_XBUF[5],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." tree.end tree "MCASP_RBUF - array[6]" group.long 0x280++0x03 line.long 0x00 "MCASP_RBUF[0],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x284++0x03 line.long 0x00 "MCASP_RBUF[1],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x288++0x03 line.long 0x00 "MCASP_RBUF[2],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x28C++0x03 line.long 0x00 "MCASP_RBUF[3],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x290++0x03 line.long 0x00 "MCASP_RBUF[4],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x294++0x03 line.long 0x00 "MCASP_RBUF[5],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." tree.end textline " " width 16. group.long 0x1000++0x03 line.long 0x00 "MCASP_WFIFOCTL,Write FIFO Control Register" bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event" hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer" rgroup.long 0x1004++0x03 line.long 0x00 "MCASP_WFIFOSTS,Write FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level" group.long 0x1008++0x03 line.long 0x00 "MCASP_RFIFOCTL,Read FIFO Control Register" bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event" hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer" rgroup.long 0x100C++0x03 line.long 0x00 "MCASP_RFIFOSTS,Read FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level" width 11. tree.end tree "MCASP1" base ad:0x4803C000 width 24. rgroup.long 0x000++0x03 line.long 0x00 "MCASP_REV,Revision Identification Register" hexmask.long 0x00 0.--31. 1. " REV , Identifies revision of peripheral." group.long 0x004++0x03 line.long 0x00 "MCASP_PWRIDLESYSCONFIG,Power Idle SYSCONFIG Register" bitfld.long 0x00 0.--1. " IDLEMODE ,Power management Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle," group.long 0x010++0x03 line.long 0x00 "MCASP_PFUNC,Pin Function Register" bitfld.long 0x00 31. " AFSR ,Determines if AFSR pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 30. " AHCLKR ,Determines if AHCLKR pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 29. " ACLKR ,Determines if ACLKR pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 28. " AFSX ,Determines if AFSX pin functions as McASP or GPIO" "McASP,GPIO" textline " " bitfld.long 0x00 27. " AHCLKX ,Determines if AHCLKX pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 26. " ACLKX ,Determines if ACLKX pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 25. " AMUTE ,Determines if AMUTE pin functions as McASP or GPIO" "McASP,GPIO" textline " " bitfld.long 0x00 3. " AXR_3 ,Determines if AXR3 pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 2. " AXR_2 ,Determines if AXR2 pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 1. " AXR_1 ,Determines if AXR1 pin functions as McASP or GPIO" "McASP,GPIO" bitfld.long 0x00 0. " AXR_0 ,Determines if AXR0 pin functions as McASP or GPIO" "McASP,GPIO" group.long 0x014++0x03 line.long 0x00 "MCASP_PDIR,Pin Direction Register" bitfld.long 0x00 31. " AFSR ,Determines if AFSR pin functions as an input or output" "Input,Output" bitfld.long 0x00 30. " AHCLKR ,Determines if AHCLKR pin functions as an input or output" "Input,Output" bitfld.long 0x00 29. " ACLKR ,Determines if ACLKR pin functions as an input or output" "Input,Output" bitfld.long 0x00 28. " AFSX ,Determines if AFSX pin functions as an input or output" "Input,Output" textline " " bitfld.long 0x00 27. " AHCLKX ,Determines if AHCLKX pin functions as an input or output" "Input,Output" bitfld.long 0x00 26. " ACLKX ,Determines if ACLKX pin functions as an input or output" "Input,Output" bitfld.long 0x00 25. " AMUTE ,Determines if AMUTE pin functions as an input or output" "Input,Output" textline " " bitfld.long 0x00 3. " AXR_3 ,Determines if AXR3 pin functions as an input or output" "Input,Output" bitfld.long 0x00 2. " AXR_2 ,Determines if AXR2 pin functions as an input or output" "Input,Output" bitfld.long 0x00 1. " AXR_1 ,Determines if AXR1 pin functions as an input or output" "Input,Output" bitfld.long 0x00 0. " AXR_0 ,Determines if AXRn pin functions as an input or output" "Input,Output" group.long 0x018++0x03 line.long 0x00 "MCASP_PDOUT,Pin Data Output Register" bitfld.long 0x00 31. " AFSR ,Determines drive on AFSR output pin" "Low,High" bitfld.long 0x00 30. " AHCLKR ,Determines drive on AHCLKR output pin" "Low,High" bitfld.long 0x00 29. " ACLKR ,Determines drive on ACLKR output pin" "Low,High" bitfld.long 0x00 28. " AFSX ,Determines drive on AFSX output pin" "Low,High" textline " " bitfld.long 0x00 27. " AHCLKX ,Determines drive on AHCLKX output pin" "Low,High" bitfld.long 0x00 26. " ACLKX ,Determines drive on ACLKX output pin" "Low,High" bitfld.long 0x00 25. " AMUTE ,Determines drive on AMUTE output pin" "Low,High" textline " " bitfld.long 0x00 3. " AXR_3 ,Determines drive on AXR3 output pin" "Low,High" bitfld.long 0x00 2. " AXR_2 ,Determines drive on AXR2 output pin" "Low,High" bitfld.long 0x00 1. " AXR_1 ,Determines drive on AXR1 output pin" "Low,High" bitfld.long 0x00 0. " AXR_0 ,Determines drive on AXR0 output pin" "Low,High" group.long 0x01C++0x03 line.long 0x00 "MCASP_PDIN,Pin Data Input Register" bitfld.long 0x00 31. " AFSR ,Logic level on AFSR pin" "Low,High" bitfld.long 0x00 30. " AHCLKR ,Logic level on AHCLKR pin" "Low,High" bitfld.long 0x00 29. " ACLKR ,Logic level on ACLKR pin" "Low,High" bitfld.long 0x00 28. " AFSX ,Logic level on AFSX pin" "Low,High" textline " " bitfld.long 0x00 27. " AHCLKX ,Logic level on AHCLKX pin" "Low,High" bitfld.long 0x00 26. " ACLKX ,Logic level on ACLKX pin" "Low,High" bitfld.long 0x00 25. " AMUTE ,Logic level on AMUTE pin" "Low,High" textline " " bitfld.long 0x00 3. " AXR_3 ,Logic level on AXR3 pin" "Low,High" bitfld.long 0x00 2. " AXR_2 ,Logic level on AXR2 pin" "Low,High" bitfld.long 0x00 1. " AXR_1 ,Logic level on AXR1 pin" "Low,High" bitfld.long 0x00 0. " AXR_0 ,Logic level on AXR0 pin" "Low,High" group.long 0x020++0x03 line.long 0x00 "MCASP_PDCLR,Pin Data Clear Register" bitfld.long 0x00 31. " AFSR ,Clear AFSR pin" "No effect,Clear" bitfld.long 0x00 30. " AHCLKR ,Clear AHCLKR pin" "No effect,Clear" bitfld.long 0x00 29. " ACLKR ,Clear ACLKR pin" "No effect,Clear" bitfld.long 0x00 28. " AFSX ,Clear AFSX pin" "No effect,Clear" textline " " bitfld.long 0x00 27. " AHCLKX ,Clear AHCLKX pin" "No effect,Clear" bitfld.long 0x00 26. " ACLKX ,Clear ACLKX pin" "No effect,Clear" bitfld.long 0x00 25. " AMUTE ,Clear AMUTE pin" "No effect,Clear" textline " " bitfld.long 0x00 3. " AXR_3 ,Clear AXR3 pin" "No effect,Clear" bitfld.long 0x00 2. " AXR_2 ,Clear AXR2 pin" "No effect,Clear" bitfld.long 0x00 1. " AXR_1 ,Clear AXR1 pin" "No effect,Clear" bitfld.long 0x00 0. " AXR_0 ,Clear AXR0 pin" "No effect,Clear" group.long 0x044++0x03 line.long 0x00 "MCASP_GBLCTL,Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable bit" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable bit" "Reset,No reset" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable bit" "Cleared,Active" bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "Reset,Running" textline " " bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable bit" "Reset,Running" bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable bit" "Reset,Active" bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable bit" "Reset,No reset" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable bit" "Cleared,Active" textline " " bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit" "Reset,Running" bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable bit" "Reset,Running" group.long 0x048++0x03 line.long 0x00 "MCASP_AMUTE,Audio Mute Control Register" bitfld.long 0x00 12. " XDMAERR ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 11. " RDMAERR ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 10. " XCKFAIL ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 9. " RCKFAIL ,Drive AMUTE active enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " XSYNCERR ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 7. " RSYNCERR ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " XUNDRN ,Drive AMUTE active enable bit" "Disabled,Enabled" bitfld.long 0x00 5. " ROVRN ,Drive AMUTE active enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " INSTAT ,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "Inactive,Active" bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled" bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select bit" "Active high,Active low" bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable bit" "Disabled,High,Low," if (((d.l(ad:0x4803C000+0x04C))&0x01)==0x01) //this.DLBEN== "YES" group.long 0x04C++0x03 line.long 0x00 "MCASP_DLBCTL,Digital Loopback Control Register" bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode bits" "Default,Both sections,," bitfld.long 0x00 1. " ORD ,Loopback order bit" "Odd,Even" bitfld.long 0x00 0. " DLBEN ,Loopback mode enable bit" "Disabled,Enabled" else group.long 0x04C++0x03 line.long 0x00 "MCASP_DLBCTL,Digital Loopback Control Register" bitfld.long 0x00 0. " DLBEN ,Loopback mode enable bit" "Disabled,Enabled" endif group.long 0x050++0x03 line.long 0x00 "MCASP_DITCTL,DIT Mode Control Register" bitfld.long 0x00 3. " VB ,Valid bit for odd time slots (DIT right subframe)" "0,1" bitfld.long 0x00 2. " VA ,Valid bit for even time slots (DIT left subframe)" "0,1" bitfld.long 0x00 0. " DITEN ,DIT mode enable bit" "Disabled,Enabled" group.long 0x060++0x03 line.long 0x00 "MCASP_RGBLCTL,Receiver Global Control Register" rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable bit" "Disabled,Enabled" rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "Disabled,Enabled" textline " " rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable bit" "Reset,Active" bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable bit" "Reset,No reset" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable bit" "Cleared,Active" textline " " bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit" "Reset,Running" bitfld.long 0x00 0. " RCLKRST ,Receive clock divider reset enable bit" "Reset,Running" group.long 0x064++0x03 line.long 0x00 "MCASP_RMASK,Receive Format Unit Bit Mask Register" bitfld.long 0x00 31. " RMASK_31 ,Receive data mask 31 enable bit" "Masked,Returned" bitfld.long 0x00 30. " RMASK_30 ,Receive data mask 30 enable bit" "Masked,Returned" bitfld.long 0x00 29. " RMASK_29 ,Receive data mask 29 enable bit" "Masked,Returned" bitfld.long 0x00 28. " RMASK_28 ,Receive data mask 28 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 27. " RMASK_27 ,Receive data mask 27 enable bit" "Masked,Returned" bitfld.long 0x00 26. " RMASK_26 ,Receive data mask 26 enable bit" "Masked,Returned" bitfld.long 0x00 25. " RMASK_25 ,Receive data mask 25 enable bit" "Masked,Returned" bitfld.long 0x00 24. " RMASK_24 ,Receive data mask 24 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 23. " RMASK_23 ,Receive data mask 23 enable bit" "Masked,Returned" bitfld.long 0x00 22. " RMASK_22 ,Receive data mask 22 enable bit" "Masked,Returned" bitfld.long 0x00 21. " RMASK_21 ,Receive data mask 21 enable bit" "Masked,Returned" bitfld.long 0x00 20. " RMASK_20 ,Receive data mask 20 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 19. " RMASK_19 ,Receive data mask 19 enable bit" "Masked,Returned" bitfld.long 0x00 18. " RMASK_18 ,Receive data mask 18 enable bit" "Masked,Returned" bitfld.long 0x00 17. " RMASK_17 ,Receive data mask 17 enable bit" "Masked,Returned" bitfld.long 0x00 16. " RMASK_16 ,Receive data mask 16 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 15. " RMASK_15 ,Receive data mask 15 enable bit" "Masked,Returned" bitfld.long 0x00 14. " RMASK_14 ,Receive data mask 14 enable bit" "Masked,Returned" bitfld.long 0x00 13. " RMASK_13 ,Receive data mask 13 enable bit" "Masked,Returned" bitfld.long 0x00 12. " RMASK_12 ,Receive data mask 12 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 11. " RMASK_11 ,Receive data mask 11 enable bit" "Masked,Returned" bitfld.long 0x00 10. " RMASK_10 ,Receive data mask 10 enable bit" "Masked,Returned" bitfld.long 0x00 9. " RMASK_9 ,Receive data mask 9 enable bit" "Masked,Returned" bitfld.long 0x00 8. " RMASK_8 ,Receive data mask 8 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 7. " RMASK_7 ,Receive data mask 7 enable bit" "Masked,Returned" bitfld.long 0x00 6. " RMASK_6 ,Receive data mask 6 enable bit" "Masked,Returned" bitfld.long 0x00 5. " RMASK_5 ,Receive data mask 5 enable bit" "Masked,Returned" bitfld.long 0x00 4. " RMASK_4 ,Receive data mask 4 enable bit" "Masked,Returned" textline " " bitfld.long 0x00 3. " RMASK_3 ,Receive data mask 3 enable bit" "Masked,Returned" bitfld.long 0x00 2. " RMASK_2 ,Receive data mask 2 enable bit" "Masked,Returned" bitfld.long 0x00 1. " RMASK_1 ,Receive data mask 1 enable bit" "Masked,Returned" bitfld.long 0x00 0. " RMASK_0 ,Receive data mask 0 enable bit" "Masked,Returned" group.long 0x068++0x03 line.long 0x00 "MCASP_RFMT,Receive Bit Stream Format Register" bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit," bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " RPAD , Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT," bitfld.long 0x00 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU or DMA from RBUF[n]) is used to pad the extra bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" ",,,8,,12,,16,,20,,24,,28,,32" bitfld.long 0x00 3. " RBUSEL ,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "Data port,Conf. bus" bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0,4,8,12,16,20,24,28" group.long 0x06C++0x03 line.long 0x00 "MCASP_AFSRCTL,Receive Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select bits" bitfld.long 0x00 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period" "Single bit,Single word" bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select bit" "Externally-generated,Internally-generated" bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select bit" "Rising edge,Failing edge" group.long 0x070++0x03 line.long 0x00 "MCASP_ACLKRCTL,Receive Clock Control Register" bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select bit" "Failing edge,Rising edge" bitfld.long 0x00 5. " CLKRM ,Receive bit clock source bit" "External,Internal" bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x074++0x03 line.long 0x00 "MCASP_AHCLKRCTL,Receive High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source bit" "External,Internal" bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR" group.long 0x078++0x03 line.long 0x00 "MCASP_RTDM,Receive TDM Time Slot 0-31 Register" bitfld.long 0x00 31. " RTDMS_31 ,Receiver mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " RTDMS_30 ,Receiver mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " RTDMS_29 ,Receiver mode during TDM time slot 29" "Inactive,Active" bitfld.long 0x00 28. " RTDMS_28 ,Receiver mode during TDM time slot 28" "Inactive,Active" textline " " bitfld.long 0x00 27. " RTDMS_27 ,Receiver mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " RTDMS_26 ,Receiver mode during TDM time slot 26" "Inactive,Active" bitfld.long 0x00 25. " RTDMS_25 ,Receiver mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " RTDMS_24 ,Receiver mode during TDM time slot 24" "Inactive,Active" textline " " bitfld.long 0x00 23. " RTDMS_23 ,Receiver mode during TDM time slot 23" "Inactive,Active" bitfld.long 0x00 22. " RTDMS_22 ,Receiver mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " RTDMS_21 ,Receiver mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " RTDMS_20 ,Receiver mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " RTDMS_19 ,Receiver mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " RTDMS_18 ,Receiver mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " RTDMS_17 ,Receiver mode during TDM time slot 17" "Inactive,Active" bitfld.long 0x00 16. " RTDMS_16 ,Receiver mode during TDM time slot 16" "Inactive,Active" textline " " bitfld.long 0x00 15. " RTDMS_15 ,Receiver mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " RTDMS_14 ,Receiver mode during TDM time slot 14" "Inactive,Active" bitfld.long 0x00 13. " RTDMS_13 ,Receiver mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " RTDMS_12 ,Receiver mode during TDM time slot 12" "Inactive,Active" textline " " bitfld.long 0x00 11. " RTDMS_11 ,Receiver mode during TDM time slot 11" "Inactive,Active" bitfld.long 0x00 10. " RTDMS_10 ,Receiver mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " RTDMS_9 ,Receiver mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " RTDMS_8 ,Receiver mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " RTDMS_7 ,Receiver mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " RTDMS_6 ,Receiver mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " RTDMS_5 ,Receiver mode during TDM time slot 5" "Inactive,Active" bitfld.long 0x00 4. " RTDMS_4 ,Receiver mode during TDM time slot 4" "Inactive,Active" textline " " bitfld.long 0x00 3. " RTDMS_3 ,Receiver mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " RTDMS_2 ,Receiver mode during TDM time slot 2" "Inactive,Active" bitfld.long 0x00 1. " RTDMS_1 ,Receiver mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " RTDMS_0 ,Receiver mode during TDM time slot 0" "Inactive,Active" group.long 0x07C++0x03 line.long 0x00 "MCASP_RINTCTL,Receiver Interrupt Control Register" bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable bit" "Disabled,Enabled" group.long 0x080++0x03 line.long 0x00 "MCASP_RSTAT,Receiver Status Register" bitfld.long 0x00 8. " RERR ,Logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "Not occurred,Occurred" eventfld.long 0x00 7. " RDMAERR ,Receive DMA error flag" "Not occurred,Occurred" eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "No new frame,New frame" eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No new data,Data transfered" textline " " eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last" rbitfld.long 0x00 3. " RTDMSLOT ,Returns the LSB of RSLOT" "Odd,Even" eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure flag" "Not occurred,Occurred" eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " ROVRN ,Receiver overrun flag" "Not occurred,Occurred" rgroup.long 0x084++0x03 line.long 0x00 "MCASP_RSLOT,Current Receive TDM Time Slot Register" hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count" group.long 0x088++0x03 line.long 0x00 "MCASP_RCLKCHK,Receive Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value (from previous measurement)" hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary" hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary" bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,,,,,,," group.long 0x08C++0x03 line.long 0x00 "MCASP_REVTCTL,Receiver DMA Event Control Register" bitfld.long 0x00 0. " RDATDMA ,Receive data DMA request enable bit" "Enabled," group.long 0x0A0++0x03 line.long 0x00 "MCASP_XGBLCTL,Transmitter Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable bit" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable bit" "Reset,No reset" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable bit" "Cleared,Active" bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "Reset,Running" textline " " bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable bit" "Reset,Running" rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable bit" "Disabled,Enabled" textline " " rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit" "Disabled,Enabled" rbitfld.long 0x00 0. " RCLKRST ,Receive clock divider reset enable bit" "Disabled,Enabled" group.long 0x0A4++0x03 line.long 0x00 "MCASP_XMASK,Transmit Format Unit Bit Mask Register" bitfld.long 0x00 31. " XMASK_31 ,Transmit data mask n enable bit_31" "Masked,Transmitted" bitfld.long 0x00 30. " XMASK_30 ,Transmit data mask n enable bit_30" "Masked,Transmitted" bitfld.long 0x00 29. " XMASK_29 ,Transmit data mask n enable bit_29" "Masked,Transmitted" bitfld.long 0x00 28. " XMASK_28 ,Transmit data mask n enable bit_28" "Masked,Transmitted" textline " " bitfld.long 0x00 27. " XMASK_27 ,Transmit data mask n enable bit_27" "Masked,Transmitted" bitfld.long 0x00 26. " XMASK_26 ,Transmit data mask n enable bit_26" "Masked,Transmitted" bitfld.long 0x00 25. " XMASK_25 ,Transmit data mask n enable bit_25" "Masked,Transmitted" bitfld.long 0x00 24. " XMASK_24 ,Transmit data mask n enable bit_24" "Masked,Transmitted" textline " " bitfld.long 0x00 23. " XMASK_23 ,Transmit data mask n enable bit_23" "Masked,Transmitted" bitfld.long 0x00 22. " XMASK_22 ,Transmit data mask n enable bit_22" "Masked,Transmitted" bitfld.long 0x00 21. " XMASK_21 ,Transmit data mask n enable bit_21" "Masked,Transmitted" bitfld.long 0x00 20. " XMASK_20 ,Transmit data mask n enable bit_20" "Masked,Transmitted" textline " " bitfld.long 0x00 19. " XMASK_19 ,Transmit data mask n enable bit_19" "Masked,Transmitted" bitfld.long 0x00 18. " XMASK_18 ,Transmit data mask n enable bit_18" "Masked,Transmitted" bitfld.long 0x00 17. " XMASK_17 ,Transmit data mask n enable bit_17" "Masked,Transmitted" bitfld.long 0x00 16. " XMASK_16 ,Transmit data mask n enable bit_16" "Masked,Transmitted" textline " " bitfld.long 0x00 15. " XMASK_15 ,Transmit data mask n enable bit_15" "Masked,Transmitted" bitfld.long 0x00 14. " XMASK_14 ,Transmit data mask n enable bit_14" "Masked,Transmitted" bitfld.long 0x00 13. " XMASK_13 ,Transmit data mask n enable bit_13" "Masked,Transmitted" bitfld.long 0x00 12. " XMASK_12 ,Transmit data mask n enable bit_12" "Masked,Transmitted" textline " " bitfld.long 0x00 11. " XMASK_11 ,Transmit data mask n enable bit_11" "Masked,Transmitted" bitfld.long 0x00 10. " XMASK_10 ,Transmit data mask n enable bit_10" "Masked,Transmitted" bitfld.long 0x00 9. " XMASK_9 ,Transmit data mask n enable bit_9" "Masked,Transmitted" bitfld.long 0x00 8. " XMASK_8 ,Transmit data mask n enable bit_8" "Masked,Transmitted" textline " " bitfld.long 0x00 7. " XMASK_7 ,Transmit data mask n enable bit_7" "Masked,Transmitted" bitfld.long 0x00 6. " XMASK_6 ,Transmit data mask n enable bit_6" "Masked,Transmitted" bitfld.long 0x00 5. " XMASK_5 ,Transmit data mask n enable bit_5" "Masked,Transmitted" bitfld.long 0x00 4. " XMASK_4 ,Transmit data mask n enable bit_4" "Masked,Transmitted" textline " " bitfld.long 0x00 3. " XMASK_3 ,Transmit data mask n enable bit_3" "Masked,Transmitted" bitfld.long 0x00 2. " XMASK_2 ,Transmit data mask n enable bit_2" "Masked,Transmitted" bitfld.long 0x00 1. " XMASK_1 ,Transmit data mask n enable bit_1" "Masked,Transmitted" bitfld.long 0x00 0. " XMASK_0 ,Transmit data mask n enable bit_0" "Masked,Transmitted" group.long 0x0A8++0x03 line.long 0x00 "MCASP_XFMT,Transmit Bit Stream Format Register" bitfld.long 0x00 16.--17. " XDATDLY ,Transmit sync bit delay" "0-bit,1-bit,2-bit," bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK" "0,1,XPBIT," bitfld.long 0x00 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" ",,,8,,12,,16,,20,,24,,28,,32" bitfld.long 0x00 3. " XBUSEL ,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus (CFG) or the data (DAT) port" "Data port,Conf. bus" bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,4,8,12,16,20,24,28" group.long 0x0AC++0x03 line.long 0x00 "MCASP_AFSXCTL,Transmit Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select bits" bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period" "Single bit,Single word" bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select bit" "Externally,Internally" bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select bit" "Rising edge,Failing edge" group.long 0x0B0++0x03 line.long 0x00 "MCASP_ACLKXCTL,Transmit Clock Control Register" bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select bit" "Rising edge,Falling edge" bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable bit" "Synchronous,Asynchronous" bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source bit" "External,Internal" bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" group.long 0x0B4++0x03 line.long 0x00 "MCASP_AHCLKXCTL,Transmit High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source bit" "External,Internal" bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX" group.long 0x0B8++0x03 line.long 0x00 "MCASP_XTDM,Transmit TDM Time Slot 0-31 Register" bitfld.long 0x00 31. " XTDMS_31 ,Transmitter mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " XTDMS_30 ,Transmitter mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " XTDMS_29 ,Transmitter mode during TDM time slot 29" "Inactive,Active" bitfld.long 0x00 28. " XTDMS_28 ,Transmitter mode during TDM time slot 28" "Inactive,Active" textline " " bitfld.long 0x00 27. " XTDMS_27 ,Transmitter mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " XTDMS_26 ,Transmitter mode during TDM time slot 26" "Inactive,Active" bitfld.long 0x00 25. " XTDMS_25 ,Transmitter mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " XTDMS_24 ,Transmitter mode during TDM time slot 24" "Inactive,Active" textline " " bitfld.long 0x00 23. " XTDMS_23 ,Transmitter mode during TDM time slot 23" "Inactive,Active" bitfld.long 0x00 22. " XTDMS_22 ,Transmitter mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " XTDMS_21 ,Transmitter mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " XTDMS_20 ,Transmitter mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " XTDMS_19 ,Transmitter mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " XTDMS_18 ,Transmitter mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " XTDMS_17 ,Transmitter mode during TDM time slot 17" "Inactive,Active" bitfld.long 0x00 16. " XTDMS_16 ,Transmitter mode during TDM time slot 16" "Inactive,Active" textline " " bitfld.long 0x00 15. " XTDMS_15 ,Transmitter mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " XTDMS_14 ,Transmitter mode during TDM time slot 14" "Inactive,Active" bitfld.long 0x00 13. " XTDMS_13 ,Transmitter mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " XTDMS_12 ,Transmitter mode during TDM time slot 12" "Inactive,Active" textline " " bitfld.long 0x00 11. " XTDMS_11 ,Transmitter mode during TDM time slot 11" "Inactive,Active" bitfld.long 0x00 10. " XTDMS_10 ,Transmitter mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " XTDMS_9 ,Transmitter mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " XTDMS_8 ,Transmitter mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " XTDMS_7 ,Transmitter mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " XTDMS_6 ,Transmitter mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " XTDMS_5 ,Transmitter mode during TDM time slot 5" "Inactive,Active" bitfld.long 0x00 4. " XTDMS_4 ,Transmitter mode during TDM time slot 4" "Inactive,Active" textline " " bitfld.long 0x00 3. " XTDMS_3 ,Transmitter mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " XTDMS_2 ,Transmitter mode during TDM time slot 2" "Inactive,Active" bitfld.long 0x00 1. " XTDMS_1 ,Transmitter mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " XTDMS_0 ,Transmitter mode during TDM time slot 0" "Inactive,Active" group.long 0x0BC++0x03 line.long 0x00 "MCASP_XINTCTL,Transmitter Interrupt Control Register" bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "Disabled,Enabled" group.long 0x0C0++0x03 line.long 0x00 "MCASP_XSTAT,Transmitter Status Register" bitfld.long 0x00 8. " XERR ,Logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "Not occurred,Occurred" eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error flag" "Not occurred,Occurred" eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "No new frame,New fame" eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "Not ready,Ready" textline " " eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last" rbitfld.long 0x00 3. " XTDMSLOT ,Returns the LSB of XSLOT" "Odd,Even" eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure flag" "Not occurred,Occurred" eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun flag" "Not occurred,Occurred" rgroup.long 0x0C4++0x03 line.long 0x00 "MCASP_XSLOT,Current Transmit TDM Time Slot Register" hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count" group.long 0x0C8++0x03 line.long 0x00 "MCASP_XCLKCHK,Transmit Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " XCNT , Transmit clock count value" hexmask.long.byte 0x00 16.--23. 1. " XMAX , Transmit clock maximum boundary" hexmask.long.byte 0x00 8.--15. 1. " XMIN , Transmit clock minimum boundary" bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,,,,,,," group.long 0x0CC++0x03 line.long 0x00 "MCASP_XEVTCTL,Transmitter DMA Event Control Register" bitfld.long 0x00 0. " XDATDMA ,Transmit data DMA request enable bit" "Enabled," width 18. tree "MCASP_DITCSRA - array[6]" group.long 0x100++0x03 line.long 0x00 "MCASP_DITCSRA[0],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x104++0x03 line.long 0x00 "MCASP_DITCSRA[1],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x108++0x03 line.long 0x00 "MCASP_DITCSRA[2],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x10C++0x03 line.long 0x00 "MCASP_DITCSRA[3],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x110++0x03 line.long 0x00 "MCASP_DITCSRA[4],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." group.long 0x114++0x03 line.long 0x00 "MCASP_DITCSRA[5],Left (Even TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRA , DIT left channel status registers." tree.end tree "MCASP_DITCSRB - array[6]" group.long 0x118++0x03 line.long 0x00 "MCASP_DITCSRB[0],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x11C++0x03 line.long 0x00 "MCASP_DITCSRB[1],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x120++0x03 line.long 0x00 "MCASP_DITCSRB[2],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x124++0x03 line.long 0x00 "MCASP_DITCSRB[3],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x128++0x03 line.long 0x00 "MCASP_DITCSRB[4],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." group.long 0x12C++0x03 line.long 0x00 "MCASP_DITCSRB[5],Right (Odd TDM Time Slot) Channel Status Registers(DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITCSRB , DIT right channel status registers." tree.end tree "MCASP_DITUDRA - array[6]" group.long 0x130++0x03 line.long 0x00 "MCASP_DITUDRA[0],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x134++0x03 line.long 0x00 "MCASP_DITUDRA[1],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x138++0x03 line.long 0x00 "MCASP_DITUDRA[2],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x13C++0x03 line.long 0x00 "MCASP_DITUDRA[3],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x140++0x03 line.long 0x00 "MCASP_DITUDRA[4],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." group.long 0x144++0x03 line.long 0x00 "MCASP_DITUDRA[5],Left (Even TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRA , DIT left channel user data registers." tree.end tree "MCASP_DITUDRB - array[6]" group.long 0x148++0x03 line.long 0x00 "MCASP_DITUDRB[0],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x14C++0x03 line.long 0x00 "MCASP_DITUDRB[1],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x150++0x03 line.long 0x00 "MCASP_DITUDRB[2],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x154++0x03 line.long 0x00 "MCASP_DITUDRB[3],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x158++0x03 line.long 0x00 "MCASP_DITUDRB[4],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." group.long 0x15C++0x03 line.long 0x00 "MCASP_DITUDRB[5],Right (Odd TDM Time Slot) Channel User Data Registers (DIT Mode)" hexmask.long 0x00 0.--31. 1. " DITUDRB , DIT right channel user data registers." tree.end width 16. tree "MCASP_SRCTL - array[6]" group.long 0x180++0x03 line.long 0x00 "MCASP_SRCTL[0],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x184++0x03 line.long 0x00 "MCASP_SRCTL[1],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x188++0x03 line.long 0x00 "MCASP_SRCTL[2],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x18C++0x03 line.long 0x00 "MCASP_SRCTL[3],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x190++0x03 line.long 0x00 "MCASP_SRCTL[4],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," group.long 0x194++0x03 line.long 0x00 "MCASP_SRCTL[5],Serializer Control Register" rbitfld.long 0x00 5. " RRDY ,Receive buffer ready bit" "Not ready,Ready" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready bit" "Not ready,Ready" bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode bit" "3-state,,Logic low,Logic high" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode bit" "Inactive,Transmitter,Receiver," tree.end width 15. tree "MCASP_XBUF - array[6]" group.long 0x200++0x03 line.long 0x00 "MCASP_XBUF[0],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x204++0x03 line.long 0x00 "MCASP_XBUF[1],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x208++0x03 line.long 0x00 "MCASP_XBUF[2],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x20C++0x03 line.long 0x00 "MCASP_XBUF[3],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x210++0x03 line.long 0x00 "MCASP_XBUF[4],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." group.long 0x214++0x03 line.long 0x00 "MCASP_XBUF[5],Transmit Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " XBUF , Transmit buffers for serializers." tree.end tree "MCASP_RBUF - array[6]" group.long 0x280++0x03 line.long 0x00 "MCASP_RBUF[0],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x284++0x03 line.long 0x00 "MCASP_RBUF[1],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x288++0x03 line.long 0x00 "MCASP_RBUF[2],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x28C++0x03 line.long 0x00 "MCASP_RBUF[3],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x290++0x03 line.long 0x00 "MCASP_RBUF[4],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." group.long 0x294++0x03 line.long 0x00 "MCASP_RBUF[5],Receive Buffer Register for Serializers" hexmask.long 0x00 0.--31. 1. " RBUF , Receive buffers for serializers." tree.end textline " " width 16. group.long 0x1000++0x03 line.long 0x00 "MCASP_WFIFOCTL,Write FIFO Control Register" bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event" hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer" rgroup.long 0x1004++0x03 line.long 0x00 "MCASP_WFIFOSTS,Write FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level" group.long 0x1008++0x03 line.long 0x00 "MCASP_RFIFOCTL,Read FIFO Control Register" bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event" hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer" rgroup.long 0x100C++0x03 line.long 0x00 "MCASP_RFIFOSTS,Read FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level" width 11. tree.end tree.end tree "CAN(Controller Area Network)" tree "DCAN 0" base ad:0x481CC000 width 15. group.long 0x000++0x03 line.long 0x00 "DCAN_CTL,CAN Control Register" bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity when in local power-down mode" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "No request,Request" bitfld.long 0x00 20. " DE3 ,Enable DMA request line for IF3" "Disabled,Enabled" bitfld.long 0x00 19. " DE2 ,Enable DMA request line for IF2" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " DE1 ,Enable DMA request line for IF1" "Disabled,Enabled" bitfld.long 0x00 17. " IE1 ,Interrupt line 1 enable" "Disabled,Enabled" rbitfld.long 0x00 16. " INITDBG ,Internal init state while debug access" "No,Yes" bitfld.long 0x00 15. " SWR ,SW reset enable" "No reset,Reset" textline " " bitfld.long 0x00 10.--13. " PMD , Parity on/off" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 9. " ABO ,Auto-Bus-On enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption debug support enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " CCE ,Configuration change enable" "Access disabled,Assess enabled" bitfld.long 0x00 5. " DAR ,Disable automatic retransmission" "No,Yes" textline " " bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " SIE ,Status change interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE0 ,Interrupt line 0 enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal operation,Entered" hgroup.long 0x004++0x03 hide.long 0x00 "DCAN_ES,Error and Status Register" in rgroup.long 0x008++0x03 line.long 0x00 "DCAN_ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive error passive" "Not passive,Passive" hexmask.long.byte 0x00 8.--14. 1. " REC , Receive error counter" hexmask.long.byte 0x00 0.--7. 1. " TEC , Transmit error counter" if (((d.l(ad:0x481CC000+0x00))&0x40)==0x40)&&(((d.l(ad:0x481CC000+0x00))&0x01)==0x01) //DCAN_CTL.CCE== "Enabled" && DCAN_CTL.INIT== "Entered" group.long 0x00C++0x03 line.long 0x00 "DCAN_BTR,Bit Timing Register" rbitfld.long 0x00 16.--19. " BRPE , Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 12.--14. " TSEG2 , Time segment after the sample point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 , Time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6.--7. " SJW , Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP , Baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x00C++0x03 line.long 0x00 "DCAN_BTR,Bit Timing Register" bitfld.long 0x00 16.--19. " BRPE , Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 , Time segment after the sample point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 , Time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6.--7. " SJW , Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP , Baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif rgroup.long 0x010++0x03 line.long 0x00 "DCAN_INT,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID_23_16 , Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INT0ID_15_0 , Interrupt Identifier" if (((d.l(ad:0x481CC000+0x00))&0x80)==0x80) //DCAN_CTL.TEST== "Enabled" group.long 0x014++0x03 line.long 0x00 "DCAN_TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM direct access enable" "Normal operation,Enabled" bitfld.long 0x00 8. " EXL ,External loopback mode" "Disabled,Enabled" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" textline " " bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Sample point,Dominant value,Recessive value" bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled" else rgroup.long 0x014++0x03 line.long 0x00 "DCAN_TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM direct access enable" "Normal operation,Enabled" bitfld.long 0x00 8. " EXL ,External loopback mode" "Disabled,Enabled" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" textline " " bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Sample point,Dominant value,Recessive value" bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled" endif rgroup.long 0x01C++0x03 line.long 0x00 "DCAN_PERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WORD_NUMBER , Word number where parity error has been detected" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER , Message number" group.long 0x080++0x03 line.long 0x00 "DCAN_ABOTR,Auto-Bus-On Time Register" hexmask.long 0x00 0.--31. 1. " ABO_TIME , Number of OCP clock cycles before a Bus-Off recovery sequence is started by clearing the Init bit" rgroup.long 0x084++0x03 line.long 0x00 "DCAN_TXRQ_X,Transmission Request X Register" bitfld.long 0x00 14.--15. " TXRQSTREG8 , TxRqstReg8" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 , TxRqstReg7" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 , TxRqstReg6" "0,1,2,3" bitfld.long 0x00 8.--9. " TXRQSTREG5 , TxRqstReg5" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " TXRQSTREG4 , TxRqstReg4" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 , TxRqstReg3" "0,1,2,3" bitfld.long 0x00 2.--3. " TXRQSTREG2 , TxRqstReg2" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 , TxRqstReg1" "0,1,2,3" rgroup.long 0x088++0x03 line.long 0x00 "DCAN_TXRQ12,Transmission Request Register 12" bitfld.long 0x00 31. " TXRQS_31 ,Transmission request bit 31" "Not requested,Requested" bitfld.long 0x00 30. " TXRQS_30 ,Transmission request bit 30" "Not requested,Requested" bitfld.long 0x00 29. " TXRQS_29 ,Transmission request bit 29" "Not requested,Requested" bitfld.long 0x00 28. " TXRQS_28 ,Transmission request bit 28" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQS_27 ,Transmission request bit 27" "Not requested,Requested" bitfld.long 0x00 26. " TXRQS_26 ,Transmission request bit 26" "Not requested,Requested" bitfld.long 0x00 25. " TXRQS_25 ,Transmission request bit 25" "Not requested,Requested" bitfld.long 0x00 24. " TXRQS_24 ,Transmission request bit 24" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQS_23 ,Transmission request bit 23" "Not requested,Requested" bitfld.long 0x00 22. " TXRQS_22 ,Transmission request bit 22" "Not requested,Requested" bitfld.long 0x00 21. " TXRQS_21 ,Transmission request bit 21" "Not requested,Requested" bitfld.long 0x00 20. " TXRQS_20 ,Transmission request bit 20" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQS_19 ,Transmission request bit 19" "Not requested,Requested" bitfld.long 0x00 18. " TXRQS_18 ,Transmission request bit 18" "Not requested,Requested" bitfld.long 0x00 17. " TXRQS_17 ,Transmission request bit 17" "Not requested,Requested" bitfld.long 0x00 16. " TXRQS_16 ,Transmission request bit 16" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQS_15 ,Transmission request bit 15" "Not requested,Requested" bitfld.long 0x00 14. " TXRQS_14 ,Transmission request bit 14" "Not requested,Requested" bitfld.long 0x00 13. " TXRQS_13 ,Transmission request bit 13" "Not requested,Requested" bitfld.long 0x00 12. " TXRQS_12 ,Transmission request bit 12" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQS_11 ,Transmission request bit 11" "Not requested,Requested" bitfld.long 0x00 10. " TXRQS_10 ,Transmission request bit 10" "Not requested,Requested" bitfld.long 0x00 9. " TXRQS_9 ,Transmission request bit 9" "Not requested,Requested" bitfld.long 0x00 8. " TXRQS_8 ,Transmission request bit 8" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQS_7 ,Transmission request bit 7" "Not requested,Requested" bitfld.long 0x00 6. " TXRQS_6 ,Transmission request bit 6" "Not requested,Requested" bitfld.long 0x00 5. " TXRQS_5 ,Transmission request bit 5" "Not requested,Requested" bitfld.long 0x00 4. " TXRQS_4 ,Transmission request bit 4" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQS_3 ,Transmission request bit 3" "Not requested,Requested" bitfld.long 0x00 2. " TXRQS_2 ,Transmission request bit 2" "Not requested,Requested" bitfld.long 0x00 1. " TXRQS_1 ,Transmission request bit 1" "Not requested,Requested" bitfld.long 0x00 0. " TXRQS_0 ,Transmission request bit 0" "Not requested,Requested" rgroup.long 0x08C++0x03 line.long 0x00 "DCAN_TXRQ34,Transmission Request Register 34" bitfld.long 0x00 31. " TXRQS_63 ,Transmission request bit 63" "Not requested,Requested" bitfld.long 0x00 30. " TXRQS_62 ,Transmission request bit 62" "Not requested,Requested" bitfld.long 0x00 29. " TXRQS_61 ,Transmission request bit 61" "Not requested,Requested" bitfld.long 0x00 28. " TXRQS_60 ,Transmission request bit 60" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQS_59 ,Transmission request bit 59" "Not requested,Requested" bitfld.long 0x00 26. " TXRQS_58 ,Transmission request bit 58" "Not requested,Requested" bitfld.long 0x00 25. " TXRQS_57 ,Transmission request bit 57" "Not requested,Requested" bitfld.long 0x00 24. " TXRQS_56 ,Transmission request bit 56" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQS_55 ,Transmission request bit 55" "Not requested,Requested" bitfld.long 0x00 22. " TXRQS_54 ,Transmission request bit 54" "Not requested,Requested" bitfld.long 0x00 21. " TXRQS_53 ,Transmission request bit 53" "Not requested,Requested" bitfld.long 0x00 20. " TXRQS_52 ,Transmission request bit 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQS_51 ,Transmission request bit 51" "Not requested,Requested" bitfld.long 0x00 18. " TXRQS_50 ,Transmission request bit 50" "Not requested,Requested" bitfld.long 0x00 17. " TXRQS_49 ,Transmission request bit 49" "Not requested,Requested" bitfld.long 0x00 16. " TXRQS_48 ,Transmission request bit 48" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQS_47 ,Transmission request bit 47" "Not requested,Requested" bitfld.long 0x00 14. " TXRQS_46 ,Transmission request bit 46" "Not requested,Requested" bitfld.long 0x00 13. " TXRQS_45 ,Transmission request bit 45" "Not requested,Requested" bitfld.long 0x00 12. " TXRQS_44 ,Transmission request bit 44" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQS_43 ,Transmission request bit 43" "Not requested,Requested" bitfld.long 0x00 10. " TXRQS_42 ,Transmission request bit 42" "Not requested,Requested" bitfld.long 0x00 9. " TXRQS_41 ,Transmission request bit 41" "Not requested,Requested" bitfld.long 0x00 8. " TXRQS_40 ,Transmission request bit 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQS_39 ,Transmission request bit 39" "Not requested,Requested" bitfld.long 0x00 6. " TXRQS_38 ,Transmission request bit 38" "Not requested,Requested" bitfld.long 0x00 5. " TXRQS_37 ,Transmission request bit 37" "Not requested,Requested" bitfld.long 0x00 4. " TXRQS_36 ,Transmission request bit 36" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQS_35 ,Transmission request bit 35" "Not requested,Requested" bitfld.long 0x00 2. " TXRQS_34 ,Transmission request bit 34" "Not requested,Requested" bitfld.long 0x00 1. " TXRQS_33 ,Transmission request bit 33" "Not requested,Requested" bitfld.long 0x00 0. " TXRQS_32 ,Transmission request bit 32" "Not requested,Requested" rgroup.long 0x090++0x03 line.long 0x00 "DCAN_TXRQ56,Transmission Request Register 56" bitfld.long 0x00 31. " TXRQS_95 ,Transmission request bit 95" "Not requested,Requested" bitfld.long 0x00 30. " TXRQS_94 ,Transmission request bit 94" "Not requested,Requested" bitfld.long 0x00 29. " TXRQS_93 ,Transmission request bit 93" "Not requested,Requested" bitfld.long 0x00 28. " TXRQS_92 ,Transmission request bit 92" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQS_91 ,Transmission request bit 91" "Not requested,Requested" bitfld.long 0x00 26. " TXRQS_90 ,Transmission request bit 90" "Not requested,Requested" bitfld.long 0x00 25. " TXRQS_89 ,Transmission request bit 89" "Not requested,Requested" bitfld.long 0x00 24. " TXRQS_88 ,Transmission request bit 88" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQS_87 ,Transmission request bit 87" "Not requested,Requested" bitfld.long 0x00 22. " TXRQS_86 ,Transmission request bit 86" "Not requested,Requested" bitfld.long 0x00 21. " TXRQS_85 ,Transmission request bit 85" "Not requested,Requested" bitfld.long 0x00 20. " TXRQS_84 ,Transmission request bit 84" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQS_83 ,Transmission request bit 83" "Not requested,Requested" bitfld.long 0x00 18. " TXRQS_82 ,Transmission request bit 82" "Not requested,Requested" bitfld.long 0x00 17. " TXRQS_81 ,Transmission request bit 81" "Not requested,Requested" bitfld.long 0x00 16. " TXRQS_80 ,Transmission request bit 80" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQS_79 ,Transmission request bit 79" "Not requested,Requested" bitfld.long 0x00 14. " TXRQS_78 ,Transmission request bit 78" "Not requested,Requested" bitfld.long 0x00 13. " TXRQS_77 ,Transmission request bit 77" "Not requested,Requested" bitfld.long 0x00 12. " TXRQS_76 ,Transmission request bit 76" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQS_75 ,Transmission request bit 75" "Not requested,Requested" bitfld.long 0x00 10. " TXRQS_74 ,Transmission request bit 74" "Not requested,Requested" bitfld.long 0x00 9. " TXRQS_73 ,Transmission request bit 73" "Not requested,Requested" bitfld.long 0x00 8. " TXRQS_72 ,Transmission request bit 72" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQS_71 ,Transmission request bit 71" "Not requested,Requested" bitfld.long 0x00 6. " TXRQS_70 ,Transmission request bit 70" "Not requested,Requested" bitfld.long 0x00 5. " TXRQS_69 ,Transmission request bit 69" "Not requested,Requested" bitfld.long 0x00 4. " TXRQS_68 ,Transmission request bit 68" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQS_67 ,Transmission request bit 67" "Not requested,Requested" bitfld.long 0x00 2. " TXRQS_66 ,Transmission request bit 66" "Not requested,Requested" bitfld.long 0x00 1. " TXRQS_65 ,Transmission request bit 65" "Not requested,Requested" bitfld.long 0x00 0. " TXRQS_64 ,Transmission request bit 64" "Not requested,Requested" rgroup.long 0x094++0x03 line.long 0x00 "DCAN_TXRQ78,Transmission Request Register 78" bitfld.long 0x00 31. " TXRQS_127 ,Transmission request bit 127" "Not requested,Requested" bitfld.long 0x00 30. " TXRQS_126 ,Transmission request bit 126" "Not requested,Requested" bitfld.long 0x00 29. " TXRQS_125 ,Transmission request bit 125" "Not requested,Requested" bitfld.long 0x00 28. " TXRQS_124 ,Transmission request bit 124" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQS_123 ,Transmission request bit 123" "Not requested,Requested" bitfld.long 0x00 26. " TXRQS_122 ,Transmission request bit 122" "Not requested,Requested" bitfld.long 0x00 25. " TXRQS_121 ,Transmission request bit 121" "Not requested,Requested" bitfld.long 0x00 24. " TXRQS_120 ,Transmission request bit 120" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQS_119 ,Transmission request bit 119" "Not requested,Requested" bitfld.long 0x00 22. " TXRQS_118 ,Transmission request bit 118" "Not requested,Requested" bitfld.long 0x00 21. " TXRQS_117 ,Transmission request bit 117" "Not requested,Requested" bitfld.long 0x00 20. " TXRQS_116 ,Transmission request bit 116" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQS_115 ,Transmission request bit 115" "Not requested,Requested" bitfld.long 0x00 18. " TXRQS_114 ,Transmission request bit 114" "Not requested,Requested" bitfld.long 0x00 17. " TXRQS_113 ,Transmission request bit 113" "Not requested,Requested" bitfld.long 0x00 16. " TXRQS_112 ,Transmission request bit 112" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQS_111 ,Transmission request bit 111" "Not requested,Requested" bitfld.long 0x00 14. " TXRQS_110 ,Transmission request bit 110" "Not requested,Requested" bitfld.long 0x00 13. " TXRQS_109 ,Transmission request bit 109" "Not requested,Requested" bitfld.long 0x00 12. " TXRQS_108 ,Transmission request bit 108" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQS_107 ,Transmission request bit 107" "Not requested,Requested" bitfld.long 0x00 10. " TXRQS_106 ,Transmission request bit 106" "Not requested,Requested" bitfld.long 0x00 9. " TXRQS_105 ,Transmission request bit 105" "Not requested,Requested" bitfld.long 0x00 8. " TXRQS_104 ,Transmission request bit 104" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQS_103 ,Transmission request bit 103" "Not requested,Requested" bitfld.long 0x00 6. " TXRQS_102 ,Transmission request bit 102" "Not requested,Requested" bitfld.long 0x00 5. " TXRQS_101 ,Transmission request bit 101" "Not requested,Requested" bitfld.long 0x00 4. " TXRQS_100 ,Transmission request bit 100" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQS_99 ,Transmission request bit 99" "Not requested,Requested" bitfld.long 0x00 2. " TXRQS_98 ,Transmission request bit 98" "Not requested,Requested" bitfld.long 0x00 1. " TXRQS_97 ,Transmission request bit 97" "Not requested,Requested" bitfld.long 0x00 0. " TXRQS_96 ,Transmission request bit 96" "Not requested,Requested" rgroup.long 0x098++0x03 line.long 0x00 "DCAN_NWDAT_X,New Data X Register" bitfld.long 0x00 14.--15. " NEWDATREG8 , NewDatReg8" "0,1,2,3" bitfld.long 0x00 12.--13. " NEWDATREG7 , NewDatReg7" "0,1,2,3" bitfld.long 0x00 10.--11. " NEWDATREG6 , NewDatReg6" "0,1,2,3" bitfld.long 0x00 8.--9. " NEWDATREG5 , NewDatReg5" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " NEWDATREG4 , NewDatReg4" "0,1,2,3" bitfld.long 0x00 4.--5. " NEWDATREG3 , NewDatReg3" "0,1,2,3" bitfld.long 0x00 2.--3. " NEWDATREG2 , NewDatReg2" "0,1,2,3" bitfld.long 0x00 0.--1. " NEWDATREG1 , NewDatReg1" "0,1,2,3" rgroup.long 0x09C++0x03 line.long 0x00 "DCAN_NWDAT12,New Data Register 12" bitfld.long 0x00 31. " NEWDAT_31 ,New Data Bit 31" "Not new,New" bitfld.long 0x00 30. " NEWDAT_30 ,New Data Bit 30" "Not new,New" bitfld.long 0x00 29. " NEWDAT_29 ,New Data Bit 29" "Not new,New" bitfld.long 0x00 28. " NEWDAT_28 ,New Data Bit 28" "Not new,New" textline " " bitfld.long 0x00 27. " NEWDAT_27 ,New Data Bit 27" "Not new,New" bitfld.long 0x00 26. " NEWDAT_26 ,New Data Bit 26" "Not new,New" bitfld.long 0x00 25. " NEWDAT_25 ,New Data Bit 25" "Not new,New" bitfld.long 0x00 24. " NEWDAT_24 ,New Data Bit 24" "Not new,New" textline " " bitfld.long 0x00 23. " NEWDAT_23 ,New Data Bit 23" "Not new,New" bitfld.long 0x00 22. " NEWDAT_22 ,New Data Bit 22" "Not new,New" bitfld.long 0x00 21. " NEWDAT_21 ,New Data Bit 21" "Not new,New" bitfld.long 0x00 20. " NEWDAT_20 ,New Data Bit 20" "Not new,New" textline " " bitfld.long 0x00 19. " NEWDAT_19 ,New Data Bit 19" "Not new,New" bitfld.long 0x00 18. " NEWDAT_18 ,New Data Bit 18" "Not new,New" bitfld.long 0x00 17. " NEWDAT_17 ,New Data Bit 17" "Not new,New" bitfld.long 0x00 16. " NEWDAT_16 ,New Data Bit 16" "Not new,New" textline " " bitfld.long 0x00 15. " NEWDAT_15 ,New Data Bit 15" "Not new,New" bitfld.long 0x00 14. " NEWDAT_14 ,New Data Bit 14" "Not new,New" bitfld.long 0x00 13. " NEWDAT_13 ,New Data Bit 13" "Not new,New" bitfld.long 0x00 12. " NEWDAT_12 ,New Data Bit 12" "Not new,New" textline " " bitfld.long 0x00 11. " NEWDAT_11 ,New Data Bit 11" "Not new,New" bitfld.long 0x00 10. " NEWDAT_10 ,New Data Bit 10" "Not new,New" bitfld.long 0x00 9. " NEWDAT_9 ,New Data Bit 9" "Not new,New" bitfld.long 0x00 8. " NEWDAT_8 ,New Data Bit 8" "Not new,New" textline " " bitfld.long 0x00 7. " NEWDAT_7 ,New Data Bit 7" "Not new,New" bitfld.long 0x00 6. " NEWDAT_6 ,New Data Bit 6" "Not new,New" bitfld.long 0x00 5. " NEWDAT_5 ,New Data Bit 5" "Not new,New" bitfld.long 0x00 4. " NEWDAT_4 ,New Data Bit 4" "Not new,New" textline " " bitfld.long 0x00 3. " NEWDAT_3 ,New Data Bit 3" "Not new,New" bitfld.long 0x00 2. " NEWDAT_2 ,New Data Bit 2" "Not new,New" bitfld.long 0x00 1. " NEWDAT_1 ,New Data Bit 1" "Not new,New" bitfld.long 0x00 0. " NEWDAT_0 ,New Data Bit 0" "Not new,New" rgroup.long 0x0A0++0x03 line.long 0x00 "DCAN_NWDAT34,New Data Register 34" bitfld.long 0x00 31. " NEWDAT_63 ,New Data Bit 63" "Not new,New" bitfld.long 0x00 30. " NEWDAT_62 ,New Data Bit 62" "Not new,New" bitfld.long 0x00 29. " NEWDAT_61 ,New Data Bit 61" "Not new,New" bitfld.long 0x00 28. " NEWDAT_60 ,New Data Bit 60" "Not new,New" textline " " bitfld.long 0x00 27. " NEWDAT_59 ,New Data Bit 59" "Not new,New" bitfld.long 0x00 26. " NEWDAT_58 ,New Data Bit 58" "Not new,New" bitfld.long 0x00 25. " NEWDAT_57 ,New Data Bit 57" "Not new,New" bitfld.long 0x00 24. " NEWDAT_56 ,New Data Bit 56" "Not new,New" textline " " bitfld.long 0x00 23. " NEWDAT_55 ,New Data Bit 55" "Not new,New" bitfld.long 0x00 22. " NEWDAT_54 ,New Data Bit 54" "Not new,New" bitfld.long 0x00 21. " NEWDAT_53 ,New Data Bit 53" "Not new,New" bitfld.long 0x00 20. " NEWDAT_52 ,New Data Bit 52" "Not new,New" textline " " bitfld.long 0x00 19. " NEWDAT_51 ,New Data Bit 51" "Not new,New" bitfld.long 0x00 18. " NEWDAT_50 ,New Data Bit 50" "Not new,New" bitfld.long 0x00 17. " NEWDAT_49 ,New Data Bit 49" "Not new,New" bitfld.long 0x00 16. " NEWDAT_48 ,New Data Bit 48" "Not new,New" textline " " bitfld.long 0x00 15. " NEWDAT_47 ,New Data Bit 47" "Not new,New" bitfld.long 0x00 14. " NEWDAT_46 ,New Data Bit 46" "Not new,New" bitfld.long 0x00 13. " NEWDAT_45 ,New Data Bit 45" "Not new,New" bitfld.long 0x00 12. " NEWDAT_44 ,New Data Bit 44" "Not new,New" textline " " bitfld.long 0x00 11. " NEWDAT_43 ,New Data Bit 43" "Not new,New" bitfld.long 0x00 10. " NEWDAT_42 ,New Data Bit 42" "Not new,New" bitfld.long 0x00 9. " NEWDAT_41 ,New Data Bit 41" "Not new,New" bitfld.long 0x00 8. " NEWDAT_40 ,New Data Bit 40" "Not new,New" textline " " bitfld.long 0x00 7. " NEWDAT_39 ,New Data Bit 39" "Not new,New" bitfld.long 0x00 6. " NEWDAT_38 ,New Data Bit 38" "Not new,New" bitfld.long 0x00 5. " NEWDAT_37 ,New Data Bit 37" "Not new,New" bitfld.long 0x00 4. " NEWDAT_36 ,New Data Bit 36" "Not new,New" textline " " bitfld.long 0x00 3. " NEWDAT_35 ,New Data Bit 35" "Not new,New" bitfld.long 0x00 2. " NEWDAT_34 ,New Data Bit 34" "Not new,New" bitfld.long 0x00 1. " NEWDAT_33 ,New Data Bit 33" "Not new,New" bitfld.long 0x00 0. " NEWDAT_32 ,New Data Bit 32" "Not new,New" rgroup.long 0x0A4++0x03 line.long 0x00 "DCAN_NWDAT56,New Data Register 56" bitfld.long 0x00 31. " NEWDAT_95 ,New Data Bit 95" "Not new,New" bitfld.long 0x00 30. " NEWDAT_94 ,New Data Bit 94" "Not new,New" bitfld.long 0x00 29. " NEWDAT_93 ,New Data Bit 93" "Not new,New" bitfld.long 0x00 28. " NEWDAT_92 ,New Data Bit 92" "Not new,New" textline " " bitfld.long 0x00 27. " NEWDAT_91 ,New Data Bit 91" "Not new,New" bitfld.long 0x00 26. " NEWDAT_90 ,New Data Bit 90" "Not new,New" bitfld.long 0x00 25. " NEWDAT_89 ,New Data Bit 89" "Not new,New" bitfld.long 0x00 24. " NEWDAT_88 ,New Data Bit 88" "Not new,New" textline " " bitfld.long 0x00 23. " NEWDAT_87 ,New Data Bit 87" "Not new,New" bitfld.long 0x00 22. " NEWDAT_86 ,New Data Bit 86" "Not new,New" bitfld.long 0x00 21. " NEWDAT_85 ,New Data Bit 85" "Not new,New" bitfld.long 0x00 20. " NEWDAT_84 ,New Data Bit 84" "Not new,New" textline " " bitfld.long 0x00 19. " NEWDAT_83 ,New Data Bit 83" "Not new,New" bitfld.long 0x00 18. " NEWDAT_82 ,New Data Bit 82" "Not new,New" bitfld.long 0x00 17. " NEWDAT_81 ,New Data Bit 81" "Not new,New" bitfld.long 0x00 16. " NEWDAT_80 ,New Data Bit 80" "Not new,New" textline " " bitfld.long 0x00 15. " NEWDAT_79 ,New Data Bit 79" "Not new,New" bitfld.long 0x00 14. " NEWDAT_78 ,New Data Bit 78" "Not new,New" bitfld.long 0x00 13. " NEWDAT_77 ,New Data Bit 77" "Not new,New" bitfld.long 0x00 12. " NEWDAT_76 ,New Data Bit 76" "Not new,New" textline " " bitfld.long 0x00 11. " NEWDAT_75 ,New Data Bit 75" "Not new,New" bitfld.long 0x00 10. " NEWDAT_74 ,New Data Bit 74" "Not new,New" bitfld.long 0x00 9. " NEWDAT_73 ,New Data Bit 73" "Not new,New" bitfld.long 0x00 8. " NEWDAT_72 ,New Data Bit 72" "Not new,New" textline " " bitfld.long 0x00 7. " NEWDAT_71 ,New Data Bit 71" "Not new,New" bitfld.long 0x00 6. " NEWDAT_70 ,New Data Bit 70" "Not new,New" bitfld.long 0x00 5. " NEWDAT_69 ,New Data Bit 69" "Not new,New" bitfld.long 0x00 4. " NEWDAT_68 ,New Data Bit 68" "Not new,New" textline " " bitfld.long 0x00 3. " NEWDAT_67 ,New Data Bit 67" "Not new,New" bitfld.long 0x00 2. " NEWDAT_66 ,New Data Bit 66" "Not new,New" bitfld.long 0x00 1. " NEWDAT_65 ,New Data Bit 65" "Not new,New" bitfld.long 0x00 0. " NEWDAT_64 ,New Data Bit 64" "Not new,New" rgroup.long 0x0A8++0x03 line.long 0x00 "DCAN_NWDAT78,New Data Register 78" bitfld.long 0x00 31. " NEWDAT_127 ,New Data Bit 127" "Not new,New" bitfld.long 0x00 30. " NEWDAT_126 ,New Data Bit 126" "Not new,New" bitfld.long 0x00 29. " NEWDAT_125 ,New Data Bit 125" "Not new,New" bitfld.long 0x00 28. " NEWDAT_124 ,New Data Bit 124" "Not new,New" textline " " bitfld.long 0x00 27. " NEWDAT_123 ,New Data Bit 123" "Not new,New" bitfld.long 0x00 26. " NEWDAT_122 ,New Data Bit 122" "Not new,New" bitfld.long 0x00 25. " NEWDAT_121 ,New Data Bit 121" "Not new,New" bitfld.long 0x00 24. " NEWDAT_120 ,New Data Bit 120" "Not new,New" textline " " bitfld.long 0x00 23. " NEWDAT_119 ,New Data Bit 119" "Not new,New" bitfld.long 0x00 22. " NEWDAT_118 ,New Data Bit 118" "Not new,New" bitfld.long 0x00 21. " NEWDAT_117 ,New Data Bit 117" "Not new,New" bitfld.long 0x00 20. " NEWDAT_116 ,New Data Bit 116" "Not new,New" textline " " bitfld.long 0x00 19. " NEWDAT_115 ,New Data Bit 115" "Not new,New" bitfld.long 0x00 18. " NEWDAT_114 ,New Data Bit 114" "Not new,New" bitfld.long 0x00 17. " NEWDAT_113 ,New Data Bit 113" "Not new,New" bitfld.long 0x00 16. " NEWDAT_112 ,New Data Bit 112" "Not new,New" textline " " bitfld.long 0x00 15. " NEWDAT_111 ,New Data Bit 111" "Not new,New" bitfld.long 0x00 14. " NEWDAT_110 ,New Data Bit 110" "Not new,New" bitfld.long 0x00 13. " NEWDAT_109 ,New Data Bit 109" "Not new,New" bitfld.long 0x00 12. " NEWDAT_108 ,New Data Bit 108" "Not new,New" textline " " bitfld.long 0x00 11. " NEWDAT_107 ,New Data Bit 107" "Not new,New" bitfld.long 0x00 10. " NEWDAT_106 ,New Data Bit 106" "Not new,New" bitfld.long 0x00 9. " NEWDAT_105 ,New Data Bit 105" "Not new,New" bitfld.long 0x00 8. " NEWDAT_104 ,New Data Bit 104" "Not new,New" textline " " bitfld.long 0x00 7. " NEWDAT_103 ,New Data Bit 103" "Not new,New" bitfld.long 0x00 6. " NEWDAT_102 ,New Data Bit 102" "Not new,New" bitfld.long 0x00 5. " NEWDAT_101 ,New Data Bit 101" "Not new,New" bitfld.long 0x00 4. " NEWDAT_100 ,New Data Bit 100" "Not new,New" textline " " bitfld.long 0x00 3. " NEWDAT_99 ,New Data Bit 99" "Not new,New" bitfld.long 0x00 2. " NEWDAT_98 ,New Data Bit 98" "Not new,New" bitfld.long 0x00 1. " NEWDAT_97 ,New Data Bit 97" "Not new,New" bitfld.long 0x00 0. " NEWDAT_96 ,New Data Bit 96" "Not new,New" rgroup.long 0x0AC++0x03 line.long 0x00 "DCAN_INTPND_X,Interrupt Pending X Register" bitfld.long 0x00 14.--15. " INTPNDREG8 , IntPndReg8" "0,1,2,3" bitfld.long 0x00 12.--13. " INTPNDREG7 , IntPndReg7" "0,1,2,3" bitfld.long 0x00 10.--11. " INTPNDREG6 , IntPndReg6" "0,1,2,3" bitfld.long 0x00 8.--9. " INTPNDREG5 , IntPndReg5" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " INTPNDREG4 , IntPndReg4" "0,1,2,3" bitfld.long 0x00 4.--5. " INTPNDREG3 , IntPndReg3" "0,1,2,3" bitfld.long 0x00 2.--3. " INTPNDREG2 , IntPndReg2" "0,1,2,3" bitfld.long 0x00 0.--1. " INTPNDREG1 , IntPndReg1" "0,1,2,3" rgroup.long 0x0B0++0x03 line.long 0x00 "DCAN_INTPND12,Interrupt Pending Register 12" bitfld.long 0x00 31. " INTPND_31 ,Interrupt Pending Bit 31" "Not Source,Source" bitfld.long 0x00 30. " INTPND_30 ,Interrupt Pending Bit 30" "Not Source,Source" bitfld.long 0x00 29. " INTPND_29 ,Interrupt Pending Bit 29" "Not Source,Source" bitfld.long 0x00 28. " INTPND_28 ,Interrupt Pending Bit 28" "Not Source,Source" textline " " bitfld.long 0x00 27. " INTPND_27 ,Interrupt Pending Bit 27" "Not Source,Source" bitfld.long 0x00 26. " INTPND_26 ,Interrupt Pending Bit 26" "Not Source,Source" bitfld.long 0x00 25. " INTPND_25 ,Interrupt Pending Bit 25" "Not Source,Source" bitfld.long 0x00 24. " INTPND_24 ,Interrupt Pending Bit 24" "Not Source,Source" textline " " bitfld.long 0x00 23. " INTPND_23 ,Interrupt Pending Bit 23" "Not Source,Source" bitfld.long 0x00 22. " INTPND_22 ,Interrupt Pending Bit 22" "Not Source,Source" bitfld.long 0x00 21. " INTPND_21 ,Interrupt Pending Bit 21" "Not Source,Source" bitfld.long 0x00 20. " INTPND_20 ,Interrupt Pending Bit 20" "Not Source,Source" textline " " bitfld.long 0x00 19. " INTPND_19 ,Interrupt Pending Bit 19" "Not Source,Source" bitfld.long 0x00 18. " INTPND_18 ,Interrupt Pending Bit 18" "Not Source,Source" bitfld.long 0x00 17. " INTPND_17 ,Interrupt Pending Bit 17" "Not Source,Source" bitfld.long 0x00 16. " INTPND_16 ,Interrupt Pending Bit 16" "Not Source,Source" textline " " bitfld.long 0x00 15. " INTPND_15 ,Interrupt Pending Bit 15" "Not Source,Source" bitfld.long 0x00 14. " INTPND_14 ,Interrupt Pending Bit 14" "Not Source,Source" bitfld.long 0x00 13. " INTPND_13 ,Interrupt Pending Bit 13" "Not Source,Source" bitfld.long 0x00 12. " INTPND_12 ,Interrupt Pending Bit 12" "Not Source,Source" textline " " bitfld.long 0x00 11. " INTPND_11 ,Interrupt Pending Bit 11" "Not Source,Source" bitfld.long 0x00 10. " INTPND_10 ,Interrupt Pending Bit 10" "Not Source,Source" bitfld.long 0x00 9. " INTPND_9 ,Interrupt Pending Bit 9" "Not Source,Source" bitfld.long 0x00 8. " INTPND_8 ,Interrupt Pending Bit 8" "Not Source,Source" textline " " bitfld.long 0x00 7. " INTPND_7 ,Interrupt Pending Bit 7" "Not Source,Source" bitfld.long 0x00 6. " INTPND_6 ,Interrupt Pending Bit 6" "Not Source,Source" bitfld.long 0x00 5. " INTPND_5 ,Interrupt Pending Bit 5" "Not Source,Source" bitfld.long 0x00 4. " INTPND_4 ,Interrupt Pending Bit 4" "Not Source,Source" textline " " bitfld.long 0x00 3. " INTPND_3 ,Interrupt Pending Bit 3" "Not Source,Source" bitfld.long 0x00 2. " INTPND_2 ,Interrupt Pending Bit 2" "Not Source,Source" bitfld.long 0x00 1. " INTPND_1 ,Interrupt Pending Bit 1" "Not Source,Source" bitfld.long 0x00 0. " INTPND_0 ,Interrupt Pending Bit 0" "Not Source,Source" rgroup.long 0x0B4++0x03 line.long 0x00 "DCAN_INTPND34,Interrupt Pending Register 34" bitfld.long 0x00 31. " INTPND_63 ,Interrupt Pending Bit 63" "Not Source,Source" bitfld.long 0x00 30. " INTPND_62 ,Interrupt Pending Bit 62" "Not Source,Source" bitfld.long 0x00 29. " INTPND_61 ,Interrupt Pending Bit 61" "Not Source,Source" bitfld.long 0x00 28. " INTPND_60 ,Interrupt Pending Bit 60" "Not Source,Source" textline " " bitfld.long 0x00 27. " INTPND_59 ,Interrupt Pending Bit 59" "Not Source,Source" bitfld.long 0x00 26. " INTPND_58 ,Interrupt Pending Bit 58" "Not Source,Source" bitfld.long 0x00 25. " INTPND_57 ,Interrupt Pending Bit 57" "Not Source,Source" bitfld.long 0x00 24. " INTPND_56 ,Interrupt Pending Bit 56" "Not Source,Source" textline " " bitfld.long 0x00 23. " INTPND_55 ,Interrupt Pending Bit 55" "Not Source,Source" bitfld.long 0x00 22. " INTPND_54 ,Interrupt Pending Bit 54" "Not Source,Source" bitfld.long 0x00 21. " INTPND_53 ,Interrupt Pending Bit 53" "Not Source,Source" bitfld.long 0x00 20. " INTPND_52 ,Interrupt Pending Bit 52" "Not Source,Source" textline " " bitfld.long 0x00 19. " INTPND_51 ,Interrupt Pending Bit 51" "Not Source,Source" bitfld.long 0x00 18. " INTPND_50 ,Interrupt Pending Bit 50" "Not Source,Source" bitfld.long 0x00 17. " INTPND_49 ,Interrupt Pending Bit 49" "Not Source,Source" bitfld.long 0x00 16. " INTPND_48 ,Interrupt Pending Bit 48" "Not Source,Source" textline " " bitfld.long 0x00 15. " INTPND_47 ,Interrupt Pending Bit 47" "Not Source,Source" bitfld.long 0x00 14. " INTPND_46 ,Interrupt Pending Bit 46" "Not Source,Source" bitfld.long 0x00 13. " INTPND_45 ,Interrupt Pending Bit 45" "Not Source,Source" bitfld.long 0x00 12. " INTPND_44 ,Interrupt Pending Bit 44" "Not Source,Source" textline " " bitfld.long 0x00 11. " INTPND_43 ,Interrupt Pending Bit 43" "Not Source,Source" bitfld.long 0x00 10. " INTPND_42 ,Interrupt Pending Bit 42" "Not Source,Source" bitfld.long 0x00 9. " INTPND_41 ,Interrupt Pending Bit 41" "Not Source,Source" bitfld.long 0x00 8. " INTPND_40 ,Interrupt Pending Bit 40" "Not Source,Source" textline " " bitfld.long 0x00 7. " INTPND_39 ,Interrupt Pending Bit 39" "Not Source,Source" bitfld.long 0x00 6. " INTPND_38 ,Interrupt Pending Bit 38" "Not Source,Source" bitfld.long 0x00 5. " INTPND_37 ,Interrupt Pending Bit 37" "Not Source,Source" bitfld.long 0x00 4. " INTPND_36 ,Interrupt Pending Bit 36" "Not Source,Source" textline " " bitfld.long 0x00 3. " INTPND_35 ,Interrupt Pending Bit 35" "Not Source,Source" bitfld.long 0x00 2. " INTPND_34 ,Interrupt Pending Bit 34" "Not Source,Source" bitfld.long 0x00 1. " INTPND_33 ,Interrupt Pending Bit 33" "Not Source,Source" bitfld.long 0x00 0. " INTPND_32 ,Interrupt Pending Bit 32" "Not Source,Source" rgroup.long 0x0B8++0x03 line.long 0x00 "DCAN_INTPND56,Interrupt Pending Register 56" bitfld.long 0x00 31. " INTPND_95 ,Interrupt Pending Bit 95" "Not Source,Source" bitfld.long 0x00 30. " INTPND_94 ,Interrupt Pending Bit 94" "Not Source,Source" bitfld.long 0x00 29. " INTPND_93 ,Interrupt Pending Bit 93" "Not Source,Source" bitfld.long 0x00 28. " INTPND_92 ,Interrupt Pending Bit 92" "Not Source,Source" textline " " bitfld.long 0x00 27. " INTPND_91 ,Interrupt Pending Bit 91" "Not Source,Source" bitfld.long 0x00 26. " INTPND_90 ,Interrupt Pending Bit 90" "Not Source,Source" bitfld.long 0x00 25. " INTPND_89 ,Interrupt Pending Bit 89" "Not Source,Source" bitfld.long 0x00 24. " INTPND_88 ,Interrupt Pending Bit 88" "Not Source,Source" textline " " bitfld.long 0x00 23. " INTPND_87 ,Interrupt Pending Bit 87" "Not Source,Source" bitfld.long 0x00 22. " INTPND_86 ,Interrupt Pending Bit 86" "Not Source,Source" bitfld.long 0x00 21. " INTPND_85 ,Interrupt Pending Bit 85" "Not Source,Source" bitfld.long 0x00 20. " INTPND_84 ,Interrupt Pending Bit 84" "Not Source,Source" textline " " bitfld.long 0x00 19. " INTPND_83 ,Interrupt Pending Bit 83" "Not Source,Source" bitfld.long 0x00 18. " INTPND_82 ,Interrupt Pending Bit 82" "Not Source,Source" bitfld.long 0x00 17. " INTPND_81 ,Interrupt Pending Bit 81" "Not Source,Source" bitfld.long 0x00 16. " INTPND_80 ,Interrupt Pending Bit 80" "Not Source,Source" textline " " bitfld.long 0x00 15. " INTPND_79 ,Interrupt Pending Bit 79" "Not Source,Source" bitfld.long 0x00 14. " INTPND_78 ,Interrupt Pending Bit 78" "Not Source,Source" bitfld.long 0x00 13. " INTPND_77 ,Interrupt Pending Bit 77" "Not Source,Source" bitfld.long 0x00 12. " INTPND_76 ,Interrupt Pending Bit 76" "Not Source,Source" textline " " bitfld.long 0x00 11. " INTPND_75 ,Interrupt Pending Bit 75" "Not Source,Source" bitfld.long 0x00 10. " INTPND_74 ,Interrupt Pending Bit 74" "Not Source,Source" bitfld.long 0x00 9. " INTPND_73 ,Interrupt Pending Bit 73" "Not Source,Source" bitfld.long 0x00 8. " INTPND_72 ,Interrupt Pending Bit 72" "Not Source,Source" textline " " bitfld.long 0x00 7. " INTPND_71 ,Interrupt Pending Bit 71" "Not Source,Source" bitfld.long 0x00 6. " INTPND_70 ,Interrupt Pending Bit 70" "Not Source,Source" bitfld.long 0x00 5. " INTPND_69 ,Interrupt Pending Bit 69" "Not Source,Source" bitfld.long 0x00 4. " INTPND_68 ,Interrupt Pending Bit 68" "Not Source,Source" textline " " bitfld.long 0x00 3. " INTPND_67 ,Interrupt Pending Bit 67" "Not Source,Source" bitfld.long 0x00 2. " INTPND_66 ,Interrupt Pending Bit 66" "Not Source,Source" bitfld.long 0x00 1. " INTPND_65 ,Interrupt Pending Bit 65" "Not Source,Source" bitfld.long 0x00 0. " INTPND_64 ,Interrupt Pending Bit 64" "Not Source,Source" rgroup.long 0x0BC++0x03 line.long 0x00 "DCAN_INTPND78,Interrupt Pending Register 78" bitfld.long 0x00 31. " INTPND_127 ,Interrupt Pending Bit 127" "Not Source,Source" bitfld.long 0x00 30. " INTPND_126 ,Interrupt Pending Bit 126" "Not Source,Source" bitfld.long 0x00 29. " INTPND_125 ,Interrupt Pending Bit 125" "Not Source,Source" bitfld.long 0x00 28. " INTPND_124 ,Interrupt Pending Bit 124" "Not Source,Source" textline " " bitfld.long 0x00 27. " INTPND_123 ,Interrupt Pending Bit 123" "Not Source,Source" bitfld.long 0x00 26. " INTPND_122 ,Interrupt Pending Bit 122" "Not Source,Source" bitfld.long 0x00 25. " INTPND_121 ,Interrupt Pending Bit 121" "Not Source,Source" bitfld.long 0x00 24. " INTPND_120 ,Interrupt Pending Bit 120" "Not Source,Source" textline " " bitfld.long 0x00 23. " INTPND_119 ,Interrupt Pending Bit 119" "Not Source,Source" bitfld.long 0x00 22. " INTPND_118 ,Interrupt Pending Bit 118" "Not Source,Source" bitfld.long 0x00 21. " INTPND_117 ,Interrupt Pending Bit 117" "Not Source,Source" bitfld.long 0x00 20. " INTPND_116 ,Interrupt Pending Bit 116" "Not Source,Source" textline " " bitfld.long 0x00 19. " INTPND_115 ,Interrupt Pending Bit 115" "Not Source,Source" bitfld.long 0x00 18. " INTPND_114 ,Interrupt Pending Bit 114" "Not Source,Source" bitfld.long 0x00 17. " INTPND_113 ,Interrupt Pending Bit 113" "Not Source,Source" bitfld.long 0x00 16. " INTPND_112 ,Interrupt Pending Bit 112" "Not Source,Source" textline " " bitfld.long 0x00 15. " INTPND_111 ,Interrupt Pending Bit 111" "Not Source,Source" bitfld.long 0x00 14. " INTPND_110 ,Interrupt Pending Bit 110" "Not Source,Source" bitfld.long 0x00 13. " INTPND_109 ,Interrupt Pending Bit 109" "Not Source,Source" bitfld.long 0x00 12. " INTPND_108 ,Interrupt Pending Bit 108" "Not Source,Source" textline " " bitfld.long 0x00 11. " INTPND_107 ,Interrupt Pending Bit 107" "Not Source,Source" bitfld.long 0x00 10. " INTPND_106 ,Interrupt Pending Bit 106" "Not Source,Source" bitfld.long 0x00 9. " INTPND_105 ,Interrupt Pending Bit 105" "Not Source,Source" bitfld.long 0x00 8. " INTPND_104 ,Interrupt Pending Bit 104" "Not Source,Source" textline " " bitfld.long 0x00 7. " INTPND_103 ,Interrupt Pending Bit 103" "Not Source,Source" bitfld.long 0x00 6. " INTPND_102 ,Interrupt Pending Bit 102" "Not Source,Source" bitfld.long 0x00 5. " INTPND_101 ,Interrupt Pending Bit 101" "Not Source,Source" bitfld.long 0x00 4. " INTPND_100 ,Interrupt Pending Bit 100" "Not Source,Source" textline " " bitfld.long 0x00 3. " INTPND_99 ,Interrupt Pending Bit 99" "Not Source,Source" bitfld.long 0x00 2. " INTPND_98 ,Interrupt Pending Bit 98" "Not Source,Source" bitfld.long 0x00 1. " INTPND_97 ,Interrupt Pending Bit 97" "Not Source,Source" bitfld.long 0x00 0. " INTPND_96 ,Interrupt Pending Bit 96" "Not Source,Source" rgroup.long 0x0C0++0x03 line.long 0x00 "DCAN_MSGVAL_X,Message Valid X Register" bitfld.long 0x00 14.--15. " MSGVALREG8 , MsgValReg8" "0,1,2,3" bitfld.long 0x00 12.--13. " MSGVALREG7 , MsgValReg7" "0,1,2,3" bitfld.long 0x00 10.--11. " MSGVALREG6 , MsgValReg6" "0,1,2,3" bitfld.long 0x00 8.--9. " MSGVALREG5 , MsgValReg5" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " MSGVALREG4 , MsgValReg4" "0,1,2,3" bitfld.long 0x00 4.--5. " MSGVALREG3 , MsgValReg3" "0,1,2,3" bitfld.long 0x00 2.--3. " MSGVALREG2 , MsgValReg2" "0,1,2,3" bitfld.long 0x00 0.--1. " MSGVALREG1 , MsgValReg1" "0,1,2,3" rgroup.long 0x0C4++0x03 line.long 0x00 "DCAN_MSGVAL12,Message Valid Register 12" bitfld.long 0x00 31. " MSGVAL_31 ,Message valid bit 31" "Not valid,Valid" bitfld.long 0x00 30. " MSGVAL_30 ,Message valid bit 30" "Not valid,Valid" bitfld.long 0x00 29. " MSGVAL_29 ,Message valid bit 29" "Not valid,Valid" bitfld.long 0x00 28. " MSGVAL_28 ,Message valid bit 28" "Not valid,Valid" textline " " bitfld.long 0x00 27. " MSGVAL_27 ,Message valid bit 27" "Not valid,Valid" bitfld.long 0x00 26. " MSGVAL_26 ,Message valid bit 26" "Not valid,Valid" bitfld.long 0x00 25. " MSGVAL_25 ,Message valid bit 25" "Not valid,Valid" bitfld.long 0x00 24. " MSGVAL_24 ,Message valid bit 24" "Not valid,Valid" textline " " bitfld.long 0x00 23. " MSGVAL_23 ,Message valid bit 23" "Not valid,Valid" bitfld.long 0x00 22. " MSGVAL_22 ,Message valid bit 22" "Not valid,Valid" bitfld.long 0x00 21. " MSGVAL_21 ,Message valid bit 21" "Not valid,Valid" bitfld.long 0x00 20. " MSGVAL_20 ,Message valid bit 20" "Not valid,Valid" textline " " bitfld.long 0x00 19. " MSGVAL_19 ,Message valid bit 19" "Not valid,Valid" bitfld.long 0x00 18. " MSGVAL_18 ,Message valid bit 18" "Not valid,Valid" bitfld.long 0x00 17. " MSGVAL_17 ,Message valid bit 17" "Not valid,Valid" bitfld.long 0x00 16. " MSGVAL_16 ,Message valid bit 16" "Not valid,Valid" textline " " bitfld.long 0x00 15. " MSGVAL_15 ,Message valid bit 15" "Not valid,Valid" bitfld.long 0x00 14. " MSGVAL_14 ,Message valid bit 14" "Not valid,Valid" bitfld.long 0x00 13. " MSGVAL_13 ,Message valid bit 13" "Not valid,Valid" bitfld.long 0x00 12. " MSGVAL_12 ,Message valid bit 12" "Not valid,Valid" textline " " bitfld.long 0x00 11. " MSGVAL_11 ,Message valid bit 11" "Not valid,Valid" bitfld.long 0x00 10. " MSGVAL_10 ,Message valid bit 10" "Not valid,Valid" bitfld.long 0x00 9. " MSGVAL_9 ,Message valid bit 9" "Not valid,Valid" bitfld.long 0x00 8. " MSGVAL_8 ,Message valid bit 8" "Not valid,Valid" textline " " bitfld.long 0x00 7. " MSGVAL_7 ,Message valid bit 7" "Not valid,Valid" bitfld.long 0x00 6. " MSGVAL_6 ,Message valid bit 6" "Not valid,Valid" bitfld.long 0x00 5. " MSGVAL_5 ,Message valid bit 5" "Not valid,Valid" bitfld.long 0x00 4. " MSGVAL_4 ,Message valid bit 4" "Not valid,Valid" textline " " bitfld.long 0x00 3. " MSGVAL_3 ,Message valid bit 3" "Not valid,Valid" bitfld.long 0x00 2. " MSGVAL_2 ,Message valid bit 2" "Not valid,Valid" bitfld.long 0x00 1. " MSGVAL_1 ,Message valid bit 1" "Not valid,Valid" bitfld.long 0x00 0. " MSGVAL_0 ,Message valid bit 0" "Not valid,Valid" rgroup.long 0x0C8++0x03 line.long 0x00 "DCAN_MSGVAL34,Message Valid Register 34" bitfld.long 0x00 31. " MSGVAL_63 ,Message valid bit 63" "Not valid,Valid" bitfld.long 0x00 30. " MSGVAL_62 ,Message valid bit 62" "Not valid,Valid" bitfld.long 0x00 29. " MSGVAL_61 ,Message valid bit 61" "Not valid,Valid" bitfld.long 0x00 28. " MSGVAL_60 ,Message valid bit 60" "Not valid,Valid" textline " " bitfld.long 0x00 27. " MSGVAL_59 ,Message valid bit 59" "Not valid,Valid" bitfld.long 0x00 26. " MSGVAL_58 ,Message valid bit 58" "Not valid,Valid" bitfld.long 0x00 25. " MSGVAL_57 ,Message valid bit 57" "Not valid,Valid" bitfld.long 0x00 24. " MSGVAL_56 ,Message valid bit 56" "Not valid,Valid" textline " " bitfld.long 0x00 23. " MSGVAL_55 ,Message valid bit 55" "Not valid,Valid" bitfld.long 0x00 22. " MSGVAL_54 ,Message valid bit 54" "Not valid,Valid" bitfld.long 0x00 21. " MSGVAL_53 ,Message valid bit 53" "Not valid,Valid" bitfld.long 0x00 20. " MSGVAL_52 ,Message valid bit 52" "Not valid,Valid" textline " " bitfld.long 0x00 19. " MSGVAL_51 ,Message valid bit 51" "Not valid,Valid" bitfld.long 0x00 18. " MSGVAL_50 ,Message valid bit 50" "Not valid,Valid" bitfld.long 0x00 17. " MSGVAL_49 ,Message valid bit 49" "Not valid,Valid" bitfld.long 0x00 16. " MSGVAL_48 ,Message valid bit 48" "Not valid,Valid" textline " " bitfld.long 0x00 15. " MSGVAL_47 ,Message valid bit 47" "Not valid,Valid" bitfld.long 0x00 14. " MSGVAL_46 ,Message valid bit 46" "Not valid,Valid" bitfld.long 0x00 13. " MSGVAL_45 ,Message valid bit 45" "Not valid,Valid" bitfld.long 0x00 12. " MSGVAL_44 ,Message valid bit 44" "Not valid,Valid" textline " " bitfld.long 0x00 11. " MSGVAL_43 ,Message valid bit 43" "Not valid,Valid" bitfld.long 0x00 10. " MSGVAL_42 ,Message valid bit 42" "Not valid,Valid" bitfld.long 0x00 9. " MSGVAL_41 ,Message valid bit 41" "Not valid,Valid" bitfld.long 0x00 8. " MSGVAL_40 ,Message valid bit 40" "Not valid,Valid" textline " " bitfld.long 0x00 7. " MSGVAL_39 ,Message valid bit 39" "Not valid,Valid" bitfld.long 0x00 6. " MSGVAL_38 ,Message valid bit 38" "Not valid,Valid" bitfld.long 0x00 5. " MSGVAL_37 ,Message valid bit 37" "Not valid,Valid" bitfld.long 0x00 4. " MSGVAL_36 ,Message valid bit 36" "Not valid,Valid" textline " " bitfld.long 0x00 3. " MSGVAL_35 ,Message valid bit 35" "Not valid,Valid" bitfld.long 0x00 2. " MSGVAL_34 ,Message valid bit 34" "Not valid,Valid" bitfld.long 0x00 1. " MSGVAL_33 ,Message valid bit 33" "Not valid,Valid" bitfld.long 0x00 0. " MSGVAL_32 ,Message valid bit 32" "Not valid,Valid" rgroup.long 0x0CC++0x03 line.long 0x00 "DCAN_MSGVAL56,Message Valid Register 56" bitfld.long 0x00 31. " MSGVAL_95 ,Message valid bit 95" "Not valid,Valid" bitfld.long 0x00 30. " MSGVAL_94 ,Message valid bit 94" "Not valid,Valid" bitfld.long 0x00 29. " MSGVAL_93 ,Message valid bit 93" "Not valid,Valid" bitfld.long 0x00 28. " MSGVAL_92 ,Message valid bit 92" "Not valid,Valid" textline " " bitfld.long 0x00 27. " MSGVAL_91 ,Message valid bit 91" "Not valid,Valid" bitfld.long 0x00 26. " MSGVAL_90 ,Message valid bit 90" "Not valid,Valid" bitfld.long 0x00 25. " MSGVAL_89 ,Message valid bit 89" "Not valid,Valid" bitfld.long 0x00 24. " MSGVAL_88 ,Message valid bit 88" "Not valid,Valid" textline " " bitfld.long 0x00 23. " MSGVAL_87 ,Message valid bit 87" "Not valid,Valid" bitfld.long 0x00 22. " MSGVAL_86 ,Message valid bit 86" "Not valid,Valid" bitfld.long 0x00 21. " MSGVAL_85 ,Message valid bit 85" "Not valid,Valid" bitfld.long 0x00 20. " MSGVAL_84 ,Message valid bit 84" "Not valid,Valid" textline " " bitfld.long 0x00 19. " MSGVAL_83 ,Message valid bit 83" "Not valid,Valid" bitfld.long 0x00 18. " MSGVAL_82 ,Message valid bit 82" "Not valid,Valid" bitfld.long 0x00 17. " MSGVAL_81 ,Message valid bit 81" "Not valid,Valid" bitfld.long 0x00 16. " MSGVAL_80 ,Message valid bit 80" "Not valid,Valid" textline " " bitfld.long 0x00 15. " MSGVAL_79 ,Message valid bit 79" "Not valid,Valid" bitfld.long 0x00 14. " MSGVAL_78 ,Message valid bit 78" "Not valid,Valid" bitfld.long 0x00 13. " MSGVAL_77 ,Message valid bit 77" "Not valid,Valid" bitfld.long 0x00 12. " MSGVAL_76 ,Message valid bit 76" "Not valid,Valid" textline " " bitfld.long 0x00 11. " MSGVAL_75 ,Message valid bit 75" "Not valid,Valid" bitfld.long 0x00 10. " MSGVAL_74 ,Message valid bit 74" "Not valid,Valid" bitfld.long 0x00 9. " MSGVAL_73 ,Message valid bit 73" "Not valid,Valid" bitfld.long 0x00 8. " MSGVAL_72 ,Message valid bit 72" "Not valid,Valid" textline " " bitfld.long 0x00 7. " MSGVAL_71 ,Message valid bit 71" "Not valid,Valid" bitfld.long 0x00 6. " MSGVAL_70 ,Message valid bit 70" "Not valid,Valid" bitfld.long 0x00 5. " MSGVAL_69 ,Message valid bit 69" "Not valid,Valid" bitfld.long 0x00 4. " MSGVAL_68 ,Message valid bit 68" "Not valid,Valid" textline " " bitfld.long 0x00 3. " MSGVAL_67 ,Message valid bit 67" "Not valid,Valid" bitfld.long 0x00 2. " MSGVAL_66 ,Message valid bit 66" "Not valid,Valid" bitfld.long 0x00 1. " MSGVAL_65 ,Message valid bit 65" "Not valid,Valid" bitfld.long 0x00 0. " MSGVAL_64 ,Message valid bit 64" "Not valid,Valid" rgroup.long 0x0D0++0x03 line.long 0x00 "DCAN_MSGVAL78,Message Valid Register 78" bitfld.long 0x00 31. " MSGVAL_127 ,Message valid bit 127" "Not valid,Valid" bitfld.long 0x00 30. " MSGVAL_126 ,Message valid bit 126" "Not valid,Valid" bitfld.long 0x00 29. " MSGVAL_125 ,Message valid bit 125" "Not valid,Valid" bitfld.long 0x00 28. " MSGVAL_124 ,Message valid bit 124" "Not valid,Valid" textline " " bitfld.long 0x00 27. " MSGVAL_123 ,Message valid bit 123" "Not valid,Valid" bitfld.long 0x00 26. " MSGVAL_122 ,Message valid bit 122" "Not valid,Valid" bitfld.long 0x00 25. " MSGVAL_121 ,Message valid bit 121" "Not valid,Valid" bitfld.long 0x00 24. " MSGVAL_120 ,Message valid bit 120" "Not valid,Valid" textline " " bitfld.long 0x00 23. " MSGVAL_119 ,Message valid bit 119" "Not valid,Valid" bitfld.long 0x00 22. " MSGVAL_118 ,Message valid bit 118" "Not valid,Valid" bitfld.long 0x00 21. " MSGVAL_117 ,Message valid bit 117" "Not valid,Valid" bitfld.long 0x00 20. " MSGVAL_116 ,Message valid bit 116" "Not valid,Valid" textline " " bitfld.long 0x00 19. " MSGVAL_115 ,Message valid bit 115" "Not valid,Valid" bitfld.long 0x00 18. " MSGVAL_114 ,Message valid bit 114" "Not valid,Valid" bitfld.long 0x00 17. " MSGVAL_113 ,Message valid bit 113" "Not valid,Valid" bitfld.long 0x00 16. " MSGVAL_112 ,Message valid bit 112" "Not valid,Valid" textline " " bitfld.long 0x00 15. " MSGVAL_111 ,Message valid bit 111" "Not valid,Valid" bitfld.long 0x00 14. " MSGVAL_110 ,Message valid bit 110" "Not valid,Valid" bitfld.long 0x00 13. " MSGVAL_109 ,Message valid bit 109" "Not valid,Valid" bitfld.long 0x00 12. " MSGVAL_108 ,Message valid bit 108" "Not valid,Valid" textline " " bitfld.long 0x00 11. " MSGVAL_107 ,Message valid bit 107" "Not valid,Valid" bitfld.long 0x00 10. " MSGVAL_106 ,Message valid bit 106" "Not valid,Valid" bitfld.long 0x00 9. " MSGVAL_105 ,Message valid bit 105" "Not valid,Valid" bitfld.long 0x00 8. " MSGVAL_104 ,Message valid bit 104" "Not valid,Valid" textline " " bitfld.long 0x00 7. " MSGVAL_103 ,Message valid bit 103" "Not valid,Valid" bitfld.long 0x00 6. " MSGVAL_102 ,Message valid bit 102" "Not valid,Valid" bitfld.long 0x00 5. " MSGVAL_101 ,Message valid bit 101" "Not valid,Valid" bitfld.long 0x00 4. " MSGVAL_100 ,Message valid bit 100" "Not valid,Valid" textline " " bitfld.long 0x00 3. " MSGVAL_99 ,Message valid bit 99" "Not valid,Valid" bitfld.long 0x00 2. " MSGVAL_98 ,Message valid bit 98" "Not valid,Valid" bitfld.long 0x00 1. " MSGVAL_97 ,Message valid bit 97" "Not valid,Valid" bitfld.long 0x00 0. " MSGVAL_96 ,Message valid bit 96" "Not valid,Valid" rgroup.long 0x0D8++0x03 line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer Register 12" bitfld.long 0x00 31. " INTMUX_31 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 31" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX_30 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 30" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX_29 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 29" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTMUX_28 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 28" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTMUX_27 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 27" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX_26 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 26" "DCAN0INT,DCAN1INT" bitfld.long 0x00 25. " INTMUX_25 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 25" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX_24 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 24" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTMUX_23 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 23" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTMUX_22 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 22" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX_21 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 21" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX_20 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 20" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX_19 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 19" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX_18 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 18" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX_17 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 17" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTMUX_16 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 16" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTMUX_15 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 15" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX_14 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 14" "DCAN0INT,DCAN1INT" bitfld.long 0x00 13. " INTMUX_13 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 13" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX_12 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 12" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTMUX_11 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 11" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTMUX_10 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 10" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX_9 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 9" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX_8 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 8" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX_7 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 7" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX_6 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 6" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX_5 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 5" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTMUX_4 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 4" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTMUX_3 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 3" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX_2 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 2" "DCAN0INT,DCAN1INT" bitfld.long 0x00 1. " INTMUX_1 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 1" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX_0 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 0" "DCAN0INT,DCAN1INT" rgroup.long 0x0DC++0x03 line.long 0x00 "DCAN_INTMUX34,Interrupt Multiplexer Register 34" bitfld.long 0x00 31. " INTMUX_63 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 63" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX_62 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 62" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX_61 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 61" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTMUX_60 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 60" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTMUX_59 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 59" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX_58 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 58" "DCAN0INT,DCAN1INT" bitfld.long 0x00 25. " INTMUX_57 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 57" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX_56 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 56" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTMUX_55 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 55" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTMUX_54 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 54" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX_53 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 53" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX_52 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 52" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX_51 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 51" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX_50 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 50" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX_49 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 49" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTMUX_48 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 48" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTMUX_47 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 47" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX_46 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 46" "DCAN0INT,DCAN1INT" bitfld.long 0x00 13. " INTMUX_45 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 45" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX_44 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 44" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTMUX_43 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 43" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTMUX_42 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 42" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX_41 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 41" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX_40 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 40" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX_39 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 39" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX_38 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 38" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX_37 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 37" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTMUX_36 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 36" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTMUX_35 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 35" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX_34 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 34" "DCAN0INT,DCAN1INT" bitfld.long 0x00 1. " INTMUX_33 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 33" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX_32 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 32" "DCAN0INT,DCAN1INT" rgroup.long 0x0E0++0x03 line.long 0x00 "DCAN_INTMUX56,Interrupt Multiplexer Register 56" bitfld.long 0x00 31. " INTMUX_95 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 95" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX_94 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 94" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX_93 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 93" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTMUX_92 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 92" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTMUX_91 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 91" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX_90 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 90" "DCAN0INT,DCAN1INT" bitfld.long 0x00 25. " INTMUX_89 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 89" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX_88 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 88" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTMUX_87 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 87" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTMUX_86 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 86" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX_85 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 85" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX_84 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 84" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX_83 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 83" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX_82 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 82" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX_81 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 81" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTMUX_80 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 80" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTMUX_79 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 79" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX_78 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 78" "DCAN0INT,DCAN1INT" bitfld.long 0x00 13. " INTMUX_77 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 77" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX_76 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 76" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTMUX_75 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 75" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTMUX_74 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 74" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX_73 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 73" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX_72 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 72" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX_71 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 71" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX_70 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 70" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX_69 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 69" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTMUX_68 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 68" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTMUX_67 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 67" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX_66 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 66" "DCAN0INT,DCAN1INT" bitfld.long 0x00 1. " INTMUX_65 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 65" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX_64 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 64" "DCAN0INT,DCAN1INT" rgroup.long 0x0E4++0x03 line.long 0x00 "DCAN_INTMUX78,Interrupt Multiplexer Register 78" bitfld.long 0x00 31. " INTMUX_127 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 127" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX_126 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 126" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX_125 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 125" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTMUX_124 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 124" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTMUX_123 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 123" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX_122 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 122" "DCAN0INT,DCAN1INT" bitfld.long 0x00 25. " INTMUX_121 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 121" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX_120 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 120" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTMUX_119 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 119" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTMUX_118 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 118" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX_117 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 117" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX_116 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 116" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX_115 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 115" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX_114 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 114" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX_113 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 113" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTMUX_112 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 112" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTMUX_111 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 111" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX_110 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 110" "DCAN0INT,DCAN1INT" bitfld.long 0x00 13. " INTMUX_109 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 109" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX_108 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 108" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTMUX_107 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 107" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTMUX_106 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 106" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX_105 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 105" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX_104 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 104" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX_103 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 103" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX_102 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 102" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX_101 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 101" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTMUX_100 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 100" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTMUX_99 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 99" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX_98 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 98" "DCAN0INT,DCAN1INT" bitfld.long 0x00 1. " INTMUX_97 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 97" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX_96 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 96" "DCAN0INT,DCAN1INT" if (((d.l(ad:0x481CC000+0x100))&0x8000)==0x8000) //this.BUSY== "BUSY" rgroup.long 0x100++0x03 line.long 0x00 "DCAN_IF1CMD,IF1 Command Registers" bitfld.long 0x00 23. " WR_RD ,Write/Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred" bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred" bitfld.long 0x00 20. " CTRL ,Access control bits" "Not changed,Transferred" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not clear,Clear" bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Clear" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0 to 3" "Not changed,Transferred" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4 to 7" "Not changed,Transferred" textline " " bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent request,Req. after completed" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer" rgroup.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" else group.long 0x100++0x03 line.long 0x00 "DCAN_IF1CMD,IF1 Command Registers" bitfld.long 0x00 23. " WR_RD ,Write/Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred" bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred" bitfld.long 0x00 20. " CTRL ,Access control bits" "Not changed,Transferred" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not clear,Clear" bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Clear" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0 to 3" "Not changed,Transferred" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4 to 7" "Not changed,Transferred" textline " " bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent request,Req. after completed" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer" group.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" endif if (((d.l(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((d.l(ad:0x481CC000+0x108))&0x40000000)==0x40000000) rgroup.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((d.l(ad:0x481CC000+0x108))&0x40000000)==0x00000000) rgroup.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((d.l(ad:0x481CC000+0x108))&0x40000000)==0x40000000) group.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((d.l(ad:0x481CC000+0x108))&0x40000000)==0x00000000) group.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" endif if (((d.l(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((d.l(ad:0x481CC000+0x108))&0x20000000)==0x20000000) group.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((d.l(ad:0x481CC000+0x108))&0x20000000)==0x00000000) group.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((d.l(ad:0x481CC000+0x108))&0x20000000)==0x20000000) rgroup.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((d.l(ad:0x481CC000+0x108))&0x20000000)==0x00000000) rgroup.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x110++0x03 line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x114++0x03 line.long 0x00 "DCAN_IF1DATB,IF1 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" if (((d.l(ad:0x481CC000+0x120))&0x8000)==0x8000) //this.BUSY== "BUSY" rgroup.long 0x120++0x03 line.long 0x00 "DCAN_IF2CMD,IF2 Command Registers" bitfld.long 0x00 23. " WR_RD ,Write/Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred" bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred" bitfld.long 0x00 20. " CTRL ,Access control bits" "Not changed,Transferred" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not clear,Clear" bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Clear" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0 to 3" "Not changed,Transferred" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4 to 7" "Not changed,Transferred" textline " " bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent request,Req. after completed" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer" rgroup.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" else group.long 0x120++0x03 line.long 0x00 "DCAN_IF2CMD,IF2 Command Registers" bitfld.long 0x00 23. " WR_RD ,Write/Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred" bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred" bitfld.long 0x00 20. " CTRL ,Access control bits" "Not changed,Transferred" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not clear,Clear" bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Clear" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0 to 3" "Not changed,Transferred" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4 to 7" "Not changed,Transferred" textline " " bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent request,Req. after completed" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer" group.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" endif if (((d.l(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((d.l(ad:0x481CC000+0x128))&0x40000000)==0x40000000) rgroup.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((d.l(ad:0x481CC000+0x128))&0x40000000)==0x00000000) rgroup.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((d.l(ad:0x481CC000+0x128))&0x40000000)==0x40000000) group.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((d.l(ad:0x481CC000+0x128))&0x40000000)==0x00000000) group.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" endif if (((d.l(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((d.l(ad:0x481CC000+0x128))&0x20000000)==0x20000000) group.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((d.l(ad:0x481CC000+0x128))&0x20000000)==0x00000000) group.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((d.l(ad:0x481CC000+0x128))&0x20000000)==0x20000000) rgroup.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((d.l(ad:0x481CC000+0x128))&0x20000000)==0x00000000) rgroup.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x130++0x03 line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x134++0x03 line.long 0x00 "DCAN_IF2DATB,IF2 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x140++0x03 line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register" rbitfld.long 0x00 15. " IF3_UPD ,IF3 Update Data" "Not loaded,New data loaded" rbitfld.long 0x00 12. " IF3_SDB ,IF3 Status of Data B read access" "Not available,Available" rbitfld.long 0x00 11. " IF3_SDA ,IF3 Status of Data A read access" "Not available,Available" textline " " rbitfld.long 0x00 10. " IF3_SC ,IF3 Status of control bits read access" "Not available,Available" rbitfld.long 0x00 9. " IF3_SA ,IF3 Status of Arbitration data read access" "Not available,Available" rbitfld.long 0x00 8. " IF3_SM ,IF3 Status of Mask data read access" "Not available,Available" textline " " bitfld.long 0x00 4. " DATAB ,Data B read observation" "Not read,Read" bitfld.long 0x00 3. " DATAA ,Data A read observation" "Not read,Read" bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "Not read,Read" textline " " bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "Not read,Read" bitfld.long 0x00 0. " MASK ,Mask data read observation" "Not read,Read" rgroup.long 0x144++0x03 line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register" rbitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" rbitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" if (((d.l(ad:0x481CC000+0x148))&0x40000000)==0x0000) rgroup.long 0x148++0x03 line.long 0x00 "DCAN_IF3ARB,IF3 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" else rgroup.long 0x148++0x03 line.long 0x00 "DCAN_IF3ARB,IF3 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" endif rgroup.long 0x14C++0x03 line.long 0x00 "DCAN_IF3MCTL,IF3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x150++0x03 line.long 0x00 "DCAN_IF3DATA,IF3 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" rgroup.long 0x154++0x03 line.long 0x00 "DCAN_IF3DATB,IF3 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x160++0x03 line.long 0x00 "DCAN_IF3UPD12,IF3 Update Enable Register 12" bitfld.long 0x00 31. " IF3UPDEN_31 ,IF3 Update Enabled bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDEN_30 ,IF3 Update Enabled bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDEN_29 ,IF3 Update Enabled bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDEN_28 ,IF3 Update Enabled bit 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDEN_27 ,IF3 Update Enabled bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDEN_26 ,IF3 Update Enabled bit 26" "Disabled,Enabled" bitfld.long 0x00 25. " IF3UPDEN_25 ,IF3 Update Enabled bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDEN_24 ,IF3 Update Enabled bit 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDEN_23 ,IF3 Update Enabled bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDEN_22 ,IF3 Update Enabled bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDEN_21 ,IF3 Update Enabled bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDEN_20 ,IF3 Update Enabled bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDEN_19 ,IF3 Update Enabled bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDEN_18 ,IF3 Update Enabled bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDEN_17 ,IF3 Update Enabled bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDEN_16 ,IF3 Update Enabled bit 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDEN_15 ,IF3 Update Enabled bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDEN_14 ,IF3 Update Enabled bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " IF3UPDEN_13 ,IF3 Update Enabled bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDEN_12 ,IF3 Update Enabled bit 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDEN_11 ,IF3 Update Enabled bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDEN_10 ,IF3 Update Enabled bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDEN_9 ,IF3 Update Enabled bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDEN_8 ,IF3 Update Enabled bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDEN_7 ,IF3 Update Enabled bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDEN_6 ,IF3 Update Enabled bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDEN_5 ,IF3 Update Enabled bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDEN_4 ,IF3 Update Enabled bit 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDEN_3 ,IF3 Update Enabled bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDEN_2 ,IF3 Update Enabled bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " IF3UPDEN_1 ,IF3 Update Enabled bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDEN_0 ,IF3 Update Enabled bit 0" "Disabled,Enabled" group.long 0x164++0x03 line.long 0x00 "DCAN_IF3UPD34,IF3 Update Enable Register 34" bitfld.long 0x00 31. " IF3UPDEN_63 ,IF3 Update Enabled bit 63" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDEN_62 ,IF3 Update Enabled bit 62" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDEN_61 ,IF3 Update Enabled bit 61" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDEN_60 ,IF3 Update Enabled bit 60" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDEN_59 ,IF3 Update Enabled bit 59" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDEN_58 ,IF3 Update Enabled bit 58" "Disabled,Enabled" bitfld.long 0x00 25. " IF3UPDEN_57 ,IF3 Update Enabled bit 57" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDEN_56 ,IF3 Update Enabled bit 56" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDEN_55 ,IF3 Update Enabled bit 55" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDEN_54 ,IF3 Update Enabled bit 54" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDEN_53 ,IF3 Update Enabled bit 53" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDEN_52 ,IF3 Update Enabled bit 52" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDEN_51 ,IF3 Update Enabled bit 51" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDEN_50 ,IF3 Update Enabled bit 50" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDEN_49 ,IF3 Update Enabled bit 49" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDEN_48 ,IF3 Update Enabled bit 48" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDEN_47 ,IF3 Update Enabled bit 47" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDEN_46 ,IF3 Update Enabled bit 46" "Disabled,Enabled" bitfld.long 0x00 13. " IF3UPDEN_45 ,IF3 Update Enabled bit 45" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDEN_44 ,IF3 Update Enabled bit 44" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDEN_43 ,IF3 Update Enabled bit 43" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDEN_42 ,IF3 Update Enabled bit 42" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDEN_41 ,IF3 Update Enabled bit 41" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDEN_40 ,IF3 Update Enabled bit 40" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDEN_39 ,IF3 Update Enabled bit 39" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDEN_38 ,IF3 Update Enabled bit 38" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDEN_37 ,IF3 Update Enabled bit 37" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDEN_36 ,IF3 Update Enabled bit 36" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDEN_35 ,IF3 Update Enabled bit 35" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDEN_34 ,IF3 Update Enabled bit 34" "Disabled,Enabled" bitfld.long 0x00 1. " IF3UPDEN_33 ,IF3 Update Enabled bit 33" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDEN_32 ,IF3 Update Enabled bit 32" "Disabled,Enabled" group.long 0x168++0x03 line.long 0x00 "DCAN_IF3UPD56,IF3 Update Enable Register 56" bitfld.long 0x00 31. " IF3UPDEN_95 ,IF3 Update Enabled bit 95" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDEN_94 ,IF3 Update Enabled bit 94" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDEN_93 ,IF3 Update Enabled bit 93" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDEN_92 ,IF3 Update Enabled bit 92" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDEN_91 ,IF3 Update Enabled bit 91" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDEN_90 ,IF3 Update Enabled bit 90" "Disabled,Enabled" bitfld.long 0x00 25. " IF3UPDEN_89 ,IF3 Update Enabled bit 89" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDEN_88 ,IF3 Update Enabled bit 88" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDEN_87 ,IF3 Update Enabled bit 87" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDEN_86 ,IF3 Update Enabled bit 86" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDEN_85 ,IF3 Update Enabled bit 85" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDEN_84 ,IF3 Update Enabled bit 84" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDEN_83 ,IF3 Update Enabled bit 83" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDEN_82 ,IF3 Update Enabled bit 82" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDEN_81 ,IF3 Update Enabled bit 81" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDEN_80 ,IF3 Update Enabled bit 80" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDEN_79 ,IF3 Update Enabled bit 79" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDEN_78 ,IF3 Update Enabled bit 78" "Disabled,Enabled" bitfld.long 0x00 13. " IF3UPDEN_77 ,IF3 Update Enabled bit 77" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDEN_76 ,IF3 Update Enabled bit 76" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDEN_75 ,IF3 Update Enabled bit 75" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDEN_74 ,IF3 Update Enabled bit 74" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDEN_73 ,IF3 Update Enabled bit 73" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDEN_72 ,IF3 Update Enabled bit 72" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDEN_71 ,IF3 Update Enabled bit 71" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDEN_70 ,IF3 Update Enabled bit 70" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDEN_69 ,IF3 Update Enabled bit 69" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDEN_68 ,IF3 Update Enabled bit 68" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDEN_67 ,IF3 Update Enabled bit 67" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDEN_66 ,IF3 Update Enabled bit 66" "Disabled,Enabled" bitfld.long 0x00 1. " IF3UPDEN_65 ,IF3 Update Enabled bit 65" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDEN_64 ,IF3 Update Enabled bit 64" "Disabled,Enabled" group.long 0x16C++0x03 line.long 0x00 "DCAN_IF3UPD78,IF3 Update Enable Register 78" bitfld.long 0x00 31. " IF3UPDEN_127 ,IF3 Update Enabled bit 127" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDEN_126 ,IF3 Update Enabled bit 126" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDEN_125 ,IF3 Update Enabled bit 125" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDEN_124 ,IF3 Update Enabled bit 124" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDEN_123 ,IF3 Update Enabled bit 123" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDEN_122 ,IF3 Update Enabled bit 122" "Disabled,Enabled" bitfld.long 0x00 25. " IF3UPDEN_121 ,IF3 Update Enabled bit 121" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDEN_120 ,IF3 Update Enabled bit 120" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDEN_119 ,IF3 Update Enabled bit 119" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDEN_118 ,IF3 Update Enabled bit 118" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDEN_117 ,IF3 Update Enabled bit 117" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDEN_116 ,IF3 Update Enabled bit 116" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDEN_115 ,IF3 Update Enabled bit 115" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDEN_114 ,IF3 Update Enabled bit 114" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDEN_113 ,IF3 Update Enabled bit 113" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDEN_112 ,IF3 Update Enabled bit 112" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDEN_111 ,IF3 Update Enabled bit 111" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDEN_110 ,IF3 Update Enabled bit 110" "Disabled,Enabled" bitfld.long 0x00 13. " IF3UPDEN_109 ,IF3 Update Enabled bit 109" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDEN_108 ,IF3 Update Enabled bit 108" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDEN_107 ,IF3 Update Enabled bit 107" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDEN_106 ,IF3 Update Enabled bit 106" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDEN_105 ,IF3 Update Enabled bit 105" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDEN_104 ,IF3 Update Enabled bit 104" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDEN_103 ,IF3 Update Enabled bit 103" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDEN_102 ,IF3 Update Enabled bit 102" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDEN_101 ,IF3 Update Enabled bit 101" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDEN_100 ,IF3 Update Enabled bit 100" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDEN_99 ,IF3 Update Enabled bit 99" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDEN_98 ,IF3 Update Enabled bit 98" "Disabled,Enabled" bitfld.long 0x00 1. " IF3UPDEN_97 ,IF3 Update Enabled bit 97" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDEN_96 ,IF3 Update Enabled bit 96" "Disabled,Enabled" if (((d.l(ad:0x481CC000+0x00))&0x01)==0x01) group.long 0x1E0++0x03 line.long 0x00 "DCAN_TIOC,CAN TX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX pull up/pull down select" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO mode,Func. mode" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" rbitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" group.long 0x1E4++0x03 line.long 0x00 "DCAN_RIOC,CAN RX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_RX pull up/pull down select" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,CAN_RX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_RX open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FUNC ,CAN_RX function" "GIO mode,Func. mode" bitfld.long 0x00 2. " DIR ,CAN_RX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_RX data out write" "Low,High" rbitfld.long 0x00 0. " IN ,CAN_RX data in" "Low,High" else rgroup.long 0x1E0++0x03 line.long 0x00 "DCAN_TIOC,CAN TX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX pull up/pull down select" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO mode,Func. mode" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" rbitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" rgroup.long 0x1E4++0x03 line.long 0x00 "DCAN_RIOC,CAN RX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_RX pull up/pull down select" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,CAN_RX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_RX open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FUNC ,CAN_RX function" "GIO mode,Func. mode" bitfld.long 0x00 2. " DIR ,CAN_RX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_RX data out write" "Low,High" rbitfld.long 0x00 0. " IN ,CAN_RX data in" "Low,High" endif width 11. tree.end tree "DCAN 1" base ad:0x481D0000 width 15. group.long 0x000++0x03 line.long 0x00 "DCAN_CTL,CAN Control Register" bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity when in local power-down mode" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "No request,Request" bitfld.long 0x00 20. " DE3 ,Enable DMA request line for IF3" "Disabled,Enabled" bitfld.long 0x00 19. " DE2 ,Enable DMA request line for IF2" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " DE1 ,Enable DMA request line for IF1" "Disabled,Enabled" bitfld.long 0x00 17. " IE1 ,Interrupt line 1 enable" "Disabled,Enabled" rbitfld.long 0x00 16. " INITDBG ,Internal init state while debug access" "No,Yes" bitfld.long 0x00 15. " SWR ,SW reset enable" "No reset,Reset" textline " " bitfld.long 0x00 10.--13. " PMD , Parity on/off" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 9. " ABO ,Auto-Bus-On enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption debug support enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TEST ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 6. " CCE ,Configuration change enable" "Access disabled,Assess enabled" bitfld.long 0x00 5. " DAR ,Disable automatic retransmission" "No,Yes" textline " " bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " SIE ,Status change interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE0 ,Interrupt line 0 enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization" "Normal operation,Entered" hgroup.long 0x004++0x03 hide.long 0x00 "DCAN_ES,Error and Status Register" in rgroup.long 0x008++0x03 line.long 0x00 "DCAN_ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive error passive" "Not passive,Passive" hexmask.long.byte 0x00 8.--14. 1. " REC , Receive error counter" hexmask.long.byte 0x00 0.--7. 1. " TEC , Transmit error counter" if (((d.l(ad:0x481D0000+0x00))&0x40)==0x40)&&(((d.l(ad:0x481D0000+0x00))&0x01)==0x01) //DCAN_CTL.CCE== "Enabled" && DCAN_CTL.INIT== "Entered" group.long 0x00C++0x03 line.long 0x00 "DCAN_BTR,Bit Timing Register" rbitfld.long 0x00 16.--19. " BRPE , Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 12.--14. " TSEG2 , Time segment after the sample point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 , Time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6.--7. " SJW , Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP , Baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x00C++0x03 line.long 0x00 "DCAN_BTR,Bit Timing Register" bitfld.long 0x00 16.--19. " BRPE , Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 , Time segment after the sample point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 , Time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6.--7. " SJW , Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP , Baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif rgroup.long 0x010++0x03 line.long 0x00 "DCAN_INT,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID_23_16 , Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INT0ID_15_0 , Interrupt Identifier" if (((d.l(ad:0x481D0000+0x00))&0x80)==0x80) //DCAN_CTL.TEST== "Enabled" group.long 0x014++0x03 line.long 0x00 "DCAN_TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM direct access enable" "Normal operation,Enabled" bitfld.long 0x00 8. " EXL ,External loopback mode" "Disabled,Enabled" rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" textline " " bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Sample point,Dominant value,Recessive value" bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled" else rgroup.long 0x014++0x03 line.long 0x00 "DCAN_TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM direct access enable" "Normal operation,Enabled" bitfld.long 0x00 8. " EXL ,External loopback mode" "Disabled,Enabled" bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive" textline " " bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Sample point,Dominant value,Recessive value" bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled" endif rgroup.long 0x01C++0x03 line.long 0x00 "DCAN_PERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WORD_NUMBER , Word number where parity error has been detected" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER , Message number" group.long 0x080++0x03 line.long 0x00 "DCAN_ABOTR,Auto-Bus-On Time Register" hexmask.long 0x00 0.--31. 1. " ABO_TIME , Number of OCP clock cycles before a Bus-Off recovery sequence is started by clearing the Init bit" rgroup.long 0x084++0x03 line.long 0x00 "DCAN_TXRQ_X,Transmission Request X Register" bitfld.long 0x00 14.--15. " TXRQSTREG8 , TxRqstReg8" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 , TxRqstReg7" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 , TxRqstReg6" "0,1,2,3" bitfld.long 0x00 8.--9. " TXRQSTREG5 , TxRqstReg5" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " TXRQSTREG4 , TxRqstReg4" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 , TxRqstReg3" "0,1,2,3" bitfld.long 0x00 2.--3. " TXRQSTREG2 , TxRqstReg2" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 , TxRqstReg1" "0,1,2,3" rgroup.long 0x088++0x03 line.long 0x00 "DCAN_TXRQ12,Transmission Request Register 12" bitfld.long 0x00 31. " TXRQS_31 ,Transmission request bit 31" "Not requested,Requested" bitfld.long 0x00 30. " TXRQS_30 ,Transmission request bit 30" "Not requested,Requested" bitfld.long 0x00 29. " TXRQS_29 ,Transmission request bit 29" "Not requested,Requested" bitfld.long 0x00 28. " TXRQS_28 ,Transmission request bit 28" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQS_27 ,Transmission request bit 27" "Not requested,Requested" bitfld.long 0x00 26. " TXRQS_26 ,Transmission request bit 26" "Not requested,Requested" bitfld.long 0x00 25. " TXRQS_25 ,Transmission request bit 25" "Not requested,Requested" bitfld.long 0x00 24. " TXRQS_24 ,Transmission request bit 24" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQS_23 ,Transmission request bit 23" "Not requested,Requested" bitfld.long 0x00 22. " TXRQS_22 ,Transmission request bit 22" "Not requested,Requested" bitfld.long 0x00 21. " TXRQS_21 ,Transmission request bit 21" "Not requested,Requested" bitfld.long 0x00 20. " TXRQS_20 ,Transmission request bit 20" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQS_19 ,Transmission request bit 19" "Not requested,Requested" bitfld.long 0x00 18. " TXRQS_18 ,Transmission request bit 18" "Not requested,Requested" bitfld.long 0x00 17. " TXRQS_17 ,Transmission request bit 17" "Not requested,Requested" bitfld.long 0x00 16. " TXRQS_16 ,Transmission request bit 16" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQS_15 ,Transmission request bit 15" "Not requested,Requested" bitfld.long 0x00 14. " TXRQS_14 ,Transmission request bit 14" "Not requested,Requested" bitfld.long 0x00 13. " TXRQS_13 ,Transmission request bit 13" "Not requested,Requested" bitfld.long 0x00 12. " TXRQS_12 ,Transmission request bit 12" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQS_11 ,Transmission request bit 11" "Not requested,Requested" bitfld.long 0x00 10. " TXRQS_10 ,Transmission request bit 10" "Not requested,Requested" bitfld.long 0x00 9. " TXRQS_9 ,Transmission request bit 9" "Not requested,Requested" bitfld.long 0x00 8. " TXRQS_8 ,Transmission request bit 8" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQS_7 ,Transmission request bit 7" "Not requested,Requested" bitfld.long 0x00 6. " TXRQS_6 ,Transmission request bit 6" "Not requested,Requested" bitfld.long 0x00 5. " TXRQS_5 ,Transmission request bit 5" "Not requested,Requested" bitfld.long 0x00 4. " TXRQS_4 ,Transmission request bit 4" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQS_3 ,Transmission request bit 3" "Not requested,Requested" bitfld.long 0x00 2. " TXRQS_2 ,Transmission request bit 2" "Not requested,Requested" bitfld.long 0x00 1. " TXRQS_1 ,Transmission request bit 1" "Not requested,Requested" bitfld.long 0x00 0. " TXRQS_0 ,Transmission request bit 0" "Not requested,Requested" rgroup.long 0x08C++0x03 line.long 0x00 "DCAN_TXRQ34,Transmission Request Register 34" bitfld.long 0x00 31. " TXRQS_63 ,Transmission request bit 63" "Not requested,Requested" bitfld.long 0x00 30. " TXRQS_62 ,Transmission request bit 62" "Not requested,Requested" bitfld.long 0x00 29. " TXRQS_61 ,Transmission request bit 61" "Not requested,Requested" bitfld.long 0x00 28. " TXRQS_60 ,Transmission request bit 60" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQS_59 ,Transmission request bit 59" "Not requested,Requested" bitfld.long 0x00 26. " TXRQS_58 ,Transmission request bit 58" "Not requested,Requested" bitfld.long 0x00 25. " TXRQS_57 ,Transmission request bit 57" "Not requested,Requested" bitfld.long 0x00 24. " TXRQS_56 ,Transmission request bit 56" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQS_55 ,Transmission request bit 55" "Not requested,Requested" bitfld.long 0x00 22. " TXRQS_54 ,Transmission request bit 54" "Not requested,Requested" bitfld.long 0x00 21. " TXRQS_53 ,Transmission request bit 53" "Not requested,Requested" bitfld.long 0x00 20. " TXRQS_52 ,Transmission request bit 52" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQS_51 ,Transmission request bit 51" "Not requested,Requested" bitfld.long 0x00 18. " TXRQS_50 ,Transmission request bit 50" "Not requested,Requested" bitfld.long 0x00 17. " TXRQS_49 ,Transmission request bit 49" "Not requested,Requested" bitfld.long 0x00 16. " TXRQS_48 ,Transmission request bit 48" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQS_47 ,Transmission request bit 47" "Not requested,Requested" bitfld.long 0x00 14. " TXRQS_46 ,Transmission request bit 46" "Not requested,Requested" bitfld.long 0x00 13. " TXRQS_45 ,Transmission request bit 45" "Not requested,Requested" bitfld.long 0x00 12. " TXRQS_44 ,Transmission request bit 44" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQS_43 ,Transmission request bit 43" "Not requested,Requested" bitfld.long 0x00 10. " TXRQS_42 ,Transmission request bit 42" "Not requested,Requested" bitfld.long 0x00 9. " TXRQS_41 ,Transmission request bit 41" "Not requested,Requested" bitfld.long 0x00 8. " TXRQS_40 ,Transmission request bit 40" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQS_39 ,Transmission request bit 39" "Not requested,Requested" bitfld.long 0x00 6. " TXRQS_38 ,Transmission request bit 38" "Not requested,Requested" bitfld.long 0x00 5. " TXRQS_37 ,Transmission request bit 37" "Not requested,Requested" bitfld.long 0x00 4. " TXRQS_36 ,Transmission request bit 36" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQS_35 ,Transmission request bit 35" "Not requested,Requested" bitfld.long 0x00 2. " TXRQS_34 ,Transmission request bit 34" "Not requested,Requested" bitfld.long 0x00 1. " TXRQS_33 ,Transmission request bit 33" "Not requested,Requested" bitfld.long 0x00 0. " TXRQS_32 ,Transmission request bit 32" "Not requested,Requested" rgroup.long 0x090++0x03 line.long 0x00 "DCAN_TXRQ56,Transmission Request Register 56" bitfld.long 0x00 31. " TXRQS_95 ,Transmission request bit 95" "Not requested,Requested" bitfld.long 0x00 30. " TXRQS_94 ,Transmission request bit 94" "Not requested,Requested" bitfld.long 0x00 29. " TXRQS_93 ,Transmission request bit 93" "Not requested,Requested" bitfld.long 0x00 28. " TXRQS_92 ,Transmission request bit 92" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQS_91 ,Transmission request bit 91" "Not requested,Requested" bitfld.long 0x00 26. " TXRQS_90 ,Transmission request bit 90" "Not requested,Requested" bitfld.long 0x00 25. " TXRQS_89 ,Transmission request bit 89" "Not requested,Requested" bitfld.long 0x00 24. " TXRQS_88 ,Transmission request bit 88" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQS_87 ,Transmission request bit 87" "Not requested,Requested" bitfld.long 0x00 22. " TXRQS_86 ,Transmission request bit 86" "Not requested,Requested" bitfld.long 0x00 21. " TXRQS_85 ,Transmission request bit 85" "Not requested,Requested" bitfld.long 0x00 20. " TXRQS_84 ,Transmission request bit 84" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQS_83 ,Transmission request bit 83" "Not requested,Requested" bitfld.long 0x00 18. " TXRQS_82 ,Transmission request bit 82" "Not requested,Requested" bitfld.long 0x00 17. " TXRQS_81 ,Transmission request bit 81" "Not requested,Requested" bitfld.long 0x00 16. " TXRQS_80 ,Transmission request bit 80" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQS_79 ,Transmission request bit 79" "Not requested,Requested" bitfld.long 0x00 14. " TXRQS_78 ,Transmission request bit 78" "Not requested,Requested" bitfld.long 0x00 13. " TXRQS_77 ,Transmission request bit 77" "Not requested,Requested" bitfld.long 0x00 12. " TXRQS_76 ,Transmission request bit 76" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQS_75 ,Transmission request bit 75" "Not requested,Requested" bitfld.long 0x00 10. " TXRQS_74 ,Transmission request bit 74" "Not requested,Requested" bitfld.long 0x00 9. " TXRQS_73 ,Transmission request bit 73" "Not requested,Requested" bitfld.long 0x00 8. " TXRQS_72 ,Transmission request bit 72" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQS_71 ,Transmission request bit 71" "Not requested,Requested" bitfld.long 0x00 6. " TXRQS_70 ,Transmission request bit 70" "Not requested,Requested" bitfld.long 0x00 5. " TXRQS_69 ,Transmission request bit 69" "Not requested,Requested" bitfld.long 0x00 4. " TXRQS_68 ,Transmission request bit 68" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQS_67 ,Transmission request bit 67" "Not requested,Requested" bitfld.long 0x00 2. " TXRQS_66 ,Transmission request bit 66" "Not requested,Requested" bitfld.long 0x00 1. " TXRQS_65 ,Transmission request bit 65" "Not requested,Requested" bitfld.long 0x00 0. " TXRQS_64 ,Transmission request bit 64" "Not requested,Requested" rgroup.long 0x094++0x03 line.long 0x00 "DCAN_TXRQ78,Transmission Request Register 78" bitfld.long 0x00 31. " TXRQS_127 ,Transmission request bit 127" "Not requested,Requested" bitfld.long 0x00 30. " TXRQS_126 ,Transmission request bit 126" "Not requested,Requested" bitfld.long 0x00 29. " TXRQS_125 ,Transmission request bit 125" "Not requested,Requested" bitfld.long 0x00 28. " TXRQS_124 ,Transmission request bit 124" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQS_123 ,Transmission request bit 123" "Not requested,Requested" bitfld.long 0x00 26. " TXRQS_122 ,Transmission request bit 122" "Not requested,Requested" bitfld.long 0x00 25. " TXRQS_121 ,Transmission request bit 121" "Not requested,Requested" bitfld.long 0x00 24. " TXRQS_120 ,Transmission request bit 120" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQS_119 ,Transmission request bit 119" "Not requested,Requested" bitfld.long 0x00 22. " TXRQS_118 ,Transmission request bit 118" "Not requested,Requested" bitfld.long 0x00 21. " TXRQS_117 ,Transmission request bit 117" "Not requested,Requested" bitfld.long 0x00 20. " TXRQS_116 ,Transmission request bit 116" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQS_115 ,Transmission request bit 115" "Not requested,Requested" bitfld.long 0x00 18. " TXRQS_114 ,Transmission request bit 114" "Not requested,Requested" bitfld.long 0x00 17. " TXRQS_113 ,Transmission request bit 113" "Not requested,Requested" bitfld.long 0x00 16. " TXRQS_112 ,Transmission request bit 112" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQS_111 ,Transmission request bit 111" "Not requested,Requested" bitfld.long 0x00 14. " TXRQS_110 ,Transmission request bit 110" "Not requested,Requested" bitfld.long 0x00 13. " TXRQS_109 ,Transmission request bit 109" "Not requested,Requested" bitfld.long 0x00 12. " TXRQS_108 ,Transmission request bit 108" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQS_107 ,Transmission request bit 107" "Not requested,Requested" bitfld.long 0x00 10. " TXRQS_106 ,Transmission request bit 106" "Not requested,Requested" bitfld.long 0x00 9. " TXRQS_105 ,Transmission request bit 105" "Not requested,Requested" bitfld.long 0x00 8. " TXRQS_104 ,Transmission request bit 104" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQS_103 ,Transmission request bit 103" "Not requested,Requested" bitfld.long 0x00 6. " TXRQS_102 ,Transmission request bit 102" "Not requested,Requested" bitfld.long 0x00 5. " TXRQS_101 ,Transmission request bit 101" "Not requested,Requested" bitfld.long 0x00 4. " TXRQS_100 ,Transmission request bit 100" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQS_99 ,Transmission request bit 99" "Not requested,Requested" bitfld.long 0x00 2. " TXRQS_98 ,Transmission request bit 98" "Not requested,Requested" bitfld.long 0x00 1. " TXRQS_97 ,Transmission request bit 97" "Not requested,Requested" bitfld.long 0x00 0. " TXRQS_96 ,Transmission request bit 96" "Not requested,Requested" rgroup.long 0x098++0x03 line.long 0x00 "DCAN_NWDAT_X,New Data X Register" bitfld.long 0x00 14.--15. " NEWDATREG8 , NewDatReg8" "0,1,2,3" bitfld.long 0x00 12.--13. " NEWDATREG7 , NewDatReg7" "0,1,2,3" bitfld.long 0x00 10.--11. " NEWDATREG6 , NewDatReg6" "0,1,2,3" bitfld.long 0x00 8.--9. " NEWDATREG5 , NewDatReg5" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " NEWDATREG4 , NewDatReg4" "0,1,2,3" bitfld.long 0x00 4.--5. " NEWDATREG3 , NewDatReg3" "0,1,2,3" bitfld.long 0x00 2.--3. " NEWDATREG2 , NewDatReg2" "0,1,2,3" bitfld.long 0x00 0.--1. " NEWDATREG1 , NewDatReg1" "0,1,2,3" rgroup.long 0x09C++0x03 line.long 0x00 "DCAN_NWDAT12,New Data Register 12" bitfld.long 0x00 31. " NEWDAT_31 ,New Data Bit 31" "Not new,New" bitfld.long 0x00 30. " NEWDAT_30 ,New Data Bit 30" "Not new,New" bitfld.long 0x00 29. " NEWDAT_29 ,New Data Bit 29" "Not new,New" bitfld.long 0x00 28. " NEWDAT_28 ,New Data Bit 28" "Not new,New" textline " " bitfld.long 0x00 27. " NEWDAT_27 ,New Data Bit 27" "Not new,New" bitfld.long 0x00 26. " NEWDAT_26 ,New Data Bit 26" "Not new,New" bitfld.long 0x00 25. " NEWDAT_25 ,New Data Bit 25" "Not new,New" bitfld.long 0x00 24. " NEWDAT_24 ,New Data Bit 24" "Not new,New" textline " " bitfld.long 0x00 23. " NEWDAT_23 ,New Data Bit 23" "Not new,New" bitfld.long 0x00 22. " NEWDAT_22 ,New Data Bit 22" "Not new,New" bitfld.long 0x00 21. " NEWDAT_21 ,New Data Bit 21" "Not new,New" bitfld.long 0x00 20. " NEWDAT_20 ,New Data Bit 20" "Not new,New" textline " " bitfld.long 0x00 19. " NEWDAT_19 ,New Data Bit 19" "Not new,New" bitfld.long 0x00 18. " NEWDAT_18 ,New Data Bit 18" "Not new,New" bitfld.long 0x00 17. " NEWDAT_17 ,New Data Bit 17" "Not new,New" bitfld.long 0x00 16. " NEWDAT_16 ,New Data Bit 16" "Not new,New" textline " " bitfld.long 0x00 15. " NEWDAT_15 ,New Data Bit 15" "Not new,New" bitfld.long 0x00 14. " NEWDAT_14 ,New Data Bit 14" "Not new,New" bitfld.long 0x00 13. " NEWDAT_13 ,New Data Bit 13" "Not new,New" bitfld.long 0x00 12. " NEWDAT_12 ,New Data Bit 12" "Not new,New" textline " " bitfld.long 0x00 11. " NEWDAT_11 ,New Data Bit 11" "Not new,New" bitfld.long 0x00 10. " NEWDAT_10 ,New Data Bit 10" "Not new,New" bitfld.long 0x00 9. " NEWDAT_9 ,New Data Bit 9" "Not new,New" bitfld.long 0x00 8. " NEWDAT_8 ,New Data Bit 8" "Not new,New" textline " " bitfld.long 0x00 7. " NEWDAT_7 ,New Data Bit 7" "Not new,New" bitfld.long 0x00 6. " NEWDAT_6 ,New Data Bit 6" "Not new,New" bitfld.long 0x00 5. " NEWDAT_5 ,New Data Bit 5" "Not new,New" bitfld.long 0x00 4. " NEWDAT_4 ,New Data Bit 4" "Not new,New" textline " " bitfld.long 0x00 3. " NEWDAT_3 ,New Data Bit 3" "Not new,New" bitfld.long 0x00 2. " NEWDAT_2 ,New Data Bit 2" "Not new,New" bitfld.long 0x00 1. " NEWDAT_1 ,New Data Bit 1" "Not new,New" bitfld.long 0x00 0. " NEWDAT_0 ,New Data Bit 0" "Not new,New" rgroup.long 0x0A0++0x03 line.long 0x00 "DCAN_NWDAT34,New Data Register 34" bitfld.long 0x00 31. " NEWDAT_63 ,New Data Bit 63" "Not new,New" bitfld.long 0x00 30. " NEWDAT_62 ,New Data Bit 62" "Not new,New" bitfld.long 0x00 29. " NEWDAT_61 ,New Data Bit 61" "Not new,New" bitfld.long 0x00 28. " NEWDAT_60 ,New Data Bit 60" "Not new,New" textline " " bitfld.long 0x00 27. " NEWDAT_59 ,New Data Bit 59" "Not new,New" bitfld.long 0x00 26. " NEWDAT_58 ,New Data Bit 58" "Not new,New" bitfld.long 0x00 25. " NEWDAT_57 ,New Data Bit 57" "Not new,New" bitfld.long 0x00 24. " NEWDAT_56 ,New Data Bit 56" "Not new,New" textline " " bitfld.long 0x00 23. " NEWDAT_55 ,New Data Bit 55" "Not new,New" bitfld.long 0x00 22. " NEWDAT_54 ,New Data Bit 54" "Not new,New" bitfld.long 0x00 21. " NEWDAT_53 ,New Data Bit 53" "Not new,New" bitfld.long 0x00 20. " NEWDAT_52 ,New Data Bit 52" "Not new,New" textline " " bitfld.long 0x00 19. " NEWDAT_51 ,New Data Bit 51" "Not new,New" bitfld.long 0x00 18. " NEWDAT_50 ,New Data Bit 50" "Not new,New" bitfld.long 0x00 17. " NEWDAT_49 ,New Data Bit 49" "Not new,New" bitfld.long 0x00 16. " NEWDAT_48 ,New Data Bit 48" "Not new,New" textline " " bitfld.long 0x00 15. " NEWDAT_47 ,New Data Bit 47" "Not new,New" bitfld.long 0x00 14. " NEWDAT_46 ,New Data Bit 46" "Not new,New" bitfld.long 0x00 13. " NEWDAT_45 ,New Data Bit 45" "Not new,New" bitfld.long 0x00 12. " NEWDAT_44 ,New Data Bit 44" "Not new,New" textline " " bitfld.long 0x00 11. " NEWDAT_43 ,New Data Bit 43" "Not new,New" bitfld.long 0x00 10. " NEWDAT_42 ,New Data Bit 42" "Not new,New" bitfld.long 0x00 9. " NEWDAT_41 ,New Data Bit 41" "Not new,New" bitfld.long 0x00 8. " NEWDAT_40 ,New Data Bit 40" "Not new,New" textline " " bitfld.long 0x00 7. " NEWDAT_39 ,New Data Bit 39" "Not new,New" bitfld.long 0x00 6. " NEWDAT_38 ,New Data Bit 38" "Not new,New" bitfld.long 0x00 5. " NEWDAT_37 ,New Data Bit 37" "Not new,New" bitfld.long 0x00 4. " NEWDAT_36 ,New Data Bit 36" "Not new,New" textline " " bitfld.long 0x00 3. " NEWDAT_35 ,New Data Bit 35" "Not new,New" bitfld.long 0x00 2. " NEWDAT_34 ,New Data Bit 34" "Not new,New" bitfld.long 0x00 1. " NEWDAT_33 ,New Data Bit 33" "Not new,New" bitfld.long 0x00 0. " NEWDAT_32 ,New Data Bit 32" "Not new,New" rgroup.long 0x0A4++0x03 line.long 0x00 "DCAN_NWDAT56,New Data Register 56" bitfld.long 0x00 31. " NEWDAT_95 ,New Data Bit 95" "Not new,New" bitfld.long 0x00 30. " NEWDAT_94 ,New Data Bit 94" "Not new,New" bitfld.long 0x00 29. " NEWDAT_93 ,New Data Bit 93" "Not new,New" bitfld.long 0x00 28. " NEWDAT_92 ,New Data Bit 92" "Not new,New" textline " " bitfld.long 0x00 27. " NEWDAT_91 ,New Data Bit 91" "Not new,New" bitfld.long 0x00 26. " NEWDAT_90 ,New Data Bit 90" "Not new,New" bitfld.long 0x00 25. " NEWDAT_89 ,New Data Bit 89" "Not new,New" bitfld.long 0x00 24. " NEWDAT_88 ,New Data Bit 88" "Not new,New" textline " " bitfld.long 0x00 23. " NEWDAT_87 ,New Data Bit 87" "Not new,New" bitfld.long 0x00 22. " NEWDAT_86 ,New Data Bit 86" "Not new,New" bitfld.long 0x00 21. " NEWDAT_85 ,New Data Bit 85" "Not new,New" bitfld.long 0x00 20. " NEWDAT_84 ,New Data Bit 84" "Not new,New" textline " " bitfld.long 0x00 19. " NEWDAT_83 ,New Data Bit 83" "Not new,New" bitfld.long 0x00 18. " NEWDAT_82 ,New Data Bit 82" "Not new,New" bitfld.long 0x00 17. " NEWDAT_81 ,New Data Bit 81" "Not new,New" bitfld.long 0x00 16. " NEWDAT_80 ,New Data Bit 80" "Not new,New" textline " " bitfld.long 0x00 15. " NEWDAT_79 ,New Data Bit 79" "Not new,New" bitfld.long 0x00 14. " NEWDAT_78 ,New Data Bit 78" "Not new,New" bitfld.long 0x00 13. " NEWDAT_77 ,New Data Bit 77" "Not new,New" bitfld.long 0x00 12. " NEWDAT_76 ,New Data Bit 76" "Not new,New" textline " " bitfld.long 0x00 11. " NEWDAT_75 ,New Data Bit 75" "Not new,New" bitfld.long 0x00 10. " NEWDAT_74 ,New Data Bit 74" "Not new,New" bitfld.long 0x00 9. " NEWDAT_73 ,New Data Bit 73" "Not new,New" bitfld.long 0x00 8. " NEWDAT_72 ,New Data Bit 72" "Not new,New" textline " " bitfld.long 0x00 7. " NEWDAT_71 ,New Data Bit 71" "Not new,New" bitfld.long 0x00 6. " NEWDAT_70 ,New Data Bit 70" "Not new,New" bitfld.long 0x00 5. " NEWDAT_69 ,New Data Bit 69" "Not new,New" bitfld.long 0x00 4. " NEWDAT_68 ,New Data Bit 68" "Not new,New" textline " " bitfld.long 0x00 3. " NEWDAT_67 ,New Data Bit 67" "Not new,New" bitfld.long 0x00 2. " NEWDAT_66 ,New Data Bit 66" "Not new,New" bitfld.long 0x00 1. " NEWDAT_65 ,New Data Bit 65" "Not new,New" bitfld.long 0x00 0. " NEWDAT_64 ,New Data Bit 64" "Not new,New" rgroup.long 0x0A8++0x03 line.long 0x00 "DCAN_NWDAT78,New Data Register 78" bitfld.long 0x00 31. " NEWDAT_127 ,New Data Bit 127" "Not new,New" bitfld.long 0x00 30. " NEWDAT_126 ,New Data Bit 126" "Not new,New" bitfld.long 0x00 29. " NEWDAT_125 ,New Data Bit 125" "Not new,New" bitfld.long 0x00 28. " NEWDAT_124 ,New Data Bit 124" "Not new,New" textline " " bitfld.long 0x00 27. " NEWDAT_123 ,New Data Bit 123" "Not new,New" bitfld.long 0x00 26. " NEWDAT_122 ,New Data Bit 122" "Not new,New" bitfld.long 0x00 25. " NEWDAT_121 ,New Data Bit 121" "Not new,New" bitfld.long 0x00 24. " NEWDAT_120 ,New Data Bit 120" "Not new,New" textline " " bitfld.long 0x00 23. " NEWDAT_119 ,New Data Bit 119" "Not new,New" bitfld.long 0x00 22. " NEWDAT_118 ,New Data Bit 118" "Not new,New" bitfld.long 0x00 21. " NEWDAT_117 ,New Data Bit 117" "Not new,New" bitfld.long 0x00 20. " NEWDAT_116 ,New Data Bit 116" "Not new,New" textline " " bitfld.long 0x00 19. " NEWDAT_115 ,New Data Bit 115" "Not new,New" bitfld.long 0x00 18. " NEWDAT_114 ,New Data Bit 114" "Not new,New" bitfld.long 0x00 17. " NEWDAT_113 ,New Data Bit 113" "Not new,New" bitfld.long 0x00 16. " NEWDAT_112 ,New Data Bit 112" "Not new,New" textline " " bitfld.long 0x00 15. " NEWDAT_111 ,New Data Bit 111" "Not new,New" bitfld.long 0x00 14. " NEWDAT_110 ,New Data Bit 110" "Not new,New" bitfld.long 0x00 13. " NEWDAT_109 ,New Data Bit 109" "Not new,New" bitfld.long 0x00 12. " NEWDAT_108 ,New Data Bit 108" "Not new,New" textline " " bitfld.long 0x00 11. " NEWDAT_107 ,New Data Bit 107" "Not new,New" bitfld.long 0x00 10. " NEWDAT_106 ,New Data Bit 106" "Not new,New" bitfld.long 0x00 9. " NEWDAT_105 ,New Data Bit 105" "Not new,New" bitfld.long 0x00 8. " NEWDAT_104 ,New Data Bit 104" "Not new,New" textline " " bitfld.long 0x00 7. " NEWDAT_103 ,New Data Bit 103" "Not new,New" bitfld.long 0x00 6. " NEWDAT_102 ,New Data Bit 102" "Not new,New" bitfld.long 0x00 5. " NEWDAT_101 ,New Data Bit 101" "Not new,New" bitfld.long 0x00 4. " NEWDAT_100 ,New Data Bit 100" "Not new,New" textline " " bitfld.long 0x00 3. " NEWDAT_99 ,New Data Bit 99" "Not new,New" bitfld.long 0x00 2. " NEWDAT_98 ,New Data Bit 98" "Not new,New" bitfld.long 0x00 1. " NEWDAT_97 ,New Data Bit 97" "Not new,New" bitfld.long 0x00 0. " NEWDAT_96 ,New Data Bit 96" "Not new,New" rgroup.long 0x0AC++0x03 line.long 0x00 "DCAN_INTPND_X,Interrupt Pending X Register" bitfld.long 0x00 14.--15. " INTPNDREG8 , IntPndReg8" "0,1,2,3" bitfld.long 0x00 12.--13. " INTPNDREG7 , IntPndReg7" "0,1,2,3" bitfld.long 0x00 10.--11. " INTPNDREG6 , IntPndReg6" "0,1,2,3" bitfld.long 0x00 8.--9. " INTPNDREG5 , IntPndReg5" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " INTPNDREG4 , IntPndReg4" "0,1,2,3" bitfld.long 0x00 4.--5. " INTPNDREG3 , IntPndReg3" "0,1,2,3" bitfld.long 0x00 2.--3. " INTPNDREG2 , IntPndReg2" "0,1,2,3" bitfld.long 0x00 0.--1. " INTPNDREG1 , IntPndReg1" "0,1,2,3" rgroup.long 0x0B0++0x03 line.long 0x00 "DCAN_INTPND12,Interrupt Pending Register 12" bitfld.long 0x00 31. " INTPND_31 ,Interrupt Pending Bit 31" "Not Source,Source" bitfld.long 0x00 30. " INTPND_30 ,Interrupt Pending Bit 30" "Not Source,Source" bitfld.long 0x00 29. " INTPND_29 ,Interrupt Pending Bit 29" "Not Source,Source" bitfld.long 0x00 28. " INTPND_28 ,Interrupt Pending Bit 28" "Not Source,Source" textline " " bitfld.long 0x00 27. " INTPND_27 ,Interrupt Pending Bit 27" "Not Source,Source" bitfld.long 0x00 26. " INTPND_26 ,Interrupt Pending Bit 26" "Not Source,Source" bitfld.long 0x00 25. " INTPND_25 ,Interrupt Pending Bit 25" "Not Source,Source" bitfld.long 0x00 24. " INTPND_24 ,Interrupt Pending Bit 24" "Not Source,Source" textline " " bitfld.long 0x00 23. " INTPND_23 ,Interrupt Pending Bit 23" "Not Source,Source" bitfld.long 0x00 22. " INTPND_22 ,Interrupt Pending Bit 22" "Not Source,Source" bitfld.long 0x00 21. " INTPND_21 ,Interrupt Pending Bit 21" "Not Source,Source" bitfld.long 0x00 20. " INTPND_20 ,Interrupt Pending Bit 20" "Not Source,Source" textline " " bitfld.long 0x00 19. " INTPND_19 ,Interrupt Pending Bit 19" "Not Source,Source" bitfld.long 0x00 18. " INTPND_18 ,Interrupt Pending Bit 18" "Not Source,Source" bitfld.long 0x00 17. " INTPND_17 ,Interrupt Pending Bit 17" "Not Source,Source" bitfld.long 0x00 16. " INTPND_16 ,Interrupt Pending Bit 16" "Not Source,Source" textline " " bitfld.long 0x00 15. " INTPND_15 ,Interrupt Pending Bit 15" "Not Source,Source" bitfld.long 0x00 14. " INTPND_14 ,Interrupt Pending Bit 14" "Not Source,Source" bitfld.long 0x00 13. " INTPND_13 ,Interrupt Pending Bit 13" "Not Source,Source" bitfld.long 0x00 12. " INTPND_12 ,Interrupt Pending Bit 12" "Not Source,Source" textline " " bitfld.long 0x00 11. " INTPND_11 ,Interrupt Pending Bit 11" "Not Source,Source" bitfld.long 0x00 10. " INTPND_10 ,Interrupt Pending Bit 10" "Not Source,Source" bitfld.long 0x00 9. " INTPND_9 ,Interrupt Pending Bit 9" "Not Source,Source" bitfld.long 0x00 8. " INTPND_8 ,Interrupt Pending Bit 8" "Not Source,Source" textline " " bitfld.long 0x00 7. " INTPND_7 ,Interrupt Pending Bit 7" "Not Source,Source" bitfld.long 0x00 6. " INTPND_6 ,Interrupt Pending Bit 6" "Not Source,Source" bitfld.long 0x00 5. " INTPND_5 ,Interrupt Pending Bit 5" "Not Source,Source" bitfld.long 0x00 4. " INTPND_4 ,Interrupt Pending Bit 4" "Not Source,Source" textline " " bitfld.long 0x00 3. " INTPND_3 ,Interrupt Pending Bit 3" "Not Source,Source" bitfld.long 0x00 2. " INTPND_2 ,Interrupt Pending Bit 2" "Not Source,Source" bitfld.long 0x00 1. " INTPND_1 ,Interrupt Pending Bit 1" "Not Source,Source" bitfld.long 0x00 0. " INTPND_0 ,Interrupt Pending Bit 0" "Not Source,Source" rgroup.long 0x0B4++0x03 line.long 0x00 "DCAN_INTPND34,Interrupt Pending Register 34" bitfld.long 0x00 31. " INTPND_63 ,Interrupt Pending Bit 63" "Not Source,Source" bitfld.long 0x00 30. " INTPND_62 ,Interrupt Pending Bit 62" "Not Source,Source" bitfld.long 0x00 29. " INTPND_61 ,Interrupt Pending Bit 61" "Not Source,Source" bitfld.long 0x00 28. " INTPND_60 ,Interrupt Pending Bit 60" "Not Source,Source" textline " " bitfld.long 0x00 27. " INTPND_59 ,Interrupt Pending Bit 59" "Not Source,Source" bitfld.long 0x00 26. " INTPND_58 ,Interrupt Pending Bit 58" "Not Source,Source" bitfld.long 0x00 25. " INTPND_57 ,Interrupt Pending Bit 57" "Not Source,Source" bitfld.long 0x00 24. " INTPND_56 ,Interrupt Pending Bit 56" "Not Source,Source" textline " " bitfld.long 0x00 23. " INTPND_55 ,Interrupt Pending Bit 55" "Not Source,Source" bitfld.long 0x00 22. " INTPND_54 ,Interrupt Pending Bit 54" "Not Source,Source" bitfld.long 0x00 21. " INTPND_53 ,Interrupt Pending Bit 53" "Not Source,Source" bitfld.long 0x00 20. " INTPND_52 ,Interrupt Pending Bit 52" "Not Source,Source" textline " " bitfld.long 0x00 19. " INTPND_51 ,Interrupt Pending Bit 51" "Not Source,Source" bitfld.long 0x00 18. " INTPND_50 ,Interrupt Pending Bit 50" "Not Source,Source" bitfld.long 0x00 17. " INTPND_49 ,Interrupt Pending Bit 49" "Not Source,Source" bitfld.long 0x00 16. " INTPND_48 ,Interrupt Pending Bit 48" "Not Source,Source" textline " " bitfld.long 0x00 15. " INTPND_47 ,Interrupt Pending Bit 47" "Not Source,Source" bitfld.long 0x00 14. " INTPND_46 ,Interrupt Pending Bit 46" "Not Source,Source" bitfld.long 0x00 13. " INTPND_45 ,Interrupt Pending Bit 45" "Not Source,Source" bitfld.long 0x00 12. " INTPND_44 ,Interrupt Pending Bit 44" "Not Source,Source" textline " " bitfld.long 0x00 11. " INTPND_43 ,Interrupt Pending Bit 43" "Not Source,Source" bitfld.long 0x00 10. " INTPND_42 ,Interrupt Pending Bit 42" "Not Source,Source" bitfld.long 0x00 9. " INTPND_41 ,Interrupt Pending Bit 41" "Not Source,Source" bitfld.long 0x00 8. " INTPND_40 ,Interrupt Pending Bit 40" "Not Source,Source" textline " " bitfld.long 0x00 7. " INTPND_39 ,Interrupt Pending Bit 39" "Not Source,Source" bitfld.long 0x00 6. " INTPND_38 ,Interrupt Pending Bit 38" "Not Source,Source" bitfld.long 0x00 5. " INTPND_37 ,Interrupt Pending Bit 37" "Not Source,Source" bitfld.long 0x00 4. " INTPND_36 ,Interrupt Pending Bit 36" "Not Source,Source" textline " " bitfld.long 0x00 3. " INTPND_35 ,Interrupt Pending Bit 35" "Not Source,Source" bitfld.long 0x00 2. " INTPND_34 ,Interrupt Pending Bit 34" "Not Source,Source" bitfld.long 0x00 1. " INTPND_33 ,Interrupt Pending Bit 33" "Not Source,Source" bitfld.long 0x00 0. " INTPND_32 ,Interrupt Pending Bit 32" "Not Source,Source" rgroup.long 0x0B8++0x03 line.long 0x00 "DCAN_INTPND56,Interrupt Pending Register 56" bitfld.long 0x00 31. " INTPND_95 ,Interrupt Pending Bit 95" "Not Source,Source" bitfld.long 0x00 30. " INTPND_94 ,Interrupt Pending Bit 94" "Not Source,Source" bitfld.long 0x00 29. " INTPND_93 ,Interrupt Pending Bit 93" "Not Source,Source" bitfld.long 0x00 28. " INTPND_92 ,Interrupt Pending Bit 92" "Not Source,Source" textline " " bitfld.long 0x00 27. " INTPND_91 ,Interrupt Pending Bit 91" "Not Source,Source" bitfld.long 0x00 26. " INTPND_90 ,Interrupt Pending Bit 90" "Not Source,Source" bitfld.long 0x00 25. " INTPND_89 ,Interrupt Pending Bit 89" "Not Source,Source" bitfld.long 0x00 24. " INTPND_88 ,Interrupt Pending Bit 88" "Not Source,Source" textline " " bitfld.long 0x00 23. " INTPND_87 ,Interrupt Pending Bit 87" "Not Source,Source" bitfld.long 0x00 22. " INTPND_86 ,Interrupt Pending Bit 86" "Not Source,Source" bitfld.long 0x00 21. " INTPND_85 ,Interrupt Pending Bit 85" "Not Source,Source" bitfld.long 0x00 20. " INTPND_84 ,Interrupt Pending Bit 84" "Not Source,Source" textline " " bitfld.long 0x00 19. " INTPND_83 ,Interrupt Pending Bit 83" "Not Source,Source" bitfld.long 0x00 18. " INTPND_82 ,Interrupt Pending Bit 82" "Not Source,Source" bitfld.long 0x00 17. " INTPND_81 ,Interrupt Pending Bit 81" "Not Source,Source" bitfld.long 0x00 16. " INTPND_80 ,Interrupt Pending Bit 80" "Not Source,Source" textline " " bitfld.long 0x00 15. " INTPND_79 ,Interrupt Pending Bit 79" "Not Source,Source" bitfld.long 0x00 14. " INTPND_78 ,Interrupt Pending Bit 78" "Not Source,Source" bitfld.long 0x00 13. " INTPND_77 ,Interrupt Pending Bit 77" "Not Source,Source" bitfld.long 0x00 12. " INTPND_76 ,Interrupt Pending Bit 76" "Not Source,Source" textline " " bitfld.long 0x00 11. " INTPND_75 ,Interrupt Pending Bit 75" "Not Source,Source" bitfld.long 0x00 10. " INTPND_74 ,Interrupt Pending Bit 74" "Not Source,Source" bitfld.long 0x00 9. " INTPND_73 ,Interrupt Pending Bit 73" "Not Source,Source" bitfld.long 0x00 8. " INTPND_72 ,Interrupt Pending Bit 72" "Not Source,Source" textline " " bitfld.long 0x00 7. " INTPND_71 ,Interrupt Pending Bit 71" "Not Source,Source" bitfld.long 0x00 6. " INTPND_70 ,Interrupt Pending Bit 70" "Not Source,Source" bitfld.long 0x00 5. " INTPND_69 ,Interrupt Pending Bit 69" "Not Source,Source" bitfld.long 0x00 4. " INTPND_68 ,Interrupt Pending Bit 68" "Not Source,Source" textline " " bitfld.long 0x00 3. " INTPND_67 ,Interrupt Pending Bit 67" "Not Source,Source" bitfld.long 0x00 2. " INTPND_66 ,Interrupt Pending Bit 66" "Not Source,Source" bitfld.long 0x00 1. " INTPND_65 ,Interrupt Pending Bit 65" "Not Source,Source" bitfld.long 0x00 0. " INTPND_64 ,Interrupt Pending Bit 64" "Not Source,Source" rgroup.long 0x0BC++0x03 line.long 0x00 "DCAN_INTPND78,Interrupt Pending Register 78" bitfld.long 0x00 31. " INTPND_127 ,Interrupt Pending Bit 127" "Not Source,Source" bitfld.long 0x00 30. " INTPND_126 ,Interrupt Pending Bit 126" "Not Source,Source" bitfld.long 0x00 29. " INTPND_125 ,Interrupt Pending Bit 125" "Not Source,Source" bitfld.long 0x00 28. " INTPND_124 ,Interrupt Pending Bit 124" "Not Source,Source" textline " " bitfld.long 0x00 27. " INTPND_123 ,Interrupt Pending Bit 123" "Not Source,Source" bitfld.long 0x00 26. " INTPND_122 ,Interrupt Pending Bit 122" "Not Source,Source" bitfld.long 0x00 25. " INTPND_121 ,Interrupt Pending Bit 121" "Not Source,Source" bitfld.long 0x00 24. " INTPND_120 ,Interrupt Pending Bit 120" "Not Source,Source" textline " " bitfld.long 0x00 23. " INTPND_119 ,Interrupt Pending Bit 119" "Not Source,Source" bitfld.long 0x00 22. " INTPND_118 ,Interrupt Pending Bit 118" "Not Source,Source" bitfld.long 0x00 21. " INTPND_117 ,Interrupt Pending Bit 117" "Not Source,Source" bitfld.long 0x00 20. " INTPND_116 ,Interrupt Pending Bit 116" "Not Source,Source" textline " " bitfld.long 0x00 19. " INTPND_115 ,Interrupt Pending Bit 115" "Not Source,Source" bitfld.long 0x00 18. " INTPND_114 ,Interrupt Pending Bit 114" "Not Source,Source" bitfld.long 0x00 17. " INTPND_113 ,Interrupt Pending Bit 113" "Not Source,Source" bitfld.long 0x00 16. " INTPND_112 ,Interrupt Pending Bit 112" "Not Source,Source" textline " " bitfld.long 0x00 15. " INTPND_111 ,Interrupt Pending Bit 111" "Not Source,Source" bitfld.long 0x00 14. " INTPND_110 ,Interrupt Pending Bit 110" "Not Source,Source" bitfld.long 0x00 13. " INTPND_109 ,Interrupt Pending Bit 109" "Not Source,Source" bitfld.long 0x00 12. " INTPND_108 ,Interrupt Pending Bit 108" "Not Source,Source" textline " " bitfld.long 0x00 11. " INTPND_107 ,Interrupt Pending Bit 107" "Not Source,Source" bitfld.long 0x00 10. " INTPND_106 ,Interrupt Pending Bit 106" "Not Source,Source" bitfld.long 0x00 9. " INTPND_105 ,Interrupt Pending Bit 105" "Not Source,Source" bitfld.long 0x00 8. " INTPND_104 ,Interrupt Pending Bit 104" "Not Source,Source" textline " " bitfld.long 0x00 7. " INTPND_103 ,Interrupt Pending Bit 103" "Not Source,Source" bitfld.long 0x00 6. " INTPND_102 ,Interrupt Pending Bit 102" "Not Source,Source" bitfld.long 0x00 5. " INTPND_101 ,Interrupt Pending Bit 101" "Not Source,Source" bitfld.long 0x00 4. " INTPND_100 ,Interrupt Pending Bit 100" "Not Source,Source" textline " " bitfld.long 0x00 3. " INTPND_99 ,Interrupt Pending Bit 99" "Not Source,Source" bitfld.long 0x00 2. " INTPND_98 ,Interrupt Pending Bit 98" "Not Source,Source" bitfld.long 0x00 1. " INTPND_97 ,Interrupt Pending Bit 97" "Not Source,Source" bitfld.long 0x00 0. " INTPND_96 ,Interrupt Pending Bit 96" "Not Source,Source" rgroup.long 0x0C0++0x03 line.long 0x00 "DCAN_MSGVAL_X,Message Valid X Register" bitfld.long 0x00 14.--15. " MSGVALREG8 , MsgValReg8" "0,1,2,3" bitfld.long 0x00 12.--13. " MSGVALREG7 , MsgValReg7" "0,1,2,3" bitfld.long 0x00 10.--11. " MSGVALREG6 , MsgValReg6" "0,1,2,3" bitfld.long 0x00 8.--9. " MSGVALREG5 , MsgValReg5" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " MSGVALREG4 , MsgValReg4" "0,1,2,3" bitfld.long 0x00 4.--5. " MSGVALREG3 , MsgValReg3" "0,1,2,3" bitfld.long 0x00 2.--3. " MSGVALREG2 , MsgValReg2" "0,1,2,3" bitfld.long 0x00 0.--1. " MSGVALREG1 , MsgValReg1" "0,1,2,3" rgroup.long 0x0C4++0x03 line.long 0x00 "DCAN_MSGVAL12,Message Valid Register 12" bitfld.long 0x00 31. " MSGVAL_31 ,Message valid bit 31" "Not valid,Valid" bitfld.long 0x00 30. " MSGVAL_30 ,Message valid bit 30" "Not valid,Valid" bitfld.long 0x00 29. " MSGVAL_29 ,Message valid bit 29" "Not valid,Valid" bitfld.long 0x00 28. " MSGVAL_28 ,Message valid bit 28" "Not valid,Valid" textline " " bitfld.long 0x00 27. " MSGVAL_27 ,Message valid bit 27" "Not valid,Valid" bitfld.long 0x00 26. " MSGVAL_26 ,Message valid bit 26" "Not valid,Valid" bitfld.long 0x00 25. " MSGVAL_25 ,Message valid bit 25" "Not valid,Valid" bitfld.long 0x00 24. " MSGVAL_24 ,Message valid bit 24" "Not valid,Valid" textline " " bitfld.long 0x00 23. " MSGVAL_23 ,Message valid bit 23" "Not valid,Valid" bitfld.long 0x00 22. " MSGVAL_22 ,Message valid bit 22" "Not valid,Valid" bitfld.long 0x00 21. " MSGVAL_21 ,Message valid bit 21" "Not valid,Valid" bitfld.long 0x00 20. " MSGVAL_20 ,Message valid bit 20" "Not valid,Valid" textline " " bitfld.long 0x00 19. " MSGVAL_19 ,Message valid bit 19" "Not valid,Valid" bitfld.long 0x00 18. " MSGVAL_18 ,Message valid bit 18" "Not valid,Valid" bitfld.long 0x00 17. " MSGVAL_17 ,Message valid bit 17" "Not valid,Valid" bitfld.long 0x00 16. " MSGVAL_16 ,Message valid bit 16" "Not valid,Valid" textline " " bitfld.long 0x00 15. " MSGVAL_15 ,Message valid bit 15" "Not valid,Valid" bitfld.long 0x00 14. " MSGVAL_14 ,Message valid bit 14" "Not valid,Valid" bitfld.long 0x00 13. " MSGVAL_13 ,Message valid bit 13" "Not valid,Valid" bitfld.long 0x00 12. " MSGVAL_12 ,Message valid bit 12" "Not valid,Valid" textline " " bitfld.long 0x00 11. " MSGVAL_11 ,Message valid bit 11" "Not valid,Valid" bitfld.long 0x00 10. " MSGVAL_10 ,Message valid bit 10" "Not valid,Valid" bitfld.long 0x00 9. " MSGVAL_9 ,Message valid bit 9" "Not valid,Valid" bitfld.long 0x00 8. " MSGVAL_8 ,Message valid bit 8" "Not valid,Valid" textline " " bitfld.long 0x00 7. " MSGVAL_7 ,Message valid bit 7" "Not valid,Valid" bitfld.long 0x00 6. " MSGVAL_6 ,Message valid bit 6" "Not valid,Valid" bitfld.long 0x00 5. " MSGVAL_5 ,Message valid bit 5" "Not valid,Valid" bitfld.long 0x00 4. " MSGVAL_4 ,Message valid bit 4" "Not valid,Valid" textline " " bitfld.long 0x00 3. " MSGVAL_3 ,Message valid bit 3" "Not valid,Valid" bitfld.long 0x00 2. " MSGVAL_2 ,Message valid bit 2" "Not valid,Valid" bitfld.long 0x00 1. " MSGVAL_1 ,Message valid bit 1" "Not valid,Valid" bitfld.long 0x00 0. " MSGVAL_0 ,Message valid bit 0" "Not valid,Valid" rgroup.long 0x0C8++0x03 line.long 0x00 "DCAN_MSGVAL34,Message Valid Register 34" bitfld.long 0x00 31. " MSGVAL_63 ,Message valid bit 63" "Not valid,Valid" bitfld.long 0x00 30. " MSGVAL_62 ,Message valid bit 62" "Not valid,Valid" bitfld.long 0x00 29. " MSGVAL_61 ,Message valid bit 61" "Not valid,Valid" bitfld.long 0x00 28. " MSGVAL_60 ,Message valid bit 60" "Not valid,Valid" textline " " bitfld.long 0x00 27. " MSGVAL_59 ,Message valid bit 59" "Not valid,Valid" bitfld.long 0x00 26. " MSGVAL_58 ,Message valid bit 58" "Not valid,Valid" bitfld.long 0x00 25. " MSGVAL_57 ,Message valid bit 57" "Not valid,Valid" bitfld.long 0x00 24. " MSGVAL_56 ,Message valid bit 56" "Not valid,Valid" textline " " bitfld.long 0x00 23. " MSGVAL_55 ,Message valid bit 55" "Not valid,Valid" bitfld.long 0x00 22. " MSGVAL_54 ,Message valid bit 54" "Not valid,Valid" bitfld.long 0x00 21. " MSGVAL_53 ,Message valid bit 53" "Not valid,Valid" bitfld.long 0x00 20. " MSGVAL_52 ,Message valid bit 52" "Not valid,Valid" textline " " bitfld.long 0x00 19. " MSGVAL_51 ,Message valid bit 51" "Not valid,Valid" bitfld.long 0x00 18. " MSGVAL_50 ,Message valid bit 50" "Not valid,Valid" bitfld.long 0x00 17. " MSGVAL_49 ,Message valid bit 49" "Not valid,Valid" bitfld.long 0x00 16. " MSGVAL_48 ,Message valid bit 48" "Not valid,Valid" textline " " bitfld.long 0x00 15. " MSGVAL_47 ,Message valid bit 47" "Not valid,Valid" bitfld.long 0x00 14. " MSGVAL_46 ,Message valid bit 46" "Not valid,Valid" bitfld.long 0x00 13. " MSGVAL_45 ,Message valid bit 45" "Not valid,Valid" bitfld.long 0x00 12. " MSGVAL_44 ,Message valid bit 44" "Not valid,Valid" textline " " bitfld.long 0x00 11. " MSGVAL_43 ,Message valid bit 43" "Not valid,Valid" bitfld.long 0x00 10. " MSGVAL_42 ,Message valid bit 42" "Not valid,Valid" bitfld.long 0x00 9. " MSGVAL_41 ,Message valid bit 41" "Not valid,Valid" bitfld.long 0x00 8. " MSGVAL_40 ,Message valid bit 40" "Not valid,Valid" textline " " bitfld.long 0x00 7. " MSGVAL_39 ,Message valid bit 39" "Not valid,Valid" bitfld.long 0x00 6. " MSGVAL_38 ,Message valid bit 38" "Not valid,Valid" bitfld.long 0x00 5. " MSGVAL_37 ,Message valid bit 37" "Not valid,Valid" bitfld.long 0x00 4. " MSGVAL_36 ,Message valid bit 36" "Not valid,Valid" textline " " bitfld.long 0x00 3. " MSGVAL_35 ,Message valid bit 35" "Not valid,Valid" bitfld.long 0x00 2. " MSGVAL_34 ,Message valid bit 34" "Not valid,Valid" bitfld.long 0x00 1. " MSGVAL_33 ,Message valid bit 33" "Not valid,Valid" bitfld.long 0x00 0. " MSGVAL_32 ,Message valid bit 32" "Not valid,Valid" rgroup.long 0x0CC++0x03 line.long 0x00 "DCAN_MSGVAL56,Message Valid Register 56" bitfld.long 0x00 31. " MSGVAL_95 ,Message valid bit 95" "Not valid,Valid" bitfld.long 0x00 30. " MSGVAL_94 ,Message valid bit 94" "Not valid,Valid" bitfld.long 0x00 29. " MSGVAL_93 ,Message valid bit 93" "Not valid,Valid" bitfld.long 0x00 28. " MSGVAL_92 ,Message valid bit 92" "Not valid,Valid" textline " " bitfld.long 0x00 27. " MSGVAL_91 ,Message valid bit 91" "Not valid,Valid" bitfld.long 0x00 26. " MSGVAL_90 ,Message valid bit 90" "Not valid,Valid" bitfld.long 0x00 25. " MSGVAL_89 ,Message valid bit 89" "Not valid,Valid" bitfld.long 0x00 24. " MSGVAL_88 ,Message valid bit 88" "Not valid,Valid" textline " " bitfld.long 0x00 23. " MSGVAL_87 ,Message valid bit 87" "Not valid,Valid" bitfld.long 0x00 22. " MSGVAL_86 ,Message valid bit 86" "Not valid,Valid" bitfld.long 0x00 21. " MSGVAL_85 ,Message valid bit 85" "Not valid,Valid" bitfld.long 0x00 20. " MSGVAL_84 ,Message valid bit 84" "Not valid,Valid" textline " " bitfld.long 0x00 19. " MSGVAL_83 ,Message valid bit 83" "Not valid,Valid" bitfld.long 0x00 18. " MSGVAL_82 ,Message valid bit 82" "Not valid,Valid" bitfld.long 0x00 17. " MSGVAL_81 ,Message valid bit 81" "Not valid,Valid" bitfld.long 0x00 16. " MSGVAL_80 ,Message valid bit 80" "Not valid,Valid" textline " " bitfld.long 0x00 15. " MSGVAL_79 ,Message valid bit 79" "Not valid,Valid" bitfld.long 0x00 14. " MSGVAL_78 ,Message valid bit 78" "Not valid,Valid" bitfld.long 0x00 13. " MSGVAL_77 ,Message valid bit 77" "Not valid,Valid" bitfld.long 0x00 12. " MSGVAL_76 ,Message valid bit 76" "Not valid,Valid" textline " " bitfld.long 0x00 11. " MSGVAL_75 ,Message valid bit 75" "Not valid,Valid" bitfld.long 0x00 10. " MSGVAL_74 ,Message valid bit 74" "Not valid,Valid" bitfld.long 0x00 9. " MSGVAL_73 ,Message valid bit 73" "Not valid,Valid" bitfld.long 0x00 8. " MSGVAL_72 ,Message valid bit 72" "Not valid,Valid" textline " " bitfld.long 0x00 7. " MSGVAL_71 ,Message valid bit 71" "Not valid,Valid" bitfld.long 0x00 6. " MSGVAL_70 ,Message valid bit 70" "Not valid,Valid" bitfld.long 0x00 5. " MSGVAL_69 ,Message valid bit 69" "Not valid,Valid" bitfld.long 0x00 4. " MSGVAL_68 ,Message valid bit 68" "Not valid,Valid" textline " " bitfld.long 0x00 3. " MSGVAL_67 ,Message valid bit 67" "Not valid,Valid" bitfld.long 0x00 2. " MSGVAL_66 ,Message valid bit 66" "Not valid,Valid" bitfld.long 0x00 1. " MSGVAL_65 ,Message valid bit 65" "Not valid,Valid" bitfld.long 0x00 0. " MSGVAL_64 ,Message valid bit 64" "Not valid,Valid" rgroup.long 0x0D0++0x03 line.long 0x00 "DCAN_MSGVAL78,Message Valid Register 78" bitfld.long 0x00 31. " MSGVAL_127 ,Message valid bit 127" "Not valid,Valid" bitfld.long 0x00 30. " MSGVAL_126 ,Message valid bit 126" "Not valid,Valid" bitfld.long 0x00 29. " MSGVAL_125 ,Message valid bit 125" "Not valid,Valid" bitfld.long 0x00 28. " MSGVAL_124 ,Message valid bit 124" "Not valid,Valid" textline " " bitfld.long 0x00 27. " MSGVAL_123 ,Message valid bit 123" "Not valid,Valid" bitfld.long 0x00 26. " MSGVAL_122 ,Message valid bit 122" "Not valid,Valid" bitfld.long 0x00 25. " MSGVAL_121 ,Message valid bit 121" "Not valid,Valid" bitfld.long 0x00 24. " MSGVAL_120 ,Message valid bit 120" "Not valid,Valid" textline " " bitfld.long 0x00 23. " MSGVAL_119 ,Message valid bit 119" "Not valid,Valid" bitfld.long 0x00 22. " MSGVAL_118 ,Message valid bit 118" "Not valid,Valid" bitfld.long 0x00 21. " MSGVAL_117 ,Message valid bit 117" "Not valid,Valid" bitfld.long 0x00 20. " MSGVAL_116 ,Message valid bit 116" "Not valid,Valid" textline " " bitfld.long 0x00 19. " MSGVAL_115 ,Message valid bit 115" "Not valid,Valid" bitfld.long 0x00 18. " MSGVAL_114 ,Message valid bit 114" "Not valid,Valid" bitfld.long 0x00 17. " MSGVAL_113 ,Message valid bit 113" "Not valid,Valid" bitfld.long 0x00 16. " MSGVAL_112 ,Message valid bit 112" "Not valid,Valid" textline " " bitfld.long 0x00 15. " MSGVAL_111 ,Message valid bit 111" "Not valid,Valid" bitfld.long 0x00 14. " MSGVAL_110 ,Message valid bit 110" "Not valid,Valid" bitfld.long 0x00 13. " MSGVAL_109 ,Message valid bit 109" "Not valid,Valid" bitfld.long 0x00 12. " MSGVAL_108 ,Message valid bit 108" "Not valid,Valid" textline " " bitfld.long 0x00 11. " MSGVAL_107 ,Message valid bit 107" "Not valid,Valid" bitfld.long 0x00 10. " MSGVAL_106 ,Message valid bit 106" "Not valid,Valid" bitfld.long 0x00 9. " MSGVAL_105 ,Message valid bit 105" "Not valid,Valid" bitfld.long 0x00 8. " MSGVAL_104 ,Message valid bit 104" "Not valid,Valid" textline " " bitfld.long 0x00 7. " MSGVAL_103 ,Message valid bit 103" "Not valid,Valid" bitfld.long 0x00 6. " MSGVAL_102 ,Message valid bit 102" "Not valid,Valid" bitfld.long 0x00 5. " MSGVAL_101 ,Message valid bit 101" "Not valid,Valid" bitfld.long 0x00 4. " MSGVAL_100 ,Message valid bit 100" "Not valid,Valid" textline " " bitfld.long 0x00 3. " MSGVAL_99 ,Message valid bit 99" "Not valid,Valid" bitfld.long 0x00 2. " MSGVAL_98 ,Message valid bit 98" "Not valid,Valid" bitfld.long 0x00 1. " MSGVAL_97 ,Message valid bit 97" "Not valid,Valid" bitfld.long 0x00 0. " MSGVAL_96 ,Message valid bit 96" "Not valid,Valid" rgroup.long 0x0D8++0x03 line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer Register 12" bitfld.long 0x00 31. " INTMUX_31 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 31" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX_30 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 30" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX_29 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 29" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTMUX_28 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 28" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTMUX_27 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 27" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX_26 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 26" "DCAN0INT,DCAN1INT" bitfld.long 0x00 25. " INTMUX_25 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 25" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX_24 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 24" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTMUX_23 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 23" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTMUX_22 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 22" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX_21 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 21" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX_20 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 20" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX_19 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 19" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX_18 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 18" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX_17 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 17" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTMUX_16 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 16" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTMUX_15 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 15" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX_14 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 14" "DCAN0INT,DCAN1INT" bitfld.long 0x00 13. " INTMUX_13 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 13" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX_12 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 12" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTMUX_11 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 11" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTMUX_10 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 10" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX_9 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 9" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX_8 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 8" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX_7 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 7" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX_6 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 6" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX_5 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 5" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTMUX_4 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 4" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTMUX_3 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 3" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX_2 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 2" "DCAN0INT,DCAN1INT" bitfld.long 0x00 1. " INTMUX_1 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 1" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX_0 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 0" "DCAN0INT,DCAN1INT" rgroup.long 0x0DC++0x03 line.long 0x00 "DCAN_INTMUX34,Interrupt Multiplexer Register 34" bitfld.long 0x00 31. " INTMUX_63 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 63" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX_62 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 62" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX_61 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 61" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTMUX_60 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 60" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTMUX_59 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 59" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX_58 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 58" "DCAN0INT,DCAN1INT" bitfld.long 0x00 25. " INTMUX_57 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 57" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX_56 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 56" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTMUX_55 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 55" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTMUX_54 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 54" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX_53 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 53" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX_52 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 52" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX_51 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 51" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX_50 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 50" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX_49 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 49" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTMUX_48 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 48" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTMUX_47 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 47" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX_46 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 46" "DCAN0INT,DCAN1INT" bitfld.long 0x00 13. " INTMUX_45 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 45" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX_44 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 44" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTMUX_43 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 43" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTMUX_42 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 42" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX_41 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 41" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX_40 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 40" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX_39 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 39" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX_38 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 38" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX_37 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 37" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTMUX_36 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 36" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTMUX_35 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 35" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX_34 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 34" "DCAN0INT,DCAN1INT" bitfld.long 0x00 1. " INTMUX_33 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 33" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX_32 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 32" "DCAN0INT,DCAN1INT" rgroup.long 0x0E0++0x03 line.long 0x00 "DCAN_INTMUX56,Interrupt Multiplexer Register 56" bitfld.long 0x00 31. " INTMUX_95 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 95" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX_94 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 94" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX_93 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 93" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTMUX_92 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 92" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTMUX_91 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 91" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX_90 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 90" "DCAN0INT,DCAN1INT" bitfld.long 0x00 25. " INTMUX_89 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 89" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX_88 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 88" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTMUX_87 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 87" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTMUX_86 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 86" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX_85 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 85" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX_84 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 84" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX_83 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 83" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX_82 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 82" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX_81 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 81" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTMUX_80 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 80" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTMUX_79 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 79" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX_78 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 78" "DCAN0INT,DCAN1INT" bitfld.long 0x00 13. " INTMUX_77 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 77" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX_76 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 76" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTMUX_75 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 75" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTMUX_74 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 74" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX_73 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 73" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX_72 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 72" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX_71 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 71" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX_70 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 70" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX_69 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 69" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTMUX_68 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 68" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTMUX_67 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 67" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX_66 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 66" "DCAN0INT,DCAN1INT" bitfld.long 0x00 1. " INTMUX_65 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 65" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX_64 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 64" "DCAN0INT,DCAN1INT" rgroup.long 0x0E4++0x03 line.long 0x00 "DCAN_INTMUX78,Interrupt Multiplexer Register 78" bitfld.long 0x00 31. " INTMUX_127 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 127" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX_126 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 126" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX_125 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 125" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTMUX_124 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 124" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTMUX_123 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 123" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX_122 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 122" "DCAN0INT,DCAN1INT" bitfld.long 0x00 25. " INTMUX_121 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 121" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX_120 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 120" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTMUX_119 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 119" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTMUX_118 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 118" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX_117 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 117" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX_116 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 116" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX_115 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 115" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX_114 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 114" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX_113 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 113" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTMUX_112 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 112" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTMUX_111 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 111" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX_110 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 110" "DCAN0INT,DCAN1INT" bitfld.long 0x00 13. " INTMUX_109 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 109" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX_108 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 108" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTMUX_107 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 107" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTMUX_106 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 106" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX_105 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 105" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX_104 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 104" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX_103 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 103" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX_102 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 102" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX_101 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 101" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTMUX_100 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 100" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTMUX_99 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 99" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX_98 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 98" "DCAN0INT,DCAN1INT" bitfld.long 0x00 1. " INTMUX_97 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 97" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX_96 ,Multiplexes IntPnd value DCAN0INT/ DCAN1INT interrupt lines 96" "DCAN0INT,DCAN1INT" if (((d.l(ad:0x481D0000+0x100))&0x8000)==0x8000) //this.BUSY== "BUSY" rgroup.long 0x100++0x03 line.long 0x00 "DCAN_IF1CMD,IF1 Command Registers" bitfld.long 0x00 23. " WR_RD ,Write/Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred" bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred" bitfld.long 0x00 20. " CTRL ,Access control bits" "Not changed,Transferred" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not clear,Clear" bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Clear" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0 to 3" "Not changed,Transferred" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4 to 7" "Not changed,Transferred" textline " " bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent request,Req. after completed" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer" rgroup.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" else group.long 0x100++0x03 line.long 0x00 "DCAN_IF1CMD,IF1 Command Registers" bitfld.long 0x00 23. " WR_RD ,Write/Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred" bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred" bitfld.long 0x00 20. " CTRL ,Access control bits" "Not changed,Transferred" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not clear,Clear" bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Clear" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0 to 3" "Not changed,Transferred" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4 to 7" "Not changed,Transferred" textline " " bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent request,Req. after completed" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer" group.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" endif if (((d.l(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((d.l(ad:0x481D0000+0x108))&0x40000000)==0x40000000) rgroup.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((d.l(ad:0x481D0000+0x108))&0x40000000)==0x00000000) rgroup.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((d.l(ad:0x481D0000+0x108))&0x40000000)==0x40000000) group.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((d.l(ad:0x481D0000+0x108))&0x40000000)==0x00000000) group.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" endif if (((d.l(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((d.l(ad:0x481D0000+0x108))&0x20000000)==0x20000000) group.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((d.l(ad:0x481D0000+0x108))&0x20000000)==0x00000000) group.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((d.l(ad:0x481D0000+0x108))&0x20000000)==0x20000000) rgroup.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((d.l(ad:0x481D0000+0x108))&0x20000000)==0x00000000) rgroup.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x110++0x03 line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x114++0x03 line.long 0x00 "DCAN_IF1DATB,IF1 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" if (((d.l(ad:0x481D0000+0x120))&0x8000)==0x8000) //this.BUSY== "BUSY" rgroup.long 0x120++0x03 line.long 0x00 "DCAN_IF2CMD,IF2 Command Registers" bitfld.long 0x00 23. " WR_RD ,Write/Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred" bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred" bitfld.long 0x00 20. " CTRL ,Access control bits" "Not changed,Transferred" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not clear,Clear" bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Clear" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0 to 3" "Not changed,Transferred" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4 to 7" "Not changed,Transferred" textline " " bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent request,Req. after completed" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer" rgroup.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" else group.long 0x120++0x03 line.long 0x00 "DCAN_IF2CMD,IF2 Command Registers" bitfld.long 0x00 23. " WR_RD ,Write/Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred" bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred" bitfld.long 0x00 20. " CTRL ,Access control bits" "Not changed,Transferred" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not clear,Clear" bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Clear" bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0 to 3" "Not changed,Transferred" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4 to 7" "Not changed,Transferred" textline " " bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent request,Req. after completed" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer" group.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" endif if (((d.l(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((d.l(ad:0x481D0000+0x128))&0x40000000)==0x40000000) rgroup.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((d.l(ad:0x481D0000+0x128))&0x40000000)==0x00000000) rgroup.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((d.l(ad:0x481D0000+0x128))&0x40000000)==0x40000000) group.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" elif (((d.l(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((d.l(ad:0x481D0000+0x128))&0x40000000)==0x00000000) group.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" endif if (((d.l(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((d.l(ad:0x481D0000+0x128))&0x20000000)==0x20000000) group.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((d.l(ad:0x481D0000+0x128))&0x20000000)==0x00000000) group.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((d.l(ad:0x481D0000+0x128))&0x20000000)==0x20000000) rgroup.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((d.l(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((d.l(ad:0x481D0000+0x128))&0x20000000)==0x00000000) rgroup.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x130++0x03 line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x134++0x03 line.long 0x00 "DCAN_IF2DATB,IF2 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x140++0x03 line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register" rbitfld.long 0x00 15. " IF3_UPD ,IF3 Update Data" "Not loaded,New data loaded" rbitfld.long 0x00 12. " IF3_SDB ,IF3 Status of Data B read access" "Not available,Available" rbitfld.long 0x00 11. " IF3_SDA ,IF3 Status of Data A read access" "Not available,Available" textline " " rbitfld.long 0x00 10. " IF3_SC ,IF3 Status of control bits read access" "Not available,Available" rbitfld.long 0x00 9. " IF3_SA ,IF3 Status of Arbitration data read access" "Not available,Available" rbitfld.long 0x00 8. " IF3_SM ,IF3 Status of Mask data read access" "Not available,Available" textline " " bitfld.long 0x00 4. " DATAB ,Data B read observation" "Not read,Read" bitfld.long 0x00 3. " DATAA ,Data A read observation" "Not read,Read" bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "Not read,Read" textline " " bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "Not read,Read" bitfld.long 0x00 0. " MASK ,Mask data read observation" "Not read,Read" rgroup.long 0x144++0x03 line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register" rbitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not used,Used" rbitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not used,Used" bitfld.long 0x00 28. " MSK_28 ,Identifier Mask28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MSK_27 ,Identifier Mask27" "Not masked,Masked" bitfld.long 0x00 26. " MSK_26 ,Identifier Mask26" "Not masked,Masked" bitfld.long 0x00 25. " MSK_25 ,Identifier Mask25" "Not masked,Masked" bitfld.long 0x00 24. " MSK_24 ,Identifier Mask24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " MSK_23 ,Identifier Mask23" "Not masked,Masked" bitfld.long 0x00 22. " MSK_22 ,Identifier Mask22" "Not masked,Masked" bitfld.long 0x00 21. " MSK_21 ,Identifier Mask21" "Not masked,Masked" bitfld.long 0x00 20. " MSK_20 ,Identifier Mask20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK_19 ,Identifier Mask19" "Not masked,Masked" bitfld.long 0x00 18. " MSK_18 ,Identifier Mask18" "Not masked,Masked" bitfld.long 0x00 17. " MSK_17 ,Identifier Mask17" "Not masked,Masked" bitfld.long 0x00 16. " MSK_16 ,Identifier Mask16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " MSK_15 ,Identifier Mask15" "Not masked,Masked" bitfld.long 0x00 14. " MSK_14 ,Identifier Mask14" "Not masked,Masked" bitfld.long 0x00 13. " MSK_13 ,Identifier Mask13" "Not masked,Masked" bitfld.long 0x00 12. " MSK_12 ,Identifier Mask12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " MSK_11 ,Identifier Mask11" "Not masked,Masked" bitfld.long 0x00 10. " MSK_10 ,Identifier Mask10" "Not masked,Masked" bitfld.long 0x00 9. " MSK_9 ,Identifier Mask9" "Not masked,Masked" bitfld.long 0x00 8. " MSK_8 ,Identifier Mask8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK_7 ,Identifier Mask7" "Not masked,Masked" bitfld.long 0x00 6. " MSK_6 ,Identifier Mask6" "Not masked,Masked" bitfld.long 0x00 5. " MSK_5 ,Identifier Mask5" "Not masked,Masked" bitfld.long 0x00 4. " MSK_4 ,Identifier Mask4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MSK_3 ,Identifier Mask3" "Not masked,Masked" bitfld.long 0x00 2. " MSK_2 ,Identifier Mask2" "Not masked,Masked" bitfld.long 0x00 1. " MSK_1 ,Identifier Mask1" "Not masked,Masked" bitfld.long 0x00 0. " MSK_0 ,Identifier Mask0" "Not masked,Masked" if (((d.l(ad:0x481D0000+0x148))&0x40000000)==0x0000) rgroup.long 0x148++0x03 line.long 0x00 "DCAN_IF3ARB,IF3 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28_TO_ID0 , Message identifier" else rgroup.long 0x148++0x03 line.long 0x00 "DCAN_IF3ARB,IF3 Arbitration Register" bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended identifier" "11-bit,29-bit" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28_TO_ID0 , Message identifier" endif rgroup.long 0x14C++0x03 line.long 0x00 "DCAN_IF3MCTL,IF3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New data" "No new,New" bitfld.long 0x00 14. " MSGLST ,Message lost" "No message lost,Message lost" bitfld.long 0x00 13. " INTPND ,Interrupt pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data frame has 0 to 8 data bits" "8 bytes,Cores. obj. size" bitfld.long 0x00 0.--3. " DLC , Data length code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x150++0x03 line.long 0x00 "DCAN_IF3DATA,IF3 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" rgroup.long 0x154++0x03 line.long 0x00 "DCAN_IF3DATB,IF3 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x160++0x03 line.long 0x00 "DCAN_IF3UPD12,IF3 Update Enable Register 12" bitfld.long 0x00 31. " IF3UPDEN_31 ,IF3 Update Enabled bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDEN_30 ,IF3 Update Enabled bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDEN_29 ,IF3 Update Enabled bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDEN_28 ,IF3 Update Enabled bit 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDEN_27 ,IF3 Update Enabled bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDEN_26 ,IF3 Update Enabled bit 26" "Disabled,Enabled" bitfld.long 0x00 25. " IF3UPDEN_25 ,IF3 Update Enabled bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDEN_24 ,IF3 Update Enabled bit 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDEN_23 ,IF3 Update Enabled bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDEN_22 ,IF3 Update Enabled bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDEN_21 ,IF3 Update Enabled bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDEN_20 ,IF3 Update Enabled bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDEN_19 ,IF3 Update Enabled bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDEN_18 ,IF3 Update Enabled bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDEN_17 ,IF3 Update Enabled bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDEN_16 ,IF3 Update Enabled bit 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDEN_15 ,IF3 Update Enabled bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDEN_14 ,IF3 Update Enabled bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " IF3UPDEN_13 ,IF3 Update Enabled bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDEN_12 ,IF3 Update Enabled bit 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDEN_11 ,IF3 Update Enabled bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDEN_10 ,IF3 Update Enabled bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDEN_9 ,IF3 Update Enabled bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDEN_8 ,IF3 Update Enabled bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDEN_7 ,IF3 Update Enabled bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDEN_6 ,IF3 Update Enabled bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDEN_5 ,IF3 Update Enabled bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDEN_4 ,IF3 Update Enabled bit 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDEN_3 ,IF3 Update Enabled bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDEN_2 ,IF3 Update Enabled bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " IF3UPDEN_1 ,IF3 Update Enabled bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDEN_0 ,IF3 Update Enabled bit 0" "Disabled,Enabled" group.long 0x164++0x03 line.long 0x00 "DCAN_IF3UPD34,IF3 Update Enable Register 34" bitfld.long 0x00 31. " IF3UPDEN_63 ,IF3 Update Enabled bit 63" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDEN_62 ,IF3 Update Enabled bit 62" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDEN_61 ,IF3 Update Enabled bit 61" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDEN_60 ,IF3 Update Enabled bit 60" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDEN_59 ,IF3 Update Enabled bit 59" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDEN_58 ,IF3 Update Enabled bit 58" "Disabled,Enabled" bitfld.long 0x00 25. " IF3UPDEN_57 ,IF3 Update Enabled bit 57" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDEN_56 ,IF3 Update Enabled bit 56" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDEN_55 ,IF3 Update Enabled bit 55" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDEN_54 ,IF3 Update Enabled bit 54" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDEN_53 ,IF3 Update Enabled bit 53" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDEN_52 ,IF3 Update Enabled bit 52" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDEN_51 ,IF3 Update Enabled bit 51" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDEN_50 ,IF3 Update Enabled bit 50" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDEN_49 ,IF3 Update Enabled bit 49" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDEN_48 ,IF3 Update Enabled bit 48" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDEN_47 ,IF3 Update Enabled bit 47" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDEN_46 ,IF3 Update Enabled bit 46" "Disabled,Enabled" bitfld.long 0x00 13. " IF3UPDEN_45 ,IF3 Update Enabled bit 45" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDEN_44 ,IF3 Update Enabled bit 44" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDEN_43 ,IF3 Update Enabled bit 43" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDEN_42 ,IF3 Update Enabled bit 42" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDEN_41 ,IF3 Update Enabled bit 41" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDEN_40 ,IF3 Update Enabled bit 40" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDEN_39 ,IF3 Update Enabled bit 39" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDEN_38 ,IF3 Update Enabled bit 38" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDEN_37 ,IF3 Update Enabled bit 37" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDEN_36 ,IF3 Update Enabled bit 36" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDEN_35 ,IF3 Update Enabled bit 35" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDEN_34 ,IF3 Update Enabled bit 34" "Disabled,Enabled" bitfld.long 0x00 1. " IF3UPDEN_33 ,IF3 Update Enabled bit 33" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDEN_32 ,IF3 Update Enabled bit 32" "Disabled,Enabled" group.long 0x168++0x03 line.long 0x00 "DCAN_IF3UPD56,IF3 Update Enable Register 56" bitfld.long 0x00 31. " IF3UPDEN_95 ,IF3 Update Enabled bit 95" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDEN_94 ,IF3 Update Enabled bit 94" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDEN_93 ,IF3 Update Enabled bit 93" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDEN_92 ,IF3 Update Enabled bit 92" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDEN_91 ,IF3 Update Enabled bit 91" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDEN_90 ,IF3 Update Enabled bit 90" "Disabled,Enabled" bitfld.long 0x00 25. " IF3UPDEN_89 ,IF3 Update Enabled bit 89" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDEN_88 ,IF3 Update Enabled bit 88" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDEN_87 ,IF3 Update Enabled bit 87" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDEN_86 ,IF3 Update Enabled bit 86" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDEN_85 ,IF3 Update Enabled bit 85" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDEN_84 ,IF3 Update Enabled bit 84" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDEN_83 ,IF3 Update Enabled bit 83" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDEN_82 ,IF3 Update Enabled bit 82" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDEN_81 ,IF3 Update Enabled bit 81" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDEN_80 ,IF3 Update Enabled bit 80" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDEN_79 ,IF3 Update Enabled bit 79" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDEN_78 ,IF3 Update Enabled bit 78" "Disabled,Enabled" bitfld.long 0x00 13. " IF3UPDEN_77 ,IF3 Update Enabled bit 77" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDEN_76 ,IF3 Update Enabled bit 76" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDEN_75 ,IF3 Update Enabled bit 75" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDEN_74 ,IF3 Update Enabled bit 74" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDEN_73 ,IF3 Update Enabled bit 73" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDEN_72 ,IF3 Update Enabled bit 72" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDEN_71 ,IF3 Update Enabled bit 71" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDEN_70 ,IF3 Update Enabled bit 70" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDEN_69 ,IF3 Update Enabled bit 69" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDEN_68 ,IF3 Update Enabled bit 68" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDEN_67 ,IF3 Update Enabled bit 67" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDEN_66 ,IF3 Update Enabled bit 66" "Disabled,Enabled" bitfld.long 0x00 1. " IF3UPDEN_65 ,IF3 Update Enabled bit 65" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDEN_64 ,IF3 Update Enabled bit 64" "Disabled,Enabled" group.long 0x16C++0x03 line.long 0x00 "DCAN_IF3UPD78,IF3 Update Enable Register 78" bitfld.long 0x00 31. " IF3UPDEN_127 ,IF3 Update Enabled bit 127" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDEN_126 ,IF3 Update Enabled bit 126" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDEN_125 ,IF3 Update Enabled bit 125" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDEN_124 ,IF3 Update Enabled bit 124" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDEN_123 ,IF3 Update Enabled bit 123" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDEN_122 ,IF3 Update Enabled bit 122" "Disabled,Enabled" bitfld.long 0x00 25. " IF3UPDEN_121 ,IF3 Update Enabled bit 121" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDEN_120 ,IF3 Update Enabled bit 120" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDEN_119 ,IF3 Update Enabled bit 119" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDEN_118 ,IF3 Update Enabled bit 118" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDEN_117 ,IF3 Update Enabled bit 117" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDEN_116 ,IF3 Update Enabled bit 116" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDEN_115 ,IF3 Update Enabled bit 115" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDEN_114 ,IF3 Update Enabled bit 114" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDEN_113 ,IF3 Update Enabled bit 113" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDEN_112 ,IF3 Update Enabled bit 112" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDEN_111 ,IF3 Update Enabled bit 111" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDEN_110 ,IF3 Update Enabled bit 110" "Disabled,Enabled" bitfld.long 0x00 13. " IF3UPDEN_109 ,IF3 Update Enabled bit 109" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDEN_108 ,IF3 Update Enabled bit 108" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDEN_107 ,IF3 Update Enabled bit 107" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDEN_106 ,IF3 Update Enabled bit 106" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDEN_105 ,IF3 Update Enabled bit 105" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDEN_104 ,IF3 Update Enabled bit 104" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDEN_103 ,IF3 Update Enabled bit 103" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDEN_102 ,IF3 Update Enabled bit 102" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDEN_101 ,IF3 Update Enabled bit 101" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDEN_100 ,IF3 Update Enabled bit 100" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDEN_99 ,IF3 Update Enabled bit 99" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDEN_98 ,IF3 Update Enabled bit 98" "Disabled,Enabled" bitfld.long 0x00 1. " IF3UPDEN_97 ,IF3 Update Enabled bit 97" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDEN_96 ,IF3 Update Enabled bit 96" "Disabled,Enabled" if (((d.l(ad:0x481D0000+0x00))&0x01)==0x01) group.long 0x1E0++0x03 line.long 0x00 "DCAN_TIOC,CAN TX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX pull up/pull down select" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO mode,Func. mode" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" rbitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" group.long 0x1E4++0x03 line.long 0x00 "DCAN_RIOC,CAN RX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_RX pull up/pull down select" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,CAN_RX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_RX open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FUNC ,CAN_RX function" "GIO mode,Func. mode" bitfld.long 0x00 2. " DIR ,CAN_RX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_RX data out write" "Low,High" rbitfld.long 0x00 0. " IN ,CAN_RX data in" "Low,High" else rgroup.long 0x1E0++0x03 line.long 0x00 "DCAN_TIOC,CAN TX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX pull up/pull down select" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO mode,Func. mode" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" rbitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" rgroup.long 0x1E4++0x03 line.long 0x00 "DCAN_RIOC,CAN RX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_RX pull up/pull down select" "Pull down,Pull up" bitfld.long 0x00 17. " PD ,CAN_RX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_RX open drain enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FUNC ,CAN_RX function" "GIO mode,Func. mode" bitfld.long 0x00 2. " DIR ,CAN_RX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_RX data out write" "Low,High" rbitfld.long 0x00 0. " IN ,CAN_RX data in" "Low,High" endif width 11. tree.end tree.end tree "MCSPI(Multichannel Serial Port Interface)" tree "MCSPI 0" base ad:0x48030000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x04++0x03 line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, i.e. typically the module's HDL generics" bitfld.long 0x00 6. " RETMODE ,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "Disabled,Enabled" bitfld.long 0x00 1.--5. " FFNBYTE ,Defines the value of FFNBYTE generic parameter" "-,16,32,-,64,-,-,-,128,-,256,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 0. " USEFIFO ,This bit field indicates if a FIFO is integrated within controller design with its management" "No,Yes" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the hard coded RTL revision number" bitfld.long 0x00 4.--7. " Major ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " Minor ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " width 17. if (((d.l(ad:0x48030000+0x110))&0x4)==0x4) //this.ENAWAKEUP== "Enabled" group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode,Idle mode wakeup capable" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" else group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode," bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" endif rgroup.long 0x114++0x03 line.long 0x00 "MCSPI_SYSSTS,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" if (((d.l(ad:0x48030000+0x128))&0x4)==0x4) //MCSPI_MODULCTRL.MS== "slave" group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only)(Channel 0)" "Not overflow,Overflow" eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" else group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" endif group.long 0x11C++0x03 line.long 0x00 "MCSPI_IRQEN,This register allows to enable/disable the module internal sources of interrupt, on an event-by-event basis" bitfld.long 0x00 17. " EOW_EN ,End of Word count Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. " WKE ,Wake Up event interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " RX3_FULL_EN ,Receiver register Full Interrupt Enable" "Disabled,Enabled(Channel 3)" bitfld.long 0x00 13. " TX3_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 3)" "Disabled,Enabled" bitfld.long 0x00 12. " TX3_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 3)" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RX2_FULL_EN ,Receiver register Full Interrupt Enable(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 9. " TX2_UNDERFLOW_EN ,TX2_UNDERFLOW_EN(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 8. " TX2_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 2)" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " RX1_FULL_EN ,Receiver register Full Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 5. " TX1_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 4. " TX1_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 1)" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RX0_OVERFLOW_EN ,Receiver register Overflow Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 2. " RX0_FULL_EN ,Receiver register Full Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 1. " TX0_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 0)" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TX0_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 0)" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "MCSPI_WAKEUPEN,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis" bitfld.long 0x00 0. " WKEN ,WakeUp functionality in slave mode" "Not allowed,Allowed" textline " " group.long 0x124++0x03 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect" bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Forced" bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0]" "Output,Input" bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input" bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input" textline " " bitfld.long 0x00 7. " WAKD ,SWAKEUP output" "Low,High" bitfld.long 0x00 6. " SPICLK ,Signal data value" "Low,High" bitfld.long 0x00 5. " SPIDAT_1 ,Signal data value" "Low,High" bitfld.long 0x00 4. " SPIDAT_0 ,Signal data value" "Low,High" textline " " bitfld.long 0x00 3. " SPIEN_3 ,Signal data value" "Low,High" bitfld.long 0x00 2. " SPIEN_2 ,Signal data value" "Low,High" bitfld.long 0x00 1. " SPIEN_1 ,Signal data value" "Low,High" bitfld.long 0x00 0. " SPIEN_0 ,Signal data value" "Low,High" if (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //this.MS== "slave" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //this.MS== "slave" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //this.MS== "Master" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //this.MS== "Master" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 4.--6. " INITDLY ,Initial spi delay for first transfer" "No delay,4 clk delay,8 clk delay,16 clk delay,32 clk delay,,," bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" endif textline " " if (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 0 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 0 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 0 Receiver Register Status" "Empty,Full" group.long 0x134++0x03 line.long 0x00 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x138++0x03 line.long 0x00 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RX0,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 1 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 1 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 1 Receiver Register Status" "Empty,Full" group.long 0x148++0x03 line.long 0x00 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RX1,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS2 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x158++0x03 line.long 0x00 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" bitfld.long 0x00 6. " R2FFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R2FFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T2FFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T2FFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 2 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T2S ,Channel 2 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R2S ,Channel 2 Receiver Register Status" "Empty,Full" group.long 0x15C++0x03 line.long 0x00 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x160++0x03 line.long 0x00 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x164++0x03 line.long 0x00 "MCSPI_RX2,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48030000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48030000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x16C++0x03 line.long 0x00 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" bitfld.long 0x00 6. " R3FFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R3FFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T3FFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T3FFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 3 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T3S ,Channel 3 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R3S ,Channel 3 Receiver Register Status" "Empty,Full" group.long 0x170++0x03 line.long 0x00 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x174++0x03 line.long 0x00 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x178++0x03 line.long 0x00 "MCSPI_RX3,This register contains a single SPI word received through the serial link" group.long 0x17C++0x03 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.byte 0x00 16.--31. 1. " WCNT ,Spi word counter" hexmask.long.byte 0x00 0.--15. 1. " AFL ,Buffer Almost Full" hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty" if (((d.l(ad:0x48030000+0x128))&0x100)==0x100) group.long 0x180++0x03 line.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" else hgroup.long 0x180++0x03 hide.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" hgroup.long 0x1A0++0x03 hide.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" endif width 11. tree.end tree "MCSPI 1" base ad:0x481A0000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x04++0x03 line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, i.e. typically the module's HDL generics" bitfld.long 0x00 6. " RETMODE ,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "Disabled,Enabled" bitfld.long 0x00 1.--5. " FFNBYTE ,Defines the value of FFNBYTE generic parameter" "-,16,32,-,64,-,-,-,128,-,256,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 0. " USEFIFO ,This bit field indicates if a FIFO is integrated within controller design with its management" "No,Yes" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the hard coded RTL revision number" bitfld.long 0x00 4.--7. " Major ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " Minor ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " width 17. if (((d.l(ad:0x481A0000+0x110))&0x4)==0x4) //this.ENAWAKEUP== "Enabled" group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode,Idle mode wakeup capable" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" else group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode," bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" endif rgroup.long 0x114++0x03 line.long 0x00 "MCSPI_SYSSTS,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" if (((d.l(ad:0x481A0000+0x128))&0x4)==0x4) //MCSPI_MODULCTRL.MS== "slave" group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only)(Channel 0)" "Not overflow,Overflow" eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" else group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" endif group.long 0x11C++0x03 line.long 0x00 "MCSPI_IRQEN,This register allows to enable/disable the module internal sources of interrupt, on an event-by-event basis" bitfld.long 0x00 17. " EOW_EN ,End of Word count Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. " WKE ,Wake Up event interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " RX3_FULL_EN ,Receiver register Full Interrupt Enable" "Disabled,Enabled(Channel 3)" bitfld.long 0x00 13. " TX3_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 3)" "Disabled,Enabled" bitfld.long 0x00 12. " TX3_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 3)" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RX2_FULL_EN ,Receiver register Full Interrupt Enable(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 9. " TX2_UNDERFLOW_EN ,TX2_UNDERFLOW_EN(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 8. " TX2_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 2)" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " RX1_FULL_EN ,Receiver register Full Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 5. " TX1_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 4. " TX1_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 1)" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RX0_OVERFLOW_EN ,Receiver register Overflow Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 2. " RX0_FULL_EN ,Receiver register Full Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 1. " TX0_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 0)" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TX0_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 0)" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "MCSPI_WAKEUPEN,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis" bitfld.long 0x00 0. " WKEN ,WakeUp functionality in slave mode" "Not allowed,Allowed" textline " " group.long 0x124++0x03 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect" bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Forced" bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0]" "Output,Input" bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input" bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input" textline " " bitfld.long 0x00 7. " WAKD ,SWAKEUP output" "Low,High" bitfld.long 0x00 6. " SPICLK ,Signal data value" "Low,High" bitfld.long 0x00 5. " SPIDAT_1 ,Signal data value" "Low,High" bitfld.long 0x00 4. " SPIDAT_0 ,Signal data value" "Low,High" textline " " bitfld.long 0x00 3. " SPIEN_3 ,Signal data value" "Low,High" bitfld.long 0x00 2. " SPIEN_2 ,Signal data value" "Low,High" bitfld.long 0x00 1. " SPIEN_1 ,Signal data value" "Low,High" bitfld.long 0x00 0. " SPIEN_0 ,Signal data value" "Low,High" if (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //this.MS== "slave" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //this.MS== "slave" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //this.MS== "Master" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //this.MS== "Master" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 4.--6. " INITDLY ,Initial spi delay for first transfer" "No delay,4 clk delay,8 clk delay,16 clk delay,32 clk delay,,," bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" endif textline " " if (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 0 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 0 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 0 Receiver Register Status" "Empty,Full" group.long 0x134++0x03 line.long 0x00 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x138++0x03 line.long 0x00 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RX0,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 1 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 1 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 1 Receiver Register Status" "Empty,Full" group.long 0x148++0x03 line.long 0x00 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RX1,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS2 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x158++0x03 line.long 0x00 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" bitfld.long 0x00 6. " R2FFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R2FFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T2FFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T2FFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 2 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T2S ,Channel 2 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R2S ,Channel 2 Receiver Register Status" "Empty,Full" group.long 0x15C++0x03 line.long 0x00 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x160++0x03 line.long 0x00 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x164++0x03 line.long 0x00 "MCSPI_RX2,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A0000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A0000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x16C++0x03 line.long 0x00 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" bitfld.long 0x00 6. " R3FFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R3FFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T3FFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T3FFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 3 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T3S ,Channel 3 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R3S ,Channel 3 Receiver Register Status" "Empty,Full" group.long 0x170++0x03 line.long 0x00 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x174++0x03 line.long 0x00 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x178++0x03 line.long 0x00 "MCSPI_RX3,This register contains a single SPI word received through the serial link" group.long 0x17C++0x03 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.byte 0x00 16.--31. 1. " WCNT ,Spi word counter" hexmask.long.byte 0x00 0.--15. 1. " AFL ,Buffer Almost Full" hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty" if (((d.l(ad:0x481A0000+0x128))&0x100)==0x100) group.long 0x180++0x03 line.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" else hgroup.long 0x180++0x03 hide.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" hgroup.long 0x1A0++0x03 hide.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" endif width 11. tree.end tree "MCSPI 2" base ad:0x481A2000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x04++0x03 line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, i.e. typically the module's HDL generics" bitfld.long 0x00 6. " RETMODE ,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "Disabled,Enabled" bitfld.long 0x00 1.--5. " FFNBYTE ,Defines the value of FFNBYTE generic parameter" "-,16,32,-,64,-,-,-,128,-,256,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 0. " USEFIFO ,This bit field indicates if a FIFO is integrated within controller design with its management" "No,Yes" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the hard coded RTL revision number" bitfld.long 0x00 4.--7. " Major ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " Minor ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " width 17. if (((d.l(ad:0x481A2000+0x110))&0x4)==0x4) //this.ENAWAKEUP== "Enabled" group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode,Idle mode wakeup capable" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" else group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode," bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" endif rgroup.long 0x114++0x03 line.long 0x00 "MCSPI_SYSSTS,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" if (((d.l(ad:0x481A2000+0x128))&0x4)==0x4) //MCSPI_MODULCTRL.MS== "slave" group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only)(Channel 0)" "Not overflow,Overflow" eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" else group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" endif group.long 0x11C++0x03 line.long 0x00 "MCSPI_IRQEN,This register allows to enable/disable the module internal sources of interrupt, on an event-by-event basis" bitfld.long 0x00 17. " EOW_EN ,End of Word count Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. " WKE ,Wake Up event interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " RX3_FULL_EN ,Receiver register Full Interrupt Enable" "Disabled,Enabled(Channel 3)" bitfld.long 0x00 13. " TX3_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 3)" "Disabled,Enabled" bitfld.long 0x00 12. " TX3_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 3)" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RX2_FULL_EN ,Receiver register Full Interrupt Enable(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 9. " TX2_UNDERFLOW_EN ,TX2_UNDERFLOW_EN(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 8. " TX2_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 2)" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " RX1_FULL_EN ,Receiver register Full Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 5. " TX1_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 4. " TX1_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 1)" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RX0_OVERFLOW_EN ,Receiver register Overflow Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 2. " RX0_FULL_EN ,Receiver register Full Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 1. " TX0_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 0)" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TX0_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 0)" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "MCSPI_WAKEUPEN,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis" bitfld.long 0x00 0. " WKEN ,WakeUp functionality in slave mode" "Not allowed,Allowed" textline " " group.long 0x124++0x03 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect" bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Forced" bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0]" "Output,Input" bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input" bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input" textline " " bitfld.long 0x00 7. " WAKD ,SWAKEUP output" "Low,High" bitfld.long 0x00 6. " SPICLK ,Signal data value" "Low,High" bitfld.long 0x00 5. " SPIDAT_1 ,Signal data value" "Low,High" bitfld.long 0x00 4. " SPIDAT_0 ,Signal data value" "Low,High" textline " " bitfld.long 0x00 3. " SPIEN_3 ,Signal data value" "Low,High" bitfld.long 0x00 2. " SPIEN_2 ,Signal data value" "Low,High" bitfld.long 0x00 1. " SPIEN_1 ,Signal data value" "Low,High" bitfld.long 0x00 0. " SPIEN_0 ,Signal data value" "Low,High" if (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //this.MS== "slave" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //this.MS== "slave" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //this.MS== "Master" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //this.MS== "Master" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 4.--6. " INITDLY ,Initial spi delay for first transfer" "No delay,4 clk delay,8 clk delay,16 clk delay,32 clk delay,,," bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" endif textline " " if (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 0 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 0 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 0 Receiver Register Status" "Empty,Full" group.long 0x134++0x03 line.long 0x00 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x138++0x03 line.long 0x00 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RX0,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 1 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 1 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 1 Receiver Register Status" "Empty,Full" group.long 0x148++0x03 line.long 0x00 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RX1,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS2 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x158++0x03 line.long 0x00 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" bitfld.long 0x00 6. " R2FFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R2FFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T2FFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T2FFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 2 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T2S ,Channel 2 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R2S ,Channel 2 Receiver Register Status" "Empty,Full" group.long 0x15C++0x03 line.long 0x00 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x160++0x03 line.long 0x00 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x164++0x03 line.long 0x00 "MCSPI_RX2,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A2000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A2000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x16C++0x03 line.long 0x00 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" bitfld.long 0x00 6. " R3FFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R3FFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T3FFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T3FFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 3 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T3S ,Channel 3 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R3S ,Channel 3 Receiver Register Status" "Empty,Full" group.long 0x170++0x03 line.long 0x00 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x174++0x03 line.long 0x00 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x178++0x03 line.long 0x00 "MCSPI_RX3,This register contains a single SPI word received through the serial link" group.long 0x17C++0x03 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.byte 0x00 16.--31. 1. " WCNT ,Spi word counter" hexmask.long.byte 0x00 0.--15. 1. " AFL ,Buffer Almost Full" hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty" if (((d.l(ad:0x481A2000+0x128))&0x100)==0x100) group.long 0x180++0x03 line.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" else hgroup.long 0x180++0x03 hide.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" hgroup.long 0x1A0++0x03 hide.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" endif width 11. tree.end tree "MCSPI 3" base ad:0x481A4000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x04++0x03 line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, i.e. typically the module's HDL generics" bitfld.long 0x00 6. " RETMODE ,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "Disabled,Enabled" bitfld.long 0x00 1.--5. " FFNBYTE ,Defines the value of FFNBYTE generic parameter" "-,16,32,-,64,-,-,-,128,-,256,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 0. " USEFIFO ,This bit field indicates if a FIFO is integrated within controller design with its management" "No,Yes" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the hard coded RTL revision number" bitfld.long 0x00 4.--7. " Major ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " Minor ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " width 17. if (((d.l(ad:0x481A4000+0x110))&0x4)==0x4) //this.ENAWAKEUP== "Enabled" group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode,Idle mode wakeup capable" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" else group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode," bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" endif rgroup.long 0x114++0x03 line.long 0x00 "MCSPI_SYSSTS,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" if (((d.l(ad:0x481A4000+0x128))&0x4)==0x4) //MCSPI_MODULCTRL.MS== "slave" group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only)(Channel 0)" "Not overflow,Overflow" eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" else group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" endif group.long 0x11C++0x03 line.long 0x00 "MCSPI_IRQEN,This register allows to enable/disable the module internal sources of interrupt, on an event-by-event basis" bitfld.long 0x00 17. " EOW_EN ,End of Word count Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. " WKE ,Wake Up event interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " RX3_FULL_EN ,Receiver register Full Interrupt Enable" "Disabled,Enabled(Channel 3)" bitfld.long 0x00 13. " TX3_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 3)" "Disabled,Enabled" bitfld.long 0x00 12. " TX3_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 3)" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RX2_FULL_EN ,Receiver register Full Interrupt Enable(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 9. " TX2_UNDERFLOW_EN ,TX2_UNDERFLOW_EN(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 8. " TX2_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 2)" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " RX1_FULL_EN ,Receiver register Full Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 5. " TX1_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 4. " TX1_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 1)" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RX0_OVERFLOW_EN ,Receiver register Overflow Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 2. " RX0_FULL_EN ,Receiver register Full Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 1. " TX0_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 0)" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TX0_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 0)" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "MCSPI_WAKEUPEN,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis" bitfld.long 0x00 0. " WKEN ,WakeUp functionality in slave mode" "Not allowed,Allowed" textline " " group.long 0x124++0x03 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect" bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Forced" bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0]" "Output,Input" bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input" bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input" textline " " bitfld.long 0x00 7. " WAKD ,SWAKEUP output" "Low,High" bitfld.long 0x00 6. " SPICLK ,Signal data value" "Low,High" bitfld.long 0x00 5. " SPIDAT_1 ,Signal data value" "Low,High" bitfld.long 0x00 4. " SPIDAT_0 ,Signal data value" "Low,High" textline " " bitfld.long 0x00 3. " SPIEN_3 ,Signal data value" "Low,High" bitfld.long 0x00 2. " SPIEN_2 ,Signal data value" "Low,High" bitfld.long 0x00 1. " SPIEN_1 ,Signal data value" "Low,High" bitfld.long 0x00 0. " SPIEN_0 ,Signal data value" "Low,High" if (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //this.MS== "slave" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //this.MS== "slave" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //this.MS== "Master" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //this.MS== "Master" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 4.--6. " INITDLY ,Initial spi delay for first transfer" "No delay,4 clk delay,8 clk delay,16 clk delay,32 clk delay,,," bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" endif textline " " if (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 0 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 0 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 0 Receiver Register Status" "Empty,Full" group.long 0x134++0x03 line.long 0x00 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x138++0x03 line.long 0x00 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RX0,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 1 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 1 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 1 Receiver Register Status" "Empty,Full" group.long 0x148++0x03 line.long 0x00 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RX1,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS2 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x158++0x03 line.long 0x00 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" bitfld.long 0x00 6. " R2FFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R2FFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T2FFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T2FFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 2 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T2S ,Channel 2 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R2S ,Channel 2 Receiver Register Status" "Empty,Full" group.long 0x15C++0x03 line.long 0x00 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x160++0x03 line.long 0x00 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x164++0x03 line.long 0x00 "MCSPI_RX2,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x4)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x481A4000+0x128))&0x4)==0x0)&&(((d.l(ad:0x481A4000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x16C++0x03 line.long 0x00 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" bitfld.long 0x00 6. " R3FFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R3FFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T3FFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T3FFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 3 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T3S ,Channel 3 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R3S ,Channel 3 Receiver Register Status" "Empty,Full" group.long 0x170++0x03 line.long 0x00 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x174++0x03 line.long 0x00 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x178++0x03 line.long 0x00 "MCSPI_RX3,This register contains a single SPI word received through the serial link" group.long 0x17C++0x03 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.byte 0x00 16.--31. 1. " WCNT ,Spi word counter" hexmask.long.byte 0x00 0.--15. 1. " AFL ,Buffer Almost Full" hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty" if (((d.l(ad:0x481A4000+0x128))&0x100)==0x100) group.long 0x180++0x03 line.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" else hgroup.long 0x180++0x03 hide.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" hgroup.long 0x1A0++0x03 hide.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" endif width 11. tree.end tree "MCSPI 4" base ad:0x48345000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "ASP or WTBU,Highlander 0.8,," hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " R_RTL ,RTL Version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x04++0x03 line.long 0x00 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, i.e. typically the module's HDL generics" bitfld.long 0x00 6. " RETMODE ,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "Disabled,Enabled" bitfld.long 0x00 1.--5. " FFNBYTE ,Defines the value of FFNBYTE generic parameter" "-,16,32,-,64,-,-,-,128,-,256,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" bitfld.long 0x00 0. " USEFIFO ,This bit field indicates if a FIFO is integrated within controller design with its management" "No,Yes" group.long 0x10++0x03 line.long 0x00 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" rgroup.long 0x100++0x03 line.long 0x00 "MCSPI_REVISION,This register contains the hard coded RTL revision number" bitfld.long 0x00 4.--7. " Major ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " Minor ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " width 17. if (((d.l(ad:0x48345000+0x110))&0x4)==0x4) //this.ENAWAKEUP== "Enabled" group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode,Idle mode wakeup capable" bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" else group.long 0x110++0x03 line.long 0x00 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "OCP & Func.off,OCP maintained/Func. off,Func. maintained/OCP off,OCP & Func. maintained" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal behavior,Idle mode," bitfld.long 0x00 2. " ENAWAKEUP ,WakeUp feature control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP Clock gating strategy" "Free-running,Gating strategy" endif rgroup.long 0x114++0x03 line.long 0x00 "MCSPI_SYSSTS,This register provides status information about the module excluding the interrupt status information" bitfld.long 0x00 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" if (((d.l(ad:0x48345000+0x128))&0x4)==0x4) //MCSPI_MODULCTRL.MS== "slave" group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only)(Channel 0)" "Not overflow,Overflow" eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" else group.long 0x118++0x03 line.long 0x00 "MCSPI_IRQSTS,The interrupt status regroups all the status of the module internal events that can generate an interrupt" eventfld.long 0x00 17. " EOW ,End of word count event" "No,Yes" eventfld.long 0x00 16. " WKS ,Wake Up event in slave mode" "Disabled,Wake up" textline " " eventfld.long 0x00 14. " RX3_FULL ,Receiver register full or almost full(Channel 3)" "Not full,Full" eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow(Channel 3)" "Not underflow,Underflow" eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty or almost empty(Channel 3)" "Not empty,Empty" textline " " eventfld.long 0x00 10. " RX2_FULL ,Receiver register full or almost full(Channel 2)" "Not full,Full" eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow(Channel 2)" "Not underflow,Underflow" eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty or almost empty(Channel 2)" "Not empty,Empty" textline " " eventfld.long 0x00 6. " RX1_FULL ,Receiver register full or almost full(Channel 1)" "Not full,Full" eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow(Channel 1)" "Not underflow,Underflow" eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty or almost empty(Channel 1)" "Not empty,Empty" textline " " eventfld.long 0x00 2. " RX0_FULL ,Receiver register full or almost full(Channel 0)" "Not full,Full" eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow(Channel 0)" "Not underflow,Underflow" eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty or almost empty(Channel 0)" "Not empty,Empty" endif group.long 0x11C++0x03 line.long 0x00 "MCSPI_IRQEN,This register allows to enable/disable the module internal sources of interrupt, on an event-by-event basis" bitfld.long 0x00 17. " EOW_EN ,End of Word count Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. " WKE ,Wake Up event interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " RX3_FULL_EN ,Receiver register Full Interrupt Enable" "Disabled,Enabled(Channel 3)" bitfld.long 0x00 13. " TX3_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 3)" "Disabled,Enabled" bitfld.long 0x00 12. " TX3_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 3)" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " RX2_FULL_EN ,Receiver register Full Interrupt Enable(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 9. " TX2_UNDERFLOW_EN ,TX2_UNDERFLOW_EN(Channel 2)" "Disabled,Enabled" bitfld.long 0x00 8. " TX2_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 2)" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " RX1_FULL_EN ,Receiver register Full Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 5. " TX1_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 1)" "Disabled,Enabled" bitfld.long 0x00 4. " TX1_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 1)" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RX0_OVERFLOW_EN ,Receiver register Overflow Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 2. " RX0_FULL_EN ,Receiver register Full Interrupt Enable(Channel 0)" "Disabled,Enabled" bitfld.long 0x00 1. " TX0_UNDERFLOW_EN ,Transmitter register Underflow Interrupt Enable(Channel 0)" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " TX0_EMPTY_EN ,Transmitter register Empty Interrupt Enable(Channel 0)" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "MCSPI_WAKEUPEN,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis" bitfld.long 0x00 0. " WKEN ,WakeUp functionality in slave mode" "Not allowed,Allowed" textline " " group.long 0x124++0x03 line.long 0x00 "MCSPI_SYST,This register is used to check the correctness of the system interconnect" bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Forced" bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0]" "Output,Input" bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input" bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input" textline " " bitfld.long 0x00 7. " WAKD ,SWAKEUP output" "Low,High" bitfld.long 0x00 6. " SPICLK ,Signal data value" "Low,High" bitfld.long 0x00 5. " SPIDAT_1 ,Signal data value" "Low,High" bitfld.long 0x00 4. " SPIDAT_0 ,Signal data value" "Low,High" textline " " bitfld.long 0x00 3. " SPIEN_3 ,Signal data value" "Low,High" bitfld.long 0x00 2. " SPIEN_2 ,Signal data value" "Low,High" bitfld.long 0x00 1. " SPIEN_1 ,Signal data value" "Low,High" bitfld.long 0x00 0. " SPIEN_0 ,Signal data value" "Low,High" if (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //this.MS== "slave" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //this.MS== "slave" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //this.MS== "Master" && this.SINGLE== "Multi" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //this.MS== "Master" && this.SINGLE== "Single" group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address" "MCSPI_TX(i) and MCSPI_RX(i),MCSPI_DAFTX and MCSPI_DAFRX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 4.--6. " INITDLY ,Initial spi delay for first transfer" "No delay,4 clk delay,8 clk delay,16 clk delay,32 clk delay,,," bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" textline " " bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,Pin mode selection" "3PinMode,4PinMode" bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel (master mode only)" "Multi,Single" endif textline " " if (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x130++0x03 line.long 0x00 "MCSPI_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0" bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 0 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 0 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 0 Receiver Register Status" "Empty,Full" group.long 0x134++0x03 line.long 0x00 "MCSPI_CH0CTRL,This register is dedicated to enable the channel 0" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x138++0x03 line.long 0x00 "MCSPI_TX0,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x13C++0x03 line.long 0x00 "MCSPI_RX0,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,This register is dedicated to the configuration of the channel 1" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS1 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x144++0x03 line.long 0x00 "MCSPI_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1" bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 1 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " TXS ,Channel 1 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " RXS ,Channel 1 Receiver Register Status" "Empty,Full" group.long 0x148++0x03 line.long 0x00 "MCSPI_CH1CTRL,This register is dedicated to enable the channel 1" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "MCSPI_TX1,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x150++0x03 line.long 0x00 "MCSPI_RX1,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS0 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,This register is dedicated to the configuration of the channel 2" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS2 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x158++0x03 line.long 0x00 "MCSPI_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2" bitfld.long 0x00 6. " R2FFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R2FFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T2FFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T2FFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 2 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T2S ,Channel 2 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R2S ,Channel 2 Receiver Register Status" "Empty,Full" group.long 0x15C++0x03 line.long 0x00 "MCSPI_CH2CTRL,This register is dedicated to enable the channel 2" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x160++0x03 line.long 0x00 "MCSPI_TX2,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x164++0x03 line.long 0x00 "MCSPI_RX2,This register contains a single SPI word received through the serial link" if (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x4)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "slave" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN 0,SPIEN 1,SPIEN 2,SPIEN 3" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x0) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Multi" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" elif (((d.l(ad:0x48345000+0x128))&0x4)==0x0)&&(((d.l(ad:0x48345000+0x128))&0x1)==0x1) //MCSPI_MODULCTRL.MS== "Master" && MCSPI_MODULCTRL.SINGLE== "Single" group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,This register is dedicated to the configuration of the channel 3" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Disabled,Enabled" bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Disabled,Enabled" bitfld.long 0x00 25.--26. " TCS3 ,Chip Select Time Control" "0.5 clock,1.5 clock,2.5 clock,3.5 clock" textline " " bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "0,1" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " IS ,Input Select" "Line 0,Line 1" bitfld.long 0x00 17. " DPE1 ,Transmission Enable for data line 1" "Enabled,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission Enable for data line 0" "Enabled,Disabled" bitfld.long 0x00 15. " DMAR ,DMA Read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA Write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/Receive modes" "Trn. & Rec.,Receive,Transmit," bitfld.long 0x00 7.--11. " WL ,SPI word length" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" bitfld.long 0x00 6. " EPOL ,SPIEN polarity" "High,Low" textline " " bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,16384,32768," bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif rgroup.long 0x16C++0x03 line.long 0x00 "MCSPI_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3" bitfld.long 0x00 6. " R3FFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full" bitfld.long 0x00 5. " R3FFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty" bitfld.long 0x00 4. " T3FFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full" bitfld.long 0x00 3. " T3FFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty" textline " " bitfld.long 0x00 2. " EOT ,Channel 3 End of transfer Status" "No,Yes" bitfld.long 0x00 1. " T3S ,Channel 3 Transmitter Register Status" "Full,Empty" bitfld.long 0x00 0. " R3S ,Channel 3 Receiver Register Status" "Empty,Full" group.long 0x170++0x03 line.long 0x00 "MCSPI_CH3CTRL,This register is dedicated to enable the channel 3" hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x00 0. " EN ,Channel Enable" "Disabled,Enabled" group.long 0x174++0x03 line.long 0x00 "MCSPI_TX3,This register contains a single SPI word to transmit on the serial link" rgroup.long 0x178++0x03 line.long 0x00 "MCSPI_RX3,This register contains a single SPI word received through the serial link" group.long 0x17C++0x03 line.long 0x00 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer" hexmask.long.byte 0x00 16.--31. 1. " WCNT ,Spi word counter" hexmask.long.byte 0x00 0.--15. 1. " AFL ,Buffer Almost Full" hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty" if (((d.l(ad:0x48345000+0x128))&0x100)==0x100) group.long 0x180++0x03 line.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" rgroup.long 0x1A0++0x03 line.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" else hgroup.long 0x180++0x03 hide.long 0x00 "MCSPI_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit" hgroup.long 0x1A0++0x03 hide.long 0x00 "MCSPI_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit" endif width 11. tree.end tree.end tree "QSPI" tree "QSPI 0" base ad:0x47900000 width 23. rgroup.long 0x000++0x03 line.long 0x00 "QSPI_PID," bitfld.long 0x00 30.--31. " SCHEME , The scheme of the register used" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC , The function of the module being used" bitfld.long 0x00 11.--15. " RTL_VERSION , RTL version number " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR , Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,CUSTOM" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision Number" group.long 0x010++0x03 line.long 0x00 "QSPI_SYSCONFIG,QSPI_SYSCONFIG" bitfld.long 0x00 2.--3. " IDLE_MODE ,Configuration of the local target state management mode" "Idle state,No-idle,Smart-idle,Smart-idle wakeup-capable" group.long 0x020++0x03 line.long 0x00 "QSPI_INTR_STS_RAW_SET,This register contains the raw interrupt status" bitfld.long 0x00 1. " WIRQ_RAW ,Word Interrupt Status" "Inactive,Active" bitfld.long 0x00 0. " FIRQ_RAW ,Frame Interrupt Status" "Inactive,Active" group.long 0x024++0x03 line.long 0x00 "QSPI_INTR_STS_EN_CLR,Interrupt Status Enabled/Clear Register" bitfld.long 0x00 1. " WIRQ_ENA ,Word Interrupt Enabled Status" "Inactive,Active" bitfld.long 0x00 0. " FIRQ_ENA ,Frame Interrupt Enabled Status" "Inactive,Active" group.long 0x028++0x03 line.long 0x00 "QSPI_INTR_EN_SET_REG,Interrupt Enable/Set Register" bitfld.long 0x00 1. " WIRQ_ENA_SET ,Word Interrupt Enable/Set" "Inactive,Active" bitfld.long 0x00 0. " FIRQ_ENA_SET ,Frame Interrupt Enable/Set" "Inactive,Active" group.long 0x02C++0x03 line.long 0x00 "QSPI_INTR_EN_CLR_REG,Interrupt Enable/Clear Register" bitfld.long 0x00 1. " WIRQ_ENA_CLR ,Word Interrupt Enable/Clear" "Inactive,Active" bitfld.long 0x00 0. " FIRQ_ENA_CLR ,Frame Interrupt Enable/Clear" "Inactive,Active" group.long 0x030++0x03 line.long 0x00 "QSPI_INTC_EOI_REG,INTC EOI Register" if (((d.l(ad:0x47900000+0x04C))&0x01)==0x01) //QSPI_STS_REG.BUSY== "busy" rgroup.long 0x040++0x03 line.long 0x00 "QSPI_CLOCK_CNTRL_REG,SPI Clock Control (SPICC) Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " DCLK_DIV , Serial data clock divide by ratio" rgroup.long 0x044++0x03 line.long 0x00 "QSPI_DC_REG,SPI Device Control (SPIDC) Register" bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 if [ CKP3 =0|CKP3 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Active low,Active high" textline " " bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "Not transferred,Transferred" bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 if [ CKP2 =0|CKP2 =1 ]" "Failing/rising,Rising/failing" textline " " bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Active low,Active high" bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "Not transferred,Transferred" bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "Same cycle,1 DCLK,2 DCLK,3 DCLK" textline " " bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 if [ CKP1 =0|CKP1 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Active low,Active high" bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1" textline " " bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 if [ CKP0 =0|CKP0 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select" "Active low,Active high" textline " " bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select" "Not transferred,Transferred" rgroup.long 0x048++0x03 line.long 0x00 "QSPI_CMD_REG,SPI Command Register (SPICR)" bitfld.long 0x00 28.--29. " CSNUM ,Device select" "0 active,,," bitfld.long 0x00 19.--23. " WLEN ,Word length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits" bitfld.long 0x00 16.--18. " CMD ,Transfer command" ",4 pin Read Single,4 pin Write Single,4 pin Read Dual,,3 pin Read Single,3 pin Write Single,6 pin Read Quad" textline " " bitfld.long 0x00 15. " FIRQ ,Frame count interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WIRQ ,Word count interrupt enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " FLEN ,Frame Length" else group.long 0x040++0x03 line.long 0x00 "QSPI_CLOCK_CNTRL_REG,SPI Clock Control (SPICC) Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " DCLK_DIV , Serial data clock divide by ratio" group.long 0x044++0x03 line.long 0x00 "QSPI_DC_REG,SPI Device Control (SPIDC) Register" bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 if [ CKP3 =0|CKP3 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Active low,Active high" textline " " bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "Not transferred,Transferred" bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 if [ CKP2 =0|CKP2 =1 ]" "Failing/rising,Rising/failing" textline " " bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Active low,Active high" bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "Not transferred,Transferred" bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "Same cycle,1 DCLK,2 DCLK,3 DCLK" textline " " bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 if [ CKP1 =0|CKP1 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Active low,Active high" bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1" textline " " bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 if [ CKP0 =0|CKP0 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select" "Active low,Active high" textline " " bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select" "Not transferred,Transferred" group.long 0x048++0x03 line.long 0x00 "QSPI_CMD_REG,SPI Command Register (SPICR)" bitfld.long 0x00 28.--29. " CSNUM ,Device select" "0 active,,," bitfld.long 0x00 19.--23. " WLEN ,Word length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits" bitfld.long 0x00 16.--18. " CMD ,Transfer command" ",4 pin Read Single,4 pin Write Single,4 pin Read Dual,,3 pin Read Single,3 pin Write Single,6 pin Read Quad" textline " " bitfld.long 0x00 15. " FIRQ ,Frame count interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WIRQ ,Word count interrupt enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " FLEN ,Frame Length" endif group.long 0x04C++0x03 line.long 0x00 "QSPI_STS_REG,SPI Status Register (SPISR)" hexmask.long.word 0x00 16.--27. 1. " WDCNT , Word count" bitfld.long 0x00 2. " FC ,Frame complete" "Not completed,Completed" textline " " bitfld.long 0x00 1. " WC ,Word complete" "Not completed,Completed" bitfld.long 0x00 0. " BUSY ,Busy bit" "Idle,Busy" if (((d.l(ad:0x47900000+0x04C))&0x01)==0x01) //QSPI_STS_REG.BUSY== "busy" rgroup.long 0x050++0x03 line.long 0x00 "QSPI_DATA_REG,SPI Data Register (SPIDR)" else group.long 0x050++0x03 line.long 0x00 "QSPI_DATA_REG,SPI Data Register (SPIDR)" endif width 19. tree "QSPI_SETUP_REG - array[4]" group.long 0x054++0x03 line.long 0x00 "QSPI_SETUP_REG[0],Memory Mapped SPI Setup Register 0" bitfld.long 0x00 24.--28. " NUM_D_BITS , Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--23. 1. " WCMD , Write command" bitfld.long 0x00 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command" "Normal read,Dual read,Normal read,Quad read" textline " " bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "No bytes,1,2,3" bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x00 0.--7. 1. " RCMD , Read Command" group.long 0x058++0x03 line.long 0x00 "QSPI_SETUP_REG[1],Memory Mapped SPI Setup Register 1" bitfld.long 0x00 24.--28. " NUM_D_BITS , Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--23. 1. " WCMD , Write command" bitfld.long 0x00 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command" "Normal read,Dual read,Normal read,Quad read" textline " " bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "No bytes,1,2,3" bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x00 0.--7. 1. " RCMD , Read Command" group.long 0x05C++0x03 line.long 0x00 "QSPI_SETUP_REG[2],Memory Mapped SPI Setup Register 2" bitfld.long 0x00 24.--28. " NUM_D_BITS , Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--23. 1. " WCMD , Write command" bitfld.long 0x00 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command" "Normal read,Dual read,Normal read,Quad read" textline " " bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "No bytes,1,2,3" bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x00 0.--7. 1. " RCMD , Read Command" group.long 0x060++0x03 line.long 0x00 "QSPI_SETUP_REG[3],Memory Mapped SPI Setup Register 3" bitfld.long 0x00 24.--28. " NUM_D_BITS , Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--23. 1. " WCMD , Write command" bitfld.long 0x00 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command" "Normal read,Dual read,Normal read,Quad read" textline " " bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "No bytes,1,2,3" bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x00 0.--7. 1. " RCMD , Read Command" tree.end textline " " group.long 0x064++0x03 line.long 0x00 "QSPI_SWITCH_REG,Memory Mapped SPI Switch Register" bitfld.long 0x00 1. " MM_INT_EN ,Memory Mapped mode interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " MMPT_S ,MMPT select" "Port is selected,Memory mapped" group.long 0x068++0x03 line.long 0x00 "QSPI_DATA_REG_1,SPI Data1 Register (SPIDR1)" group.long 0x06C++0x03 line.long 0x00 "QSPI_DATA_REG_2,SPI Data2 Register (SPIDR2)" group.long 0x070++0x03 line.long 0x00 "QSPI_DATA_REG_3,SPI Data3 Register (SPIDR3)" width 11. tree.end tree "QSPI 1" base ad:0x30000000 width 23. rgroup.long 0x000++0x03 line.long 0x00 "QSPI_PID," bitfld.long 0x00 30.--31. " SCHEME , The scheme of the register used" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC , The function of the module being used" bitfld.long 0x00 11.--15. " RTL_VERSION , RTL version number " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR , Major revision number" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,CUSTOM" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision Number" group.long 0x010++0x03 line.long 0x00 "QSPI_SYSCONFIG,QSPI_SYSCONFIG" bitfld.long 0x00 2.--3. " IDLE_MODE ,Configuration of the local target state management mode" "Idle state,No-idle,Smart-idle,Smart-idle wakeup-capable" group.long 0x020++0x03 line.long 0x00 "QSPI_INTR_STS_RAW_SET,This register contains the raw interrupt status" bitfld.long 0x00 1. " WIRQ_RAW ,Word Interrupt Status" "Inactive,Active" bitfld.long 0x00 0. " FIRQ_RAW ,Frame Interrupt Status" "Inactive,Active" group.long 0x024++0x03 line.long 0x00 "QSPI_INTR_STS_EN_CLR,Interrupt Status Enabled/Clear Register" bitfld.long 0x00 1. " WIRQ_ENA ,Word Interrupt Enabled Status" "Inactive,Active" bitfld.long 0x00 0. " FIRQ_ENA ,Frame Interrupt Enabled Status" "Inactive,Active" group.long 0x028++0x03 line.long 0x00 "QSPI_INTR_EN_SET_REG,Interrupt Enable/Set Register" bitfld.long 0x00 1. " WIRQ_ENA_SET ,Word Interrupt Enable/Set" "Inactive,Active" bitfld.long 0x00 0. " FIRQ_ENA_SET ,Frame Interrupt Enable/Set" "Inactive,Active" group.long 0x02C++0x03 line.long 0x00 "QSPI_INTR_EN_CLR_REG,Interrupt Enable/Clear Register" bitfld.long 0x00 1. " WIRQ_ENA_CLR ,Word Interrupt Enable/Clear" "Inactive,Active" bitfld.long 0x00 0. " FIRQ_ENA_CLR ,Frame Interrupt Enable/Clear" "Inactive,Active" group.long 0x030++0x03 line.long 0x00 "QSPI_INTC_EOI_REG,INTC EOI Register" if (((d.l(ad:0x30000000+0x04C))&0x01)==0x01) //QSPI_STS_REG.BUSY== "busy" rgroup.long 0x040++0x03 line.long 0x00 "QSPI_CLOCK_CNTRL_REG,SPI Clock Control (SPICC) Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " DCLK_DIV , Serial data clock divide by ratio" rgroup.long 0x044++0x03 line.long 0x00 "QSPI_DC_REG,SPI Device Control (SPIDC) Register" bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 if [ CKP3 =0|CKP3 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Active low,Active high" textline " " bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "Not transferred,Transferred" bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 if [ CKP2 =0|CKP2 =1 ]" "Failing/rising,Rising/failing" textline " " bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Active low,Active high" bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "Not transferred,Transferred" bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "Same cycle,1 DCLK,2 DCLK,3 DCLK" textline " " bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 if [ CKP1 =0|CKP1 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Active low,Active high" bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1" textline " " bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 if [ CKP0 =0|CKP0 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select" "Active low,Active high" textline " " bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select" "Not transferred,Transferred" rgroup.long 0x048++0x03 line.long 0x00 "QSPI_CMD_REG,SPI Command Register (SPICR)" bitfld.long 0x00 28.--29. " CSNUM ,Device select" "0 active,,," bitfld.long 0x00 19.--23. " WLEN ,Word length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits" bitfld.long 0x00 16.--18. " CMD ,Transfer command" ",4 pin Read Single,4 pin Write Single,4 pin Read Dual,,3 pin Read Single,3 pin Write Single,6 pin Read Quad" textline " " bitfld.long 0x00 15. " FIRQ ,Frame count interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WIRQ ,Word count interrupt enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " FLEN ,Frame Length" else group.long 0x040++0x03 line.long 0x00 "QSPI_CLOCK_CNTRL_REG,SPI Clock Control (SPICC) Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " DCLK_DIV , Serial data clock divide by ratio" group.long 0x044++0x03 line.long 0x00 "QSPI_DC_REG,SPI Device Control (SPIDC) Register" bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 if [ CKP3 =0|CKP3 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Active low,Active high" textline " " bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "Not transferred,Transferred" bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 if [ CKP2 =0|CKP2 =1 ]" "Failing/rising,Rising/failing" textline " " bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Active low,Active high" bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "Not transferred,Transferred" bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "Same cycle,1 DCLK,2 DCLK,3 DCLK" textline " " bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 if [ CKP1 =0|CKP1 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Active low,Active high" bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1" textline " " bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "Same cycle,1 DCLK,2 DCLK,3 DCLK" bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 if [ CKP0 =0|CKP0 =1 ]" "Failing/rising,Rising/failing" bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select" "Active low,Active high" textline " " bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select" "Not transferred,Transferred" group.long 0x048++0x03 line.long 0x00 "QSPI_CMD_REG,SPI Command Register (SPICR)" bitfld.long 0x00 28.--29. " CSNUM ,Device select" "0 active,,," bitfld.long 0x00 19.--23. " WLEN ,Word length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits,19 bits,20 bits,21 bits,22 bits,23 bits,24 bits,25 bits,26 bits,27 bits,28 bits,29 bits,30 bits,31 bits,32 bits" bitfld.long 0x00 16.--18. " CMD ,Transfer command" ",4 pin Read Single,4 pin Write Single,4 pin Read Dual,,3 pin Read Single,3 pin Write Single,6 pin Read Quad" textline " " bitfld.long 0x00 15. " FIRQ ,Frame count interrupt enable" "Disabled,Enabled" bitfld.long 0x00 14. " WIRQ ,Word count interrupt enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " FLEN ,Frame Length" endif group.long 0x04C++0x03 line.long 0x00 "QSPI_STS_REG,SPI Status Register (SPISR)" hexmask.long.word 0x00 16.--27. 1. " WDCNT , Word count" bitfld.long 0x00 2. " FC ,Frame complete" "Not completed,Completed" textline " " bitfld.long 0x00 1. " WC ,Word complete" "Not completed,Completed" bitfld.long 0x00 0. " BUSY ,Busy bit" "Idle,Busy" if (((d.l(ad:0x30000000+0x04C))&0x01)==0x01) //QSPI_STS_REG.BUSY== "busy" rgroup.long 0x050++0x03 line.long 0x00 "QSPI_DATA_REG,SPI Data Register (SPIDR)" else group.long 0x050++0x03 line.long 0x00 "QSPI_DATA_REG,SPI Data Register (SPIDR)" endif width 19. tree "QSPI_SETUP_REG - array[4]" group.long 0x054++0x03 line.long 0x00 "QSPI_SETUP_REG[0],Memory Mapped SPI Setup Register 0" bitfld.long 0x00 24.--28. " NUM_D_BITS , Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--23. 1. " WCMD , Write command" bitfld.long 0x00 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command" "Normal read,Dual read,Normal read,Quad read" textline " " bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "No bytes,1,2,3" bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x00 0.--7. 1. " RCMD , Read Command" group.long 0x058++0x03 line.long 0x00 "QSPI_SETUP_REG[1],Memory Mapped SPI Setup Register 1" bitfld.long 0x00 24.--28. " NUM_D_BITS , Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--23. 1. " WCMD , Write command" bitfld.long 0x00 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command" "Normal read,Dual read,Normal read,Quad read" textline " " bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "No bytes,1,2,3" bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x00 0.--7. 1. " RCMD , Read Command" group.long 0x05C++0x03 line.long 0x00 "QSPI_SETUP_REG[2],Memory Mapped SPI Setup Register 2" bitfld.long 0x00 24.--28. " NUM_D_BITS , Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--23. 1. " WCMD , Write command" bitfld.long 0x00 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command" "Normal read,Dual read,Normal read,Quad read" textline " " bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "No bytes,1,2,3" bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x00 0.--7. 1. " RCMD , Read Command" group.long 0x060++0x03 line.long 0x00 "QSPI_SETUP_REG[3],Memory Mapped SPI Setup Register 3" bitfld.long 0x00 24.--28. " NUM_D_BITS , Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--23. 1. " WCMD , Write command" bitfld.long 0x00 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command" "Normal read,Dual read,Normal read,Quad read" textline " " bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "No bytes,1,2,3" bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes" hexmask.long.byte 0x00 0.--7. 1. " RCMD , Read Command" tree.end textline " " group.long 0x064++0x03 line.long 0x00 "QSPI_SWITCH_REG,Memory Mapped SPI Switch Register" bitfld.long 0x00 1. " MM_INT_EN ,Memory Mapped mode interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " MMPT_S ,MMPT select" "Port is selected,Memory mapped" group.long 0x068++0x03 line.long 0x00 "QSPI_DATA_REG_1,SPI Data1 Register (SPIDR1)" group.long 0x06C++0x03 line.long 0x00 "QSPI_DATA_REG_2,SPI Data2 Register (SPIDR2)" group.long 0x070++0x03 line.long 0x00 "QSPI_DATA_REG_3,SPI Data3 Register (SPIDR3)" width 11. tree.end tree.end tree "GPIO(General-Purpose Input/Output)" tree "GPIO 0" base ad:0x44E07000 width 16. rgroup.long 0x000++0x03 line.long 0x00 "GPIO_REVISION,Revision number of the GPIO module" bitfld.long 0x00 30.--31. " SCHEME , Used to distinguish between old Scheme and current. [[br]]" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC , Indicates a software compatible module family" bitfld.long 0x00 11.--15. " RTL , RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR , Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision" group.long 0x010++0x03 line.long 0x00 "GPIO_SYSCONFIG,Controls the various parameters of the L4 interconnect" bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management Req/Ack control" "Force-idle,No-idle,Smart-idle,Smart Idle Wakeup" bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software Reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Clock gating" textline " " group.long 0x020++0x03 line.long 0x00 "GPIO_EOI,This module supports DMA events with its interrupt signal" bitfld.long 0x00 0. " DMAEVT_ACK ,Write 0 to acknowledge DMA event has been completed" "Not completed,Completed" width 19. group.long 0x024++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_0,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x028++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_1,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x02C++0x03 line.long 0x00 "GPIO_IRQSTS_0,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x030++0x03 line.long 0x00 "GPIO_IRQSTS_1,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x034++0x03 line.long 0x00 "GPIO_IRQSTS_SET_0,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x038++0x03 line.long 0x00 "GPIO_IRQSTS_SET_1,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x03C++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_0,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x040++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_1,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x044++0x03 line.long 0x00 "GPIO_IRQWAKEN_0,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" group.long 0x048++0x03 line.long 0x00 "GPIO_IRQWAKEN_1,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" textline " " width 13. rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTS,The GPIO_SYSSTS register provides the reset status information about the GPIO module" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x03 line.long 0x00 "GPIO_CTRL,The GPIO_CTRL register controls the clock gating functionality" bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating Ratio" "Normal,/2,/4,/8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" group.long 0x134++0x03 line.long 0x00 "GPIO_OE,The GPIO_OE register is used to enable the pins output capabilities" bitfld.long 0x00 31. " OUTPUTEN_31 ,Output Data Enable 31" "Output,Input" bitfld.long 0x00 30. " OUTPUTEN_30 ,Output Data Enable 30" "Output,Input" bitfld.long 0x00 29. " OUTPUTEN_29 ,Output Data Enable 29" "Output,Input" bitfld.long 0x00 28. " OUTPUTEN_28 ,Output Data Enable 28" "Output,Input" textline " " bitfld.long 0x00 27. " OUTPUTEN_27 ,Output Data Enable 27" "Output,Input" bitfld.long 0x00 26. " OUTPUTEN_26 ,Output Data Enable 26" "Output,Input" bitfld.long 0x00 25. " OUTPUTEN_25 ,Output Data Enable 25" "Output,Input" bitfld.long 0x00 24. " OUTPUTEN_24 ,Output Data Enable 24" "Output,Input" textline " " bitfld.long 0x00 23. " OUTPUTEN_23 ,Output Data Enable 23" "Output,Input" bitfld.long 0x00 22. " OUTPUTEN_22 ,Output Data Enable 22" "Output,Input" bitfld.long 0x00 21. " OUTPUTEN_21 ,Output Data Enable 21" "Output,Input" bitfld.long 0x00 20. " OUTPUTEN_20 ,Output Data Enable 20" "Output,Input" textline " " bitfld.long 0x00 19. " OUTPUTEN_19 ,Output Data Enable 19" "Output,Input" bitfld.long 0x00 18. " OUTPUTEN_18 ,Output Data Enable 18" "Output,Input" bitfld.long 0x00 17. " OUTPUTEN_17 ,Output Data Enable 17" "Output,Input" bitfld.long 0x00 16. " OUTPUTEN_16 ,Output Data Enable 16" "Output,Input" textline " " bitfld.long 0x00 15. " OUTPUTEN_15 ,Output Data Enable 15" "Output,Input" bitfld.long 0x00 14. " OUTPUTEN_14 ,Output Data Enable 14" "Output,Input" bitfld.long 0x00 13. " OUTPUTEN_13 ,Output Data Enable 13" "Output,Input" bitfld.long 0x00 12. " OUTPUTEN_12 ,Output Data Enable 12" "Output,Input" textline " " bitfld.long 0x00 11. " OUTPUTEN_11 ,Output Data Enable 11" "Output,Input" bitfld.long 0x00 10. " OUTPUTEN_10 ,Output Data Enable 10" "Output,Input" bitfld.long 0x00 9. " OUTPUTEN_9 ,Output Data Enable 9" "Output,Input" bitfld.long 0x00 8. " OUTPUTEN_8 ,Output Data Enable 8" "Output,Input" textline " " bitfld.long 0x00 7. " OUTPUTEN_7 ,Output Data Enable 7" "Output,Input" bitfld.long 0x00 6. " OUTPUTEN_6 ,Output Data Enable 6" "Output,Input" bitfld.long 0x00 5. " OUTPUTEN_5 ,Output Data Enable 5" "Output,Input" bitfld.long 0x00 4. " OUTPUTEN_4 ,Output Data Enable 4" "Output,Input" textline " " bitfld.long 0x00 3. " OUTPUTEN_3 ,Output Data Enable 3" "Output,Input" bitfld.long 0x00 2. " OUTPUTEN_2 ,Output Data Enable 2" "Output,Input" bitfld.long 0x00 1. " OUTPUTEN_1 ,Output Data Enable 1" "Output,Input" bitfld.long 0x00 0. " OUTPUTEN_0 ,Output Data Enable 0" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,The GPIO_DATAIN register is used to register the data that is read from the GPIO pins" hexmask.long 0x00 0.--31. 1. " DATAIN , Sampled input data" group.long 0x13C++0x03 line.long 0x00 "GPIO_DATAOUT,The GPIO_DATAOUT register is used for setting the value of the GPIO output pins" hexmask.long 0x00 0.--31. 1. " DATAOUT , Data to set on output pins" textline " " width 21. group.long 0x140++0x03 line.long 0x00 "GPIO_LEVELDETECT0,Register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT0_31 ,Low Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT0_30 ,Low Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT0_29 ,Low Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT0_28 ,Low Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT0_27 ,Low Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT0_26 ,Low Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT0_25 ,Low Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT0_24 ,Low Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT0_23 ,Low Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT0_22 ,Low Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT0_21 ,Low Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT0_20 ,Low Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT0_19 ,Low Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT0_18 ,Low Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT0_17 ,Low Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT0_16 ,Low Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT0_15 ,Low Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT0_14 ,Low Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT0_13 ,Low Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT0_12 ,Low Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT0_11 ,Low Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT0_10 ,Low Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT0_9 ,Low Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT0_8 ,Low Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT0_7 ,Low Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT0_6 ,Low Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT0_5 ,Low Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT0_4 ,Low Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT0_3 ,Low Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT0_2 ,Low Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT0_1 ,Low Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT0_0 ,Low Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "GPIO_LEVELDETECT1,Register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT1_31 ,High Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT1_30 ,High Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT1_29 ,High Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT1_28 ,High Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT1_27 ,High Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT1_26 ,High Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT1_25 ,High Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT1_24 ,High Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT1_23 ,High Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT1_22 ,High Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT1_21 ,High Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT1_20 ,High Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT1_19 ,High Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT1_18 ,High Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT1_17 ,High Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT1_16 ,High Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT1_15 ,High Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT1_14 ,High Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT1_13 ,High Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT1_12 ,High Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT1_11 ,High Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT1_10 ,High Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT1_9 ,High Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT1_8 ,High Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT1_7 ,High Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT1_6 ,High Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT1_5 ,High Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT1_4 ,High Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT1_3 ,High Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT1_2 ,High Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT1_1 ,High Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT1_0 ,High Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x148++0x03 line.long 0x00 "GPIO_RISINGDETECT,Register is used to enable/disable for each input lines the rising-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " RISINGDETECT_31 ,Rising Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " RISINGDETECT_30 ,Rising Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " RISINGDETECT_29 ,Rising Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " RISINGDETECT_28 ,Rising Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RISINGDETECT_27 ,Rising Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " RISINGDETECT_26 ,Rising Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " RISINGDETECT_25 ,Rising Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " RISINGDETECT_24 ,Rising Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " RISINGDETECT_23 ,Rising Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " RISINGDETECT_22 ,Rising Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " RISINGDETECT_21 ,Rising Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " RISINGDETECT_20 ,Rising Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RISINGDETECT_19 ,Rising Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " RISINGDETECT_18 ,Rising Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " RISINGDETECT_17 ,Rising Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " RISINGDETECT_16 ,Rising Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RISINGDETECT_15 ,Rising Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " RISINGDETECT_14 ,Rising Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " RISINGDETECT_13 ,Rising Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " RISINGDETECT_12 ,Rising Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " RISINGDETECT_11 ,Rising Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " RISINGDETECT_10 ,Rising Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " RISINGDETECT_9 ,Rising Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " RISINGDETECT_8 ,Rising Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " RISINGDETECT_7 ,Rising Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " RISINGDETECT_6 ,Rising Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " RISINGDETECT_5 ,Rising Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " RISINGDETECT_4 ,Rising Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RISINGDETECT_3 ,Rising Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " RISINGDETECT_2 ,Rising Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " RISINGDETECT_1 ,Rising Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " RISINGDETECT_0 ,Rising Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "GPIO_FALLINGDETECT,Register is used to enable/disable for each input lines the falling-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " FALLINGDETECT_31 ,Falling Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " FALLINGDETECT_30 ,Falling Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " FALLINGDETECT_29 ,Falling Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " FALLINGDETECT_28 ,Falling Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " FALLINGDETECT_27 ,Falling Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " FALLINGDETECT_26 ,Falling Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " FALLINGDETECT_25 ,Falling Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " FALLINGDETECT_24 ,Falling Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FALLINGDETECT_23 ,Falling Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " FALLINGDETECT_22 ,Falling Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " FALLINGDETECT_21 ,Falling Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " FALLINGDETECT_20 ,Falling Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FALLINGDETECT_19 ,Falling Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " FALLINGDETECT_18 ,Falling Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " FALLINGDETECT_17 ,Falling Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " FALLINGDETECT_16 ,Falling Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FALLINGDETECT_15 ,Falling Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " FALLINGDETECT_14 ,Falling Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " FALLINGDETECT_13 ,Falling Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " FALLINGDETECT_12 ,Falling Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " FALLINGDETECT_11 ,Falling Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " FALLINGDETECT_10 ,Falling Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " FALLINGDETECT_9 ,Falling Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " FALLINGDETECT_8 ,Falling Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FALLINGDETECT_7 ,Falling Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " FALLINGDETECT_6 ,Falling Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " FALLINGDETECT_5 ,Falling Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " FALLINGDETECT_4 ,Falling Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FALLINGDETECT_3 ,Falling Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " FALLINGDETECT_2 ,Falling Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " FALLINGDETECT_1 ,Falling Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " FALLINGDETECT_0 ,Falling Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x150++0x03 line.long 0x00 "GPIO_DEBOUNCEN,Register is used to enable/disable the debouncing feature for each input line." bitfld.long 0x00 31. " DEBOUNCEEN_31 ,Input Debounce Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " DEBOUNCEEN_30 ,Input Debounce Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " DEBOUNCEEN_29 ,Input Debounce Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " DEBOUNCEEN_28 ,Input Debounce Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " DEBOUNCEEN_27 ,Input Debounce Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " DEBOUNCEEN_26 ,Input Debounce Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " DEBOUNCEEN_25 ,Input Debounce Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " DEBOUNCEEN_24 ,Input Debounce Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DEBOUNCEEN_23 ,Input Debounce Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " DEBOUNCEEN_22 ,Input Debounce Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " DEBOUNCEEN_21 ,Input Debounce Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " DEBOUNCEEN_20 ,Input Debounce Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DEBOUNCEEN_19 ,Input Debounce Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DEBOUNCEEN_18 ,Input Debounce Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DEBOUNCEEN_17 ,Input Debounce Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DEBOUNCEEN_16 ,Input Debounce Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DEBOUNCEEN_15 ,Input Debounce Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DEBOUNCEEN_14 ,Input Debounce Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DEBOUNCEEN_13 ,Input Debounce Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DEBOUNCEEN_12 ,Input Debounce Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DEBOUNCEEN_11 ,Input Debounce Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DEBOUNCEEN_10 ,Input Debounce Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DEBOUNCEEN_9 ,Input Debounce Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DEBOUNCEEN_8 ,Input Debounce Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DEBOUNCEEN_7 ,Input Debounce Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DEBOUNCEEN_6 ,Input Debounce Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DEBOUNCEEN_5 ,Input Debounce Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DEBOUNCEEN_4 ,Input Debounce Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DEBOUNCEEN_3 ,Input Debounce Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DEBOUNCEEN_2 ,Input Debounce Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DEBOUNCEEN_1 ,Input Debounce Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DEBOUNCEEN_0 ,Input Debounce Enable 0" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "GPIO_DEBOUNCINGTIME,Register controls debouncing time" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME , Input Debouncing Value" group.long 0x190++0x03 line.long 0x00 "GPIO_CLRDATAOUT,Register clears to 0 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Clear Data Output Register 31" "No effect,Clear" bitfld.long 0x00 30. " INTLINE_30 ,Clear Data Output Register 30" "No effect,Clear" bitfld.long 0x00 29. " INTLINE_29 ,Clear Data Output Register 29" "No effect,Clear" bitfld.long 0x00 28. " INTLINE_28 ,Clear Data Output Register 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Clear Data Output Register 27" "No effect,Clear" bitfld.long 0x00 26. " INTLINE_26 ,Clear Data Output Register 26" "No effect,Clear" bitfld.long 0x00 25. " INTLINE_25 ,Clear Data Output Register 25" "No effect,Clear" bitfld.long 0x00 24. " INTLINE_24 ,Clear Data Output Register 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Clear Data Output Register 23" "No effect,Clear" bitfld.long 0x00 22. " INTLINE_22 ,Clear Data Output Register 22" "No effect,Clear" bitfld.long 0x00 21. " INTLINE_21 ,Clear Data Output Register 21" "No effect,Clear" bitfld.long 0x00 20. " INTLINE_20 ,Clear Data Output Register 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Clear Data Output Register 19" "No effect,Clear" bitfld.long 0x00 18. " INTLINE_18 ,Clear Data Output Register 18" "No effect,Clear" bitfld.long 0x00 17. " INTLINE_17 ,Clear Data Output Register 17" "No effect,Clear" bitfld.long 0x00 16. " INTLINE_16 ,Clear Data Output Register 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Clear Data Output Register 15" "No effect,Clear" bitfld.long 0x00 14. " INTLINE_14 ,Clear Data Output Register 14" "No effect,Clear" bitfld.long 0x00 13. " INTLINE_13 ,Clear Data Output Register 13" "No effect,Clear" bitfld.long 0x00 12. " INTLINE_12 ,Clear Data Output Register 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Clear Data Output Register 11" "No effect,Clear" bitfld.long 0x00 10. " INTLINE_10 ,Clear Data Output Register 10" "No effect,Clear" bitfld.long 0x00 9. " INTLINE_9 ,Clear Data Output Register 9" "No effect,Clear" bitfld.long 0x00 8. " INTLINE_8 ,Clear Data Output Register 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Clear Data Output Register 7" "No effect,Clear" bitfld.long 0x00 6. " INTLINE_6 ,Clear Data Output Register 6" "No effect,Clear" bitfld.long 0x00 5. " INTLINE_5 ,Clear Data Output Register 5" "No effect,Clear" bitfld.long 0x00 4. " INTLINE_4 ,Clear Data Output Register 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Clear Data Output Register 3" "No effect,Clear" bitfld.long 0x00 2. " INTLINE_2 ,Clear Data Output Register 2" "No effect,Clear" bitfld.long 0x00 1. " INTLINE_1 ,Clear Data Output Register 1" "No effect,Clear" bitfld.long 0x00 0. " INTLINE_0 ,Clear Data Output Register 0" "No effect,Clear" group.long 0x194++0x03 line.long 0x00 "GPIO_SETDATAOUT,Register sets to 1 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Set Data Output Register 31" "No effect,Set" bitfld.long 0x00 30. " INTLINE_30 ,Set Data Output Register 30" "No effect,Set" bitfld.long 0x00 29. " INTLINE_29 ,Set Data Output Register 29" "No effect,Set" bitfld.long 0x00 28. " INTLINE_28 ,Set Data Output Register 28" "No effect,Set" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Set Data Output Register 27" "No effect,Set" bitfld.long 0x00 26. " INTLINE_26 ,Set Data Output Register 26" "No effect,Set" bitfld.long 0x00 25. " INTLINE_25 ,Set Data Output Register 25" "No effect,Set" bitfld.long 0x00 24. " INTLINE_24 ,Set Data Output Register 24" "No effect,Set" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Set Data Output Register 23" "No effect,Set" bitfld.long 0x00 22. " INTLINE_22 ,Set Data Output Register 22" "No effect,Set" bitfld.long 0x00 21. " INTLINE_21 ,Set Data Output Register 21" "No effect,Set" bitfld.long 0x00 20. " INTLINE_20 ,Set Data Output Register 20" "No effect,Set" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Set Data Output Register 19" "No effect,Set" bitfld.long 0x00 18. " INTLINE_18 ,Set Data Output Register 18" "No effect,Set" bitfld.long 0x00 17. " INTLINE_17 ,Set Data Output Register 17" "No effect,Set" bitfld.long 0x00 16. " INTLINE_16 ,Set Data Output Register 16" "No effect,Set" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Set Data Output Register 15" "No effect,Set" bitfld.long 0x00 14. " INTLINE_14 ,Set Data Output Register 14" "No effect,Set" bitfld.long 0x00 13. " INTLINE_13 ,Set Data Output Register 13" "No effect,Set" bitfld.long 0x00 12. " INTLINE_12 ,Set Data Output Register 12" "No effect,Set" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Set Data Output Register 11" "No effect,Set" bitfld.long 0x00 10. " INTLINE_10 ,Set Data Output Register 10" "No effect,Set" bitfld.long 0x00 9. " INTLINE_9 ,Set Data Output Register 9" "No effect,Set" bitfld.long 0x00 8. " INTLINE_8 ,Set Data Output Register 8" "No effect,Set" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Set Data Output Register 7" "No effect,Set" bitfld.long 0x00 6. " INTLINE_6 ,Set Data Output Register 6" "No effect,Set" bitfld.long 0x00 5. " INTLINE_5 ,Set Data Output Register 5" "No effect,Set" bitfld.long 0x00 4. " INTLINE_4 ,Set Data Output Register 4" "No effect,Set" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Set Data Output Register 3" "No effect,Set" bitfld.long 0x00 2. " INTLINE_2 ,Set Data Output Register 2" "No effect,Set" bitfld.long 0x00 1. " INTLINE_1 ,Set Data Output Register 1" "No effect,Set" bitfld.long 0x00 0. " INTLINE_0 ,Set Data Output Register 0" "No effect,Set" width 11. tree.end tree "GPIO 1" base ad:0x4804C000 width 16. rgroup.long 0x000++0x03 line.long 0x00 "GPIO_REVISION,Revision number of the GPIO module" bitfld.long 0x00 30.--31. " SCHEME , Used to distinguish between old Scheme and current. [[br]]" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC , Indicates a software compatible module family" bitfld.long 0x00 11.--15. " RTL , RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR , Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision" group.long 0x010++0x03 line.long 0x00 "GPIO_SYSCONFIG,Controls the various parameters of the L4 interconnect" bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management Req/Ack control" "Force-idle,No-idle,Smart-idle," bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software Reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Clock gating" textline " " group.long 0x020++0x03 line.long 0x00 "GPIO_EOI,This module supports DMA events with its interrupt signal" bitfld.long 0x00 0. " DMAEVT_ACK ,Write 0 to acknowledge DMA event has been completed" "Not completed,Completed" width 19. group.long 0x024++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_0,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x028++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_1,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x02C++0x03 line.long 0x00 "GPIO_IRQSTS_0,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x030++0x03 line.long 0x00 "GPIO_IRQSTS_1,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x034++0x03 line.long 0x00 "GPIO_IRQSTS_SET_0,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x038++0x03 line.long 0x00 "GPIO_IRQSTS_SET_1,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x03C++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_0,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x040++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_1,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x044++0x03 line.long 0x00 "GPIO_IRQWAKEN_0,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" group.long 0x048++0x03 line.long 0x00 "GPIO_IRQWAKEN_1,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" textline " " width 13. rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTS,The GPIO_SYSSTS register provides the reset status information about the GPIO module" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x03 line.long 0x00 "GPIO_CTRL,The GPIO_CTRL register controls the clock gating functionality" bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating Ratio" "Normal,/2,/4,/8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" group.long 0x134++0x03 line.long 0x00 "GPIO_OE,The GPIO_OE register is used to enable the pins output capabilities" bitfld.long 0x00 31. " OUTPUTEN_31 ,Output Data Enable 31" "Output,Input" bitfld.long 0x00 30. " OUTPUTEN_30 ,Output Data Enable 30" "Output,Input" bitfld.long 0x00 29. " OUTPUTEN_29 ,Output Data Enable 29" "Output,Input" bitfld.long 0x00 28. " OUTPUTEN_28 ,Output Data Enable 28" "Output,Input" textline " " bitfld.long 0x00 27. " OUTPUTEN_27 ,Output Data Enable 27" "Output,Input" bitfld.long 0x00 26. " OUTPUTEN_26 ,Output Data Enable 26" "Output,Input" bitfld.long 0x00 25. " OUTPUTEN_25 ,Output Data Enable 25" "Output,Input" bitfld.long 0x00 24. " OUTPUTEN_24 ,Output Data Enable 24" "Output,Input" textline " " bitfld.long 0x00 23. " OUTPUTEN_23 ,Output Data Enable 23" "Output,Input" bitfld.long 0x00 22. " OUTPUTEN_22 ,Output Data Enable 22" "Output,Input" bitfld.long 0x00 21. " OUTPUTEN_21 ,Output Data Enable 21" "Output,Input" bitfld.long 0x00 20. " OUTPUTEN_20 ,Output Data Enable 20" "Output,Input" textline " " bitfld.long 0x00 19. " OUTPUTEN_19 ,Output Data Enable 19" "Output,Input" bitfld.long 0x00 18. " OUTPUTEN_18 ,Output Data Enable 18" "Output,Input" bitfld.long 0x00 17. " OUTPUTEN_17 ,Output Data Enable 17" "Output,Input" bitfld.long 0x00 16. " OUTPUTEN_16 ,Output Data Enable 16" "Output,Input" textline " " bitfld.long 0x00 15. " OUTPUTEN_15 ,Output Data Enable 15" "Output,Input" bitfld.long 0x00 14. " OUTPUTEN_14 ,Output Data Enable 14" "Output,Input" bitfld.long 0x00 13. " OUTPUTEN_13 ,Output Data Enable 13" "Output,Input" bitfld.long 0x00 12. " OUTPUTEN_12 ,Output Data Enable 12" "Output,Input" textline " " bitfld.long 0x00 11. " OUTPUTEN_11 ,Output Data Enable 11" "Output,Input" bitfld.long 0x00 10. " OUTPUTEN_10 ,Output Data Enable 10" "Output,Input" bitfld.long 0x00 9. " OUTPUTEN_9 ,Output Data Enable 9" "Output,Input" bitfld.long 0x00 8. " OUTPUTEN_8 ,Output Data Enable 8" "Output,Input" textline " " bitfld.long 0x00 7. " OUTPUTEN_7 ,Output Data Enable 7" "Output,Input" bitfld.long 0x00 6. " OUTPUTEN_6 ,Output Data Enable 6" "Output,Input" bitfld.long 0x00 5. " OUTPUTEN_5 ,Output Data Enable 5" "Output,Input" bitfld.long 0x00 4. " OUTPUTEN_4 ,Output Data Enable 4" "Output,Input" textline " " bitfld.long 0x00 3. " OUTPUTEN_3 ,Output Data Enable 3" "Output,Input" bitfld.long 0x00 2. " OUTPUTEN_2 ,Output Data Enable 2" "Output,Input" bitfld.long 0x00 1. " OUTPUTEN_1 ,Output Data Enable 1" "Output,Input" bitfld.long 0x00 0. " OUTPUTEN_0 ,Output Data Enable 0" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,The GPIO_DATAIN register is used to register the data that is read from the GPIO pins" hexmask.long 0x00 0.--31. 1. " DATAIN , Sampled input data" group.long 0x13C++0x03 line.long 0x00 "GPIO_DATAOUT,The GPIO_DATAOUT register is used for setting the value of the GPIO output pins" hexmask.long 0x00 0.--31. 1. " DATAOUT , Data to set on output pins" textline " " width 21. group.long 0x140++0x03 line.long 0x00 "GPIO_LEVELDETECT0,Register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT0_31 ,Low Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT0_30 ,Low Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT0_29 ,Low Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT0_28 ,Low Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT0_27 ,Low Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT0_26 ,Low Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT0_25 ,Low Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT0_24 ,Low Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT0_23 ,Low Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT0_22 ,Low Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT0_21 ,Low Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT0_20 ,Low Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT0_19 ,Low Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT0_18 ,Low Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT0_17 ,Low Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT0_16 ,Low Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT0_15 ,Low Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT0_14 ,Low Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT0_13 ,Low Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT0_12 ,Low Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT0_11 ,Low Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT0_10 ,Low Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT0_9 ,Low Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT0_8 ,Low Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT0_7 ,Low Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT0_6 ,Low Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT0_5 ,Low Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT0_4 ,Low Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT0_3 ,Low Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT0_2 ,Low Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT0_1 ,Low Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT0_0 ,Low Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "GPIO_LEVELDETECT1,Register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT1_31 ,High Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT1_30 ,High Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT1_29 ,High Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT1_28 ,High Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT1_27 ,High Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT1_26 ,High Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT1_25 ,High Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT1_24 ,High Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT1_23 ,High Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT1_22 ,High Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT1_21 ,High Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT1_20 ,High Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT1_19 ,High Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT1_18 ,High Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT1_17 ,High Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT1_16 ,High Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT1_15 ,High Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT1_14 ,High Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT1_13 ,High Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT1_12 ,High Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT1_11 ,High Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT1_10 ,High Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT1_9 ,High Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT1_8 ,High Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT1_7 ,High Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT1_6 ,High Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT1_5 ,High Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT1_4 ,High Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT1_3 ,High Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT1_2 ,High Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT1_1 ,High Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT1_0 ,High Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x148++0x03 line.long 0x00 "GPIO_RISINGDETECT,Register is used to enable/disable for each input lines the rising-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " RISINGDETECT_31 ,Rising Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " RISINGDETECT_30 ,Rising Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " RISINGDETECT_29 ,Rising Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " RISINGDETECT_28 ,Rising Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RISINGDETECT_27 ,Rising Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " RISINGDETECT_26 ,Rising Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " RISINGDETECT_25 ,Rising Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " RISINGDETECT_24 ,Rising Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " RISINGDETECT_23 ,Rising Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " RISINGDETECT_22 ,Rising Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " RISINGDETECT_21 ,Rising Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " RISINGDETECT_20 ,Rising Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RISINGDETECT_19 ,Rising Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " RISINGDETECT_18 ,Rising Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " RISINGDETECT_17 ,Rising Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " RISINGDETECT_16 ,Rising Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RISINGDETECT_15 ,Rising Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " RISINGDETECT_14 ,Rising Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " RISINGDETECT_13 ,Rising Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " RISINGDETECT_12 ,Rising Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " RISINGDETECT_11 ,Rising Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " RISINGDETECT_10 ,Rising Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " RISINGDETECT_9 ,Rising Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " RISINGDETECT_8 ,Rising Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " RISINGDETECT_7 ,Rising Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " RISINGDETECT_6 ,Rising Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " RISINGDETECT_5 ,Rising Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " RISINGDETECT_4 ,Rising Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RISINGDETECT_3 ,Rising Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " RISINGDETECT_2 ,Rising Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " RISINGDETECT_1 ,Rising Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " RISINGDETECT_0 ,Rising Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "GPIO_FALLINGDETECT,Register is used to enable/disable for each input lines the falling-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " FALLINGDETECT_31 ,Falling Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " FALLINGDETECT_30 ,Falling Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " FALLINGDETECT_29 ,Falling Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " FALLINGDETECT_28 ,Falling Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " FALLINGDETECT_27 ,Falling Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " FALLINGDETECT_26 ,Falling Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " FALLINGDETECT_25 ,Falling Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " FALLINGDETECT_24 ,Falling Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FALLINGDETECT_23 ,Falling Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " FALLINGDETECT_22 ,Falling Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " FALLINGDETECT_21 ,Falling Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " FALLINGDETECT_20 ,Falling Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FALLINGDETECT_19 ,Falling Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " FALLINGDETECT_18 ,Falling Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " FALLINGDETECT_17 ,Falling Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " FALLINGDETECT_16 ,Falling Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FALLINGDETECT_15 ,Falling Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " FALLINGDETECT_14 ,Falling Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " FALLINGDETECT_13 ,Falling Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " FALLINGDETECT_12 ,Falling Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " FALLINGDETECT_11 ,Falling Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " FALLINGDETECT_10 ,Falling Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " FALLINGDETECT_9 ,Falling Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " FALLINGDETECT_8 ,Falling Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FALLINGDETECT_7 ,Falling Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " FALLINGDETECT_6 ,Falling Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " FALLINGDETECT_5 ,Falling Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " FALLINGDETECT_4 ,Falling Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FALLINGDETECT_3 ,Falling Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " FALLINGDETECT_2 ,Falling Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " FALLINGDETECT_1 ,Falling Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " FALLINGDETECT_0 ,Falling Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x150++0x03 line.long 0x00 "GPIO_DEBOUNCEN,Register is used to enable/disable the debouncing feature for each input line." bitfld.long 0x00 31. " DEBOUNCEEN_31 ,Input Debounce Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " DEBOUNCEEN_30 ,Input Debounce Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " DEBOUNCEEN_29 ,Input Debounce Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " DEBOUNCEEN_28 ,Input Debounce Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " DEBOUNCEEN_27 ,Input Debounce Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " DEBOUNCEEN_26 ,Input Debounce Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " DEBOUNCEEN_25 ,Input Debounce Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " DEBOUNCEEN_24 ,Input Debounce Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DEBOUNCEEN_23 ,Input Debounce Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " DEBOUNCEEN_22 ,Input Debounce Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " DEBOUNCEEN_21 ,Input Debounce Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " DEBOUNCEEN_20 ,Input Debounce Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DEBOUNCEEN_19 ,Input Debounce Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DEBOUNCEEN_18 ,Input Debounce Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DEBOUNCEEN_17 ,Input Debounce Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DEBOUNCEEN_16 ,Input Debounce Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DEBOUNCEEN_15 ,Input Debounce Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DEBOUNCEEN_14 ,Input Debounce Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DEBOUNCEEN_13 ,Input Debounce Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DEBOUNCEEN_12 ,Input Debounce Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DEBOUNCEEN_11 ,Input Debounce Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DEBOUNCEEN_10 ,Input Debounce Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DEBOUNCEEN_9 ,Input Debounce Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DEBOUNCEEN_8 ,Input Debounce Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DEBOUNCEEN_7 ,Input Debounce Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DEBOUNCEEN_6 ,Input Debounce Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DEBOUNCEEN_5 ,Input Debounce Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DEBOUNCEEN_4 ,Input Debounce Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DEBOUNCEEN_3 ,Input Debounce Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DEBOUNCEEN_2 ,Input Debounce Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DEBOUNCEEN_1 ,Input Debounce Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DEBOUNCEEN_0 ,Input Debounce Enable 0" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "GPIO_DEBOUNCINGTIME,Register controls debouncing time" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME , Input Debouncing Value" group.long 0x190++0x03 line.long 0x00 "GPIO_CLRDATAOUT,Register clears to 0 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Clear Data Output Register 31" "No effect,Clear" bitfld.long 0x00 30. " INTLINE_30 ,Clear Data Output Register 30" "No effect,Clear" bitfld.long 0x00 29. " INTLINE_29 ,Clear Data Output Register 29" "No effect,Clear" bitfld.long 0x00 28. " INTLINE_28 ,Clear Data Output Register 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Clear Data Output Register 27" "No effect,Clear" bitfld.long 0x00 26. " INTLINE_26 ,Clear Data Output Register 26" "No effect,Clear" bitfld.long 0x00 25. " INTLINE_25 ,Clear Data Output Register 25" "No effect,Clear" bitfld.long 0x00 24. " INTLINE_24 ,Clear Data Output Register 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Clear Data Output Register 23" "No effect,Clear" bitfld.long 0x00 22. " INTLINE_22 ,Clear Data Output Register 22" "No effect,Clear" bitfld.long 0x00 21. " INTLINE_21 ,Clear Data Output Register 21" "No effect,Clear" bitfld.long 0x00 20. " INTLINE_20 ,Clear Data Output Register 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Clear Data Output Register 19" "No effect,Clear" bitfld.long 0x00 18. " INTLINE_18 ,Clear Data Output Register 18" "No effect,Clear" bitfld.long 0x00 17. " INTLINE_17 ,Clear Data Output Register 17" "No effect,Clear" bitfld.long 0x00 16. " INTLINE_16 ,Clear Data Output Register 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Clear Data Output Register 15" "No effect,Clear" bitfld.long 0x00 14. " INTLINE_14 ,Clear Data Output Register 14" "No effect,Clear" bitfld.long 0x00 13. " INTLINE_13 ,Clear Data Output Register 13" "No effect,Clear" bitfld.long 0x00 12. " INTLINE_12 ,Clear Data Output Register 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Clear Data Output Register 11" "No effect,Clear" bitfld.long 0x00 10. " INTLINE_10 ,Clear Data Output Register 10" "No effect,Clear" bitfld.long 0x00 9. " INTLINE_9 ,Clear Data Output Register 9" "No effect,Clear" bitfld.long 0x00 8. " INTLINE_8 ,Clear Data Output Register 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Clear Data Output Register 7" "No effect,Clear" bitfld.long 0x00 6. " INTLINE_6 ,Clear Data Output Register 6" "No effect,Clear" bitfld.long 0x00 5. " INTLINE_5 ,Clear Data Output Register 5" "No effect,Clear" bitfld.long 0x00 4. " INTLINE_4 ,Clear Data Output Register 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Clear Data Output Register 3" "No effect,Clear" bitfld.long 0x00 2. " INTLINE_2 ,Clear Data Output Register 2" "No effect,Clear" bitfld.long 0x00 1. " INTLINE_1 ,Clear Data Output Register 1" "No effect,Clear" bitfld.long 0x00 0. " INTLINE_0 ,Clear Data Output Register 0" "No effect,Clear" group.long 0x194++0x03 line.long 0x00 "GPIO_SETDATAOUT,Register sets to 1 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Set Data Output Register 31" "No effect,Set" bitfld.long 0x00 30. " INTLINE_30 ,Set Data Output Register 30" "No effect,Set" bitfld.long 0x00 29. " INTLINE_29 ,Set Data Output Register 29" "No effect,Set" bitfld.long 0x00 28. " INTLINE_28 ,Set Data Output Register 28" "No effect,Set" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Set Data Output Register 27" "No effect,Set" bitfld.long 0x00 26. " INTLINE_26 ,Set Data Output Register 26" "No effect,Set" bitfld.long 0x00 25. " INTLINE_25 ,Set Data Output Register 25" "No effect,Set" bitfld.long 0x00 24. " INTLINE_24 ,Set Data Output Register 24" "No effect,Set" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Set Data Output Register 23" "No effect,Set" bitfld.long 0x00 22. " INTLINE_22 ,Set Data Output Register 22" "No effect,Set" bitfld.long 0x00 21. " INTLINE_21 ,Set Data Output Register 21" "No effect,Set" bitfld.long 0x00 20. " INTLINE_20 ,Set Data Output Register 20" "No effect,Set" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Set Data Output Register 19" "No effect,Set" bitfld.long 0x00 18. " INTLINE_18 ,Set Data Output Register 18" "No effect,Set" bitfld.long 0x00 17. " INTLINE_17 ,Set Data Output Register 17" "No effect,Set" bitfld.long 0x00 16. " INTLINE_16 ,Set Data Output Register 16" "No effect,Set" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Set Data Output Register 15" "No effect,Set" bitfld.long 0x00 14. " INTLINE_14 ,Set Data Output Register 14" "No effect,Set" bitfld.long 0x00 13. " INTLINE_13 ,Set Data Output Register 13" "No effect,Set" bitfld.long 0x00 12. " INTLINE_12 ,Set Data Output Register 12" "No effect,Set" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Set Data Output Register 11" "No effect,Set" bitfld.long 0x00 10. " INTLINE_10 ,Set Data Output Register 10" "No effect,Set" bitfld.long 0x00 9. " INTLINE_9 ,Set Data Output Register 9" "No effect,Set" bitfld.long 0x00 8. " INTLINE_8 ,Set Data Output Register 8" "No effect,Set" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Set Data Output Register 7" "No effect,Set" bitfld.long 0x00 6. " INTLINE_6 ,Set Data Output Register 6" "No effect,Set" bitfld.long 0x00 5. " INTLINE_5 ,Set Data Output Register 5" "No effect,Set" bitfld.long 0x00 4. " INTLINE_4 ,Set Data Output Register 4" "No effect,Set" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Set Data Output Register 3" "No effect,Set" bitfld.long 0x00 2. " INTLINE_2 ,Set Data Output Register 2" "No effect,Set" bitfld.long 0x00 1. " INTLINE_1 ,Set Data Output Register 1" "No effect,Set" bitfld.long 0x00 0. " INTLINE_0 ,Set Data Output Register 0" "No effect,Set" width 11. tree.end tree "GPIO 2" base ad:0x481AC000 width 16. rgroup.long 0x000++0x03 line.long 0x00 "GPIO_REVISION,Revision number of the GPIO module" bitfld.long 0x00 30.--31. " SCHEME , Used to distinguish between old Scheme and current. [[br]]" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC , Indicates a software compatible module family" bitfld.long 0x00 11.--15. " RTL , RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR , Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision" group.long 0x010++0x03 line.long 0x00 "GPIO_SYSCONFIG,Controls the various parameters of the L4 interconnect" bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management Req/Ack control" "Force-idle,No-idle,Smart-idle," bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software Reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Clock gating" textline " " group.long 0x020++0x03 line.long 0x00 "GPIO_EOI,This module supports DMA events with its interrupt signal" bitfld.long 0x00 0. " DMAEVT_ACK ,Write 0 to acknowledge DMA event has been completed" "Not completed,Completed" width 19. group.long 0x024++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_0,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x028++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_1,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x02C++0x03 line.long 0x00 "GPIO_IRQSTS_0,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x030++0x03 line.long 0x00 "GPIO_IRQSTS_1,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x034++0x03 line.long 0x00 "GPIO_IRQSTS_SET_0,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x038++0x03 line.long 0x00 "GPIO_IRQSTS_SET_1,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x03C++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_0,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x040++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_1,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x044++0x03 line.long 0x00 "GPIO_IRQWAKEN_0,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" group.long 0x048++0x03 line.long 0x00 "GPIO_IRQWAKEN_1,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" textline " " width 13. rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTS,The GPIO_SYSSTS register provides the reset status information about the GPIO module" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x03 line.long 0x00 "GPIO_CTRL,The GPIO_CTRL register controls the clock gating functionality" bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating Ratio" "Normal,/2,/4,/8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" group.long 0x134++0x03 line.long 0x00 "GPIO_OE,The GPIO_OE register is used to enable the pins output capabilities" bitfld.long 0x00 31. " OUTPUTEN_31 ,Output Data Enable 31" "Output,Input" bitfld.long 0x00 30. " OUTPUTEN_30 ,Output Data Enable 30" "Output,Input" bitfld.long 0x00 29. " OUTPUTEN_29 ,Output Data Enable 29" "Output,Input" bitfld.long 0x00 28. " OUTPUTEN_28 ,Output Data Enable 28" "Output,Input" textline " " bitfld.long 0x00 27. " OUTPUTEN_27 ,Output Data Enable 27" "Output,Input" bitfld.long 0x00 26. " OUTPUTEN_26 ,Output Data Enable 26" "Output,Input" bitfld.long 0x00 25. " OUTPUTEN_25 ,Output Data Enable 25" "Output,Input" bitfld.long 0x00 24. " OUTPUTEN_24 ,Output Data Enable 24" "Output,Input" textline " " bitfld.long 0x00 23. " OUTPUTEN_23 ,Output Data Enable 23" "Output,Input" bitfld.long 0x00 22. " OUTPUTEN_22 ,Output Data Enable 22" "Output,Input" bitfld.long 0x00 21. " OUTPUTEN_21 ,Output Data Enable 21" "Output,Input" bitfld.long 0x00 20. " OUTPUTEN_20 ,Output Data Enable 20" "Output,Input" textline " " bitfld.long 0x00 19. " OUTPUTEN_19 ,Output Data Enable 19" "Output,Input" bitfld.long 0x00 18. " OUTPUTEN_18 ,Output Data Enable 18" "Output,Input" bitfld.long 0x00 17. " OUTPUTEN_17 ,Output Data Enable 17" "Output,Input" bitfld.long 0x00 16. " OUTPUTEN_16 ,Output Data Enable 16" "Output,Input" textline " " bitfld.long 0x00 15. " OUTPUTEN_15 ,Output Data Enable 15" "Output,Input" bitfld.long 0x00 14. " OUTPUTEN_14 ,Output Data Enable 14" "Output,Input" bitfld.long 0x00 13. " OUTPUTEN_13 ,Output Data Enable 13" "Output,Input" bitfld.long 0x00 12. " OUTPUTEN_12 ,Output Data Enable 12" "Output,Input" textline " " bitfld.long 0x00 11. " OUTPUTEN_11 ,Output Data Enable 11" "Output,Input" bitfld.long 0x00 10. " OUTPUTEN_10 ,Output Data Enable 10" "Output,Input" bitfld.long 0x00 9. " OUTPUTEN_9 ,Output Data Enable 9" "Output,Input" bitfld.long 0x00 8. " OUTPUTEN_8 ,Output Data Enable 8" "Output,Input" textline " " bitfld.long 0x00 7. " OUTPUTEN_7 ,Output Data Enable 7" "Output,Input" bitfld.long 0x00 6. " OUTPUTEN_6 ,Output Data Enable 6" "Output,Input" bitfld.long 0x00 5. " OUTPUTEN_5 ,Output Data Enable 5" "Output,Input" bitfld.long 0x00 4. " OUTPUTEN_4 ,Output Data Enable 4" "Output,Input" textline " " bitfld.long 0x00 3. " OUTPUTEN_3 ,Output Data Enable 3" "Output,Input" bitfld.long 0x00 2. " OUTPUTEN_2 ,Output Data Enable 2" "Output,Input" bitfld.long 0x00 1. " OUTPUTEN_1 ,Output Data Enable 1" "Output,Input" bitfld.long 0x00 0. " OUTPUTEN_0 ,Output Data Enable 0" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,The GPIO_DATAIN register is used to register the data that is read from the GPIO pins" hexmask.long 0x00 0.--31. 1. " DATAIN , Sampled input data" group.long 0x13C++0x03 line.long 0x00 "GPIO_DATAOUT,The GPIO_DATAOUT register is used for setting the value of the GPIO output pins" hexmask.long 0x00 0.--31. 1. " DATAOUT , Data to set on output pins" textline " " width 21. group.long 0x140++0x03 line.long 0x00 "GPIO_LEVELDETECT0,Register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT0_31 ,Low Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT0_30 ,Low Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT0_29 ,Low Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT0_28 ,Low Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT0_27 ,Low Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT0_26 ,Low Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT0_25 ,Low Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT0_24 ,Low Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT0_23 ,Low Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT0_22 ,Low Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT0_21 ,Low Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT0_20 ,Low Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT0_19 ,Low Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT0_18 ,Low Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT0_17 ,Low Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT0_16 ,Low Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT0_15 ,Low Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT0_14 ,Low Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT0_13 ,Low Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT0_12 ,Low Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT0_11 ,Low Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT0_10 ,Low Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT0_9 ,Low Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT0_8 ,Low Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT0_7 ,Low Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT0_6 ,Low Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT0_5 ,Low Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT0_4 ,Low Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT0_3 ,Low Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT0_2 ,Low Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT0_1 ,Low Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT0_0 ,Low Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "GPIO_LEVELDETECT1,Register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT1_31 ,High Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT1_30 ,High Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT1_29 ,High Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT1_28 ,High Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT1_27 ,High Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT1_26 ,High Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT1_25 ,High Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT1_24 ,High Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT1_23 ,High Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT1_22 ,High Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT1_21 ,High Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT1_20 ,High Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT1_19 ,High Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT1_18 ,High Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT1_17 ,High Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT1_16 ,High Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT1_15 ,High Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT1_14 ,High Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT1_13 ,High Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT1_12 ,High Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT1_11 ,High Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT1_10 ,High Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT1_9 ,High Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT1_8 ,High Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT1_7 ,High Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT1_6 ,High Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT1_5 ,High Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT1_4 ,High Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT1_3 ,High Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT1_2 ,High Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT1_1 ,High Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT1_0 ,High Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x148++0x03 line.long 0x00 "GPIO_RISINGDETECT,Register is used to enable/disable for each input lines the rising-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " RISINGDETECT_31 ,Rising Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " RISINGDETECT_30 ,Rising Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " RISINGDETECT_29 ,Rising Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " RISINGDETECT_28 ,Rising Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RISINGDETECT_27 ,Rising Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " RISINGDETECT_26 ,Rising Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " RISINGDETECT_25 ,Rising Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " RISINGDETECT_24 ,Rising Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " RISINGDETECT_23 ,Rising Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " RISINGDETECT_22 ,Rising Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " RISINGDETECT_21 ,Rising Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " RISINGDETECT_20 ,Rising Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RISINGDETECT_19 ,Rising Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " RISINGDETECT_18 ,Rising Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " RISINGDETECT_17 ,Rising Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " RISINGDETECT_16 ,Rising Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RISINGDETECT_15 ,Rising Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " RISINGDETECT_14 ,Rising Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " RISINGDETECT_13 ,Rising Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " RISINGDETECT_12 ,Rising Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " RISINGDETECT_11 ,Rising Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " RISINGDETECT_10 ,Rising Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " RISINGDETECT_9 ,Rising Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " RISINGDETECT_8 ,Rising Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " RISINGDETECT_7 ,Rising Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " RISINGDETECT_6 ,Rising Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " RISINGDETECT_5 ,Rising Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " RISINGDETECT_4 ,Rising Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RISINGDETECT_3 ,Rising Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " RISINGDETECT_2 ,Rising Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " RISINGDETECT_1 ,Rising Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " RISINGDETECT_0 ,Rising Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "GPIO_FALLINGDETECT,Register is used to enable/disable for each input lines the falling-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " FALLINGDETECT_31 ,Falling Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " FALLINGDETECT_30 ,Falling Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " FALLINGDETECT_29 ,Falling Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " FALLINGDETECT_28 ,Falling Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " FALLINGDETECT_27 ,Falling Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " FALLINGDETECT_26 ,Falling Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " FALLINGDETECT_25 ,Falling Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " FALLINGDETECT_24 ,Falling Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FALLINGDETECT_23 ,Falling Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " FALLINGDETECT_22 ,Falling Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " FALLINGDETECT_21 ,Falling Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " FALLINGDETECT_20 ,Falling Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FALLINGDETECT_19 ,Falling Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " FALLINGDETECT_18 ,Falling Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " FALLINGDETECT_17 ,Falling Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " FALLINGDETECT_16 ,Falling Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FALLINGDETECT_15 ,Falling Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " FALLINGDETECT_14 ,Falling Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " FALLINGDETECT_13 ,Falling Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " FALLINGDETECT_12 ,Falling Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " FALLINGDETECT_11 ,Falling Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " FALLINGDETECT_10 ,Falling Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " FALLINGDETECT_9 ,Falling Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " FALLINGDETECT_8 ,Falling Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FALLINGDETECT_7 ,Falling Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " FALLINGDETECT_6 ,Falling Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " FALLINGDETECT_5 ,Falling Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " FALLINGDETECT_4 ,Falling Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FALLINGDETECT_3 ,Falling Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " FALLINGDETECT_2 ,Falling Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " FALLINGDETECT_1 ,Falling Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " FALLINGDETECT_0 ,Falling Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x150++0x03 line.long 0x00 "GPIO_DEBOUNCEN,Register is used to enable/disable the debouncing feature for each input line." bitfld.long 0x00 31. " DEBOUNCEEN_31 ,Input Debounce Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " DEBOUNCEEN_30 ,Input Debounce Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " DEBOUNCEEN_29 ,Input Debounce Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " DEBOUNCEEN_28 ,Input Debounce Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " DEBOUNCEEN_27 ,Input Debounce Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " DEBOUNCEEN_26 ,Input Debounce Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " DEBOUNCEEN_25 ,Input Debounce Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " DEBOUNCEEN_24 ,Input Debounce Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DEBOUNCEEN_23 ,Input Debounce Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " DEBOUNCEEN_22 ,Input Debounce Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " DEBOUNCEEN_21 ,Input Debounce Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " DEBOUNCEEN_20 ,Input Debounce Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DEBOUNCEEN_19 ,Input Debounce Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DEBOUNCEEN_18 ,Input Debounce Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DEBOUNCEEN_17 ,Input Debounce Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DEBOUNCEEN_16 ,Input Debounce Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DEBOUNCEEN_15 ,Input Debounce Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DEBOUNCEEN_14 ,Input Debounce Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DEBOUNCEEN_13 ,Input Debounce Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DEBOUNCEEN_12 ,Input Debounce Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DEBOUNCEEN_11 ,Input Debounce Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DEBOUNCEEN_10 ,Input Debounce Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DEBOUNCEEN_9 ,Input Debounce Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DEBOUNCEEN_8 ,Input Debounce Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DEBOUNCEEN_7 ,Input Debounce Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DEBOUNCEEN_6 ,Input Debounce Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DEBOUNCEEN_5 ,Input Debounce Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DEBOUNCEEN_4 ,Input Debounce Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DEBOUNCEEN_3 ,Input Debounce Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DEBOUNCEEN_2 ,Input Debounce Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DEBOUNCEEN_1 ,Input Debounce Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DEBOUNCEEN_0 ,Input Debounce Enable 0" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "GPIO_DEBOUNCINGTIME,Register controls debouncing time" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME , Input Debouncing Value" group.long 0x190++0x03 line.long 0x00 "GPIO_CLRDATAOUT,Register clears to 0 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Clear Data Output Register 31" "No effect,Clear" bitfld.long 0x00 30. " INTLINE_30 ,Clear Data Output Register 30" "No effect,Clear" bitfld.long 0x00 29. " INTLINE_29 ,Clear Data Output Register 29" "No effect,Clear" bitfld.long 0x00 28. " INTLINE_28 ,Clear Data Output Register 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Clear Data Output Register 27" "No effect,Clear" bitfld.long 0x00 26. " INTLINE_26 ,Clear Data Output Register 26" "No effect,Clear" bitfld.long 0x00 25. " INTLINE_25 ,Clear Data Output Register 25" "No effect,Clear" bitfld.long 0x00 24. " INTLINE_24 ,Clear Data Output Register 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Clear Data Output Register 23" "No effect,Clear" bitfld.long 0x00 22. " INTLINE_22 ,Clear Data Output Register 22" "No effect,Clear" bitfld.long 0x00 21. " INTLINE_21 ,Clear Data Output Register 21" "No effect,Clear" bitfld.long 0x00 20. " INTLINE_20 ,Clear Data Output Register 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Clear Data Output Register 19" "No effect,Clear" bitfld.long 0x00 18. " INTLINE_18 ,Clear Data Output Register 18" "No effect,Clear" bitfld.long 0x00 17. " INTLINE_17 ,Clear Data Output Register 17" "No effect,Clear" bitfld.long 0x00 16. " INTLINE_16 ,Clear Data Output Register 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Clear Data Output Register 15" "No effect,Clear" bitfld.long 0x00 14. " INTLINE_14 ,Clear Data Output Register 14" "No effect,Clear" bitfld.long 0x00 13. " INTLINE_13 ,Clear Data Output Register 13" "No effect,Clear" bitfld.long 0x00 12. " INTLINE_12 ,Clear Data Output Register 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Clear Data Output Register 11" "No effect,Clear" bitfld.long 0x00 10. " INTLINE_10 ,Clear Data Output Register 10" "No effect,Clear" bitfld.long 0x00 9. " INTLINE_9 ,Clear Data Output Register 9" "No effect,Clear" bitfld.long 0x00 8. " INTLINE_8 ,Clear Data Output Register 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Clear Data Output Register 7" "No effect,Clear" bitfld.long 0x00 6. " INTLINE_6 ,Clear Data Output Register 6" "No effect,Clear" bitfld.long 0x00 5. " INTLINE_5 ,Clear Data Output Register 5" "No effect,Clear" bitfld.long 0x00 4. " INTLINE_4 ,Clear Data Output Register 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Clear Data Output Register 3" "No effect,Clear" bitfld.long 0x00 2. " INTLINE_2 ,Clear Data Output Register 2" "No effect,Clear" bitfld.long 0x00 1. " INTLINE_1 ,Clear Data Output Register 1" "No effect,Clear" bitfld.long 0x00 0. " INTLINE_0 ,Clear Data Output Register 0" "No effect,Clear" group.long 0x194++0x03 line.long 0x00 "GPIO_SETDATAOUT,Register sets to 1 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Set Data Output Register 31" "No effect,Set" bitfld.long 0x00 30. " INTLINE_30 ,Set Data Output Register 30" "No effect,Set" bitfld.long 0x00 29. " INTLINE_29 ,Set Data Output Register 29" "No effect,Set" bitfld.long 0x00 28. " INTLINE_28 ,Set Data Output Register 28" "No effect,Set" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Set Data Output Register 27" "No effect,Set" bitfld.long 0x00 26. " INTLINE_26 ,Set Data Output Register 26" "No effect,Set" bitfld.long 0x00 25. " INTLINE_25 ,Set Data Output Register 25" "No effect,Set" bitfld.long 0x00 24. " INTLINE_24 ,Set Data Output Register 24" "No effect,Set" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Set Data Output Register 23" "No effect,Set" bitfld.long 0x00 22. " INTLINE_22 ,Set Data Output Register 22" "No effect,Set" bitfld.long 0x00 21. " INTLINE_21 ,Set Data Output Register 21" "No effect,Set" bitfld.long 0x00 20. " INTLINE_20 ,Set Data Output Register 20" "No effect,Set" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Set Data Output Register 19" "No effect,Set" bitfld.long 0x00 18. " INTLINE_18 ,Set Data Output Register 18" "No effect,Set" bitfld.long 0x00 17. " INTLINE_17 ,Set Data Output Register 17" "No effect,Set" bitfld.long 0x00 16. " INTLINE_16 ,Set Data Output Register 16" "No effect,Set" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Set Data Output Register 15" "No effect,Set" bitfld.long 0x00 14. " INTLINE_14 ,Set Data Output Register 14" "No effect,Set" bitfld.long 0x00 13. " INTLINE_13 ,Set Data Output Register 13" "No effect,Set" bitfld.long 0x00 12. " INTLINE_12 ,Set Data Output Register 12" "No effect,Set" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Set Data Output Register 11" "No effect,Set" bitfld.long 0x00 10. " INTLINE_10 ,Set Data Output Register 10" "No effect,Set" bitfld.long 0x00 9. " INTLINE_9 ,Set Data Output Register 9" "No effect,Set" bitfld.long 0x00 8. " INTLINE_8 ,Set Data Output Register 8" "No effect,Set" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Set Data Output Register 7" "No effect,Set" bitfld.long 0x00 6. " INTLINE_6 ,Set Data Output Register 6" "No effect,Set" bitfld.long 0x00 5. " INTLINE_5 ,Set Data Output Register 5" "No effect,Set" bitfld.long 0x00 4. " INTLINE_4 ,Set Data Output Register 4" "No effect,Set" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Set Data Output Register 3" "No effect,Set" bitfld.long 0x00 2. " INTLINE_2 ,Set Data Output Register 2" "No effect,Set" bitfld.long 0x00 1. " INTLINE_1 ,Set Data Output Register 1" "No effect,Set" bitfld.long 0x00 0. " INTLINE_0 ,Set Data Output Register 0" "No effect,Set" width 11. tree.end tree "GPIO 3" base ad:0x481AE000 width 16. rgroup.long 0x000++0x03 line.long 0x00 "GPIO_REVISION,Revision number of the GPIO module" bitfld.long 0x00 30.--31. " SCHEME , Used to distinguish between old Scheme and current. [[br]]" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC , Indicates a software compatible module family" bitfld.long 0x00 11.--15. " RTL , RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR , Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision" group.long 0x010++0x03 line.long 0x00 "GPIO_SYSCONFIG,Controls the various parameters of the L4 interconnect" bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management Req/Ack control" "Force-idle,No-idle,Smart-idle," bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software Reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Clock gating" textline " " group.long 0x020++0x03 line.long 0x00 "GPIO_EOI,This module supports DMA events with its interrupt signal" bitfld.long 0x00 0. " DMAEVT_ACK ,Write 0 to acknowledge DMA event has been completed" "Not completed,Completed" width 19. group.long 0x024++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_0,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x028++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_1,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x02C++0x03 line.long 0x00 "GPIO_IRQSTS_0,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x030++0x03 line.long 0x00 "GPIO_IRQSTS_1,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x034++0x03 line.long 0x00 "GPIO_IRQSTS_SET_0,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x038++0x03 line.long 0x00 "GPIO_IRQSTS_SET_1,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x03C++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_0,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x040++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_1,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x044++0x03 line.long 0x00 "GPIO_IRQWAKEN_0,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" group.long 0x048++0x03 line.long 0x00 "GPIO_IRQWAKEN_1,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" textline " " width 13. rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTS,The GPIO_SYSSTS register provides the reset status information about the GPIO module" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x03 line.long 0x00 "GPIO_CTRL,The GPIO_CTRL register controls the clock gating functionality" bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating Ratio" "Normal,/2,/4,/8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" group.long 0x134++0x03 line.long 0x00 "GPIO_OE,The GPIO_OE register is used to enable the pins output capabilities" bitfld.long 0x00 31. " OUTPUTEN_31 ,Output Data Enable 31" "Output,Input" bitfld.long 0x00 30. " OUTPUTEN_30 ,Output Data Enable 30" "Output,Input" bitfld.long 0x00 29. " OUTPUTEN_29 ,Output Data Enable 29" "Output,Input" bitfld.long 0x00 28. " OUTPUTEN_28 ,Output Data Enable 28" "Output,Input" textline " " bitfld.long 0x00 27. " OUTPUTEN_27 ,Output Data Enable 27" "Output,Input" bitfld.long 0x00 26. " OUTPUTEN_26 ,Output Data Enable 26" "Output,Input" bitfld.long 0x00 25. " OUTPUTEN_25 ,Output Data Enable 25" "Output,Input" bitfld.long 0x00 24. " OUTPUTEN_24 ,Output Data Enable 24" "Output,Input" textline " " bitfld.long 0x00 23. " OUTPUTEN_23 ,Output Data Enable 23" "Output,Input" bitfld.long 0x00 22. " OUTPUTEN_22 ,Output Data Enable 22" "Output,Input" bitfld.long 0x00 21. " OUTPUTEN_21 ,Output Data Enable 21" "Output,Input" bitfld.long 0x00 20. " OUTPUTEN_20 ,Output Data Enable 20" "Output,Input" textline " " bitfld.long 0x00 19. " OUTPUTEN_19 ,Output Data Enable 19" "Output,Input" bitfld.long 0x00 18. " OUTPUTEN_18 ,Output Data Enable 18" "Output,Input" bitfld.long 0x00 17. " OUTPUTEN_17 ,Output Data Enable 17" "Output,Input" bitfld.long 0x00 16. " OUTPUTEN_16 ,Output Data Enable 16" "Output,Input" textline " " bitfld.long 0x00 15. " OUTPUTEN_15 ,Output Data Enable 15" "Output,Input" bitfld.long 0x00 14. " OUTPUTEN_14 ,Output Data Enable 14" "Output,Input" bitfld.long 0x00 13. " OUTPUTEN_13 ,Output Data Enable 13" "Output,Input" bitfld.long 0x00 12. " OUTPUTEN_12 ,Output Data Enable 12" "Output,Input" textline " " bitfld.long 0x00 11. " OUTPUTEN_11 ,Output Data Enable 11" "Output,Input" bitfld.long 0x00 10. " OUTPUTEN_10 ,Output Data Enable 10" "Output,Input" bitfld.long 0x00 9. " OUTPUTEN_9 ,Output Data Enable 9" "Output,Input" bitfld.long 0x00 8. " OUTPUTEN_8 ,Output Data Enable 8" "Output,Input" textline " " bitfld.long 0x00 7. " OUTPUTEN_7 ,Output Data Enable 7" "Output,Input" bitfld.long 0x00 6. " OUTPUTEN_6 ,Output Data Enable 6" "Output,Input" bitfld.long 0x00 5. " OUTPUTEN_5 ,Output Data Enable 5" "Output,Input" bitfld.long 0x00 4. " OUTPUTEN_4 ,Output Data Enable 4" "Output,Input" textline " " bitfld.long 0x00 3. " OUTPUTEN_3 ,Output Data Enable 3" "Output,Input" bitfld.long 0x00 2. " OUTPUTEN_2 ,Output Data Enable 2" "Output,Input" bitfld.long 0x00 1. " OUTPUTEN_1 ,Output Data Enable 1" "Output,Input" bitfld.long 0x00 0. " OUTPUTEN_0 ,Output Data Enable 0" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,The GPIO_DATAIN register is used to register the data that is read from the GPIO pins" hexmask.long 0x00 0.--31. 1. " DATAIN , Sampled input data" group.long 0x13C++0x03 line.long 0x00 "GPIO_DATAOUT,The GPIO_DATAOUT register is used for setting the value of the GPIO output pins" hexmask.long 0x00 0.--31. 1. " DATAOUT , Data to set on output pins" textline " " width 21. group.long 0x140++0x03 line.long 0x00 "GPIO_LEVELDETECT0,Register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT0_31 ,Low Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT0_30 ,Low Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT0_29 ,Low Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT0_28 ,Low Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT0_27 ,Low Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT0_26 ,Low Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT0_25 ,Low Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT0_24 ,Low Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT0_23 ,Low Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT0_22 ,Low Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT0_21 ,Low Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT0_20 ,Low Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT0_19 ,Low Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT0_18 ,Low Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT0_17 ,Low Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT0_16 ,Low Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT0_15 ,Low Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT0_14 ,Low Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT0_13 ,Low Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT0_12 ,Low Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT0_11 ,Low Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT0_10 ,Low Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT0_9 ,Low Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT0_8 ,Low Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT0_7 ,Low Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT0_6 ,Low Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT0_5 ,Low Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT0_4 ,Low Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT0_3 ,Low Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT0_2 ,Low Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT0_1 ,Low Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT0_0 ,Low Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "GPIO_LEVELDETECT1,Register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT1_31 ,High Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT1_30 ,High Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT1_29 ,High Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT1_28 ,High Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT1_27 ,High Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT1_26 ,High Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT1_25 ,High Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT1_24 ,High Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT1_23 ,High Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT1_22 ,High Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT1_21 ,High Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT1_20 ,High Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT1_19 ,High Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT1_18 ,High Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT1_17 ,High Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT1_16 ,High Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT1_15 ,High Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT1_14 ,High Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT1_13 ,High Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT1_12 ,High Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT1_11 ,High Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT1_10 ,High Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT1_9 ,High Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT1_8 ,High Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT1_7 ,High Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT1_6 ,High Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT1_5 ,High Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT1_4 ,High Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT1_3 ,High Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT1_2 ,High Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT1_1 ,High Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT1_0 ,High Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x148++0x03 line.long 0x00 "GPIO_RISINGDETECT,Register is used to enable/disable for each input lines the rising-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " RISINGDETECT_31 ,Rising Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " RISINGDETECT_30 ,Rising Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " RISINGDETECT_29 ,Rising Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " RISINGDETECT_28 ,Rising Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RISINGDETECT_27 ,Rising Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " RISINGDETECT_26 ,Rising Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " RISINGDETECT_25 ,Rising Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " RISINGDETECT_24 ,Rising Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " RISINGDETECT_23 ,Rising Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " RISINGDETECT_22 ,Rising Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " RISINGDETECT_21 ,Rising Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " RISINGDETECT_20 ,Rising Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RISINGDETECT_19 ,Rising Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " RISINGDETECT_18 ,Rising Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " RISINGDETECT_17 ,Rising Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " RISINGDETECT_16 ,Rising Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RISINGDETECT_15 ,Rising Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " RISINGDETECT_14 ,Rising Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " RISINGDETECT_13 ,Rising Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " RISINGDETECT_12 ,Rising Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " RISINGDETECT_11 ,Rising Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " RISINGDETECT_10 ,Rising Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " RISINGDETECT_9 ,Rising Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " RISINGDETECT_8 ,Rising Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " RISINGDETECT_7 ,Rising Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " RISINGDETECT_6 ,Rising Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " RISINGDETECT_5 ,Rising Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " RISINGDETECT_4 ,Rising Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RISINGDETECT_3 ,Rising Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " RISINGDETECT_2 ,Rising Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " RISINGDETECT_1 ,Rising Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " RISINGDETECT_0 ,Rising Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "GPIO_FALLINGDETECT,Register is used to enable/disable for each input lines the falling-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " FALLINGDETECT_31 ,Falling Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " FALLINGDETECT_30 ,Falling Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " FALLINGDETECT_29 ,Falling Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " FALLINGDETECT_28 ,Falling Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " FALLINGDETECT_27 ,Falling Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " FALLINGDETECT_26 ,Falling Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " FALLINGDETECT_25 ,Falling Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " FALLINGDETECT_24 ,Falling Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FALLINGDETECT_23 ,Falling Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " FALLINGDETECT_22 ,Falling Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " FALLINGDETECT_21 ,Falling Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " FALLINGDETECT_20 ,Falling Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FALLINGDETECT_19 ,Falling Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " FALLINGDETECT_18 ,Falling Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " FALLINGDETECT_17 ,Falling Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " FALLINGDETECT_16 ,Falling Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FALLINGDETECT_15 ,Falling Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " FALLINGDETECT_14 ,Falling Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " FALLINGDETECT_13 ,Falling Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " FALLINGDETECT_12 ,Falling Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " FALLINGDETECT_11 ,Falling Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " FALLINGDETECT_10 ,Falling Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " FALLINGDETECT_9 ,Falling Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " FALLINGDETECT_8 ,Falling Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FALLINGDETECT_7 ,Falling Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " FALLINGDETECT_6 ,Falling Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " FALLINGDETECT_5 ,Falling Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " FALLINGDETECT_4 ,Falling Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FALLINGDETECT_3 ,Falling Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " FALLINGDETECT_2 ,Falling Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " FALLINGDETECT_1 ,Falling Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " FALLINGDETECT_0 ,Falling Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x150++0x03 line.long 0x00 "GPIO_DEBOUNCEN,Register is used to enable/disable the debouncing feature for each input line." bitfld.long 0x00 31. " DEBOUNCEEN_31 ,Input Debounce Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " DEBOUNCEEN_30 ,Input Debounce Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " DEBOUNCEEN_29 ,Input Debounce Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " DEBOUNCEEN_28 ,Input Debounce Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " DEBOUNCEEN_27 ,Input Debounce Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " DEBOUNCEEN_26 ,Input Debounce Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " DEBOUNCEEN_25 ,Input Debounce Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " DEBOUNCEEN_24 ,Input Debounce Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DEBOUNCEEN_23 ,Input Debounce Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " DEBOUNCEEN_22 ,Input Debounce Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " DEBOUNCEEN_21 ,Input Debounce Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " DEBOUNCEEN_20 ,Input Debounce Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DEBOUNCEEN_19 ,Input Debounce Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DEBOUNCEEN_18 ,Input Debounce Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DEBOUNCEEN_17 ,Input Debounce Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DEBOUNCEEN_16 ,Input Debounce Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DEBOUNCEEN_15 ,Input Debounce Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DEBOUNCEEN_14 ,Input Debounce Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DEBOUNCEEN_13 ,Input Debounce Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DEBOUNCEEN_12 ,Input Debounce Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DEBOUNCEEN_11 ,Input Debounce Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DEBOUNCEEN_10 ,Input Debounce Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DEBOUNCEEN_9 ,Input Debounce Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DEBOUNCEEN_8 ,Input Debounce Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DEBOUNCEEN_7 ,Input Debounce Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DEBOUNCEEN_6 ,Input Debounce Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DEBOUNCEEN_5 ,Input Debounce Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DEBOUNCEEN_4 ,Input Debounce Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DEBOUNCEEN_3 ,Input Debounce Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DEBOUNCEEN_2 ,Input Debounce Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DEBOUNCEEN_1 ,Input Debounce Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DEBOUNCEEN_0 ,Input Debounce Enable 0" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "GPIO_DEBOUNCINGTIME,Register controls debouncing time" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME , Input Debouncing Value" group.long 0x190++0x03 line.long 0x00 "GPIO_CLRDATAOUT,Register clears to 0 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Clear Data Output Register 31" "No effect,Clear" bitfld.long 0x00 30. " INTLINE_30 ,Clear Data Output Register 30" "No effect,Clear" bitfld.long 0x00 29. " INTLINE_29 ,Clear Data Output Register 29" "No effect,Clear" bitfld.long 0x00 28. " INTLINE_28 ,Clear Data Output Register 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Clear Data Output Register 27" "No effect,Clear" bitfld.long 0x00 26. " INTLINE_26 ,Clear Data Output Register 26" "No effect,Clear" bitfld.long 0x00 25. " INTLINE_25 ,Clear Data Output Register 25" "No effect,Clear" bitfld.long 0x00 24. " INTLINE_24 ,Clear Data Output Register 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Clear Data Output Register 23" "No effect,Clear" bitfld.long 0x00 22. " INTLINE_22 ,Clear Data Output Register 22" "No effect,Clear" bitfld.long 0x00 21. " INTLINE_21 ,Clear Data Output Register 21" "No effect,Clear" bitfld.long 0x00 20. " INTLINE_20 ,Clear Data Output Register 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Clear Data Output Register 19" "No effect,Clear" bitfld.long 0x00 18. " INTLINE_18 ,Clear Data Output Register 18" "No effect,Clear" bitfld.long 0x00 17. " INTLINE_17 ,Clear Data Output Register 17" "No effect,Clear" bitfld.long 0x00 16. " INTLINE_16 ,Clear Data Output Register 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Clear Data Output Register 15" "No effect,Clear" bitfld.long 0x00 14. " INTLINE_14 ,Clear Data Output Register 14" "No effect,Clear" bitfld.long 0x00 13. " INTLINE_13 ,Clear Data Output Register 13" "No effect,Clear" bitfld.long 0x00 12. " INTLINE_12 ,Clear Data Output Register 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Clear Data Output Register 11" "No effect,Clear" bitfld.long 0x00 10. " INTLINE_10 ,Clear Data Output Register 10" "No effect,Clear" bitfld.long 0x00 9. " INTLINE_9 ,Clear Data Output Register 9" "No effect,Clear" bitfld.long 0x00 8. " INTLINE_8 ,Clear Data Output Register 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Clear Data Output Register 7" "No effect,Clear" bitfld.long 0x00 6. " INTLINE_6 ,Clear Data Output Register 6" "No effect,Clear" bitfld.long 0x00 5. " INTLINE_5 ,Clear Data Output Register 5" "No effect,Clear" bitfld.long 0x00 4. " INTLINE_4 ,Clear Data Output Register 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Clear Data Output Register 3" "No effect,Clear" bitfld.long 0x00 2. " INTLINE_2 ,Clear Data Output Register 2" "No effect,Clear" bitfld.long 0x00 1. " INTLINE_1 ,Clear Data Output Register 1" "No effect,Clear" bitfld.long 0x00 0. " INTLINE_0 ,Clear Data Output Register 0" "No effect,Clear" group.long 0x194++0x03 line.long 0x00 "GPIO_SETDATAOUT,Register sets to 1 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Set Data Output Register 31" "No effect,Set" bitfld.long 0x00 30. " INTLINE_30 ,Set Data Output Register 30" "No effect,Set" bitfld.long 0x00 29. " INTLINE_29 ,Set Data Output Register 29" "No effect,Set" bitfld.long 0x00 28. " INTLINE_28 ,Set Data Output Register 28" "No effect,Set" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Set Data Output Register 27" "No effect,Set" bitfld.long 0x00 26. " INTLINE_26 ,Set Data Output Register 26" "No effect,Set" bitfld.long 0x00 25. " INTLINE_25 ,Set Data Output Register 25" "No effect,Set" bitfld.long 0x00 24. " INTLINE_24 ,Set Data Output Register 24" "No effect,Set" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Set Data Output Register 23" "No effect,Set" bitfld.long 0x00 22. " INTLINE_22 ,Set Data Output Register 22" "No effect,Set" bitfld.long 0x00 21. " INTLINE_21 ,Set Data Output Register 21" "No effect,Set" bitfld.long 0x00 20. " INTLINE_20 ,Set Data Output Register 20" "No effect,Set" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Set Data Output Register 19" "No effect,Set" bitfld.long 0x00 18. " INTLINE_18 ,Set Data Output Register 18" "No effect,Set" bitfld.long 0x00 17. " INTLINE_17 ,Set Data Output Register 17" "No effect,Set" bitfld.long 0x00 16. " INTLINE_16 ,Set Data Output Register 16" "No effect,Set" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Set Data Output Register 15" "No effect,Set" bitfld.long 0x00 14. " INTLINE_14 ,Set Data Output Register 14" "No effect,Set" bitfld.long 0x00 13. " INTLINE_13 ,Set Data Output Register 13" "No effect,Set" bitfld.long 0x00 12. " INTLINE_12 ,Set Data Output Register 12" "No effect,Set" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Set Data Output Register 11" "No effect,Set" bitfld.long 0x00 10. " INTLINE_10 ,Set Data Output Register 10" "No effect,Set" bitfld.long 0x00 9. " INTLINE_9 ,Set Data Output Register 9" "No effect,Set" bitfld.long 0x00 8. " INTLINE_8 ,Set Data Output Register 8" "No effect,Set" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Set Data Output Register 7" "No effect,Set" bitfld.long 0x00 6. " INTLINE_6 ,Set Data Output Register 6" "No effect,Set" bitfld.long 0x00 5. " INTLINE_5 ,Set Data Output Register 5" "No effect,Set" bitfld.long 0x00 4. " INTLINE_4 ,Set Data Output Register 4" "No effect,Set" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Set Data Output Register 3" "No effect,Set" bitfld.long 0x00 2. " INTLINE_2 ,Set Data Output Register 2" "No effect,Set" bitfld.long 0x00 1. " INTLINE_1 ,Set Data Output Register 1" "No effect,Set" bitfld.long 0x00 0. " INTLINE_0 ,Set Data Output Register 0" "No effect,Set" width 11. tree.end tree "GPIO 4" base ad:0x48320000 width 16. rgroup.long 0x000++0x03 line.long 0x00 "GPIO_REVISION,Revision number of the GPIO module" bitfld.long 0x00 30.--31. " SCHEME , Used to distinguish between old Scheme and current. [[br]]" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC , Indicates a software compatible module family" bitfld.long 0x00 11.--15. " RTL , RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR , Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision" group.long 0x010++0x03 line.long 0x00 "GPIO_SYSCONFIG,Controls the various parameters of the L4 interconnect" bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management Req/Ack control" "Force-idle,No-idle,Smart-idle," bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software Reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Clock gating" textline " " group.long 0x020++0x03 line.long 0x00 "GPIO_EOI,This module supports DMA events with its interrupt signal" bitfld.long 0x00 0. " DMAEVT_ACK ,Write 0 to acknowledge DMA event has been completed" "Not completed,Completed" width 19. group.long 0x024++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_0,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x028++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_1,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x02C++0x03 line.long 0x00 "GPIO_IRQSTS_0,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x030++0x03 line.long 0x00 "GPIO_IRQSTS_1,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x034++0x03 line.long 0x00 "GPIO_IRQSTS_SET_0,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x038++0x03 line.long 0x00 "GPIO_IRQSTS_SET_1,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x03C++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_0,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x040++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_1,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x044++0x03 line.long 0x00 "GPIO_IRQWAKEN_0,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" group.long 0x048++0x03 line.long 0x00 "GPIO_IRQWAKEN_1,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" textline " " width 13. rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTS,The GPIO_SYSSTS register provides the reset status information about the GPIO module" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x03 line.long 0x00 "GPIO_CTRL,The GPIO_CTRL register controls the clock gating functionality" bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating Ratio" "Normal,/2,/4,/8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" group.long 0x134++0x03 line.long 0x00 "GPIO_OE,The GPIO_OE register is used to enable the pins output capabilities" bitfld.long 0x00 31. " OUTPUTEN_31 ,Output Data Enable 31" "Output,Input" bitfld.long 0x00 30. " OUTPUTEN_30 ,Output Data Enable 30" "Output,Input" bitfld.long 0x00 29. " OUTPUTEN_29 ,Output Data Enable 29" "Output,Input" bitfld.long 0x00 28. " OUTPUTEN_28 ,Output Data Enable 28" "Output,Input" textline " " bitfld.long 0x00 27. " OUTPUTEN_27 ,Output Data Enable 27" "Output,Input" bitfld.long 0x00 26. " OUTPUTEN_26 ,Output Data Enable 26" "Output,Input" bitfld.long 0x00 25. " OUTPUTEN_25 ,Output Data Enable 25" "Output,Input" bitfld.long 0x00 24. " OUTPUTEN_24 ,Output Data Enable 24" "Output,Input" textline " " bitfld.long 0x00 23. " OUTPUTEN_23 ,Output Data Enable 23" "Output,Input" bitfld.long 0x00 22. " OUTPUTEN_22 ,Output Data Enable 22" "Output,Input" bitfld.long 0x00 21. " OUTPUTEN_21 ,Output Data Enable 21" "Output,Input" bitfld.long 0x00 20. " OUTPUTEN_20 ,Output Data Enable 20" "Output,Input" textline " " bitfld.long 0x00 19. " OUTPUTEN_19 ,Output Data Enable 19" "Output,Input" bitfld.long 0x00 18. " OUTPUTEN_18 ,Output Data Enable 18" "Output,Input" bitfld.long 0x00 17. " OUTPUTEN_17 ,Output Data Enable 17" "Output,Input" bitfld.long 0x00 16. " OUTPUTEN_16 ,Output Data Enable 16" "Output,Input" textline " " bitfld.long 0x00 15. " OUTPUTEN_15 ,Output Data Enable 15" "Output,Input" bitfld.long 0x00 14. " OUTPUTEN_14 ,Output Data Enable 14" "Output,Input" bitfld.long 0x00 13. " OUTPUTEN_13 ,Output Data Enable 13" "Output,Input" bitfld.long 0x00 12. " OUTPUTEN_12 ,Output Data Enable 12" "Output,Input" textline " " bitfld.long 0x00 11. " OUTPUTEN_11 ,Output Data Enable 11" "Output,Input" bitfld.long 0x00 10. " OUTPUTEN_10 ,Output Data Enable 10" "Output,Input" bitfld.long 0x00 9. " OUTPUTEN_9 ,Output Data Enable 9" "Output,Input" bitfld.long 0x00 8. " OUTPUTEN_8 ,Output Data Enable 8" "Output,Input" textline " " bitfld.long 0x00 7. " OUTPUTEN_7 ,Output Data Enable 7" "Output,Input" bitfld.long 0x00 6. " OUTPUTEN_6 ,Output Data Enable 6" "Output,Input" bitfld.long 0x00 5. " OUTPUTEN_5 ,Output Data Enable 5" "Output,Input" bitfld.long 0x00 4. " OUTPUTEN_4 ,Output Data Enable 4" "Output,Input" textline " " bitfld.long 0x00 3. " OUTPUTEN_3 ,Output Data Enable 3" "Output,Input" bitfld.long 0x00 2. " OUTPUTEN_2 ,Output Data Enable 2" "Output,Input" bitfld.long 0x00 1. " OUTPUTEN_1 ,Output Data Enable 1" "Output,Input" bitfld.long 0x00 0. " OUTPUTEN_0 ,Output Data Enable 0" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,The GPIO_DATAIN register is used to register the data that is read from the GPIO pins" hexmask.long 0x00 0.--31. 1. " DATAIN , Sampled input data" group.long 0x13C++0x03 line.long 0x00 "GPIO_DATAOUT,The GPIO_DATAOUT register is used for setting the value of the GPIO output pins" hexmask.long 0x00 0.--31. 1. " DATAOUT , Data to set on output pins" textline " " width 21. group.long 0x140++0x03 line.long 0x00 "GPIO_LEVELDETECT0,Register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT0_31 ,Low Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT0_30 ,Low Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT0_29 ,Low Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT0_28 ,Low Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT0_27 ,Low Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT0_26 ,Low Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT0_25 ,Low Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT0_24 ,Low Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT0_23 ,Low Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT0_22 ,Low Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT0_21 ,Low Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT0_20 ,Low Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT0_19 ,Low Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT0_18 ,Low Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT0_17 ,Low Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT0_16 ,Low Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT0_15 ,Low Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT0_14 ,Low Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT0_13 ,Low Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT0_12 ,Low Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT0_11 ,Low Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT0_10 ,Low Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT0_9 ,Low Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT0_8 ,Low Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT0_7 ,Low Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT0_6 ,Low Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT0_5 ,Low Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT0_4 ,Low Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT0_3 ,Low Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT0_2 ,Low Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT0_1 ,Low Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT0_0 ,Low Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "GPIO_LEVELDETECT1,Register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT1_31 ,High Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT1_30 ,High Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT1_29 ,High Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT1_28 ,High Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT1_27 ,High Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT1_26 ,High Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT1_25 ,High Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT1_24 ,High Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT1_23 ,High Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT1_22 ,High Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT1_21 ,High Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT1_20 ,High Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT1_19 ,High Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT1_18 ,High Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT1_17 ,High Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT1_16 ,High Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT1_15 ,High Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT1_14 ,High Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT1_13 ,High Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT1_12 ,High Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT1_11 ,High Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT1_10 ,High Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT1_9 ,High Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT1_8 ,High Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT1_7 ,High Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT1_6 ,High Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT1_5 ,High Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT1_4 ,High Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT1_3 ,High Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT1_2 ,High Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT1_1 ,High Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT1_0 ,High Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x148++0x03 line.long 0x00 "GPIO_RISINGDETECT,Register is used to enable/disable for each input lines the rising-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " RISINGDETECT_31 ,Rising Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " RISINGDETECT_30 ,Rising Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " RISINGDETECT_29 ,Rising Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " RISINGDETECT_28 ,Rising Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RISINGDETECT_27 ,Rising Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " RISINGDETECT_26 ,Rising Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " RISINGDETECT_25 ,Rising Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " RISINGDETECT_24 ,Rising Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " RISINGDETECT_23 ,Rising Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " RISINGDETECT_22 ,Rising Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " RISINGDETECT_21 ,Rising Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " RISINGDETECT_20 ,Rising Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RISINGDETECT_19 ,Rising Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " RISINGDETECT_18 ,Rising Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " RISINGDETECT_17 ,Rising Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " RISINGDETECT_16 ,Rising Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RISINGDETECT_15 ,Rising Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " RISINGDETECT_14 ,Rising Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " RISINGDETECT_13 ,Rising Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " RISINGDETECT_12 ,Rising Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " RISINGDETECT_11 ,Rising Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " RISINGDETECT_10 ,Rising Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " RISINGDETECT_9 ,Rising Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " RISINGDETECT_8 ,Rising Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " RISINGDETECT_7 ,Rising Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " RISINGDETECT_6 ,Rising Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " RISINGDETECT_5 ,Rising Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " RISINGDETECT_4 ,Rising Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RISINGDETECT_3 ,Rising Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " RISINGDETECT_2 ,Rising Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " RISINGDETECT_1 ,Rising Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " RISINGDETECT_0 ,Rising Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "GPIO_FALLINGDETECT,Register is used to enable/disable for each input lines the falling-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " FALLINGDETECT_31 ,Falling Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " FALLINGDETECT_30 ,Falling Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " FALLINGDETECT_29 ,Falling Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " FALLINGDETECT_28 ,Falling Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " FALLINGDETECT_27 ,Falling Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " FALLINGDETECT_26 ,Falling Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " FALLINGDETECT_25 ,Falling Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " FALLINGDETECT_24 ,Falling Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FALLINGDETECT_23 ,Falling Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " FALLINGDETECT_22 ,Falling Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " FALLINGDETECT_21 ,Falling Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " FALLINGDETECT_20 ,Falling Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FALLINGDETECT_19 ,Falling Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " FALLINGDETECT_18 ,Falling Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " FALLINGDETECT_17 ,Falling Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " FALLINGDETECT_16 ,Falling Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FALLINGDETECT_15 ,Falling Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " FALLINGDETECT_14 ,Falling Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " FALLINGDETECT_13 ,Falling Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " FALLINGDETECT_12 ,Falling Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " FALLINGDETECT_11 ,Falling Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " FALLINGDETECT_10 ,Falling Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " FALLINGDETECT_9 ,Falling Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " FALLINGDETECT_8 ,Falling Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FALLINGDETECT_7 ,Falling Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " FALLINGDETECT_6 ,Falling Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " FALLINGDETECT_5 ,Falling Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " FALLINGDETECT_4 ,Falling Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FALLINGDETECT_3 ,Falling Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " FALLINGDETECT_2 ,Falling Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " FALLINGDETECT_1 ,Falling Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " FALLINGDETECT_0 ,Falling Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x150++0x03 line.long 0x00 "GPIO_DEBOUNCEN,Register is used to enable/disable the debouncing feature for each input line." bitfld.long 0x00 31. " DEBOUNCEEN_31 ,Input Debounce Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " DEBOUNCEEN_30 ,Input Debounce Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " DEBOUNCEEN_29 ,Input Debounce Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " DEBOUNCEEN_28 ,Input Debounce Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " DEBOUNCEEN_27 ,Input Debounce Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " DEBOUNCEEN_26 ,Input Debounce Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " DEBOUNCEEN_25 ,Input Debounce Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " DEBOUNCEEN_24 ,Input Debounce Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DEBOUNCEEN_23 ,Input Debounce Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " DEBOUNCEEN_22 ,Input Debounce Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " DEBOUNCEEN_21 ,Input Debounce Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " DEBOUNCEEN_20 ,Input Debounce Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DEBOUNCEEN_19 ,Input Debounce Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DEBOUNCEEN_18 ,Input Debounce Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DEBOUNCEEN_17 ,Input Debounce Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DEBOUNCEEN_16 ,Input Debounce Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DEBOUNCEEN_15 ,Input Debounce Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DEBOUNCEEN_14 ,Input Debounce Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DEBOUNCEEN_13 ,Input Debounce Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DEBOUNCEEN_12 ,Input Debounce Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DEBOUNCEEN_11 ,Input Debounce Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DEBOUNCEEN_10 ,Input Debounce Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DEBOUNCEEN_9 ,Input Debounce Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DEBOUNCEEN_8 ,Input Debounce Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DEBOUNCEEN_7 ,Input Debounce Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DEBOUNCEEN_6 ,Input Debounce Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DEBOUNCEEN_5 ,Input Debounce Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DEBOUNCEEN_4 ,Input Debounce Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DEBOUNCEEN_3 ,Input Debounce Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DEBOUNCEEN_2 ,Input Debounce Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DEBOUNCEEN_1 ,Input Debounce Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DEBOUNCEEN_0 ,Input Debounce Enable 0" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "GPIO_DEBOUNCINGTIME,Register controls debouncing time" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME , Input Debouncing Value" group.long 0x190++0x03 line.long 0x00 "GPIO_CLRDATAOUT,Register clears to 0 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Clear Data Output Register 31" "No effect,Clear" bitfld.long 0x00 30. " INTLINE_30 ,Clear Data Output Register 30" "No effect,Clear" bitfld.long 0x00 29. " INTLINE_29 ,Clear Data Output Register 29" "No effect,Clear" bitfld.long 0x00 28. " INTLINE_28 ,Clear Data Output Register 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Clear Data Output Register 27" "No effect,Clear" bitfld.long 0x00 26. " INTLINE_26 ,Clear Data Output Register 26" "No effect,Clear" bitfld.long 0x00 25. " INTLINE_25 ,Clear Data Output Register 25" "No effect,Clear" bitfld.long 0x00 24. " INTLINE_24 ,Clear Data Output Register 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Clear Data Output Register 23" "No effect,Clear" bitfld.long 0x00 22. " INTLINE_22 ,Clear Data Output Register 22" "No effect,Clear" bitfld.long 0x00 21. " INTLINE_21 ,Clear Data Output Register 21" "No effect,Clear" bitfld.long 0x00 20. " INTLINE_20 ,Clear Data Output Register 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Clear Data Output Register 19" "No effect,Clear" bitfld.long 0x00 18. " INTLINE_18 ,Clear Data Output Register 18" "No effect,Clear" bitfld.long 0x00 17. " INTLINE_17 ,Clear Data Output Register 17" "No effect,Clear" bitfld.long 0x00 16. " INTLINE_16 ,Clear Data Output Register 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Clear Data Output Register 15" "No effect,Clear" bitfld.long 0x00 14. " INTLINE_14 ,Clear Data Output Register 14" "No effect,Clear" bitfld.long 0x00 13. " INTLINE_13 ,Clear Data Output Register 13" "No effect,Clear" bitfld.long 0x00 12. " INTLINE_12 ,Clear Data Output Register 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Clear Data Output Register 11" "No effect,Clear" bitfld.long 0x00 10. " INTLINE_10 ,Clear Data Output Register 10" "No effect,Clear" bitfld.long 0x00 9. " INTLINE_9 ,Clear Data Output Register 9" "No effect,Clear" bitfld.long 0x00 8. " INTLINE_8 ,Clear Data Output Register 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Clear Data Output Register 7" "No effect,Clear" bitfld.long 0x00 6. " INTLINE_6 ,Clear Data Output Register 6" "No effect,Clear" bitfld.long 0x00 5. " INTLINE_5 ,Clear Data Output Register 5" "No effect,Clear" bitfld.long 0x00 4. " INTLINE_4 ,Clear Data Output Register 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Clear Data Output Register 3" "No effect,Clear" bitfld.long 0x00 2. " INTLINE_2 ,Clear Data Output Register 2" "No effect,Clear" bitfld.long 0x00 1. " INTLINE_1 ,Clear Data Output Register 1" "No effect,Clear" bitfld.long 0x00 0. " INTLINE_0 ,Clear Data Output Register 0" "No effect,Clear" group.long 0x194++0x03 line.long 0x00 "GPIO_SETDATAOUT,Register sets to 1 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Set Data Output Register 31" "No effect,Set" bitfld.long 0x00 30. " INTLINE_30 ,Set Data Output Register 30" "No effect,Set" bitfld.long 0x00 29. " INTLINE_29 ,Set Data Output Register 29" "No effect,Set" bitfld.long 0x00 28. " INTLINE_28 ,Set Data Output Register 28" "No effect,Set" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Set Data Output Register 27" "No effect,Set" bitfld.long 0x00 26. " INTLINE_26 ,Set Data Output Register 26" "No effect,Set" bitfld.long 0x00 25. " INTLINE_25 ,Set Data Output Register 25" "No effect,Set" bitfld.long 0x00 24. " INTLINE_24 ,Set Data Output Register 24" "No effect,Set" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Set Data Output Register 23" "No effect,Set" bitfld.long 0x00 22. " INTLINE_22 ,Set Data Output Register 22" "No effect,Set" bitfld.long 0x00 21. " INTLINE_21 ,Set Data Output Register 21" "No effect,Set" bitfld.long 0x00 20. " INTLINE_20 ,Set Data Output Register 20" "No effect,Set" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Set Data Output Register 19" "No effect,Set" bitfld.long 0x00 18. " INTLINE_18 ,Set Data Output Register 18" "No effect,Set" bitfld.long 0x00 17. " INTLINE_17 ,Set Data Output Register 17" "No effect,Set" bitfld.long 0x00 16. " INTLINE_16 ,Set Data Output Register 16" "No effect,Set" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Set Data Output Register 15" "No effect,Set" bitfld.long 0x00 14. " INTLINE_14 ,Set Data Output Register 14" "No effect,Set" bitfld.long 0x00 13. " INTLINE_13 ,Set Data Output Register 13" "No effect,Set" bitfld.long 0x00 12. " INTLINE_12 ,Set Data Output Register 12" "No effect,Set" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Set Data Output Register 11" "No effect,Set" bitfld.long 0x00 10. " INTLINE_10 ,Set Data Output Register 10" "No effect,Set" bitfld.long 0x00 9. " INTLINE_9 ,Set Data Output Register 9" "No effect,Set" bitfld.long 0x00 8. " INTLINE_8 ,Set Data Output Register 8" "No effect,Set" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Set Data Output Register 7" "No effect,Set" bitfld.long 0x00 6. " INTLINE_6 ,Set Data Output Register 6" "No effect,Set" bitfld.long 0x00 5. " INTLINE_5 ,Set Data Output Register 5" "No effect,Set" bitfld.long 0x00 4. " INTLINE_4 ,Set Data Output Register 4" "No effect,Set" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Set Data Output Register 3" "No effect,Set" bitfld.long 0x00 2. " INTLINE_2 ,Set Data Output Register 2" "No effect,Set" bitfld.long 0x00 1. " INTLINE_1 ,Set Data Output Register 1" "No effect,Set" bitfld.long 0x00 0. " INTLINE_0 ,Set Data Output Register 0" "No effect,Set" width 11. tree.end tree "GPIO 5" base ad:0x48322000 width 16. rgroup.long 0x000++0x03 line.long 0x00 "GPIO_REVISION,Revision number of the GPIO module" bitfld.long 0x00 30.--31. " SCHEME , Used to distinguish between old Scheme and current. [[br]]" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC , Indicates a software compatible module family" bitfld.long 0x00 11.--15. " RTL , RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR , Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM , Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR , Minor Revision" group.long 0x010++0x03 line.long 0x00 "GPIO_SYSCONFIG,Controls the various parameters of the L4 interconnect" bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management Req/Ack control" "Force-idle,No-idle,Smart-idle," bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup control" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SOFTRESET ,Software Reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Clock gating" textline " " group.long 0x020++0x03 line.long 0x00 "GPIO_EOI,This module supports DMA events with its interrupt signal" bitfld.long 0x00 0. " DMAEVT_ACK ,Write 0 to acknowledge DMA event has been completed" "Not completed,Completed" width 19. group.long 0x024++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_0,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x028++0x03 line.long 0x00 "GPIO_IRQSTS_RAW_1,Provides core status information for the interrupt handling" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Trigged" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Trigged" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Trigged" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Trigged" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Trigged" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Trigged" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Trigged" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Trigged" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Trigged" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Trigged" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Trigged" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Trigged" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Trigged" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Trigged" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Trigged" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Trigged" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Trigged" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Trigged" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Trigged" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Trigged" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Trigged" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Trigged" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Trigged" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Trigged" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Trigged" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Trigged" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Trigged" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Trigged" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Trigged" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Trigged" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Trigged" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Trigged" group.long 0x02C++0x03 line.long 0x00 "GPIO_IRQSTS_0,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x030++0x03 line.long 0x00 "GPIO_IRQSTS_1,Provides core status information for the interrupt handling" eventfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Clear" eventfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Clear" eventfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Clear" eventfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Clear" textline " " eventfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Clear" eventfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Clear" eventfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Clear" eventfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Clear" textline " " eventfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Clear" eventfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Clear" eventfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Clear" eventfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Clear" textline " " eventfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Clear" eventfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Clear" eventfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Clear" eventfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Clear" textline " " eventfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Clear" eventfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Clear" eventfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Clear" eventfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Clear" textline " " eventfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Clear" eventfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Clear" eventfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Clear" eventfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Clear" textline " " eventfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Clear" eventfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Clear" eventfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Clear" eventfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Clear" textline " " eventfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Clear" eventfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Clear" eventfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Clear" eventfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Clear" group.long 0x034++0x03 line.long 0x00 "GPIO_IRQSTS_SET_0,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x038++0x03 line.long 0x00 "GPIO_IRQSTS_SET_1,Specific interrupt event enable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Enabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Enabled" group.long 0x03C++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_0,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x040++0x03 line.long 0x00 "GPIO_IRQSTS_CLR_1,Specific interrupt event disable register" bitfld.long 0x00 31. " INTLINE_31 ,Interrupt 31 status" "No effect,Disabled" bitfld.long 0x00 30. " INTLINE_30 ,Interrupt 30 status" "No effect,Disabled" bitfld.long 0x00 29. " INTLINE_29 ,Interrupt 29 status" "No effect,Disabled" bitfld.long 0x00 28. " INTLINE_28 ,Interrupt 28 status" "No effect,Disabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Interrupt 27 status" "No effect,Disabled" bitfld.long 0x00 26. " INTLINE_26 ,Interrupt 26 status" "No effect,Disabled" bitfld.long 0x00 25. " INTLINE_25 ,Interrupt 25 status" "No effect,Disabled" bitfld.long 0x00 24. " INTLINE_24 ,Interrupt 24 status" "No effect,Disabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Interrupt 23 status" "No effect,Disabled" bitfld.long 0x00 22. " INTLINE_22 ,Interrupt 22 status" "No effect,Disabled" bitfld.long 0x00 21. " INTLINE_21 ,Interrupt 21 status" "No effect,Disabled" bitfld.long 0x00 20. " INTLINE_20 ,Interrupt 20 status" "No effect,Disabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Interrupt 19 status" "No effect,Disabled" bitfld.long 0x00 18. " INTLINE_18 ,Interrupt 18 status" "No effect,Disabled" bitfld.long 0x00 17. " INTLINE_17 ,Interrupt 17 status" "No effect,Disabled" bitfld.long 0x00 16. " INTLINE_16 ,Interrupt 16 status" "No effect,Disabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Interrupt 15 status" "No effect,Disabled" bitfld.long 0x00 14. " INTLINE_14 ,Interrupt 14 status" "No effect,Disabled" bitfld.long 0x00 13. " INTLINE_13 ,Interrupt 13 status" "No effect,Disabled" bitfld.long 0x00 12. " INTLINE_12 ,Interrupt 12 status" "No effect,Disabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Interrupt 11 status" "No effect,Disabled" bitfld.long 0x00 10. " INTLINE_10 ,Interrupt 10 status" "No effect,Disabled" bitfld.long 0x00 9. " INTLINE_9 ,Interrupt 9 status" "No effect,Disabled" bitfld.long 0x00 8. " INTLINE_8 ,Interrupt 8 status" "No effect,Disabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Interrupt 7 status" "No effect,Disabled" bitfld.long 0x00 6. " INTLINE_6 ,Interrupt 6 status" "No effect,Disabled" bitfld.long 0x00 5. " INTLINE_5 ,Interrupt 5 status" "No effect,Disabled" bitfld.long 0x00 4. " INTLINE_4 ,Interrupt 4 status" "No effect,Disabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Interrupt 3 status" "No effect,Disabled" bitfld.long 0x00 2. " INTLINE_2 ,Interrupt 2 status" "No effect,Disabled" bitfld.long 0x00 1. " INTLINE_1 ,Interrupt 1 status" "No effect,Disabled" bitfld.long 0x00 0. " INTLINE_0 ,Interrupt 0 status" "No effect,Disabled" group.long 0x044++0x03 line.long 0x00 "GPIO_IRQWAKEN_0,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" group.long 0x048++0x03 line.long 0x00 "GPIO_IRQWAKEN_1,Register enables a specific (synchronous) IRQ request source to generate an asynchronous wakeup (on the appropriate swakeup line)" bitfld.long 0x00 31. " INTLINE_31 ,Wakeup Set for Interrupt Line 31" "Disabled,Enabled" bitfld.long 0x00 30. " INTLINE_30 ,Wakeup Set for Interrupt Line 30" "Disabled,Enabled" bitfld.long 0x00 29. " INTLINE_29 ,Wakeup Set for Interrupt Line 29" "Disabled,Enabled" bitfld.long 0x00 28. " INTLINE_28 ,Wakeup Set for Interrupt Line 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Wakeup Set for Interrupt Line 27" "Disabled,Enabled" bitfld.long 0x00 26. " INTLINE_26 ,Wakeup Set for Interrupt Line 26" "Disabled,Enabledk" bitfld.long 0x00 25. " INTLINE_25 ,Wakeup Set for Interrupt Line 25" "Disabled,Enabled" bitfld.long 0x00 24. " INTLINE_24 ,Wakeup Set for Interrupt Line 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Wakeup Set for Interrupt Line 23" "Disabled,Enabled" bitfld.long 0x00 22. " INTLINE_22 ,Wakeup Set for Interrupt Line 22" "Disabled,Enabled" bitfld.long 0x00 21. " INTLINE_21 ,Wakeup Set for Interrupt Line 21" "Disabled,Enabled" bitfld.long 0x00 20. " INTLINE_20 ,Wakeup Set for Interrupt Line 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Wakeup Set for Interrupt Line 19" "Disabled,Enabled" bitfld.long 0x00 18. " INTLINE_18 ,Wakeup Set for Interrupt Line 18" "Disabled,Enabled" bitfld.long 0x00 17. " INTLINE_17 ,Wakeup Set for Interrupt Line 17" "Disabled,Enabled" bitfld.long 0x00 16. " INTLINE_16 ,Wakeup Set for Interrupt Line 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Wakeup Set for Interrupt Line 15" "Disabled,Enabled" bitfld.long 0x00 14. " INTLINE_14 ,Wakeup Set for Interrupt Line 14" "Disabled,Enabled" bitfld.long 0x00 13. " INTLINE_13 ,Wakeup Set for Interrupt Line 13" "Disabled,Enabled" bitfld.long 0x00 12. " INTLINE_12 ,Wakeup Set for Interrupt Line 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Wakeup Set for Interrupt Line 11" "Disabled,Enabled" bitfld.long 0x00 10. " INTLINE_10 ,Wakeup Set for Interrupt Line 10" "Disabled,Enabled" bitfld.long 0x00 9. " INTLINE_9 ,Wakeup Set for Interrupt Line 9" "Disabled,Enabled" bitfld.long 0x00 8. " INTLINE_8 ,Wakeup Set for Interrupt Line 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Wakeup Set for Interrupt Line 7" "Disabled,Enabled" bitfld.long 0x00 6. " INTLINE_6 ,Wakeup Set for Interrupt Line 6" "Disabled,Enabled" bitfld.long 0x00 5. " INTLINE_5 ,Wakeup Set for Interrupt Line 5" "Disabled,Enabled" bitfld.long 0x00 4. " INTLINE_4 ,Wakeup Set for Interrupt Line 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Wakeup Set for Interrupt Line 3" "Disabled,Enabled" bitfld.long 0x00 2. " INTLINE_2 ,Wakeup Set for Interrupt Line 2" "Disabled,Enabled" bitfld.long 0x00 1. " INTLINE_1 ,Wakeup Set for Interrupt Line 1" "Disabled,Enabled" bitfld.long 0x00 0. " INTLINE_0 ,Wakeup Set for Interrupt Line 0" "Disabled,Enabled" textline " " width 13. rgroup.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTS,The GPIO_SYSSTS register provides the reset status information about the GPIO module" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x03 line.long 0x00 "GPIO_CTRL,The GPIO_CTRL register controls the clock gating functionality" bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating Ratio" "Normal,/2,/4,/8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" group.long 0x134++0x03 line.long 0x00 "GPIO_OE,The GPIO_OE register is used to enable the pins output capabilities" bitfld.long 0x00 31. " OUTPUTEN_31 ,Output Data Enable 31" "Output,Input" bitfld.long 0x00 30. " OUTPUTEN_30 ,Output Data Enable 30" "Output,Input" bitfld.long 0x00 29. " OUTPUTEN_29 ,Output Data Enable 29" "Output,Input" bitfld.long 0x00 28. " OUTPUTEN_28 ,Output Data Enable 28" "Output,Input" textline " " bitfld.long 0x00 27. " OUTPUTEN_27 ,Output Data Enable 27" "Output,Input" bitfld.long 0x00 26. " OUTPUTEN_26 ,Output Data Enable 26" "Output,Input" bitfld.long 0x00 25. " OUTPUTEN_25 ,Output Data Enable 25" "Output,Input" bitfld.long 0x00 24. " OUTPUTEN_24 ,Output Data Enable 24" "Output,Input" textline " " bitfld.long 0x00 23. " OUTPUTEN_23 ,Output Data Enable 23" "Output,Input" bitfld.long 0x00 22. " OUTPUTEN_22 ,Output Data Enable 22" "Output,Input" bitfld.long 0x00 21. " OUTPUTEN_21 ,Output Data Enable 21" "Output,Input" bitfld.long 0x00 20. " OUTPUTEN_20 ,Output Data Enable 20" "Output,Input" textline " " bitfld.long 0x00 19. " OUTPUTEN_19 ,Output Data Enable 19" "Output,Input" bitfld.long 0x00 18. " OUTPUTEN_18 ,Output Data Enable 18" "Output,Input" bitfld.long 0x00 17. " OUTPUTEN_17 ,Output Data Enable 17" "Output,Input" bitfld.long 0x00 16. " OUTPUTEN_16 ,Output Data Enable 16" "Output,Input" textline " " bitfld.long 0x00 15. " OUTPUTEN_15 ,Output Data Enable 15" "Output,Input" bitfld.long 0x00 14. " OUTPUTEN_14 ,Output Data Enable 14" "Output,Input" bitfld.long 0x00 13. " OUTPUTEN_13 ,Output Data Enable 13" "Output,Input" bitfld.long 0x00 12. " OUTPUTEN_12 ,Output Data Enable 12" "Output,Input" textline " " bitfld.long 0x00 11. " OUTPUTEN_11 ,Output Data Enable 11" "Output,Input" bitfld.long 0x00 10. " OUTPUTEN_10 ,Output Data Enable 10" "Output,Input" bitfld.long 0x00 9. " OUTPUTEN_9 ,Output Data Enable 9" "Output,Input" bitfld.long 0x00 8. " OUTPUTEN_8 ,Output Data Enable 8" "Output,Input" textline " " bitfld.long 0x00 7. " OUTPUTEN_7 ,Output Data Enable 7" "Output,Input" bitfld.long 0x00 6. " OUTPUTEN_6 ,Output Data Enable 6" "Output,Input" bitfld.long 0x00 5. " OUTPUTEN_5 ,Output Data Enable 5" "Output,Input" bitfld.long 0x00 4. " OUTPUTEN_4 ,Output Data Enable 4" "Output,Input" textline " " bitfld.long 0x00 3. " OUTPUTEN_3 ,Output Data Enable 3" "Output,Input" bitfld.long 0x00 2. " OUTPUTEN_2 ,Output Data Enable 2" "Output,Input" bitfld.long 0x00 1. " OUTPUTEN_1 ,Output Data Enable 1" "Output,Input" bitfld.long 0x00 0. " OUTPUTEN_0 ,Output Data Enable 0" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,The GPIO_DATAIN register is used to register the data that is read from the GPIO pins" hexmask.long 0x00 0.--31. 1. " DATAIN , Sampled input data" group.long 0x13C++0x03 line.long 0x00 "GPIO_DATAOUT,The GPIO_DATAOUT register is used for setting the value of the GPIO output pins" hexmask.long 0x00 0.--31. 1. " DATAOUT , Data to set on output pins" textline " " width 21. group.long 0x140++0x03 line.long 0x00 "GPIO_LEVELDETECT0,Register is used to enable/disable for each input lines the low-level (0) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT0_31 ,Low Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT0_30 ,Low Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT0_29 ,Low Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT0_28 ,Low Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT0_27 ,Low Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT0_26 ,Low Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT0_25 ,Low Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT0_24 ,Low Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT0_23 ,Low Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT0_22 ,Low Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT0_21 ,Low Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT0_20 ,Low Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT0_19 ,Low Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT0_18 ,Low Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT0_17 ,Low Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT0_16 ,Low Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT0_15 ,Low Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT0_14 ,Low Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT0_13 ,Low Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT0_12 ,Low Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT0_11 ,Low Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT0_10 ,Low Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT0_9 ,Low Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT0_8 ,Low Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT0_7 ,Low Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT0_6 ,Low Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT0_5 ,Low Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT0_4 ,Low Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT0_3 ,Low Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT0_2 ,Low Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT0_1 ,Low Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT0_0 ,Low Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x144++0x03 line.long 0x00 "GPIO_LEVELDETECT1,Register is used to enable/disable for each input lines the high-level (1) detection to be used for the interrupt request generation" bitfld.long 0x00 31. " LEVELDETECT1_31 ,High Level Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " LEVELDETECT1_30 ,High Level Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " LEVELDETECT1_29 ,High Level Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " LEVELDETECT1_28 ,High Level Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LEVELDETECT1_27 ,High Level Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " LEVELDETECT1_26 ,High Level Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " LEVELDETECT1_25 ,High Level Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " LEVELDETECT1_24 ,High Level Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " LEVELDETECT1_23 ,High Level Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " LEVELDETECT1_22 ,High Level Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " LEVELDETECT1_21 ,High Level Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " LEVELDETECT1_20 ,High Level Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " LEVELDETECT1_19 ,High Level Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " LEVELDETECT1_18 ,High Level Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " LEVELDETECT1_17 ,High Level Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " LEVELDETECT1_16 ,High Level Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " LEVELDETECT1_15 ,High Level Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LEVELDETECT1_14 ,High Level Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LEVELDETECT1_13 ,High Level Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LEVELDETECT1_12 ,High Level Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LEVELDETECT1_11 ,High Level Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LEVELDETECT1_10 ,High Level Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LEVELDETECT1_9 ,High Level Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LEVELDETECT1_8 ,High Level Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LEVELDETECT1_7 ,High Level Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LEVELDETECT1_6 ,High Level Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LEVELDETECT1_5 ,High Level Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LEVELDETECT1_4 ,High Level Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LEVELDETECT1_3 ,High Level Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LEVELDETECT1_2 ,High Level Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LEVELDETECT1_1 ,High Level Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LEVELDETECT1_0 ,High Level Interrupt Enable 0" "Disabled,Enabled" group.long 0x148++0x03 line.long 0x00 "GPIO_RISINGDETECT,Register is used to enable/disable for each input lines the rising-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " RISINGDETECT_31 ,Rising Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " RISINGDETECT_30 ,Rising Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " RISINGDETECT_29 ,Rising Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " RISINGDETECT_28 ,Rising Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RISINGDETECT_27 ,Rising Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " RISINGDETECT_26 ,Rising Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " RISINGDETECT_25 ,Rising Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " RISINGDETECT_24 ,Rising Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " RISINGDETECT_23 ,Rising Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " RISINGDETECT_22 ,Rising Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " RISINGDETECT_21 ,Rising Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " RISINGDETECT_20 ,Rising Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " RISINGDETECT_19 ,Rising Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " RISINGDETECT_18 ,Rising Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " RISINGDETECT_17 ,Rising Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " RISINGDETECT_16 ,Rising Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " RISINGDETECT_15 ,Rising Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " RISINGDETECT_14 ,Rising Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " RISINGDETECT_13 ,Rising Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " RISINGDETECT_12 ,Rising Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " RISINGDETECT_11 ,Rising Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " RISINGDETECT_10 ,Rising Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " RISINGDETECT_9 ,Rising Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " RISINGDETECT_8 ,Rising Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " RISINGDETECT_7 ,Rising Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " RISINGDETECT_6 ,Rising Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " RISINGDETECT_5 ,Rising Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " RISINGDETECT_4 ,Rising Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RISINGDETECT_3 ,Rising Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " RISINGDETECT_2 ,Rising Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " RISINGDETECT_1 ,Rising Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " RISINGDETECT_0 ,Rising Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x14C++0x03 line.long 0x00 "GPIO_FALLINGDETECT,Register is used to enable/disable for each input lines the falling-edge detection to be used for the interrupt request generation" bitfld.long 0x00 31. " FALLINGDETECT_31 ,Falling Edge Interrupt Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " FALLINGDETECT_30 ,Falling Edge Interrupt Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " FALLINGDETECT_29 ,Falling Edge Interrupt Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " FALLINGDETECT_28 ,Falling Edge Interrupt Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " FALLINGDETECT_27 ,Falling Edge Interrupt Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " FALLINGDETECT_26 ,Falling Edge Interrupt Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " FALLINGDETECT_25 ,Falling Edge Interrupt Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " FALLINGDETECT_24 ,Falling Edge Interrupt Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FALLINGDETECT_23 ,Falling Edge Interrupt Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " FALLINGDETECT_22 ,Falling Edge Interrupt Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " FALLINGDETECT_21 ,Falling Edge Interrupt Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " FALLINGDETECT_20 ,Falling Edge Interrupt Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FALLINGDETECT_19 ,Falling Edge Interrupt Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " FALLINGDETECT_18 ,Falling Edge Interrupt Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " FALLINGDETECT_17 ,Falling Edge Interrupt Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " FALLINGDETECT_16 ,Falling Edge Interrupt Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FALLINGDETECT_15 ,Falling Edge Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " FALLINGDETECT_14 ,Falling Edge Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " FALLINGDETECT_13 ,Falling Edge Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " FALLINGDETECT_12 ,Falling Edge Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " FALLINGDETECT_11 ,Falling Edge Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " FALLINGDETECT_10 ,Falling Edge Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " FALLINGDETECT_9 ,Falling Edge Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " FALLINGDETECT_8 ,Falling Edge Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FALLINGDETECT_7 ,Falling Edge Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " FALLINGDETECT_6 ,Falling Edge Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " FALLINGDETECT_5 ,Falling Edge Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " FALLINGDETECT_4 ,Falling Edge Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FALLINGDETECT_3 ,Falling Edge Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " FALLINGDETECT_2 ,Falling Edge Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " FALLINGDETECT_1 ,Falling Edge Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " FALLINGDETECT_0 ,Falling Edge Interrupt Enable 0" "Disabled,Enabled" group.long 0x150++0x03 line.long 0x00 "GPIO_DEBOUNCEN,Register is used to enable/disable the debouncing feature for each input line." bitfld.long 0x00 31. " DEBOUNCEEN_31 ,Input Debounce Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " DEBOUNCEEN_30 ,Input Debounce Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " DEBOUNCEEN_29 ,Input Debounce Enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " DEBOUNCEEN_28 ,Input Debounce Enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " DEBOUNCEEN_27 ,Input Debounce Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " DEBOUNCEEN_26 ,Input Debounce Enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " DEBOUNCEEN_25 ,Input Debounce Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " DEBOUNCEEN_24 ,Input Debounce Enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DEBOUNCEEN_23 ,Input Debounce Enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " DEBOUNCEEN_22 ,Input Debounce Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " DEBOUNCEEN_21 ,Input Debounce Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " DEBOUNCEEN_20 ,Input Debounce Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DEBOUNCEEN_19 ,Input Debounce Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DEBOUNCEEN_18 ,Input Debounce Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DEBOUNCEEN_17 ,Input Debounce Enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DEBOUNCEEN_16 ,Input Debounce Enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DEBOUNCEEN_15 ,Input Debounce Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DEBOUNCEEN_14 ,Input Debounce Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DEBOUNCEEN_13 ,Input Debounce Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DEBOUNCEEN_12 ,Input Debounce Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DEBOUNCEEN_11 ,Input Debounce Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DEBOUNCEEN_10 ,Input Debounce Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DEBOUNCEEN_9 ,Input Debounce Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DEBOUNCEEN_8 ,Input Debounce Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DEBOUNCEEN_7 ,Input Debounce Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DEBOUNCEEN_6 ,Input Debounce Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DEBOUNCEEN_5 ,Input Debounce Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DEBOUNCEEN_4 ,Input Debounce Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DEBOUNCEEN_3 ,Input Debounce Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DEBOUNCEEN_2 ,Input Debounce Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DEBOUNCEEN_1 ,Input Debounce Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DEBOUNCEEN_0 ,Input Debounce Enable 0" "Disabled,Enabled" group.long 0x154++0x03 line.long 0x00 "GPIO_DEBOUNCINGTIME,Register controls debouncing time" hexmask.long.byte 0x00 0.--7. 1. " DEBOUNCETIME , Input Debouncing Value" group.long 0x190++0x03 line.long 0x00 "GPIO_CLRDATAOUT,Register clears to 0 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Clear Data Output Register 31" "No effect,Clear" bitfld.long 0x00 30. " INTLINE_30 ,Clear Data Output Register 30" "No effect,Clear" bitfld.long 0x00 29. " INTLINE_29 ,Clear Data Output Register 29" "No effect,Clear" bitfld.long 0x00 28. " INTLINE_28 ,Clear Data Output Register 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Clear Data Output Register 27" "No effect,Clear" bitfld.long 0x00 26. " INTLINE_26 ,Clear Data Output Register 26" "No effect,Clear" bitfld.long 0x00 25. " INTLINE_25 ,Clear Data Output Register 25" "No effect,Clear" bitfld.long 0x00 24. " INTLINE_24 ,Clear Data Output Register 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Clear Data Output Register 23" "No effect,Clear" bitfld.long 0x00 22. " INTLINE_22 ,Clear Data Output Register 22" "No effect,Clear" bitfld.long 0x00 21. " INTLINE_21 ,Clear Data Output Register 21" "No effect,Clear" bitfld.long 0x00 20. " INTLINE_20 ,Clear Data Output Register 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Clear Data Output Register 19" "No effect,Clear" bitfld.long 0x00 18. " INTLINE_18 ,Clear Data Output Register 18" "No effect,Clear" bitfld.long 0x00 17. " INTLINE_17 ,Clear Data Output Register 17" "No effect,Clear" bitfld.long 0x00 16. " INTLINE_16 ,Clear Data Output Register 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Clear Data Output Register 15" "No effect,Clear" bitfld.long 0x00 14. " INTLINE_14 ,Clear Data Output Register 14" "No effect,Clear" bitfld.long 0x00 13. " INTLINE_13 ,Clear Data Output Register 13" "No effect,Clear" bitfld.long 0x00 12. " INTLINE_12 ,Clear Data Output Register 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Clear Data Output Register 11" "No effect,Clear" bitfld.long 0x00 10. " INTLINE_10 ,Clear Data Output Register 10" "No effect,Clear" bitfld.long 0x00 9. " INTLINE_9 ,Clear Data Output Register 9" "No effect,Clear" bitfld.long 0x00 8. " INTLINE_8 ,Clear Data Output Register 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Clear Data Output Register 7" "No effect,Clear" bitfld.long 0x00 6. " INTLINE_6 ,Clear Data Output Register 6" "No effect,Clear" bitfld.long 0x00 5. " INTLINE_5 ,Clear Data Output Register 5" "No effect,Clear" bitfld.long 0x00 4. " INTLINE_4 ,Clear Data Output Register 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Clear Data Output Register 3" "No effect,Clear" bitfld.long 0x00 2. " INTLINE_2 ,Clear Data Output Register 2" "No effect,Clear" bitfld.long 0x00 1. " INTLINE_1 ,Clear Data Output Register 1" "No effect,Clear" bitfld.long 0x00 0. " INTLINE_0 ,Clear Data Output Register 0" "No effect,Clear" group.long 0x194++0x03 line.long 0x00 "GPIO_SETDATAOUT,Register sets to 1 the corresponding bit in the GPIO_DATAOUT register" bitfld.long 0x00 31. " INTLINE_31 ,Set Data Output Register 31" "No effect,Set" bitfld.long 0x00 30. " INTLINE_30 ,Set Data Output Register 30" "No effect,Set" bitfld.long 0x00 29. " INTLINE_29 ,Set Data Output Register 29" "No effect,Set" bitfld.long 0x00 28. " INTLINE_28 ,Set Data Output Register 28" "No effect,Set" textline " " bitfld.long 0x00 27. " INTLINE_27 ,Set Data Output Register 27" "No effect,Set" bitfld.long 0x00 26. " INTLINE_26 ,Set Data Output Register 26" "No effect,Set" bitfld.long 0x00 25. " INTLINE_25 ,Set Data Output Register 25" "No effect,Set" bitfld.long 0x00 24. " INTLINE_24 ,Set Data Output Register 24" "No effect,Set" textline " " bitfld.long 0x00 23. " INTLINE_23 ,Set Data Output Register 23" "No effect,Set" bitfld.long 0x00 22. " INTLINE_22 ,Set Data Output Register 22" "No effect,Set" bitfld.long 0x00 21. " INTLINE_21 ,Set Data Output Register 21" "No effect,Set" bitfld.long 0x00 20. " INTLINE_20 ,Set Data Output Register 20" "No effect,Set" textline " " bitfld.long 0x00 19. " INTLINE_19 ,Set Data Output Register 19" "No effect,Set" bitfld.long 0x00 18. " INTLINE_18 ,Set Data Output Register 18" "No effect,Set" bitfld.long 0x00 17. " INTLINE_17 ,Set Data Output Register 17" "No effect,Set" bitfld.long 0x00 16. " INTLINE_16 ,Set Data Output Register 16" "No effect,Set" textline " " bitfld.long 0x00 15. " INTLINE_15 ,Set Data Output Register 15" "No effect,Set" bitfld.long 0x00 14. " INTLINE_14 ,Set Data Output Register 14" "No effect,Set" bitfld.long 0x00 13. " INTLINE_13 ,Set Data Output Register 13" "No effect,Set" bitfld.long 0x00 12. " INTLINE_12 ,Set Data Output Register 12" "No effect,Set" textline " " bitfld.long 0x00 11. " INTLINE_11 ,Set Data Output Register 11" "No effect,Set" bitfld.long 0x00 10. " INTLINE_10 ,Set Data Output Register 10" "No effect,Set" bitfld.long 0x00 9. " INTLINE_9 ,Set Data Output Register 9" "No effect,Set" bitfld.long 0x00 8. " INTLINE_8 ,Set Data Output Register 8" "No effect,Set" textline " " bitfld.long 0x00 7. " INTLINE_7 ,Set Data Output Register 7" "No effect,Set" bitfld.long 0x00 6. " INTLINE_6 ,Set Data Output Register 6" "No effect,Set" bitfld.long 0x00 5. " INTLINE_5 ,Set Data Output Register 5" "No effect,Set" bitfld.long 0x00 4. " INTLINE_4 ,Set Data Output Register 4" "No effect,Set" textline " " bitfld.long 0x00 3. " INTLINE_3 ,Set Data Output Register 3" "No effect,Set" bitfld.long 0x00 2. " INTLINE_2 ,Set Data Output Register 2" "No effect,Set" bitfld.long 0x00 1. " INTLINE_1 ,Set Data Output Register 1" "No effect,Set" bitfld.long 0x00 0. " INTLINE_0 ,Set Data Output Register 0" "No effect,Set" width 11. tree.end tree.end tree "Debug Subsystem" tree "DRM Registers" base ad:0x4b160000 width 20. if (((d.l(ad:0x4b160000+0x200))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x200))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x200++0x03 line.long 0x00 "DRM_SUSPEND_CTRL0,Watchdog Timer 1 (WDT1) Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x200++0x03 line.long 0x00 "DRM_SUSPEND_CTRL0,Watchdog Timer 1 (WDT1) Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x204))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x204))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x204++0x03 line.long 0x00 "DRM_SUSPEND_CTRL1,DMTimer0 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x204++0x03 line.long 0x00 "DRM_SUSPEND_CTRL1,DMTimer0 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x208))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x208))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x208++0x03 line.long 0x00 "DRM_SUSPEND_CTRL2,DMTimer1 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x208++0x03 line.long 0x00 "DRM_SUSPEND_CTRL2,DMTimer1 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x20C))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x20C))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x20C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL3,DMTimer2 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x20C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL3,DMTimer2 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x210))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x210))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x210++0x03 line.long 0x00 "DRM_SUSPEND_CTRL4,DMTimer3 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x210++0x03 line.long 0x00 "DRM_SUSPEND_CTRL4,DMTimer3 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x214))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x214))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x214++0x03 line.long 0x00 "DRM_SUSPEND_CTRL5,DMTimer4 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x214++0x03 line.long 0x00 "DRM_SUSPEND_CTRL5,DMTimer4 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x218))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x218))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x218++0x03 line.long 0x00 "DRM_SUSPEND_CTRL6,DMTimer5 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x218++0x03 line.long 0x00 "DRM_SUSPEND_CTRL6,DMTimer5 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x21C))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x21C))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x21C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL7,DMTimer6 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x21C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL7,DMTimer6 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x220))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x220))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x220++0x03 line.long 0x00 "DRM_SUSPEND_CTRL8,EMAC Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x220++0x03 line.long 0x00 "DRM_SUSPEND_CTRL8,EMAC Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x228))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x228))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x228++0x03 line.long 0x00 "DRM_SUSPEND_CTRL10,I2C0 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x228++0x03 line.long 0x00 "DRM_SUSPEND_CTRL10,I2C0 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x22C))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x22C))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x22C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL11,I2C1 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x22C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL11,I2C1 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x230))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x230))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x230++0x03 line.long 0x00 "DRM_SUSPEND_CTRL12,I2C2 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x230++0x03 line.long 0x00 "DRM_SUSPEND_CTRL12,I2C2 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x234))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x234))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x234++0x03 line.long 0x00 "DRM_SUSPEND_CTRL13,EHRPWM0 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x234++0x03 line.long 0x00 "DRM_SUSPEND_CTRL13,EHRPWM0 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x238))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x238))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x238++0x03 line.long 0x00 "DRM_SUSPEND_CTRL14,EHRPWM1 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x238++0x03 line.long 0x00 "DRM_SUSPEND_CTRL14,EHRPWM1 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x23C))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x23C))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x23C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL15,EHRPWM2 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x23C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL15,EHRPWM2 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x240))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x240))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x240++0x03 line.long 0x00 "DRM_SUSPEND_CTRL16,DCAN0 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x240++0x03 line.long 0x00 "DRM_SUSPEND_CTRL16,DCAN0 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x244))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x244))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x244++0x03 line.long 0x00 "DRM_SUSPEND_CTRL17,DCAN1 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x244++0x03 line.long 0x00 "DRM_SUSPEND_CTRL17,DCAN1 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x248))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x248))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x248++0x03 line.long 0x00 "DRM_SUSPEND_CTRL18,PRU-ICSS Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x248++0x03 line.long 0x00 "DRM_SUSPEND_CTRL18,PRU-ICSS Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x24C))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x24C))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x24C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL19,SyncTimer Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x24C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL19,SyncTimer Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x260))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x260))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x260++0x03 line.long 0x00 "DRM_SUSPEND_CTRL24,DMTimer7-11 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x260++0x03 line.long 0x00 "DRM_SUSPEND_CTRL24,DMTimer7-11 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x26C))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x26C))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x26C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL27,PWM3 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x26C++0x03 line.long 0x00 "DRM_SUSPEND_CTRL27,PWM3 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x270))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x270))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x270++0x03 line.long 0x00 "DRM_SUSPEND_CTRL28,PWM4 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x270++0x03 line.long 0x00 "DRM_SUSPEND_CTRL28,PWM4 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif if (((d.l(ad:0x4b160000+0x274))&0x08)==0x00)&&(((d.l(ad:0x4b160000+0x274))&0x01)==0x01) //this.SUSPEND_DEFAULT_OVERRIDE== "Disabled" group.long 0x274++0x03 line.long 0x00 "DRM_SUSPEND_CTRL29,PWM5 Suspend Control" bitfld.long 0x00 4.--8. " SUSPEND_SEL , Suspend signal selection" ",,,,,,,,,,,Cortex-A9 suspend signal,,,,,,,,,,,,,,,,,,,," rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" else group.long 0x274++0x03 line.long 0x00 "DRM_SUSPEND_CTRL29,PWM5 Suspend Control" rbitfld.long 0x00 3. " SUSPEND_DEFAULT_OVERRIDE , Enable or disable the override value in Suspend_Sel" "Enabled,Disabled" bitfld.long 0x00 0. " SENSCTRL , Sensitivity Control for suspend signals" "Normal,Suspended" endif width 11. tree.end tree.end else tree.open "ICSS_0" tree "CFG" base eahb:0x54426000 width 21. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_CFG_REVID,The Revision Register contains the ID and revision information." hexmask.long 0x0 0.--31. 1. " REVID ,Revision ID. Reset value for PRU-ICSS1 is 0x4700_0200 and for PRU-ICSS0 is 0x4701_0100." group.long 0x4++0x3 bitfld.long 0x0 0.--1. " IDLE_MODE ," "0,1,2,3" bitfld.long 0x0 2.--3. " STANDBY_MODE ," "0,1,2,3" bitfld.long 0x0 4. " STANDBY_INIT ," "0,1" textline "" bitfld.long 0x0 5. " SUB_MWAIT ,Status bit for wait state." "0,1" group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_CFG_GPCFG0,The General Purpose Configuration 0 Register defines the GPI/O configuration for PRU0." bitfld.long 0x0 0.--1. " PRU0_GPI_MODE ," "0,1,2,3" bitfld.long 0x0 2. " PRU0_GPI_CLK_MODE ,Parallel 16bit capture mode clock edge." "0,1" textline "" bitfld.long 0x0 13. " PRU0_GPI_SB ,Start Bit event for 28-bit shift mode. PRU0_GPI_SB (pru0_r31_status[29]) is set when first capture of a 1 on pru0_r31_status[0]." "0,1" bitfld.long 0x0 14. " PRU0_GPO_MODE ," "0,1" textline "" bitfld.long 0x0 25. " PRU0_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting." "0,1" textline "" group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_CFG_GPCFG1,The General Purpose Configuration 1 Register defines the GPI/O configuration for PRU1." bitfld.long 0x0 0.--1. " PRU1_GPI_MODE ," "0,1,2,3" bitfld.long 0x0 2. " PRU1_GPI_CLK_MODE ,Parallel 16bit capture mode clock edge." "0,1" textline "" bitfld.long 0x0 13. " PRU1_GPI_SB ,28-bit shift mode Start Bit event. PRU1_GPI_SB (pru1_r31_status[29]) is set when first capture of a 1 on pru1_r31_status[0]." "0,1" bitfld.long 0x0 14. " PRU1_GPO_MODE ," "0,1" textline "" bitfld.long 0x0 25. " PRU1_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting." "0,1" textline "" group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_CFG_CGR,The Clock Gating Register controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x1." bitfld.long 0x0 0. " PRU0_CLK_STOP_REQ ,PRU0 request to stop clock." "0,1" bitfld.long 0x0 1. " PRU0_CLK_STOP_ACK ,Acknowledgement that PRU0 clock can be stopped." "0,1" bitfld.long 0x0 2. " PRU0_CLK_EN ,PRU0 clock enable." "0,1" textline "" bitfld.long 0x0 3. " PRU1_CLK_STOP_REQ ,PRU1 request to stop clock." "0,1" bitfld.long 0x0 4. " PRU1_CLK_STOP_ACK ,Acknowledgement that PRU1 clock can be stopped." "0,1" bitfld.long 0x0 5. " PRU1_CLK_EN ,PRU1 clock enable." "0,1" textline "" bitfld.long 0x0 6. " INTC_CLK_STOP_REQ ,INTC request to stop clock." "0,1" bitfld.long 0x0 7. " INTC_CLK_STOP_ACK ,Acknowledgement that INTC clock can be stopped." "0,1" bitfld.long 0x0 8. " INTC_CLK_EN ,INTC clock enable." "0,1" textline "" bitfld.long 0x0 9. " UART_CLK_STOP_REQ ,UART request to stop clock." "0,1" bitfld.long 0x0 10. " UART_CLK_STOP_ACK ,Acknowledgement that UART clock can be stopped." "0,1" bitfld.long 0x0 11. " UART_CLK_EN ,UART clock enable." "0,1" textline "" bitfld.long 0x0 12. " ECAP_CLK_STOP_REQ ,ECAP request to stop clock." "0,1" bitfld.long 0x0 13. " ECAP_CLK_STOP_ACK ,Acknowledgement that ECAP clock can be stopped." "0,1" bitfld.long 0x0 14. " ECAP_CLK_EN ,ECAP clock enable." "0,1" textline "" bitfld.long 0x0 15. " IEP_CLK_STOP_REQ ,IEP request to stop clock." "0,1" bitfld.long 0x0 16. " IEP_CLK_STOP_ACK ,Acknowledgement that IEP clock can be stopped." "0,1" bitfld.long 0x0 17. " IEP_CLK_EN ,IEP clock enable." "0,1" textline "" group.long 0x14++0x3 line.long 0x0 "PRU_ICSS_CFG_ISRP,The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRU ICSS memory parity events. The raw status is set even if the event is not enabled." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_RAW ,PRU0 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_IRAM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_RAW ,PRU0 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_RAW ,PRU1 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_RAW ,PRU1 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " RAM_PE_RAW ,PRU-ICSS1 Only. RAM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x0 "PRU_ICSS_CFG_ISP,The IRQ Status Parity Register is a snapshot of the IRQ status for the PRU ICSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE ,PRU0 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE ,PRU0 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " PRU1_IMEM_PE ,PRU1 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE ,PRU1 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " RAM_PE ,PRU-ICSS1 Only. RAM Parity Error for Byte3, Byte2, Byte1, Byte0. Note RAM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x0 "PRU_ICSS_CFG_IESP,The IRQ Enable Set Parity Register enables the IRQ PRU ICSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_SET ,PRU0 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_SET ,PRU0 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_SET ,PRU1 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_SET ,PRU1 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " RAM_PE_SET ,PRU-ICSS1 Only. RAM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_CFG_IECP,The IRQ Enable Clear Parity Register disables the IRQ PRU ICSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_CLR ,PRU0 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_CLR[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_CLR ,PRU0 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_CLR[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_CLR ,PRU1 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_CLR[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_CLR ,PRU1 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_CLR[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_CFG_PMAO,The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x0000_0000." bitfld.long 0x0 0. " PMAO_PRU0 ,PRU0 OCP Master Port Address Offset Enable." "0,1" bitfld.long 0x0 1. " PMAO_PRU1 ,PRU1 OCP Master Port Address Offset Enable." "0,1" group.long 0x30++0x3 line.long 0x0 "PRU_ICSS_CFG_IEPCLK,The IEP Clock Source Register defines the source of the IEP clock." bitfld.long 0x0 0. " OCP_EN ," "0,1" group.long 0x34++0x3 line.long 0x0 "PRU_ICSS_CFG_SPP,The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores and configures the scratch pad XFR shift functionality." bitfld.long 0x0 0. " PRU1_PAD_HP_EN ,Defines which PRU wins write cycle arbitration to a common scratch pad bank." "0,1" bitfld.long 0x0 1. " XFR_SHIFT_EN ,Enables XIN/XOUT shift functionality. When enabled, R0 [4:0] (internal to PRU) defines the 32-bit offset for XIN and XOUT operations with the scratch pad." "0,1" group.long 0x40++0x3 line.long 0x0 "PRU_ICSS_CFG_PIN_MX,The Pin Mux Select Register defines the state of the PRU ICSS internal pinmuxing." hexmask.long.byte 0x0 0.--7. 1. " PIN_MUX_SEL ,Defines the state of PIN_MUX_SEL [1:0] for internal pinmuxing." width 0xB tree.end tree "PRU0_CTRL" base eahb:0x54422000 width 25. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_CTRL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " EN ,Processor Enable" "0,1" bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1" textline "" bitfld.long 0x0 3. " CTR_EN ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable" "0,1" textline "" bitfld.long 0x0 15. " RUNSTATE ,Run State" "0,1" textline "" hexmask.long.word 0x0 16.--31. 1. " PCTR_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_CTRL_STS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCTR ,Program Counter" group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_CTRL_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENS ,Wakeup Enables" group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_CTRL_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits EN and CTR_EN set in the PRU control register)." group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_CTRL_STALL,STALL COUNT" hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits EN and CTR_EN set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0" hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_IDX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_IDX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 25 in the PRU Constant Table." textline "" group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1" hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_IDX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_IDX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 27 in the PRU Constant Table." textline "" group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0" hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 29 in the PRU Constant Table." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1" hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 31 in the PRU Constant Table." width 0xB tree.end tree "PRU1_CTRL" base eahb:0x54424000 width 25. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_CTRL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " EN ,Processor Enable" "0,1" bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1" textline "" bitfld.long 0x0 3. " CTR_EN ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable" "0,1" textline "" bitfld.long 0x0 15. " RUNSTATE ,Run State" "0,1" textline "" hexmask.long.word 0x0 16.--31. 1. " PCTR_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_CTRL_STS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCTR ,Program Counter" group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_CTRL_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENS ,Wakeup Enables" group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_CTRL_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits EN and CTR_EN set in the PRU control register)." group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_CTRL_STALL,STALL COUNT" hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits EN and CTR_EN set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0" hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_IDX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_IDX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 25 in the PRU Constant Table." textline "" group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1" hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_IDX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_IDX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 27 in the PRU Constant Table." textline "" group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0" hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 29 in the PRU Constant Table." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1" hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 31 in the PRU Constant Table." width 0xB tree.end tree "INTC" base eahb:0x54420000 width 22. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_INTC_REVID,Revision ID Register" bitfld.long 0x0 0.--5. " REV_MINOR ,MINOR REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " REV_CUSTOM ,CUSTOM REVISION" "0,1,2,3" bitfld.long 0x0 8.--10. " REV_MAJOR ,MAJOR REVISION" "0,1,2,3,4,5,6,7" textline "" bitfld.long 0x0 11.--15. " REV_RTL ,RTL REVISIONS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--27. 1. " REV_MODULE ,MODULE ID" textline "" bitfld.long 0x0 30.--31. " REV_SCHEME ,SCHEME" "0,1,2,3" group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_INTC_CR,The Control Register holds global control parameters and can forces a soft reset on the module." bitfld.long 0x0 2.--3. " NEST_MODE ,The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting" "0,1,2,3" textline "" group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_INTC_GER,The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable." bitfld.long 0x0 0. " EN_HINT_ANY ,The current global enable value when read. Writes set the global enable." "0,1" group.long 0x1C++0x3 line.long 0x0 "PRU_ICSS_INTC_GNLR,Global Nesting Level Register" hexmask.long.word 0x0 0.--8. 1. " GLB_NEST_LEVEL ,The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data." "0,1" group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_INTC_SISR,The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STS_SET_IDX ,Writes set the status of the interrupt given in the index value. Reads return 0." group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_INTC_SICR,The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STS_CLR_IDX ,Writes clear the status of the interrupt given in the index value. Reads return 0." group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_INTC_EISR,The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " EN_SET_IDX ,Writes set the enable of the interrupt given in the index value. Reads return 0." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_INTC_EICR,The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " EN_CLR_IDX ,Writes clear the enable of the interrupt given in the index value. Reads return 0." group.long 0x34++0x3 line.long 0x0 "PRU_ICSS_INTC_HIEISR,The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled." hexmask.long.word 0x0 0.--9. 1. " HINT_EN_SET_IDX ,Writes set the enable of the host interrupt given in the index value. Reads return 0." group.long 0x38++0x3 line.long 0x0 "PRU_ICSS_INTC_HIDISR,The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output." hexmask.long.word 0x0 0.--9. 1. " HINT_EN_CLR_IDX ,Writes clear the enable of the host interrupt given in the index value. Reads return 0." group.long 0x80++0x3 line.long 0x0 "PRU_ICSS_INTC_GPIR,The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts." hexmask.long.word 0x0 0.--9. 1. " GLB_PRI_INTR ,The currently highest priority interrupt index pending across all the host interrupts." bitfld.long 0x0 31. " GLB_NONE ,No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending." "0,1" group.long 0x200++0x3 line.long 0x0 "PRU_ICSS_INTC_SRSR0,System Interrupt Status Raw/Set Register0" hexmask.long 0x0 0.--31. 1. " RAW_STS_31_0 ,System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.long 0x204++0x3 line.long 0x0 "PRU_ICSS_INTC_SRSR1,System Interrupt Status Raw/Set Register1" hexmask.long 0x0 0.--31. 1. " RAW_STS_63_32 ,System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.long 0x280++0x3 line.long 0x0 "PRU_ICSS_INTC_SECR0,System Interrupt Status Enabled/Clear Register0" hexmask.long 0x0 0.--31. 1. " ENA_STS_31_0 ,System interrupt enabled status and clearing of the system interrupts 0 to 31" group.long 0x284++0x3 line.long 0x0 "PRU_ICSS_INTC_SECR1,System Interrupt Status Enabled/Clear Register1" hexmask.long 0x0 0.--31. 1. " ENA_STS_63_32 ,System interrupt enabled status and clearing of the system interrupts 32 to 63" group.long 0x300++0x3 line.long 0x0 "PRU_ICSS_INTC_ESR0,The System Interrupt Enable Set Register0 enables system interrupts 0 to 31 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " EN_SET_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.long 0x304++0x3 line.long 0x0 "PRU_ICSS_INTC_ESR1,The System Interrupt Enable Set Register1 enables system interrupts 32 to 63 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " EN_SET_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.long 0x380++0x3 line.long 0x0 "PRU_ICSS_INTC_ECR0,The System Interrupt Enable Clear Register0 disables system interrupts 0 to 31 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " EN_CLR_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.long 0x384++0x3 line.long 0x0 "PRU_ICSS_INTC_ECR1,The System Interrupt Enable Clear Register1 disables system interrupts 32 to 63 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " EN_CLR_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.long 0x400++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR0,The Channel Map Register0 specify the channel for the system interrupts 0 to 3. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x404++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR1,The Channel Map Register1 specify the channel for the system interrupts 4 to 7. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_4 ,Sets the channel for the system interrupt 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_5 ,Sets the channel for the system interrupt 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_6 ,Sets the channel for the system interrupt 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_7 ,Sets the channel for the system interrupt 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x408++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR2,The Channel Map Register2 specify the channel for the system interrupts 8 to 11. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_8 ,Sets the channel for the system interrupt 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_9 ,Sets the channel for the system interrupt 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_10 ,Sets the channel for the system interrupt 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_11 ,Sets the channel for the system interrupt 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40C++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR3,The Channel Map Register3 specify the channel for the system interrupts 12 to 15. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_12 ,Sets the channel for the system interrupt 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_13 ,Sets the channel for the system interrupt 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_14 ,Sets the channel for the system interrupt 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_15 ,Sets the channel for the system interrupt 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x410++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR4,The Channel Map Register4 specify the channel for the system interrupts 16 to 19. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_16 ,Sets the channel for the system interrupt 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_17 ,Sets the channel for the system interrupt 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_18 ,Sets the channel for the system interrupt 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_19 ,Sets the channel for the system interrupt 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x414++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR5,The Channel Map Register5 specify the channel for the system interrupts 20 to 23. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_20 ,Sets the channel for the system interrupt 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_21 ,Sets the channel for the system interrupt 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_22 ,Sets the channel for the system interrupt 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_23 ,Sets the channel for the system interrupt 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x418++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR6,The Channel Map Register6 specify the channel for the system interrupts 24 to 27. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_24 ,Sets the channel for the system interrupt 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_25 ,Sets the channel for the system interrupt 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_26 ,Sets the channel for the system interrupt 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_27 ,Sets the channel for the system interrupt 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x41C++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR7,The Channel Map Register7 specify the channel for the system interrupts 28 to 31. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_28 ,Sets the channel for the system interrupt 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_29 ,Sets the channel for the system interrupt 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_30 ,Sets the channel for the system interrupt 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_31 ,Sets the channel for the system interrupt 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x420++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR8,The Channel Map Register8 specify the channel for the system interrupts 32 to 35. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_32 ,Sets the channel for the system interrupt 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_33 ,Sets the channel for the system interrupt 33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_34 ,Sets the channel for the system interrupt 34" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_35 ,Sets the channel for the system interrupt 35" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x424++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR9,The Channel Map Register9 specify the channel for the system interrupts 36 to 39. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_36 ,Sets the channel for the system interrupt 36" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_37 ,Sets the channel for the system interrupt 37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_38 ,Sets the channel for the system interrupt 38" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_39 ,Sets the channel for the system interrupt 39" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x428++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR10,The Channel Map Register10 specify the channel for the system interrupts 40 to 43. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_40 ,Sets the channel for the system interrupt 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_41 ,Sets the channel for the system interrupt 41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_42 ,Sets the channel for the system interrupt 42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_43 ,Sets the channel for the system interrupt 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x42C++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR11,The Channel Map Register11 specify the channel for the system interrupts 44 to 47. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_44 ,Sets the channel for the system interrupt 44" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_45 ,Sets the channel for the system interrupt 45" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_46 ,Sets the channel for the system interrupt 46" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_47 ,Sets the channel for the system interrupt 47" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x430++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR12,The Channel Map Register12 specify the channel for the system interrupts 48 to 51. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_48 ,Sets the channel for the system interrupt 48" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_49 ,Sets the channel for the system interrupt 49" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_50 ,Sets the channel for the system interrupt 50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_51 ,Sets the channel for the system interrupt 51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x434++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR13,The Channel Map Register13 specify the channel for the system interrupts 52 to 55. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_52 ,Sets the channel for the system interrupt 52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_53 ,Sets the channel for the system interrupt 53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_54 ,Sets the channel for the system interrupt 54" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_55 ,Sets the channel for the system interrupt 55" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x438++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR14,The Channel Map Register14 specify the channel for the system interrupts 56 to 59. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_56 ,Sets the channel for the system interrupt 56" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_57 ,Sets the channel for the system interrupt 57" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_58 ,Sets the channel for the system interrupt 58" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_59 ,Sets the channel for the system interrupt 59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x43C++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR15,The Channel Map Register15 specify the channel for the system interrupts 60 to 63. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_60 ,Sets the channel for the system interrupt 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_61 ,Sets the channel for the system interrupt 61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_62 ,Sets the channel for the system interrupt 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_63 ,Sets the channel for the system interrupt 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x0 "PRU_ICSS_INTC_HMR0,The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_0 ,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " HINT_MAP_1 ,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " HINT_MAP_2 ,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " HINT_MAP_3 ,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x804++0x3 line.long 0x0 "PRU_ICSS_INTC_HMR1,The Host Interrupt Map Register1 define the host interrupt for channels 4 to 7. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_4 ,HOST INTERRUPT MAP FOR CHANNEL 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " HINT_MAP_5 ,HOST INTERRUPT MAP FOR CHANNEL 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " HINT_MAP_6 ,HOST INTERRUPT MAP FOR CHANNEL 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " HINT_MAP_7 ,HOST INTERRUPT MAP FOR CHANNEL 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x808++0x3 line.long 0x0 "PRU_ICSS_INTC_HMR2,The Host Interrupt Map Register2 define the host interrupt for channels 8 to 9. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_8 ,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " HINT_MAP_9 ,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" group.long 0x900++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR0,The Host Interrupt Prioritized Index Register0 shows the highest priority current pending interrupt for the host interrupt 0. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_0 ,HOST INT 0 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_0 ,No pending interrupt." "0,1" group.long 0x904++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR1,The Host Interrupt Prioritized Index Register1 shows the highest priority current pending interrupt for the host interrupt 1. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_1 ,HOST INT 1 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_1 ,No pending interrupt." "0,1" group.long 0x908++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR2,The Host Interrupt Prioritized Index Register2 shows the highest priority current pending interrupt for the host interrupt 2. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_2 ,HOST INT 2 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_2 ,No pending interrupt." "0,1" group.long 0x90C++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR3,The Host Interrupt Prioritized Index Register3 shows the highest priority current pending interrupt for the host interrupt 3. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_3 ,HOST INT 3 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_3 ,No pending interrupt." "0,1" group.long 0x910++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR4,The Host Interrupt Prioritized Index Register4 shows the highest priority current pending interrupt for the host interrupt 4. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_4 ,HOST INT 4 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_4 ,No pending interrupt." "0,1" group.long 0x914++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR5,The Host Interrupt Prioritized Index Register5 shows the highest priority current pending interrupt for the host interrupt 5. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_5 ,HOST INT 5 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_5 ,No pending interrupt." "0,1" group.long 0x918++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR6,The Host Interrupt Prioritized Index Register6 shows the highest priority current pending interrupt for the host interrupt 6. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_6 ,HOST INT 6 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_6 ,No pending interrupt." "0,1" group.long 0x91C++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR7,The Host Interrupt Prioritized Index Register7 shows the highest priority current pending interrupt for the host interrupt 7. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_7 ,HOST INT 7 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_7 ,No pending interrupt." "0,1" group.long 0x920++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR8,The Host Interrupt Prioritized Index Register8 shows the highest priority current pending interrupt for the host interrupt 8. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_8 ,HOST INT 8 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_8 ,No pending interrupt." "0,1" group.long 0x924++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR9,The Host Interrupt Prioritized Index Register9 shows the highest priority current pending interrupt for the host interrupt 9. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_9 ,HOST INT 9 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_9 ,No pending interrupt." "0,1" group.long 0xD00++0x3 line.long 0x0 "PRU_ICSS_INTC_SIPR0,System Interrupt Polarity Register0" hexmask.long 0x0 0.--31. 1. " POLARITY_31_0 ,Interrupt polarity of the system interrupts 0 to 31. 0 = active low. 1 = active high." group.long 0xD04++0x3 line.long 0x0 "PRU_ICSS_INTC_SIPR1,System Interrupt Polarity Register1" hexmask.long 0x0 0.--31. 1. " POLARITY_63_32 ,Interrupt polarity of the system interrupts 32 to 63. 0 = active low. 1 = active high." group.long 0xD80++0x3 line.long 0x0 "PRU_ICSS_INTC_SITR0,The System Interrupt Type Register0 define the type of the system interrupts 0 to 31. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_31_0 ,Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.long 0xD84++0x3 line.long 0x0 "PRU_ICSS_INTC_SITR1,The System Interrupt Type Register1 define the type of the system interrupts 32 to 63. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_63_32 ,Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.long 0x1100++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR0,The Host Interrupt Nesting Level Register0 display and control the nesting level for host interrupt 0. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_0 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1104++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR1,The Host Interrupt Nesting Level Register1 display and control the nesting level for host interrupt 1. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_1 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1108++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR2,The Host Interrupt Nesting Level Register2 display and control the nesting level for host interrupt 2. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_2 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x110C++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR3,The Host Interrupt Nesting Level Register3 display and control the nesting level for host interrupt 3. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_3 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1110++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR4,The Host Interrupt Nesting Level Register4 display and control the nesting level for host interrupt 4. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_4 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1114++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR5,The Host Interrupt Nesting Level Register5 display and control the nesting level for host interrupt 5. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_5 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1118++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR6,The Host Interrupt Nesting Level Register6 display and control the nesting level for host interrupt 6. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_6 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x111C++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR7,The Host Interrupt Nesting Level Register7 display and control the nesting level for host interrupt 7. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_7 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1120++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR8,The Host Interrupt Nesting Level Register8 display and control the nesting level for host interrupt 8. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_8 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1124++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR9,The Host Interrupt Nesting Level Register9 display and control the nesting level for host interrupt 9. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_9 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1500++0x3 line.long 0x0 "PRU_ICSS_INTC_HIER,Host Interrupt Enable Registers" hexmask.long.word 0x0 0.--9. 1. " EN_HINT ,The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled" width 0xB tree.end tree "MII_RT" base eahb:0x54432000 width 9. group.long 0x0++0x3 line.long 0x0 "RXCFG0,RX CONFIG0" bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble" "0,1" textline "" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for RXCFG0) 0x1: MII RX Data from Port 1 (default for RXCFG1)" "0,1" bitfld.long 0x0 4. " RX_L2_ENABLE ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2" "0,1" textline "" bitfld.long 0x0 6. " RX_AUTOFWD_PRE ,Enables auto-forward of received preamble" "0,1" group.long 0x4++0x3 line.long 0x0 "RXCFG1,RX CONFIG1" bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble" "0,1" textline "" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for RXCFG0) 0x1: MII RX Data from Port 1 (default for RXCFG1)" "0,1" bitfld.long 0x0 4. " RX_L2_ENABLE ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2" "0,1" textline "" bitfld.long 0x0 6. " RX_AUTOFWD_PRE ,Enables auto-forward of received preamble" "0,1" group.long 0x10++0x3 line.long 0x0 "TXCFG0,TX CONFIG0" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble." "0,1" bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event" "0,1" textline "" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30" "0,1" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source" "0,1" textline "" bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence" "0,1" hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface" textline "" bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the ocp_clk must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" group.long 0x14++0x3 line.long 0x0 "TXCFG1,TX CONFIG1" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble" "0,1" bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event" "0,1" textline "" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30" "0,1" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source" "0,1" textline "" bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequenc" "0,1" hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface" textline "" bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the ocp_clk must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x0 "TXCRC0,TX CYCLIC REDUNDANCY CHECK0" hexmask.long 0x0 0.--31. 1. " TX_CRC32 ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.long 0x24++0x3 line.long 0x0 "TXCRC1,TX CYCLIC REDUNDANCY CHECK1" hexmask.long 0x0 0.--31. 1. " TX_CRC32 ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.long 0x30++0x3 line.long 0x0 "TXIPG0,TX INTERPACKET GAP0" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG)" group.long 0x34++0x3 line.long 0x0 "TXIPG1,TX INTERPACKET GAP1" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG)" group.long 0x38++0x3 line.long 0x0 "PRS0,PORT RAW STATUS0" bitfld.long 0x0 0. " pr1_mii0_col ,Current state of pr#lt#k#gt#_mii0_col" "0,1" bitfld.long 0x0 1. " pr1_mii0_crs ,Current state of pr#lt#k#gt#_mii0_crs" "0,1" group.long 0x3C++0x3 line.long 0x0 "PRS1,PORT RAW STATUS1" bitfld.long 0x0 0. " pr1_mii1_col ,Current state of pr#lt#k#gt#_mii1_col" "0,1" bitfld.long 0x0 1. " pr1_mii1_crs ,Current state of pr#lt#k#gt#_mii1_crs" "0,1" group.long 0x40++0x3 line.long 0x0 "RXFRMS0,RX FRAME SIZE0" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM_CNT ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0: 1 byte after SFD and including CRC. N: N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM_CNT ,Defines the maximum received frame count." group.long 0x44++0x3 line.long 0x0 "RXFRMS1,RX FRAME SIZE1" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM_CNT ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0: 1 byte after SFD and including CRC. N: N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM_CNT ,Defines the maximum received frame count." group.long 0x48++0x3 line.long 0x0 "RXPCNT0,RX PREAMABLE COUNT0" bitfld.long 0x0 0.--3. " RX_MIN_PRE_CNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0x5D." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C++0x3 line.long 0x0 "RXPCNT1,RX PREAMABLE COUNT1" bitfld.long 0x0 0.--3. " RX_MIN_PRE_CNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0x5D." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x3 line.long 0x0 "RXERR0,RX ERROR0" bitfld.long 0x0 0. " RX_MIN_PRE_CNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PRE_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" bitfld.long 0x0 1. " RX_MAX_PRE_CNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PRE_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" bitfld.long 0x0 2. " RX_MIN_FRM_CNT_ERR ,Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" textline "" bitfld.long 0x0 3. " RX_MAX_FRM_CNT_ERR ,Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" group.long 0x54++0x3 line.long 0x0 "RXERR1,RX ERROR1" bitfld.long 0x0 0. " RX_MIN_PRE_CNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PRE_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" bitfld.long 0x0 1. " RX_MAX_PRE_CNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PRE_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" bitfld.long 0x0 2. " RX_MIN_FRM_CNT_ERR ,Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" textline "" bitfld.long 0x0 3. " RX_MAX_FRM_CNT_ERR ,Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" group.long 0x60++0x3 line.long 0x0 "RXFLV0,RX FIFO0 Level" hexmask.long.byte 0x0 0.--7. 1. " RX_FIFO_LEVEL ,Define the number of valid bytes in the RX FIFO 0 = empty 1 = 1 Byte/ 2 Nibbles 2 = 2 Byte/ 4 Nibble ... 32 = 32 Bytes/ 64 Nibbles" group.long 0x64++0x3 line.long 0x0 "RXFLV1,RX FIFO1 Level" hexmask.long.byte 0x0 0.--7. 1. " RX_FIFO_LEVEL ,Define the number of valid bytes in the RX FIFO 0 = empty 1 = 1 Byte/ 2 Nibbles 2 = 2 Byte/ 4 Nibble ... 32 = 32 Bytes/ 64 Nibbles" group.long 0x68++0x3 line.long 0x0 "TXFLV0,TX FIFO0 Level" hexmask.long.byte 0x0 0.--7. 1. " TX_FIFO_LEVEL ,Define the number of valid nibbles in the TX FIFO 0 = empty 1 = 1 Nibble 2 = 1 Byte/ 2 Nibble ... 128 = 64 Bytes/ 128 Nibbles" group.long 0x6C++0x3 line.long 0x0 "TXFLV1,TX FIFO1 Level" hexmask.long.byte 0x0 0.--7. 1. " TX_FIFO_LEVEL ,Define the number of valid nibbles in the TX FIFO 0 = empty 1 = 1 Nibble 2 = 1 Byte/ 2 Nibble ... 128 = 64 Bytes/ 128 Nibbles" width 0xB tree.end tree "MII_MDIO" base eahb:0x54432400 width 21. group.long 0x0++0x3 line.long 0x0 "MDIO_VER," hexmask.long.byte 0x0 0.--7. 1. " REVMIN ,Management interface module minor revision value." hexmask.long.byte 0x0 8.--15. 1. " REVMAJ ,Management interface module major revision value." hexmask.long.word 0x0 16.--31. 1. " MODID ,Identifies type of peripheral." group.long 0x4++0x3 line.long 0x0 "MDIO_CTRL," hexmask.long.word 0x0 0.--15. 1. " CLKDIV ,Clock divider. [[br]]This field specifies the division ratio between CLK and the frequency of MDIO_CLK. [[br]]MDIO_CLK is disabled when clkdiv is set to 0. [[br]]MDIO_CLK frequency = clk frequency/(clkdiv+1)." bitfld.long 0x0 17. " INTTESTENB ,Interrupt test enable. [[br]]This bit can be set to 1 to enable the host to set the USERINT and LINKINT bits for test purposes." "0,1" textline "" bitfld.long 0x0 18. " FAULTENB ,Fault detect enable. [[br]]This bit has to be set to 1 to enable the physical layer fault detection." "0,1" bitfld.long 0x0 19. " FAULT ,Fault indicator. [[br]]This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them. [[br]]This indicates a physical layer fault and the module state machine is reset. [[br]]Writing a 1 to it clears this bit." "0,1" bitfld.long 0x0 20. " PREAMBLE ,Preamble disable." "0,1" textline "" bitfld.long 0x0 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline "" bitfld.long 0x0 30. " EN ,Enable control" "0,1" bitfld.long 0x0 31. " IDLE ,MDIO state machine IDLE. [[br]]Set to 1 when the state machine is in the idle state." "0,1" group.long 0x8++0x3 line.long 0x0 "MDIO_ALIVE," hexmask.long 0x0 0.--31. 1. " ALIVE ,MDIO alive" group.long 0xC++0x3 line.long 0x0 "MDIO_LINK," hexmask.long 0x0 0.--31. 1. " LINK ,MDIO link state" group.long 0x10++0x3 line.long 0x0 "MDIO_LINKINTRAW," bitfld.long 0x0 0.--1. " LINKINTRAW ,MDIO link change event, raw value" "0,1,2,3" group.long 0x14++0x3 line.long 0x0 "MDIO_LINKINTMASKED," bitfld.long 0x0 0.--1. " LINKINTMASKED ,MDIO link change interrupt, masked value" "0,1,2,3" group.long 0x20++0x3 line.long 0x0 "MDIO_USERINTRAW," bitfld.long 0x0 0.--1. " USERINTRAW ,Raw value of MDIO user command complete event for the MDIOUSERACCESS1 register through the MDIOUSERACCESS0 register, respectively" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "MDIO_USERINTMASKED," bitfld.long 0x0 0.--1. " USERINTMASKED ,Masked value of MDIO user command complete interrupt for the MDIOUSERACCESS1 register through the MDIOUSERACCESS0 register, respectively" "0,1,2,3" group.long 0x28++0x3 line.long 0x0 "MDIO_USERINTMASKSET," bitfld.long 0x0 0.--1. " USERINTMASKSET ,MDIO user interrupt mask set for USERINTMASKED, respectively" "0,1,2,3" group.long 0x2C++0x3 line.long 0x0 "MDIO_USERINTMASKCLR," bitfld.long 0x0 0.--1. " USERINTMASKCLR ,MDIO user command complete interrupt mask clear for USERINTMASKED, respectively" "0,1,2,3" group.long 0x80++0x3 line.long 0x0 "MDIO_USERACCESS0," hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. [[br]]The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. [[br]]Specifies the PHY to be accesses for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " REGADR ,Register address. [[br]]Specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline "" bitfld.long 0x0 29. " ACK ,Acknowledge. [[br]]This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. [[br]]Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline "" bitfld.long 0x0 31. " GO ,Causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process" "0,1" group.long 0x84++0x3 line.long 0x0 "MDIO_USERPHYSEL0," bitfld.long 0x0 0.--4. " PHYADDRMON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable. [[br]]Set to 1 to enable link change status interrupts for PHY address specified in PHYADDRMON. [[br]]Link change interrupts are disabled if this bit is set to 0." "0,1" textline "" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. [[br]]Set to 1 to determine link status using the MLINK pin. [[br]]Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" group.long 0x88++0x3 line.long 0x0 "MDIO_USERACCESS1," hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. [[br]]The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address[[br]] specifies the PHY to be accesses for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " REGADR ,Register address[[br]] specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline "" bitfld.long 0x0 29. " ACK ,Acknowledge. [[br]]This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. [[br]]Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline "" bitfld.long 0x0 31. " GO ,Causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process" "0,1" group.long 0x8C++0x3 line.long 0x0 "MDIO_USERPHYSEL1," bitfld.long 0x0 0.--4. " PHYADDRMON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable. [[br]]Set to 1 to enable link change status interrupts for PHY address specified in PHYADDRMON. [[br]]Link change interrupts are disabled if this bit is cleared to 0." "0,1" textline "" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. [[br]]Set to 1 to determine link status using the MLINK pin. [[br]]Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" width 0xB tree.end tree "IEP" base eahb:0x5442e000 width 32. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_GLB_CFG,GLOBAL CONFIGURE" bitfld.long 0x0 0. " CNT_ENABLE ,Counter enable" "0,1" bitfld.long 0x0 4.--7. " DEFAULT_INC ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" hexmask.long.word 0x0 8.--19. 1. " CMP_INC ,Defines the increment value when compensation is active" group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_GLB_STS,GLOBAL STATUS" bitfld.long 0x0 0. " CNT_OVF ,Counter overflow status." "0,1" group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_COMPEN,COMPENSATION" hexmask.long.tbyte 0x0 0.--23. 1. " COMPEN_CNT ,Compensation counter." group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CNT,COUNTER" hexmask.long 0x0 0.--31. 1. " COUNT ,32-bit count value. Increments by (DEFAULT_INC or CMP_INC) on every positive edge of iep_clk (200MHz)." group.long 0x40++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP_CFG,COMPARE CONFIGURE" bitfld.long 0x0 0. " CMP0_RST_CNT_EN ,Counter reset enable." "0,1" hexmask.long.byte 0x0 1.--8. 1. " CMP_EN ,Compare registers enable, where CMP_EN[0] maps to CMP[0]." group.long 0x44++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP_STS,COMPARE STATUS" hexmask.long.byte 0x0 0.--7. 1. " CMP_HIT ,Status bit for each of the compare registers, where CMP_HIT[n] maps to CMP[n]" group.long 0x48++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP0,COMPARE0" hexmask.long 0x0 0.--31. 1. " CMP0 ,Compare 0 value" group.long 0x4C++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP1,COMPARE1" hexmask.long 0x0 0.--31. 1. " CMP1 ,Compare 1 value" group.long 0x50++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP2,COMPARE2" hexmask.long 0x0 0.--31. 1. " CMP2 ,Compare 2 value" group.long 0x54++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP3,COMPARE3" hexmask.long 0x0 0.--31. 1. " CMP3 ,Compare 3 value" group.long 0x58++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP4,COMPARE4" hexmask.long 0x0 0.--31. 1. " CMP4 ,Compare 4 value" group.long 0x5C++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP5,COMPARE5" hexmask.long 0x0 0.--31. 1. " CMP5 ,Compare 5 value" group.long 0x60++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP6,COMPARE6" hexmask.long 0x0 0.--31. 1. " CMP6 ,Compare 6 value" group.long 0x64++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP7,COMPARE7" hexmask.long 0x0 0.--31. 1. " CMP7 ,Compare 7 value" group.long 0x88++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP8,COMPARE8" hexmask.long 0x0 0.--31. 1. " CMP8 ,Compare 8 value" group.long 0x8C++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP9,COMPARE9" hexmask.long 0x0 0.--31. 1. " CMP9 ,Compare 9 value" group.long 0x90++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP10,COMPARE10" hexmask.long 0x0 0.--31. 1. " CMP10 ,Compare 10 value" group.long 0x94++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP11,COMPARE11" hexmask.long 0x0 0.--31. 1. " CMP11 ,Compare 11 value" group.long 0x98++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP12,COMPARE12" hexmask.long 0x0 0.--31. 1. " CMP12 ,Compare 12 value" group.long 0x9C++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP13,COMPARE13" hexmask.long 0x0 0.--31. 1. " CMP13 ,Compare 13 value" group.long 0xA0++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP14,COMPARE14" hexmask.long 0x0 0.--31. 1. " CMP14 ,Compare 14 value" group.long 0xA4++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP15,COMPARE15" hexmask.long 0x0 0.--31. 1. " CMP15 ,Compare 15 value" group.long 0xA8++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CNT_RST,COUNT RESET" hexmask.long 0x0 0.--31. 1. " RESET_VAL ,This enables SW to define the reset state of the Master counter when it gets reset" group.long 0xAC++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_PWM,PWM" bitfld.long 0x0 0. " PWM0_RST_CNT_EN ,Enable the reset of the counter by a pwm0_sync_out event." "0,1" bitfld.long 0x0 1. " PWM0_HIT ,Raw Status bit of pwm0_sync_out event." "0,1" bitfld.long 0x0 2. " PWM3_RST_CNT_EN ,Enable the reset of the counter by a pwm3_sync_out event." "0,1" textline "" bitfld.long 0x0 3. " PWM3_HIT ,Raw Status bit of pwm3_sync_out event." "0,1" group.long 0x300++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_CTRL,DIGITAL INPUT OUTPUT CONTROL" bitfld.long 0x0 4. " IN_MODE ,Enable pr1_edio_data_in [31:0] to be sampled by external pr1_edio_latch_in signal." "0,1" group.long 0x308++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_DATA_IN,DIGITAL DATA INPUT" hexmask.long 0x0 0.--31. 1. " DATA_IN ,Data input. Sample time of digital inputs is controlled externally by using the pr1_edio_latch_in signal. Must enable by setting DIGIO_CTRL[IN_MODE]." group.long 0x30C++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_DATA_IN_RAW,DIGITAL DATA INPUT DIRECT SAMPLE" hexmask.long 0x0 0.--31. 1. " DATA_IN_RAW ,Raw data input. Direct sample of pr1_edio_data_in[31:0]." group.long 0x310++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_DATA_OUT,DIGITAL DATA OUTPUT" hexmask.long 0x0 0.--31. 1. " DATA_OUT ,Data output, pr1_edio_data_out[31:0]." group.long 0x314++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_DATA_OUT_EN,DIGITAL DATA OUT ENABLE" hexmask.long 0x0 0.--31. 1. " DATA_OUT_EN ,Enables tri-state control for pr1_edio_data_out[31:0]." group.long 0x318++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_EXP,DIGIO EXPIRATION CONFIGURE" bitfld.long 0x0 0. " SW_DATA_OUT_UPDATE ,Enable DIGIO_DATA_OUT to be driven out on pr1_edio_data_out. Only valid if OUTVALID_OVR_EN = 1." "0,1" bitfld.long 0x0 1. " OUTVALID_OVR_EN ,Enable software to control value of pr1_edio_data_out [31:0]." "0,1" width 0xB tree.end tree "PRU0_DEBUG" base eahb:0x54422400 width 23. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0" hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1" hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2" hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3" hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4" hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x14++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5" hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x18++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6" hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x1C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7" hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8" hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9" hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10" hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11" hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x30++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12" hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x34++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13" hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x38++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14" hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x3C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15" hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x40++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16" hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x44++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17" hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x48++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18" hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19" hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x50++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20" hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x54++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21" hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x58++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22" hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x5C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23" hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x60++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24" hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x64++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25" hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x68++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26" hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x6C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27" hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x70++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28" hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x74++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29" hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x78++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30" hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x7C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31" hexmask.long 0x0 0.--31. 1. " GPREG31 ," group.long 0x80++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0" hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x84++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1" hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x88++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2" hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x8C++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3" hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x90++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4" hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x94++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5" hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x98++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6" hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x9C++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7" hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8" hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9" hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10" hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xAC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11" hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12" hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13" hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14" hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xBC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15" hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16" hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17" hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18" hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xCC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19" hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20" hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21" hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22" hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xDC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23" hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xE0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24" hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C24_BLK_INDEX in the PRU Control register." group.long 0xE4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25" hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C25_BLK_INDEX in the PRU Control register." group.long 0xE8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26" hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C26_BLK_INDEX in the PRU Control register." group.long 0xEC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27" hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C27_BLK_INDEX in the PRU Control register." group.long 0xF0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28" hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C28_POINTER in the PRU Control register." group.long 0xF4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29" hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C29_POINTER in the PRU Control register." group.long 0xF8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30" hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C30_POINTER in the PRU Control register." group.long 0xFC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31" hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C31_POINTER in the PRU Control register." width 0xB tree.end tree "PRU1_DEBUG" base eahb:0x54424400 width 23. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0" hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1" hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2" hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3" hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4" hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x14++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5" hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x18++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6" hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x1C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7" hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8" hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9" hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10" hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11" hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x30++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12" hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x34++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13" hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x38++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14" hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x3C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15" hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x40++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16" hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x44++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17" hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x48++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18" hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19" hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x50++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20" hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x54++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21" hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x58++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22" hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x5C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23" hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x60++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24" hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x64++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25" hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x68++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26" hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x6C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27" hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x70++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28" hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x74++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29" hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x78++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30" hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x7C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31" hexmask.long 0x0 0.--31. 1. " GPREG31 ," group.long 0x80++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0" hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x84++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1" hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x88++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2" hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x8C++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3" hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x90++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4" hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x94++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5" hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x98++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6" hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x9C++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7" hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8" hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9" hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10" hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xAC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11" hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12" hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13" hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14" hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xBC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15" hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16" hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17" hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18" hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xCC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19" hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20" hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21" hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22" hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xDC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23" hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xE0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24" hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C24_BLK_INDEX in the PRU Control register." group.long 0xE4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25" hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C25_BLK_INDEX in the PRU Control register." group.long 0xE8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26" hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C26_BLK_INDEX in the PRU Control register." group.long 0xEC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27" hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C27_BLK_INDEX in the PRU Control register." group.long 0xF0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28" hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C28_POINTER in the PRU Control register." group.long 0xF4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29" hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C29_POINTER in the PRU Control register." group.long 0xF8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30" hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C30_POINTER in the PRU Control register." group.long 0xFC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31" hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C31_POINTER in the PRU Control register." width 0xB tree.end tree.end tree.open "ICSS_1" tree "CFG" base eahb:0x54466000 width 21. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_CFG_REVID,The Revision Register contains the ID and revision information." hexmask.long 0x0 0.--31. 1. " REVID ,Revision ID. Reset value for PRU-ICSS1 is 0x4700_0200 and for PRU-ICSS0 is 0x4701_0100." group.long 0x4++0x3 bitfld.long 0x0 0.--1. " IDLE_MODE ," "0,1,2,3" bitfld.long 0x0 2.--3. " STANDBY_MODE ," "0,1,2,3" bitfld.long 0x0 4. " STANDBY_INIT ," "0,1" textline "" bitfld.long 0x0 5. " SUB_MWAIT ,Status bit for wait state." "0,1" group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_CFG_GPCFG0,The General Purpose Configuration 0 Register defines the GPI/O configuration for PRU0." bitfld.long 0x0 0.--1. " PRU0_GPI_MODE ," "0,1,2,3" bitfld.long 0x0 2. " PRU0_GPI_CLK_MODE ,Parallel 16bit capture mode clock edge." "0,1" textline "" bitfld.long 0x0 13. " PRU0_GPI_SB ,Start Bit event for 28-bit shift mode. PRU0_GPI_SB (pru0_r31_status[29]) is set when first capture of a 1 on pru0_r31_status[0]." "0,1" bitfld.long 0x0 14. " PRU0_GPO_MODE ," "0,1" textline "" bitfld.long 0x0 25. " PRU0_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting." "0,1" textline "" group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_CFG_GPCFG1,The General Purpose Configuration 1 Register defines the GPI/O configuration for PRU1." bitfld.long 0x0 0.--1. " PRU1_GPI_MODE ," "0,1,2,3" bitfld.long 0x0 2. " PRU1_GPI_CLK_MODE ,Parallel 16bit capture mode clock edge." "0,1" textline "" bitfld.long 0x0 13. " PRU1_GPI_SB ,28-bit shift mode Start Bit event. PRU1_GPI_SB (pru1_r31_status[29]) is set when first capture of a 1 on pru1_r31_status[0]." "0,1" bitfld.long 0x0 14. " PRU1_GPO_MODE ," "0,1" textline "" bitfld.long 0x0 25. " PRU1_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting." "0,1" textline "" group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_CFG_CGR,The Clock Gating Register controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x1." bitfld.long 0x0 0. " PRU0_CLK_STOP_REQ ,PRU0 request to stop clock." "0,1" bitfld.long 0x0 1. " PRU0_CLK_STOP_ACK ,Acknowledgement that PRU0 clock can be stopped." "0,1" bitfld.long 0x0 2. " PRU0_CLK_EN ,PRU0 clock enable." "0,1" textline "" bitfld.long 0x0 3. " PRU1_CLK_STOP_REQ ,PRU1 request to stop clock." "0,1" bitfld.long 0x0 4. " PRU1_CLK_STOP_ACK ,Acknowledgement that PRU1 clock can be stopped." "0,1" bitfld.long 0x0 5. " PRU1_CLK_EN ,PRU1 clock enable." "0,1" textline "" bitfld.long 0x0 6. " INTC_CLK_STOP_REQ ,INTC request to stop clock." "0,1" bitfld.long 0x0 7. " INTC_CLK_STOP_ACK ,Acknowledgement that INTC clock can be stopped." "0,1" bitfld.long 0x0 8. " INTC_CLK_EN ,INTC clock enable." "0,1" textline "" bitfld.long 0x0 9. " UART_CLK_STOP_REQ ,UART request to stop clock." "0,1" bitfld.long 0x0 10. " UART_CLK_STOP_ACK ,Acknowledgement that UART clock can be stopped." "0,1" bitfld.long 0x0 11. " UART_CLK_EN ,UART clock enable." "0,1" textline "" bitfld.long 0x0 12. " ECAP_CLK_STOP_REQ ,ECAP request to stop clock." "0,1" bitfld.long 0x0 13. " ECAP_CLK_STOP_ACK ,Acknowledgement that ECAP clock can be stopped." "0,1" bitfld.long 0x0 14. " ECAP_CLK_EN ,ECAP clock enable." "0,1" textline "" bitfld.long 0x0 15. " IEP_CLK_STOP_REQ ,IEP request to stop clock." "0,1" bitfld.long 0x0 16. " IEP_CLK_STOP_ACK ,Acknowledgement that IEP clock can be stopped." "0,1" bitfld.long 0x0 17. " IEP_CLK_EN ,IEP clock enable." "0,1" textline "" group.long 0x14++0x3 line.long 0x0 "PRU_ICSS_CFG_ISRP,The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRU ICSS memory parity events. The raw status is set even if the event is not enabled." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_RAW ,PRU0 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_IRAM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_RAW ,PRU0 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_RAW ,PRU1 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_RAW ,PRU1 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " RAM_PE_RAW ,PRU-ICSS1 Only. RAM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_RAW[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x0 "PRU_ICSS_CFG_ISP,The IRQ Status Parity Register is a snapshot of the IRQ status for the PRU ICSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE ,PRU0 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE ,PRU0 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " PRU1_IMEM_PE ,PRU1 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE ,PRU1 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " RAM_PE ,PRU-ICSS1 Only. RAM Parity Error for Byte3, Byte2, Byte1, Byte0. Note RAM_PE[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x0 "PRU_ICSS_CFG_IESP,The IRQ Enable Set Parity Register enables the IRQ PRU ICSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_SET ,PRU0 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_SET ,PRU0 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_SET ,PRU1 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_SET ,PRU1 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " RAM_PE_SET ,PRU-ICSS1 Only. RAM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_SET[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_CFG_IECP,The IRQ Enable Clear Parity Register disables the IRQ PRU ICSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_CLR ,PRU0 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_CLR[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_CLR ,PRU0 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_CLR[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_CLR ,PRU1 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_CLR[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_CLR ,PRU1 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_CLR[0] maps to Byte0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_CFG_PMAO,The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x0000_0000." bitfld.long 0x0 0. " PMAO_PRU0 ,PRU0 OCP Master Port Address Offset Enable." "0,1" bitfld.long 0x0 1. " PMAO_PRU1 ,PRU1 OCP Master Port Address Offset Enable." "0,1" group.long 0x30++0x3 line.long 0x0 "PRU_ICSS_CFG_IEPCLK,The IEP Clock Source Register defines the source of the IEP clock." bitfld.long 0x0 0. " OCP_EN ," "0,1" group.long 0x34++0x3 line.long 0x0 "PRU_ICSS_CFG_SPP,The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores and configures the scratch pad XFR shift functionality." bitfld.long 0x0 0. " PRU1_PAD_HP_EN ,Defines which PRU wins write cycle arbitration to a common scratch pad bank." "0,1" bitfld.long 0x0 1. " XFR_SHIFT_EN ,Enables XIN/XOUT shift functionality. When enabled, R0 [4:0] (internal to PRU) defines the 32-bit offset for XIN and XOUT operations with the scratch pad." "0,1" group.long 0x40++0x3 line.long 0x0 "PRU_ICSS_CFG_PIN_MX,The Pin Mux Select Register defines the state of the PRU ICSS internal pinmuxing." hexmask.long.byte 0x0 0.--7. 1. " PIN_MUX_SEL ,Defines the state of PIN_MUX_SEL [1:0] for internal pinmuxing." width 0xB tree.end tree "PRU0_CTRL" base eahb:0x54462000 width 25. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_CTRL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " EN ,Processor Enable" "0,1" bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1" textline "" bitfld.long 0x0 3. " CTR_EN ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable" "0,1" textline "" bitfld.long 0x0 15. " RUNSTATE ,Run State" "0,1" textline "" hexmask.long.word 0x0 16.--31. 1. " PCTR_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_CTRL_STS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCTR ,Program Counter" group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_CTRL_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENS ,Wakeup Enables" group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_CTRL_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits EN and CTR_EN set in the PRU control register)." group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_CTRL_STALL,STALL COUNT" hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits EN and CTR_EN set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0" hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_IDX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_IDX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 25 in the PRU Constant Table." textline "" group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1" hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_IDX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_IDX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 27 in the PRU Constant Table." textline "" group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0" hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 29 in the PRU Constant Table." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1" hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 31 in the PRU Constant Table." width 0xB tree.end tree "PRU1_CTRL" base eahb:0x54464000 width 25. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_CTRL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " EN ,Processor Enable" "0,1" bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep." "0,1" textline "" bitfld.long 0x0 3. " CTR_EN ,PRU Cycle Counter Enable: Enables PRU cycle counters." "0,1" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable" "0,1" textline "" bitfld.long 0x0 15. " RUNSTATE ,Run State" "0,1" textline "" hexmask.long.word 0x0 16.--31. 1. " PCTR_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_CTRL_STS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCTR ,Program Counter" group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_CTRL_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENS ,Wakeup Enables" group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_CTRL_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits EN and CTR_EN set in the PRU control register)." group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_CTRL_STALL,STALL COUNT" hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits EN and CTR_EN set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0" hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_IDX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_IDX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 25 in the PRU Constant Table." textline "" group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1" hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_IDX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_IDX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11 to 8 of entry 27 in the PRU Constant Table." textline "" group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0" hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 29 in the PRU Constant Table." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_CTRL_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1" hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23 to 8 of entry 31 in the PRU Constant Table." width 0xB tree.end tree "INTC" base eahb:0x54460000 width 22. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_INTC_REVID,Revision ID Register" bitfld.long 0x0 0.--5. " REV_MINOR ,MINOR REVISION" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " REV_CUSTOM ,CUSTOM REVISION" "0,1,2,3" bitfld.long 0x0 8.--10. " REV_MAJOR ,MAJOR REVISION" "0,1,2,3,4,5,6,7" textline "" bitfld.long 0x0 11.--15. " REV_RTL ,RTL REVISIONS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--27. 1. " REV_MODULE ,MODULE ID" textline "" bitfld.long 0x0 30.--31. " REV_SCHEME ,SCHEME" "0,1,2,3" group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_INTC_CR,The Control Register holds global control parameters and can forces a soft reset on the module." bitfld.long 0x0 2.--3. " NEST_MODE ,The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting" "0,1,2,3" textline "" group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_INTC_GER,The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable." bitfld.long 0x0 0. " EN_HINT_ANY ,The current global enable value when read. Writes set the global enable." "0,1" group.long 0x1C++0x3 line.long 0x0 "PRU_ICSS_INTC_GNLR,Global Nesting Level Register" hexmask.long.word 0x0 0.--8. 1. " GLB_NEST_LEVEL ,The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data." "0,1" group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_INTC_SISR,The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STS_SET_IDX ,Writes set the status of the interrupt given in the index value. Reads return 0." group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_INTC_SICR,The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STS_CLR_IDX ,Writes clear the status of the interrupt given in the index value. Reads return 0." group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_INTC_EISR,The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " EN_SET_IDX ,Writes set the enable of the interrupt given in the index value. Reads return 0." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_INTC_EICR,The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " EN_CLR_IDX ,Writes clear the enable of the interrupt given in the index value. Reads return 0." group.long 0x34++0x3 line.long 0x0 "PRU_ICSS_INTC_HIEISR,The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled." hexmask.long.word 0x0 0.--9. 1. " HINT_EN_SET_IDX ,Writes set the enable of the host interrupt given in the index value. Reads return 0." group.long 0x38++0x3 line.long 0x0 "PRU_ICSS_INTC_HIDISR,The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output." hexmask.long.word 0x0 0.--9. 1. " HINT_EN_CLR_IDX ,Writes clear the enable of the host interrupt given in the index value. Reads return 0." group.long 0x80++0x3 line.long 0x0 "PRU_ICSS_INTC_GPIR,The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts." hexmask.long.word 0x0 0.--9. 1. " GLB_PRI_INTR ,The currently highest priority interrupt index pending across all the host interrupts." bitfld.long 0x0 31. " GLB_NONE ,No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending." "0,1" group.long 0x200++0x3 line.long 0x0 "PRU_ICSS_INTC_SRSR0,System Interrupt Status Raw/Set Register0" hexmask.long 0x0 0.--31. 1. " RAW_STS_31_0 ,System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.long 0x204++0x3 line.long 0x0 "PRU_ICSS_INTC_SRSR1,System Interrupt Status Raw/Set Register1" hexmask.long 0x0 0.--31. 1. " RAW_STS_63_32 ,System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.long 0x280++0x3 line.long 0x0 "PRU_ICSS_INTC_SECR0,System Interrupt Status Enabled/Clear Register0" hexmask.long 0x0 0.--31. 1. " ENA_STS_31_0 ,System interrupt enabled status and clearing of the system interrupts 0 to 31" group.long 0x284++0x3 line.long 0x0 "PRU_ICSS_INTC_SECR1,System Interrupt Status Enabled/Clear Register1" hexmask.long 0x0 0.--31. 1. " ENA_STS_63_32 ,System interrupt enabled status and clearing of the system interrupts 32 to 63" group.long 0x300++0x3 line.long 0x0 "PRU_ICSS_INTC_ESR0,The System Interrupt Enable Set Register0 enables system interrupts 0 to 31 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " EN_SET_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.long 0x304++0x3 line.long 0x0 "PRU_ICSS_INTC_ESR1,The System Interrupt Enable Set Register1 enables system interrupts 32 to 63 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " EN_SET_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.long 0x380++0x3 line.long 0x0 "PRU_ICSS_INTC_ECR0,The System Interrupt Enable Clear Register0 disables system interrupts 0 to 31 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " EN_CLR_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.long 0x384++0x3 line.long 0x0 "PRU_ICSS_INTC_ECR1,The System Interrupt Enable Clear Register1 disables system interrupts 32 to 63 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " EN_CLR_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.long 0x400++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR0,The Channel Map Register0 specify the channel for the system interrupts 0 to 3. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x404++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR1,The Channel Map Register1 specify the channel for the system interrupts 4 to 7. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_4 ,Sets the channel for the system interrupt 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_5 ,Sets the channel for the system interrupt 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_6 ,Sets the channel for the system interrupt 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_7 ,Sets the channel for the system interrupt 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x408++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR2,The Channel Map Register2 specify the channel for the system interrupts 8 to 11. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_8 ,Sets the channel for the system interrupt 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_9 ,Sets the channel for the system interrupt 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_10 ,Sets the channel for the system interrupt 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_11 ,Sets the channel for the system interrupt 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40C++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR3,The Channel Map Register3 specify the channel for the system interrupts 12 to 15. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_12 ,Sets the channel for the system interrupt 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_13 ,Sets the channel for the system interrupt 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_14 ,Sets the channel for the system interrupt 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_15 ,Sets the channel for the system interrupt 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x410++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR4,The Channel Map Register4 specify the channel for the system interrupts 16 to 19. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_16 ,Sets the channel for the system interrupt 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_17 ,Sets the channel for the system interrupt 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_18 ,Sets the channel for the system interrupt 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_19 ,Sets the channel for the system interrupt 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x414++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR5,The Channel Map Register5 specify the channel for the system interrupts 20 to 23. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_20 ,Sets the channel for the system interrupt 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_21 ,Sets the channel for the system interrupt 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_22 ,Sets the channel for the system interrupt 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_23 ,Sets the channel for the system interrupt 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x418++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR6,The Channel Map Register6 specify the channel for the system interrupts 24 to 27. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_24 ,Sets the channel for the system interrupt 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_25 ,Sets the channel for the system interrupt 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_26 ,Sets the channel for the system interrupt 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_27 ,Sets the channel for the system interrupt 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x41C++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR7,The Channel Map Register7 specify the channel for the system interrupts 28 to 31. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_28 ,Sets the channel for the system interrupt 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_29 ,Sets the channel for the system interrupt 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_30 ,Sets the channel for the system interrupt 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_31 ,Sets the channel for the system interrupt 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x420++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR8,The Channel Map Register8 specify the channel for the system interrupts 32 to 35. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_32 ,Sets the channel for the system interrupt 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_33 ,Sets the channel for the system interrupt 33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_34 ,Sets the channel for the system interrupt 34" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_35 ,Sets the channel for the system interrupt 35" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x424++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR9,The Channel Map Register9 specify the channel for the system interrupts 36 to 39. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_36 ,Sets the channel for the system interrupt 36" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_37 ,Sets the channel for the system interrupt 37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_38 ,Sets the channel for the system interrupt 38" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_39 ,Sets the channel for the system interrupt 39" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x428++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR10,The Channel Map Register10 specify the channel for the system interrupts 40 to 43. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_40 ,Sets the channel for the system interrupt 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_41 ,Sets the channel for the system interrupt 41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_42 ,Sets the channel for the system interrupt 42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_43 ,Sets the channel for the system interrupt 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x42C++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR11,The Channel Map Register11 specify the channel for the system interrupts 44 to 47. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_44 ,Sets the channel for the system interrupt 44" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_45 ,Sets the channel for the system interrupt 45" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_46 ,Sets the channel for the system interrupt 46" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_47 ,Sets the channel for the system interrupt 47" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x430++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR12,The Channel Map Register12 specify the channel for the system interrupts 48 to 51. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_48 ,Sets the channel for the system interrupt 48" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_49 ,Sets the channel for the system interrupt 49" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_50 ,Sets the channel for the system interrupt 50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_51 ,Sets the channel for the system interrupt 51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x434++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR13,The Channel Map Register13 specify the channel for the system interrupts 52 to 55. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_52 ,Sets the channel for the system interrupt 52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_53 ,Sets the channel for the system interrupt 53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_54 ,Sets the channel for the system interrupt 54" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_55 ,Sets the channel for the system interrupt 55" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x438++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR14,The Channel Map Register14 specify the channel for the system interrupts 56 to 59. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_56 ,Sets the channel for the system interrupt 56" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_57 ,Sets the channel for the system interrupt 57" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_58 ,Sets the channel for the system interrupt 58" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_59 ,Sets the channel for the system interrupt 59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x43C++0x3 line.long 0x0 "PRU_ICSS_INTC_CMR15,The Channel Map Register15 specify the channel for the system interrupts 60 to 63. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_60 ,Sets the channel for the system interrupt 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " CH_MAP_61 ,Sets the channel for the system interrupt 61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " CH_MAP_62 ,Sets the channel for the system interrupt 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " CH_MAP_63 ,Sets the channel for the system interrupt 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x0 "PRU_ICSS_INTC_HMR0,The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_0 ,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " HINT_MAP_1 ,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " HINT_MAP_2 ,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " HINT_MAP_3 ,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x804++0x3 line.long 0x0 "PRU_ICSS_INTC_HMR1,The Host Interrupt Map Register1 define the host interrupt for channels 4 to 7. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_4 ,HOST INTERRUPT MAP FOR CHANNEL 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " HINT_MAP_5 ,HOST INTERRUPT MAP FOR CHANNEL 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 16.--19. " HINT_MAP_6 ,HOST INTERRUPT MAP FOR CHANNEL 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" bitfld.long 0x0 24.--27. " HINT_MAP_7 ,HOST INTERRUPT MAP FOR CHANNEL 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x808++0x3 line.long 0x0 "PRU_ICSS_INTC_HMR2,The Host Interrupt Map Register2 define the host interrupt for channels 8 to 9. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_8 ,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " HINT_MAP_9 ,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" group.long 0x900++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR0,The Host Interrupt Prioritized Index Register0 shows the highest priority current pending interrupt for the host interrupt 0. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_0 ,HOST INT 0 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_0 ,No pending interrupt." "0,1" group.long 0x904++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR1,The Host Interrupt Prioritized Index Register1 shows the highest priority current pending interrupt for the host interrupt 1. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_1 ,HOST INT 1 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_1 ,No pending interrupt." "0,1" group.long 0x908++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR2,The Host Interrupt Prioritized Index Register2 shows the highest priority current pending interrupt for the host interrupt 2. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_2 ,HOST INT 2 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_2 ,No pending interrupt." "0,1" group.long 0x90C++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR3,The Host Interrupt Prioritized Index Register3 shows the highest priority current pending interrupt for the host interrupt 3. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_3 ,HOST INT 3 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_3 ,No pending interrupt." "0,1" group.long 0x910++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR4,The Host Interrupt Prioritized Index Register4 shows the highest priority current pending interrupt for the host interrupt 4. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_4 ,HOST INT 4 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_4 ,No pending interrupt." "0,1" group.long 0x914++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR5,The Host Interrupt Prioritized Index Register5 shows the highest priority current pending interrupt for the host interrupt 5. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_5 ,HOST INT 5 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_5 ,No pending interrupt." "0,1" group.long 0x918++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR6,The Host Interrupt Prioritized Index Register6 shows the highest priority current pending interrupt for the host interrupt 6. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_6 ,HOST INT 6 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_6 ,No pending interrupt." "0,1" group.long 0x91C++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR7,The Host Interrupt Prioritized Index Register7 shows the highest priority current pending interrupt for the host interrupt 7. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_7 ,HOST INT 7 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_7 ,No pending interrupt." "0,1" group.long 0x920++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR8,The Host Interrupt Prioritized Index Register8 shows the highest priority current pending interrupt for the host interrupt 8. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_8 ,HOST INT 8 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_8 ,No pending interrupt." "0,1" group.long 0x924++0x3 line.long 0x0 "PRU_ICSS_INTC_HIPIR9,The Host Interrupt Prioritized Index Register9 shows the highest priority current pending interrupt for the host interrupt 9. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT_9 ,HOST INT 9 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x0 31. " NONE_HINT_9 ,No pending interrupt." "0,1" group.long 0xD00++0x3 line.long 0x0 "PRU_ICSS_INTC_SIPR0,System Interrupt Polarity Register0" hexmask.long 0x0 0.--31. 1. " POLARITY_31_0 ,Interrupt polarity of the system interrupts 0 to 31. 0 = active low. 1 = active high." group.long 0xD04++0x3 line.long 0x0 "PRU_ICSS_INTC_SIPR1,System Interrupt Polarity Register1" hexmask.long 0x0 0.--31. 1. " POLARITY_63_32 ,Interrupt polarity of the system interrupts 32 to 63. 0 = active low. 1 = active high." group.long 0xD80++0x3 line.long 0x0 "PRU_ICSS_INTC_SITR0,The System Interrupt Type Register0 define the type of the system interrupts 0 to 31. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_31_0 ,Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.long 0xD84++0x3 line.long 0x0 "PRU_ICSS_INTC_SITR1,The System Interrupt Type Register1 define the type of the system interrupts 32 to 63. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_63_32 ,Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.long 0x1100++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR0,The Host Interrupt Nesting Level Register0 display and control the nesting level for host interrupt 0. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_0 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1104++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR1,The Host Interrupt Nesting Level Register1 display and control the nesting level for host interrupt 1. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_1 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1108++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR2,The Host Interrupt Nesting Level Register2 display and control the nesting level for host interrupt 2. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_2 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x110C++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR3,The Host Interrupt Nesting Level Register3 display and control the nesting level for host interrupt 3. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_3 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1110++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR4,The Host Interrupt Nesting Level Register4 display and control the nesting level for host interrupt 4. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_4 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1114++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR5,The Host Interrupt Nesting Level Register5 display and control the nesting level for host interrupt 5. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_5 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1118++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR6,The Host Interrupt Nesting Level Register6 display and control the nesting level for host interrupt 6. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_6 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x111C++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR7,The Host Interrupt Nesting Level Register7 display and control the nesting level for host interrupt 7. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_7 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1120++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR8,The Host Interrupt Nesting Level Register8 display and control the nesting level for host interrupt 8. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_8 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1124++0x3 line.long 0x0 "PRU_ICSS_INTC_HINLR9,The Host Interrupt Nesting Level Register9 display and control the nesting level for host interrupt 9. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT_9 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1500++0x3 line.long 0x0 "PRU_ICSS_INTC_HIER,Host Interrupt Enable Registers" hexmask.long.word 0x0 0.--9. 1. " EN_HINT ,The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled" width 0xB tree.end tree "MII_RT" base eahb:0x54472000 width 9. group.long 0x0++0x3 line.long 0x0 "RXCFG0,RX CONFIG0" bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble" "0,1" textline "" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for RXCFG0) 0x1: MII RX Data from Port 1 (default for RXCFG1)" "0,1" bitfld.long 0x0 4. " RX_L2_ENABLE ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2" "0,1" textline "" bitfld.long 0x0 6. " RX_AUTOFWD_PRE ,Enables auto-forward of received preamble" "0,1" group.long 0x4++0x3 line.long 0x0 "RXCFG1,RX CONFIG1" bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble" "0,1" textline "" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for RXCFG0) 0x1: MII RX Data from Port 1 (default for RXCFG1)" "0,1" bitfld.long 0x0 4. " RX_L2_ENABLE ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2" "0,1" textline "" bitfld.long 0x0 6. " RX_AUTOFWD_PRE ,Enables auto-forward of received preamble" "0,1" group.long 0x10++0x3 line.long 0x0 "TXCFG0,TX CONFIG0" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble." "0,1" bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event" "0,1" textline "" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30" "0,1" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source" "0,1" textline "" bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence" "0,1" hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface" textline "" bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the ocp_clk must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" group.long 0x14++0x3 line.long 0x0 "TXCFG1,TX CONFIG1" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble" "0,1" bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event" "0,1" textline "" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30" "0,1" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source" "0,1" textline "" bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequenc" "0,1" hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface" textline "" bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the ocp_clk must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x0 "TXCRC0,TX CYCLIC REDUNDANCY CHECK0" hexmask.long 0x0 0.--31. 1. " TX_CRC32 ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.long 0x24++0x3 line.long 0x0 "TXCRC1,TX CYCLIC REDUNDANCY CHECK1" hexmask.long 0x0 0.--31. 1. " TX_CRC32 ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.long 0x30++0x3 line.long 0x0 "TXIPG0,TX INTERPACKET GAP0" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG)" group.long 0x34++0x3 line.long 0x0 "TXIPG1,TX INTERPACKET GAP1" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG)" group.long 0x38++0x3 line.long 0x0 "PRS0,PORT RAW STATUS0" bitfld.long 0x0 0. " pr1_mii0_col ,Current state of pr#lt#k#gt#_mii0_col" "0,1" bitfld.long 0x0 1. " pr1_mii0_crs ,Current state of pr#lt#k#gt#_mii0_crs" "0,1" group.long 0x3C++0x3 line.long 0x0 "PRS1,PORT RAW STATUS1" bitfld.long 0x0 0. " pr1_mii1_col ,Current state of pr#lt#k#gt#_mii1_col" "0,1" bitfld.long 0x0 1. " pr1_mii1_crs ,Current state of pr#lt#k#gt#_mii1_crs" "0,1" group.long 0x40++0x3 line.long 0x0 "RXFRMS0,RX FRAME SIZE0" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM_CNT ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0: 1 byte after SFD and including CRC. N: N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM_CNT ,Defines the maximum received frame count." group.long 0x44++0x3 line.long 0x0 "RXFRMS1,RX FRAME SIZE1" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM_CNT ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0: 1 byte after SFD and including CRC. N: N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM_CNT ,Defines the maximum received frame count." group.long 0x48++0x3 line.long 0x0 "RXPCNT0,RX PREAMABLE COUNT0" bitfld.long 0x0 0.--3. " RX_MIN_PRE_CNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0x5D." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C++0x3 line.long 0x0 "RXPCNT1,RX PREAMABLE COUNT1" bitfld.long 0x0 0.--3. " RX_MIN_PRE_CNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0x5D." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x3 line.long 0x0 "RXERR0,RX ERROR0" bitfld.long 0x0 0. " RX_MIN_PRE_CNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PRE_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" bitfld.long 0x0 1. " RX_MAX_PRE_CNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PRE_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" bitfld.long 0x0 2. " RX_MIN_FRM_CNT_ERR ,Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" textline "" bitfld.long 0x0 3. " RX_MAX_FRM_CNT_ERR ,Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" group.long 0x54++0x3 line.long 0x0 "RXERR1,RX ERROR1" bitfld.long 0x0 0. " RX_MIN_PRE_CNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PRE_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" bitfld.long 0x0 1. " RX_MAX_PRE_CNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PRE_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" bitfld.long 0x0 2. " RX_MIN_FRM_CNT_ERR ,Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" textline "" bitfld.long 0x0 3. " RX_MAX_FRM_CNT_ERR ,Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred" "0,1" group.long 0x60++0x3 line.long 0x0 "RXFLV0,RX FIFO0 Level" hexmask.long.byte 0x0 0.--7. 1. " RX_FIFO_LEVEL ,Define the number of valid bytes in the RX FIFO 0 = empty 1 = 1 Byte/ 2 Nibbles 2 = 2 Byte/ 4 Nibble ... 32 = 32 Bytes/ 64 Nibbles" group.long 0x64++0x3 line.long 0x0 "RXFLV1,RX FIFO1 Level" hexmask.long.byte 0x0 0.--7. 1. " RX_FIFO_LEVEL ,Define the number of valid bytes in the RX FIFO 0 = empty 1 = 1 Byte/ 2 Nibbles 2 = 2 Byte/ 4 Nibble ... 32 = 32 Bytes/ 64 Nibbles" group.long 0x68++0x3 line.long 0x0 "TXFLV0,TX FIFO0 Level" hexmask.long.byte 0x0 0.--7. 1. " TX_FIFO_LEVEL ,Define the number of valid nibbles in the TX FIFO 0 = empty 1 = 1 Nibble 2 = 1 Byte/ 2 Nibble ... 128 = 64 Bytes/ 128 Nibbles" group.long 0x6C++0x3 line.long 0x0 "TXFLV1,TX FIFO1 Level" hexmask.long.byte 0x0 0.--7. 1. " TX_FIFO_LEVEL ,Define the number of valid nibbles in the TX FIFO 0 = empty 1 = 1 Nibble 2 = 1 Byte/ 2 Nibble ... 128 = 64 Bytes/ 128 Nibbles" width 0xB tree.end tree "MII_MDIO" base eahb:0x54472400 width 21. group.long 0x0++0x3 line.long 0x0 "MDIO_VER," hexmask.long.byte 0x0 0.--7. 1. " REVMIN ,Management interface module minor revision value." hexmask.long.byte 0x0 8.--15. 1. " REVMAJ ,Management interface module major revision value." hexmask.long.word 0x0 16.--31. 1. " MODID ,Identifies type of peripheral." group.long 0x4++0x3 line.long 0x0 "MDIO_CTRL," hexmask.long.word 0x0 0.--15. 1. " CLKDIV ,Clock divider. [[br]]This field specifies the division ratio between CLK and the frequency of MDIO_CLK. [[br]]MDIO_CLK is disabled when clkdiv is set to 0. [[br]]MDIO_CLK frequency = clk frequency/(clkdiv+1)." bitfld.long 0x0 17. " INTTESTENB ,Interrupt test enable. [[br]]This bit can be set to 1 to enable the host to set the USERINT and LINKINT bits for test purposes." "0,1" textline "" bitfld.long 0x0 18. " FAULTENB ,Fault detect enable. [[br]]This bit has to be set to 1 to enable the physical layer fault detection." "0,1" bitfld.long 0x0 19. " FAULT ,Fault indicator. [[br]]This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them. [[br]]This indicates a physical layer fault and the module state machine is reset. [[br]]Writing a 1 to it clears this bit." "0,1" bitfld.long 0x0 20. " PREAMBLE ,Preamble disable." "0,1" textline "" bitfld.long 0x0 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline "" bitfld.long 0x0 30. " EN ,Enable control" "0,1" bitfld.long 0x0 31. " IDLE ,MDIO state machine IDLE. [[br]]Set to 1 when the state machine is in the idle state." "0,1" group.long 0x8++0x3 line.long 0x0 "MDIO_ALIVE," hexmask.long 0x0 0.--31. 1. " ALIVE ,MDIO alive" group.long 0xC++0x3 line.long 0x0 "MDIO_LINK," hexmask.long 0x0 0.--31. 1. " LINK ,MDIO link state" group.long 0x10++0x3 line.long 0x0 "MDIO_LINKINTRAW," bitfld.long 0x0 0.--1. " LINKINTRAW ,MDIO link change event, raw value" "0,1,2,3" group.long 0x14++0x3 line.long 0x0 "MDIO_LINKINTMASKED," bitfld.long 0x0 0.--1. " LINKINTMASKED ,MDIO link change interrupt, masked value" "0,1,2,3" group.long 0x20++0x3 line.long 0x0 "MDIO_USERINTRAW," bitfld.long 0x0 0.--1. " USERINTRAW ,Raw value of MDIO user command complete event for the MDIOUSERACCESS1 register through the MDIOUSERACCESS0 register, respectively" "0,1,2,3" group.long 0x24++0x3 line.long 0x0 "MDIO_USERINTMASKED," bitfld.long 0x0 0.--1. " USERINTMASKED ,Masked value of MDIO user command complete interrupt for the MDIOUSERACCESS1 register through the MDIOUSERACCESS0 register, respectively" "0,1,2,3" group.long 0x28++0x3 line.long 0x0 "MDIO_USERINTMASKSET," bitfld.long 0x0 0.--1. " USERINTMASKSET ,MDIO user interrupt mask set for USERINTMASKED, respectively" "0,1,2,3" group.long 0x2C++0x3 line.long 0x0 "MDIO_USERINTMASKCLR," bitfld.long 0x0 0.--1. " USERINTMASKCLR ,MDIO user command complete interrupt mask clear for USERINTMASKED, respectively" "0,1,2,3" group.long 0x80++0x3 line.long 0x0 "MDIO_USERACCESS0," hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. [[br]]The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. [[br]]Specifies the PHY to be accesses for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " REGADR ,Register address. [[br]]Specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline "" bitfld.long 0x0 29. " ACK ,Acknowledge. [[br]]This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. [[br]]Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline "" bitfld.long 0x0 31. " GO ,Causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process" "0,1" group.long 0x84++0x3 line.long 0x0 "MDIO_USERPHYSEL0," bitfld.long 0x0 0.--4. " PHYADDRMON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable. [[br]]Set to 1 to enable link change status interrupts for PHY address specified in PHYADDRMON. [[br]]Link change interrupts are disabled if this bit is set to 0." "0,1" textline "" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. [[br]]Set to 1 to determine link status using the MLINK pin. [[br]]Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" group.long 0x88++0x3 line.long 0x0 "MDIO_USERACCESS1," hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. [[br]]The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address[[br]] specifies the PHY to be accesses for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " REGADR ,Register address[[br]] specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline "" bitfld.long 0x0 29. " ACK ,Acknowledge. [[br]]This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. [[br]]Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline "" bitfld.long 0x0 31. " GO ,Causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process" "0,1" group.long 0x8C++0x3 line.long 0x0 "MDIO_USERPHYSEL1," bitfld.long 0x0 0.--4. " PHYADDRMON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable. [[br]]Set to 1 to enable link change status interrupts for PHY address specified in PHYADDRMON. [[br]]Link change interrupts are disabled if this bit is cleared to 0." "0,1" textline "" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. [[br]]Set to 1 to determine link status using the MLINK pin. [[br]]Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" width 0xB tree.end tree "IEP" base eahb:0x5446e000 width 32. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_GLB_CFG,GLOBAL CONFIGURE" bitfld.long 0x0 0. " CNT_ENABLE ,Counter enable" "0,1" bitfld.long 0x0 4.--7. " DEFAULT_INC ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline "" hexmask.long.word 0x0 8.--19. 1. " CMP_INC ,Defines the increment value when compensation is active" group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_GLB_STS,GLOBAL STATUS" bitfld.long 0x0 0. " CNT_OVF ,Counter overflow status." "0,1" group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_COMPEN,COMPENSATION" hexmask.long.tbyte 0x0 0.--23. 1. " COMPEN_CNT ,Compensation counter." group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CNT,COUNTER" hexmask.long 0x0 0.--31. 1. " COUNT ,32-bit count value. Increments by (DEFAULT_INC or CMP_INC) on every positive edge of iep_clk (200MHz)." group.long 0x40++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP_CFG,COMPARE CONFIGURE" bitfld.long 0x0 0. " CMP0_RST_CNT_EN ,Counter reset enable." "0,1" hexmask.long.byte 0x0 1.--8. 1. " CMP_EN ,Compare registers enable, where CMP_EN[0] maps to CMP[0]." group.long 0x44++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP_STS,COMPARE STATUS" hexmask.long.byte 0x0 0.--7. 1. " CMP_HIT ,Status bit for each of the compare registers, where CMP_HIT[n] maps to CMP[n]" group.long 0x48++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP0,COMPARE0" hexmask.long 0x0 0.--31. 1. " CMP0 ,Compare 0 value" group.long 0x4C++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP1,COMPARE1" hexmask.long 0x0 0.--31. 1. " CMP1 ,Compare 1 value" group.long 0x50++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP2,COMPARE2" hexmask.long 0x0 0.--31. 1. " CMP2 ,Compare 2 value" group.long 0x54++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP3,COMPARE3" hexmask.long 0x0 0.--31. 1. " CMP3 ,Compare 3 value" group.long 0x58++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP4,COMPARE4" hexmask.long 0x0 0.--31. 1. " CMP4 ,Compare 4 value" group.long 0x5C++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP5,COMPARE5" hexmask.long 0x0 0.--31. 1. " CMP5 ,Compare 5 value" group.long 0x60++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP6,COMPARE6" hexmask.long 0x0 0.--31. 1. " CMP6 ,Compare 6 value" group.long 0x64++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP7,COMPARE7" hexmask.long 0x0 0.--31. 1. " CMP7 ,Compare 7 value" group.long 0x88++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP8,COMPARE8" hexmask.long 0x0 0.--31. 1. " CMP8 ,Compare 8 value" group.long 0x8C++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP9,COMPARE9" hexmask.long 0x0 0.--31. 1. " CMP9 ,Compare 9 value" group.long 0x90++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP10,COMPARE10" hexmask.long 0x0 0.--31. 1. " CMP10 ,Compare 10 value" group.long 0x94++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP11,COMPARE11" hexmask.long 0x0 0.--31. 1. " CMP11 ,Compare 11 value" group.long 0x98++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP12,COMPARE12" hexmask.long 0x0 0.--31. 1. " CMP12 ,Compare 12 value" group.long 0x9C++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP13,COMPARE13" hexmask.long 0x0 0.--31. 1. " CMP13 ,Compare 13 value" group.long 0xA0++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP14,COMPARE14" hexmask.long 0x0 0.--31. 1. " CMP14 ,Compare 14 value" group.long 0xA4++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CMP15,COMPARE15" hexmask.long 0x0 0.--31. 1. " CMP15 ,Compare 15 value" group.long 0xA8++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_CNT_RST,COUNT RESET" hexmask.long 0x0 0.--31. 1. " RESET_VAL ,This enables SW to define the reset state of the Master counter when it gets reset" group.long 0xAC++0x3 line.long 0x0 "PRU_ICSS_IEP_TMR_PWM,PWM" bitfld.long 0x0 0. " PWM0_RST_CNT_EN ,Enable the reset of the counter by a pwm0_sync_out event." "0,1" bitfld.long 0x0 1. " PWM0_HIT ,Raw Status bit of pwm0_sync_out event." "0,1" bitfld.long 0x0 2. " PWM3_RST_CNT_EN ,Enable the reset of the counter by a pwm3_sync_out event." "0,1" textline "" bitfld.long 0x0 3. " PWM3_HIT ,Raw Status bit of pwm3_sync_out event." "0,1" group.long 0x300++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_CTRL,DIGITAL INPUT OUTPUT CONTROL" bitfld.long 0x0 4. " IN_MODE ,Enable pr1_edio_data_in [31:0] to be sampled by external pr1_edio_latch_in signal." "0,1" group.long 0x308++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_DATA_IN,DIGITAL DATA INPUT" hexmask.long 0x0 0.--31. 1. " DATA_IN ,Data input. Sample time of digital inputs is controlled externally by using the pr1_edio_latch_in signal. Must enable by setting DIGIO_CTRL[IN_MODE]." group.long 0x30C++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_DATA_IN_RAW,DIGITAL DATA INPUT DIRECT SAMPLE" hexmask.long 0x0 0.--31. 1. " DATA_IN_RAW ,Raw data input. Direct sample of pr1_edio_data_in[31:0]." group.long 0x310++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_DATA_OUT,DIGITAL DATA OUTPUT" hexmask.long 0x0 0.--31. 1. " DATA_OUT ,Data output, pr1_edio_data_out[31:0]." group.long 0x314++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_DATA_OUT_EN,DIGITAL DATA OUT ENABLE" hexmask.long 0x0 0.--31. 1. " DATA_OUT_EN ,Enables tri-state control for pr1_edio_data_out[31:0]." group.long 0x318++0x3 line.long 0x0 "PRU_ICSS_IEP_DIGIO_EXP,DIGIO EXPIRATION CONFIGURE" bitfld.long 0x0 0. " SW_DATA_OUT_UPDATE ,Enable DIGIO_DATA_OUT to be driven out on pr1_edio_data_out. Only valid if OUTVALID_OVR_EN = 1." "0,1" bitfld.long 0x0 1. " OUTVALID_OVR_EN ,Enable software to control value of pr1_edio_data_out [31:0]." "0,1" width 0xB tree.end tree "PRU0_DEBUG" base eahb:0x54462400 width 23. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0" hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1" hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2" hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3" hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4" hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x14++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5" hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x18++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6" hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x1C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7" hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8" hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9" hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10" hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11" hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x30++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12" hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x34++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13" hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x38++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14" hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x3C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15" hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x40++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16" hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x44++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17" hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x48++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18" hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19" hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x50++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20" hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x54++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21" hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x58++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22" hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x5C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23" hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x60++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24" hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x64++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25" hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x68++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26" hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x6C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27" hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x70++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28" hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x74++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29" hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x78++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30" hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x7C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31" hexmask.long 0x0 0.--31. 1. " GPREG31 ," group.long 0x80++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0" hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x84++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1" hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x88++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2" hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x8C++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3" hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x90++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4" hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x94++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5" hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x98++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6" hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x9C++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7" hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8" hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9" hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10" hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xAC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11" hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12" hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13" hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14" hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xBC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15" hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16" hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17" hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18" hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xCC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19" hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20" hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21" hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22" hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xDC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23" hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xE0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24" hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C24_BLK_INDEX in the PRU Control register." group.long 0xE4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25" hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C25_BLK_INDEX in the PRU Control register." group.long 0xE8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26" hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C26_BLK_INDEX in the PRU Control register." group.long 0xEC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27" hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C27_BLK_INDEX in the PRU Control register." group.long 0xF0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28" hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C28_POINTER in the PRU Control register." group.long 0xF4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29" hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C29_POINTER in the PRU Control register." group.long 0xF8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30" hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C30_POINTER in the PRU Control register." group.long 0xFC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31" hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C31_POINTER in the PRU Control register." width 0xB tree.end tree "PRU1_DEBUG" base eahb:0x54464400 width 23. group.long 0x0++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0" hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1" hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x8++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2" hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0xC++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3" hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x10++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4" hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x14++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5" hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x18++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6" hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x1C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7" hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x20++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8" hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x24++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9" hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x28++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10" hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x2C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11" hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x30++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12" hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x34++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13" hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x38++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14" hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x3C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15" hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x40++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16" hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x44++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17" hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x48++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18" hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19" hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x50++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20" hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x54++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21" hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x58++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22" hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x5C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23" hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x60++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24" hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x64++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25" hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x68++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26" hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x6C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27" hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x70++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28" hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x74++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29" hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x78++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30" hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x7C++0x3 line.long 0x0 "PRU_ICSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31" hexmask.long 0x0 0.--31. 1. " GPREG31 ," group.long 0x80++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0" hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x84++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1" hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x88++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2" hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x8C++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3" hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x90++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4" hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x94++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5" hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x98++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6" hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x9C++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7" hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8" hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9" hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10" hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xAC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11" hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12" hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13" hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14" hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xBC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15" hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16" hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17" hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18" hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xCC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19" hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20" hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21" hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22" hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xDC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23" hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xE0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24" hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C24_BLK_INDEX in the PRU Control register." group.long 0xE4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25" hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C25_BLK_INDEX in the PRU Control register." group.long 0xE8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26" hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C26_BLK_INDEX in the PRU Control register." group.long 0xEC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27" hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C27_BLK_INDEX in the PRU Control register." group.long 0xF0++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28" hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C28_POINTER in the PRU Control register." group.long 0xF4++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29" hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C29_POINTER in the PRU Control register." group.long 0xF8++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30" hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C30_POINTER in the PRU Control register." group.long 0xFC++0x3 line.long 0x0 "PRU_ICSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31" hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the C31_POINTER in the PRU Control register." width 0xB tree.end tree.end endif textline ""