; -------------------------------------------------------------------------------- ; @Title: AM3352 AM3354 AM3356 AM3357 AM3358 AM3359 On-Chip Peripherals ; @Props: Released ; @Author: SKL, SLA, ZAK ; @Changelog: ; 2011-12-14 ; 2013-05-14 ; @Manufacturer: TI - Texas Instruments ; @Doc: spruh73a.pdf; spruh73g.pdf ; am335xPruReferenceGuide.pdf (SPRUHF 2012-08-05) ; @Core: Cortex-A8 ; @Chip: AM3352, AM3354, AM3356, AM3357, AM3358, AM3359 ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: peram335x.per 12528 2020-11-12 13:57:39Z bschroefel $ ; Known problems: ; PRUSS_IEP and PRUSS_MII_CFG registers description not implemented in documentation config 16. 8. width 0x0b tree "Core Registers (Cortex-A8)" width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup c15:0x0--0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup c15:0x100--0x100 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup c15:0x200--0x200 line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "ARMv6,ARMv6,ARMv6,ARMv6,ARMv7,ARMv6,ARMv6,ARMv6" bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup c15:0x300--0x300 line.long 0x0 "TLBTR,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ITLBLOCK ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DTLBLOCK ,Specifies the number of unified or data TLB lockable entries" bitfld.long 0x0 0. " S ,Unified or Separate TLBs" "Unified,Separate" rgroup c15:0x400--0x400 line.long 0x0 "MPUTR,MPU type register" rgroup c15:0x500--0x500 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitniy Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitniy Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitniy Level 0" textline " " rgroup c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup c15:0x0020++0x00 line.long 0x00 "ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0120++0x00 line.long 0x00 "ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0220++0x00 line.long 0x00 "ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0320++0x00 line.long 0x00 "ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0420++0x00 line.long 0x00 "ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup c15:0x0010++0x00 line.long 0x00 "PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup c15:0x0110++0x00 line.long 0x00 "PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup c15:0x0210++0x00 line.long 0x00 "DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup c15:0x0310++0x00 line.long 0x00 "AFR0,Auxiliary Feature Register 0" hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature" tree.end width 0x8 tree "System Control and Configuration" group c15:0x1--0x1 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable" textline " " group c15:0x101--0x101 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " L2RD ,L2 hardware reset disable" "Enable,Disable" bitfld.long 0x00 30. " L1RD ,L1 hardware reset disable" "Enable,Disable" textline " " bitfld.long 0x00 18. " CPISEL ,CP14/CP15 instruction serialization" "No,Yes" bitfld.long 0x00 17. " CPWAI ,CP14/CP15 wait on idle" "No,Yes" bitfld.long 0x00 16. " CPFL ,CP14/CP15 pipeline flush" "No,Yes" textline " " bitfld.long 0x00 15. " FETMCLK ,Force ETM clock" "No,Yes" bitfld.long 0x00 14. " FNCLK ,Force NEON clock" "No,Yes" bitfld.long 0x00 13. " FMCLK ,Force main clock" "No,Yes" textline " " bitfld.long 0x00 12. " FNSI ,Force NEON single issue" "No,Yes" bitfld.long 0x00 11. " FLSSI ,Force load/store single issue" "No,Yes" bitfld.long 0x00 10. " FSI ,Force single issue" "No,Yes" textline " " bitfld.long 0x00 9. " PLDNOP ,PLD executes as NOP" "Execute,NOP" bitfld.long 0x00 8. " WFINOP ,WFI executes as NOP" "Execute,NOP" textline " " bitfld.long 0x00 7. " DBSM ,Disable branch size mispredicts" "Enable,Disable" bitfld.long 0x00 6. " IBE ,Invalidate BTB Enable" "Disable,Enable" textline " " bitfld.long 0x00 5. " L1NEON ,NEON Data Caching Within the L1 Data Cache Enable" "Disable,Enable" bitfld.long 0x00 4. " ASA ,Speculative Accesses on AXI Enable" "Disable,Enable" textline " " bitfld.long 0x00 3. " L1PE ,L1 Cache Parity Detection Enable" "Disable,Enable" bitfld.long 0x00 1. " L2EN ,L2 Cache Enable" "Disable,Enable" bitfld.long 0x00 0. " L1ALIAS ,L1 Data Cache Hardware Alias Checks Enable" "Enable,Disable" group c15:0x201--0x201 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group c15:0x11--0x11 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" textline " " bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group c15:0x111--0x111 line.long 0x0 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" group c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " PLE ,PLE Registers Access in Nonsecure World" "Denied,Permitted" bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted" textline " " bitfld.long 0x00 16. " CL ,Lockdown Entries Allocation Within the L2 Cache in Nonsecure World" "Denied,Permitted" textline " " bitfld.long 0x00 13. " CP13 ,Coprocessor 13 in the Nonsecure World Access Permission" "Denied,Permitted" bitfld.long 0x00 12. " CP12 ,Coprocessor 12 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 9. " CP9 ,Coprocessor 9 in the Nonsecure World Access Permission" "Denied,Permitted" bitfld.long 0x00 8. " CP8 ,Coprocessor 8 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 7. " CP7 ,Coprocessor 7 in the Nonsecure World Access Permission" "Denied,Permitted" bitfld.long 0x00 6. " CP6 ,Coprocessor 6 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 5. " CP5 ,Coprocessor 5 in the Nonsecure World Access Permission" "Denied,Permitted" bitfld.long 0x00 4. " CP4 ,Coprocessor 4 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 3. " CP3 ,Coprocessor 3 in the Nonsecure World Access Permission" "Denied,Permitted" bitfld.long 0x00 2. " CP2 ,Coprocessor 2 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 1. " CP1 ,Coprocessor 1 in the Nonsecure World Access Permission" "Denied,Permitted" bitfld.long 0x00 0. " CP0 ,Coprocessor 0 in the Nonsecure World Access Permission" "Denied,Permitted" textline " " group c15:0x000c++0x00 line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address" group c15:0x10c--0x10c line.long 0x0 "MVBAR,Monitor Vector Base Address Register" hexmask.long.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address" textline " " rgroup c15:0x1C--0x1C line.long 0x0 "ISR,Interrupt status Register" bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending" bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending" bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending" tree.end width 0x0d tree "Memory Management Unit" width 8. group c15:0x1--0x1 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable" textline " " group c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address" bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" textline " " bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable" group c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address" bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" textline " " bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable" group c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable" bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable" bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000" textline " " group c15:0x3--0x3 line.long 0x0 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " group c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/decode,Reserved,Imprecise/parity/ECC,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/slave,?..." group c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/parity,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,?..." group c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" group c15:0x0015++0x00 line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register" group c15:0x0115++0x00 line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register" textline " " group c15:0x002A--0x002A line.long 0x00 "PMRRR,Primary Memory Region Remap Register" bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP" group c15:0x012A--0x012A line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate" textline " " group c15:0x000d++0x00 line.long 0x00 "FCSEPID,FCSE PID Register" hexmask.long.byte 0x00 25.--31. 1. " FCSEPID ,Process for Fast Context Switch Identification and Specification" group c15:0x10d--0x10d line.long 0x0 "CONTEXT,Context ID Register" hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID" hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID" group c15:0x020d++0x00 line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register" hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID" group c15:0x030d++0x00 line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register" hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID" group c15:0x040d++0x00 line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register" hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID" tree.end width 0xC tree "Cache Control and Configuration" rgroup c15:0x1100--0x1100 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." rgroup c15:0x1000--0x1000 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words" group c15:0x2000--0x2000 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/unified,Instruction" tree.end width 0x8 tree "L2 Cache Control and Configuration" group c15:0x1009++0x00 line.long 0x00 "L2CLR,L2 Cache Lockdown Register" bitfld.long 0x00 7. " LOCK_way_7 ,Way 7 of the L2 Cache Lockdown" "Not locked,Locked" bitfld.long 0x00 6. " LOCK_way_6 ,Way 6 of the L2 Cache Lockdown" "Not locked,Locked" bitfld.long 0x00 5. " LOCK_way_5 ,Way 5 of the L2 Cache Lockdown" "Not locked,Locked" textline " " bitfld.long 0x00 4. " LOCK_way_4 ,Way 4 of the L2 Cache Lockdown" "Not locked,Locked" bitfld.long 0x00 3. " LOCK_way_3 ,Way 3 of the L2 Cache Lockdown" "Not locked,Locked" bitfld.long 0x00 2. " LOCK_way_2 ,Way 2 of the L2 Cache Lockdown" "Not locked,Locked" textline " " bitfld.long 0x00 1. " LOCK_way_1 ,Way 1 of the L2 Cache Lockdown" "Not locked,Locked" bitfld.long 0x00 0. " LOCK_way_0 ,Way 0 of the L2 Cache Lockdown" "Not locked,Locked" group c15:0x1209++0x00 line.long 0x00 "L2CACR,L2 Cache Auxiliary Control Register" bitfld.long 0x00 28. " ECCP ,ECC/Parity Selection" "Parity,ECC" bitfld.long 0x00 27. " PLDFD ,PLD Forwarding to LS Request Disable" "Enabled,Disabled" bitfld.long 0x00 26. " PLDD ,PLD Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " WCD ,Write Combining Disable" "Enabled,Disabled" bitfld.long 0x00 24. " WADD ,External Linefill When Storing an Entire Line With Write Allocate Permission Disable" "Enabled,Disabled" bitfld.long 0x00 23. " WACD ,Combining of Data in the L2 Write Combining Buffers Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " WAD ,Allocate on Write Miss in L2 Disable" "Enabled,Disabled" bitfld.long 0x00 21. " PECCE ,Parity/ECC Enable" "Disabled,Enabled" bitfld.long 0x00 16. " L2I ,L2 Inner" "Outer,Inner" textline " " bitfld.long 0x00 6.--8. " TRAML ,Program Tag RAM Latency" "2 cycles,2 cycles,3 cycles,4 cycles,4 cycles,4 cycles,4 cycles,4 cycles" bitfld.long 0x00 0.--3. " DRAML ,Program Data RAM Latency" "3 cycles,3 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,13 cycles,13 cycles,13 cycles" textline " " rgroup c15:0x000b++0x00 line.long 0x00 "PLEISR0,PLE Identification and Status Register 0" bitfld.long 0x00 1. " CH1P ,Channel 1 Present" "Not present,Present" bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present" rgroup c15:0x010b++0x00 line.long 0x00 "PLEISR1,PLE Identification and Status Register 1" bitfld.long 0x00 1. " CH1Q ,Channel 1 Queue" "Not queued,Queued" bitfld.long 0x00 0. " CH0Q ,Channel 0 Queue" "Not queued,Queued" rgroup c15:0x020b++0x00 line.long 0x00 "PLEISR2,PLE Identification and Status Register 2" bitfld.long 0x00 1. " CH1R ,Channel 1 Run" "Not running,Running" bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running" rgroup c15:0x030b++0x00 line.long 0x00 "PLEISR3,PLE Identification and Status Register 3" bitfld.long 0x00 1. " CH1I ,Channel 1 Interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " CH0I ,Channel 0 Interrupt" "No interrupt,Interrupt" group c15:0x001b++0x00 line.long 0x00 "PLEUAR,PLE User Accessibility Register" bitfld.long 0x00 1. " U1 ,User Mode Process Access Registers for Channel 1 Permission" "Not permitted,Permitted" bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted" group c15:0x002b++0x00 line.long 0x00 "PLECNR,PLE Channel Number Register" bitfld.long 0x00 0. " CN ,PLE Channel Selection" "Channel 0,Channel 1" wgroup c15:0x003b++0x00 line.long 0x00 "PLEER0,PLE Enable Register 0" hexmask.long 0x00 0.--31. 1. " PLEE_STOP ,PLE Enable Stop" wgroup c15:0x013b++0x00 line.long 0x00 "PLEER1,PLE Enable Register 1" hexmask.long 0x00 0.--31. 1. " PLEE_START ,PLE Enable Start" wgroup c15:0x023b++0x00 line.long 0x00 "PLEER2,PLE Enable Register 2" hexmask.long 0x00 0.--31. 1. " PLEES_CLEAR ,PLE Enable Clear" group c15:0x004b++0x00 line.long 0x00 "PLECR,PLE Control Register" bitfld.long 0x00 30. " DT ,Transfer Direction" "Memory->cache,Cache->memory" bitfld.long 0x00 29. " IC ,Interrupt on Completion of the PLE Transfer" "No interrupt,Interrupt" bitfld.long 0x00 28. " IE ,Interrupt on an Error" "No interrupt,Interrupt" textline " " bitfld.long 0x00 26. " UM ,Permission Checks Type" "Privileged,User" bitfld.long 0x00 0.--2. " Wy ,L2 Cache Way for Filling Data" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7" textline " " group c15:0x005b++0x00 line.long 0x00 "PLEISAR,PLE Internal Start Address Register" hexmask.long 0x00 0.--31. 1. " PLEISA ,PLE Internal Start Address" group c15:0x007b++0x00 line.long 0x00 "PLEIEAR,PLE Internal End Address Register" hexmask.long.word 0x00 6.--17. 1. " Lines ,Number of Cache Lines Transferred" rgroup c15:0x008b++0x00 line.long 0x00 "PLECSR,PLE Channel Status Register" hexmask.long.byte 0x00 2.--8. 1. " EC ,External Address Error Status" bitfld.long 0x00 0.--1. " Status ,PLE Channel Status" "Idle,Queued,Running,Complete/error" group c15:0x00fb++0x00 line.long 0x00 "PLECIDR,PLE Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,ASID Extension to Form the Process ID and Current Process Identification" hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID of the Current Process and the Current ASID Identification" tree.end width 12. tree "System Performance Monitor" group c15:0xC9--0xC9 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled" group c15:0x1C9--0x1C9 line.long 0x0 "CNTENS,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group c15:0x2C9--0x2C9 line.long 0x0 "CNTENC,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group c15:0x3C9--0x3C9 line.long 0x0 "FLAG,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group c15:0x4C9--0x4C9 line.long 0x0 "SWINCR,Software Increment Register" eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group c15:0x5C9--0x5C9 line.long 0x0 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,..." group c15:0xD9--0xD9 line.long 0x0 "PMCCNTR,Cycle Count Register" group c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group c15:0x02d9++0x00 line.long 0x00 "PMCNT,Performance Monitor Count Register" group c15:0xE9--0xE9 line.long 0x0 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled" group c15:0x1E9--0x1E9 line.long 0x0 "INTENS,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group c15:0x2E9--0x2E9 line.long 0x0 "INTENC,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree.end width 8. tree "Debug Registers" width 10. rgroup c14:0x000--0x000 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CONTEXT ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..." textline " " bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " width 10. group c14:0x22--0x22 line.long 0x0 "DBGDSCR,Debug Status and Control Register" bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full" bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full" textline " " bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full" bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full" textline " " bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired" bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing" textline " " bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..." bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded" textline " " bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured" bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled" textline " " bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled" bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled" bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled" bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled" textline " " bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced" bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception" textline " " bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted" bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted" textline " " bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..." bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited" textline " " bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state" textline " " width 10. if (((data.long(c14:0x00))&0x01000)==0x00000) group c14:0x007--0x007 line.long 0x0 "DBGVCR,Vector Catch Register" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled" bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" else group c14:0x007--0x007 line.long 0x0 "DBGVCR,Vector Catch Register" bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled" bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled" bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" endif width 10. hgroup c14:0x020--0x020 hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)" in group c14:0x023--0x023 line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)" group c14:0x09++0x00 line.long 0x00 "DBGECR,Event Catch Register" bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled" group c14:0x0a++0x00 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal" bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal" wgroup c14:0x21++0x00 line.long 0x00 "DBGITR,Instruction Transfer Register" wgroup c14:0x24++0x00 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared" textline " " bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested" bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested" wgroup c14:0xc0++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup c14:0xc1++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented" group c14:0xc2++0x00 line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register" hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore" group c14:0xc4++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held" bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced" bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high" hgroup c14:0xc5++0x00 hide.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register" in width 11. tree "Processor Identifier Registers" rgroup c14:0x340--0x340 line.long 0x00 "CPUID,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup c14:0x341--0x341 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup c14:0x343--0x343 line.long 0x00 "TLBTYPE,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries" textline " " bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate" rgroup c14:0x348--0x348 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup c14:0x349--0x349 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup c14:0x34a--0x34a line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup c14:0x34b--0x34b line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature" rgroup c14:0x34c--0x34c line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup c14:0x34d--0x34d line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup c14:0x34e--0x34e line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup c14:0x34f--0x34f line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup c14:0x350--0x350 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c14:0x351--0x351 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..." rgroup c14:0x352--0x352 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c14:0x353--0x353 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup c14:0x354--0x354 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup c14:0x355--0x355 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end width 0xC tree "Coresight Management Registers" width 17. group c14:0x03bd++0x00 line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register" bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1" bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1" textline " " bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1" bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1" textline " " bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1" bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1" group c14:0x03be++0x00 line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register" bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1" bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1" textline " " bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1" bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1" textline " " bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1" bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1" textline " " bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1" bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1" rgroup c14:0x03bf++0x00 line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register" bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1" bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1" textline " " bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1" bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1" textline " " bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1" bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1" textline " " bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1" group c14:0x3c0--0x3c0 line.long 0x0 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group c14:0x3e8--0x3e8 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set" group c14:0x3e9--0x3e9 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared" wgroup c14:0x3ec--0x3ec line.long 0x0 "DBGLAR,Lock Access Register" rgroup c14:0x3ed--0x3ed line.long 0x0 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit" bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked" textline " " bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented" width 17. rgroup c14:0x3ee--0x3ee line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled" width 17. hgroup c14:0x3f2--0x3f2 hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)" rgroup c14:0x3f3--0x3f3 line.long 0x0 "DBGDEVTYPE,Device Type" bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup c14:0x3f8--0x3f8 line.long 0x00 "DBGPID0,Debug Peripheral ID 0" hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]" rgroup c14:0x3f9--0x3f9 line.long 0x00 "DBGPID1,Debug Peripheral ID 1" hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]" hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]" rgroup c14:0x3fa--0x3fa line.long 0x00 "DBGPID2,Debug Peripheral ID 2" hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled" hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]" rgroup c14:0x3fb--0x3fb line.long 0x00 "DBGPID3,Debug Peripheral ID 3" hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision" hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified" rgroup c14:0x3f4--0x3f4 line.long 0x00 "DBGPID4,Debug Peripheral ID 4" hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code" rgroup c14:0x3fc--0x3fc line.long 0x00 "DBGCID0,Debug Component ID 0" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0" rgroup c14:0x3fd--0x3fd line.long 0x00 "DBGCID1,Debug Component ID 1" hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1" rgroup c14:0x3fe--0x3fe line.long 0x00 "DBGCID2,Debug Component ID 2" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2" rgroup c14:0x3ff--0x3ff line.long 0x00 "DBGCID3,Debug Component ID 3" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3" tree.end tree.end width 7. tree "Breakpoint Registers" group c14:0x40++0x00 line.long 0x00 "BVR0,Breakpoint Value Register 0" group c14:0x50++0x00 line.long 0x00 "BCR0,Breakpoint Control Register 0" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x41++0x00 line.long 0x00 "BVR1,Breakpoint Value Register 1" group c14:0x51++0x00 line.long 0x00 "BCR1,Breakpoint Control Register 1" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x42++0x00 line.long 0x00 "BVR2,Breakpoint Value Register 2" group c14:0x52++0x00 line.long 0x00 "BCR2,Breakpoint Control Register 2" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x43++0x00 line.long 0x00 "BVR3,Breakpoint Value Register 3" group c14:0x53++0x00 line.long 0x00 "BCR3,Breakpoint Control Register 3" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x44++0x00 line.long 0x00 "BVR4,Breakpoint Value Register 4" group c14:0x54++0x00 line.long 0x00 "BCR4,Breakpoint Control Register 4" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x45++0x00 line.long 0x00 "BVR5,Breakpoint Value Register 5" group c14:0x55++0x00 line.long 0x00 "BCR5,Breakpoint Control Register 5" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end width 6. tree "Watchpoint Control Registers" group c14:0x60++0x00 line.long 0x00 "WVR0,Watchpoint Value Register 0" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group c14:0x70--0x70 line.long 0x0 "WCR0,Watchpoint Control Register 0" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1" bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1" bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1" bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1" bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1" bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1" bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x61++0x00 line.long 0x00 "WVR1,Watchpoint Value Register 1" hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1" group c14:0x71--0x71 line.long 0x0 "WCR1,Watchpoint Control Register 1" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1" bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1" bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1" bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1" bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1" bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1" bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x006--0x006 line.long 0x0 "WFAR,Watchpoint Fault Address Register" hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction" tree.end tree.end tree.open "PRU-ICSS" tree "PRU_ICSS_PRU_CTRL 0" base ad:0x4A322000 width 11. group.long 0x00++0x03 line.long 0x00 "CONTROL,CONTROL REGISTER" bitfld.long 0x00 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x00 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "0,1" bitfld.long 0x00 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x00 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x00 8. "SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1" bitfld.long 0x00 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1" hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.long 0x04++0x03 line.long 0x00 "STATUS,STATUS REGISTER" hexmask.long.word 0x00 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" group.long 0x08++0x03 line.long 0x00 "WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables" group.long 0x0C++0x03 line.long 0x00 "CYCLE,CYCLE COUNT" hexmask.long 0x00 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register)" group.long 0x10++0x03 line.long 0x00 "STALL,STALL COUNT" hexmask.long 0x00 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register)" group.long 0x20++0x03 line.long 0x00 "CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0" hexmask.long.byte 0x00 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." group.long 0x24++0x03 line.long 0x00 "CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1" hexmask.long.byte 0x00 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." group.long 0x28++0x03 line.long 0x00 "CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0" hexmask.long.word 0x00 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x00 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.long 0x2C++0x03 line.long 0x00 "CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1" hexmask.long.word 0x00 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x00 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0xB tree.end tree "PRU_ICSS_PRU_CTRL 1" base ad:0x4A324000 width 11. group.long 0x00++0x03 line.long 0x00 "CONTROL,CONTROL REGISTER" bitfld.long 0x00 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x00 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions" "0,1" bitfld.long 0x00 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x00 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x00 8. "SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled" "0,1" bitfld.long 0x00 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted" "0,1" hexmask.long.word 0x00 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.long 0x04++0x03 line.long 0x00 "STATUS,STATUS REGISTER" hexmask.long.word 0x00 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter" group.long 0x08++0x03 line.long 0x00 "WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x00 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables" group.long 0x0C++0x03 line.long 0x00 "CYCLE,CYCLE COUNT" hexmask.long 0x00 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register)" group.long 0x10++0x03 line.long 0x00 "STALL,STALL COUNT" hexmask.long 0x00 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register)" group.long 0x20++0x03 line.long 0x00 "CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0" hexmask.long.byte 0x00 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x00 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." group.long 0x24++0x03 line.long 0x00 "CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1" hexmask.long.byte 0x00 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x00 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." group.long 0x28++0x03 line.long 0x00 "CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0" hexmask.long.word 0x00 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x00 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.long 0x2C++0x03 line.long 0x00 "CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1" hexmask.long.word 0x00 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x00 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0xB tree.end tree "PRU_ICSS_PRU_DEBUG 0" base ad:0x4A322400 width 10. group.long 0x00++0x03 line.long 0x00 "GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0" hexmask.long 0x00 0.--31. 1. " GP_REGISTER0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x04++0x03 line.long 0x00 "GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1" hexmask.long 0x00 0.--31. 1. " GP_REGISTER1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x08++0x03 line.long 0x00 "GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2" hexmask.long 0x00 0.--31. 1. " GP_REGISTER2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x0C++0x03 line.long 0x00 "GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3" hexmask.long 0x00 0.--31. 1. " GP_REGISTER3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x10++0x03 line.long 0x00 "GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4" hexmask.long 0x00 0.--31. 1. " GP_REGISTER4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x14++0x03 line.long 0x00 "GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5" hexmask.long 0x00 0.--31. 1. " GP_REGISTER5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x18++0x03 line.long 0x00 "GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6" hexmask.long 0x00 0.--31. 1. " GP_REGISTER6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x1C++0x03 line.long 0x00 "GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7" hexmask.long 0x00 0.--31. 1. " GP_REGISTER7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x20++0x03 line.long 0x00 "GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8" hexmask.long 0x00 0.--31. 1. " GP_REGISTER8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x24++0x03 line.long 0x00 "GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9" hexmask.long 0x00 0.--31. 1. " GP_REGISTER9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x28++0x03 line.long 0x00 "GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10" hexmask.long 0x00 0.--31. 1. " GP_REGISTER10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x2C++0x03 line.long 0x00 "GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11" hexmask.long 0x00 0.--31. 1. " GP_REGISTER11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x30++0x03 line.long 0x00 "GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12" hexmask.long 0x00 0.--31. 1. " GP_REGISTER12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x34++0x03 line.long 0x00 "GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13" hexmask.long 0x00 0.--31. 1. " GP_REGISTER13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x38++0x03 line.long 0x00 "GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14" hexmask.long 0x00 0.--31. 1. " GP_REGISTER14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x3C++0x03 line.long 0x00 "GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15" hexmask.long 0x00 0.--31. 1. " GP_REGISTER15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x40++0x03 line.long 0x00 "GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16" hexmask.long 0x00 0.--31. 1. " GP_REGISTER16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x44++0x03 line.long 0x00 "GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17" hexmask.long 0x00 0.--31. 1. " GP_REGISTER17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x48++0x03 line.long 0x00 "GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18" hexmask.long 0x00 0.--31. 1. " GP_REGISTER18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4C++0x03 line.long 0x00 "GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19" hexmask.long 0x00 0.--31. 1. " GP_REGISTER19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x50++0x03 line.long 0x00 "GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20" hexmask.long 0x00 0.--31. 1. " GP_REGISTER20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x54++0x03 line.long 0x00 "GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21" hexmask.long 0x00 0.--31. 1. " GP_REGISTER21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x58++0x03 line.long 0x00 "GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22" hexmask.long 0x00 0.--31. 1. " GP_REGISTER22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x5C++0x03 line.long 0x00 "GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23" hexmask.long 0x00 0.--31. 1. " GP_REGISTER23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x60++0x03 line.long 0x00 "GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24" hexmask.long 0x00 0.--31. 1. " GP_REGISTER24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x64++0x03 line.long 0x00 "GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25" hexmask.long 0x00 0.--31. 1. " GP_REGISTER25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x68++0x03 line.long 0x00 "GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26" hexmask.long 0x00 0.--31. 1. " GP_REGISTER26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x6C++0x03 line.long 0x00 "GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27" hexmask.long 0x00 0.--31. 1. " GP_REGISTER27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x70++0x03 line.long 0x00 "GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28" hexmask.long 0x00 0.--31. 1. " GP_REGISTER28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x74++0x03 line.long 0x00 "GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29" hexmask.long 0x00 0.--31. 1. " GP_REGISTER29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x78++0x03 line.long 0x00 "GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30" hexmask.long 0x00 0.--31. 1. " GP_REGISTER30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x7C++0x03 line.long 0x00 "GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31" hexmask.long 0x00 0.--31. 1. " GPREG31 ," group.long 0x80++0x03 line.long 0x00 "CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0" hexmask.long 0x00 0.--31. 1. " CT_REGISTER0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x84++0x03 line.long 0x00 "CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1" hexmask.long 0x00 0.--31. 1. " CT_REGISTER1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x88++0x03 line.long 0x00 "CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2" hexmask.long 0x00 0.--31. 1. " CT_REGISTER2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x8C++0x03 line.long 0x00 "CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3" hexmask.long 0x00 0.--31. 1. " CT_REGISTER3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x90++0x03 line.long 0x00 "CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4" hexmask.long 0x00 0.--31. 1. " CT_REGISTER4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x94++0x03 line.long 0x00 "CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5" hexmask.long 0x00 0.--31. 1. " CT_REGISTER5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x98++0x03 line.long 0x00 "CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6" hexmask.long 0x00 0.--31. 1. " CT_REGISTER6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x9C++0x03 line.long 0x00 "CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7" hexmask.long 0x00 0.--31. 1. " CT_REGISTER7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA0++0x03 line.long 0x00 "CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8" hexmask.long 0x00 0.--31. 1. " CT_REGISTER8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA4++0x03 line.long 0x00 "CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9" hexmask.long 0x00 0.--31. 1. " CT_REGISTER9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA8++0x03 line.long 0x00 "CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10" hexmask.long 0x00 0.--31. 1. " CT_REGISTER10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xAC++0x03 line.long 0x00 "CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11" hexmask.long 0x00 0.--31. 1. " CT_REGISTER11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB0++0x03 line.long 0x00 "CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12" hexmask.long 0x00 0.--31. 1. " CT_REGISTER12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB4++0x03 line.long 0x00 "CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13" hexmask.long 0x00 0.--31. 1. " CT_REGISTER13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB8++0x03 line.long 0x00 "CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14" hexmask.long 0x00 0.--31. 1. " CT_REGISTER14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xBC++0x03 line.long 0x00 "CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15" hexmask.long 0x00 0.--31. 1. " CT_REGISTER15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC0++0x03 line.long 0x00 "CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16" hexmask.long 0x00 0.--31. 1. " CT_REGISTER16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC4++0x03 line.long 0x00 "CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17" hexmask.long 0x00 0.--31. 1. " CT_REGISTER17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC8++0x03 line.long 0x00 "CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18" hexmask.long 0x00 0.--31. 1. " CT_REGISTER18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xCC++0x03 line.long 0x00 "CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19" hexmask.long 0x00 0.--31. 1. " CT_REGISTER19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD0++0x03 line.long 0x00 "CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20" hexmask.long 0x00 0.--31. 1. " CT_REGISTER20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD4++0x03 line.long 0x00 "CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21" hexmask.long 0x00 0.--31. 1. " CT_REGISTER21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD8++0x03 line.long 0x00 "CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22" hexmask.long 0x00 0.--31. 1. " CT_REGISTER22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xDC++0x03 line.long 0x00 "CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23" hexmask.long 0x00 0.--31. 1. " CT_REGISTER23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xE0++0x03 line.long 0x00 "CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24" hexmask.long 0x00 0.--31. 1. " CT_REGISTER24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xE4++0x03 line.long 0x00 "CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25" hexmask.long 0x00 0.--31. 1. " CT_REGISTER25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xE8++0x03 line.long 0x00 "CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26" hexmask.long 0x00 0.--31. 1. " CT_REGISTER26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xEC++0x03 line.long 0x00 "CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27" hexmask.long 0x00 0.--31. 1. " CT_REGISTER27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xF0++0x03 line.long 0x00 "CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28" hexmask.long 0x00 0.--31. 1. " CT_REGISTER28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xF4++0x03 line.long 0x00 "CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29" hexmask.long 0x00 0.--31. 1. " CT_REGISTER29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xF8++0x03 line.long 0x00 "CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30" hexmask.long 0x00 0.--31. 1. " CT_REGISTER30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xFC++0x03 line.long 0x00 "CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31" hexmask.long 0x00 0.--31. 1. " CT_REGISTER31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" width 0xB tree.end tree "PRU_ICSS_PRU_DEBUG 1" base ad:0x4A324400 width 10. group.long 0x00++0x03 line.long 0x00 "GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0" hexmask.long 0x00 0.--31. 1. " GP_REGISTER0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x04++0x03 line.long 0x00 "GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1" hexmask.long 0x00 0.--31. 1. " GP_REGISTER1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x08++0x03 line.long 0x00 "GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2" hexmask.long 0x00 0.--31. 1. " GP_REGISTER2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x0C++0x03 line.long 0x00 "GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3" hexmask.long 0x00 0.--31. 1. " GP_REGISTER3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x10++0x03 line.long 0x00 "GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4" hexmask.long 0x00 0.--31. 1. " GP_REGISTER4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x14++0x03 line.long 0x00 "GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5" hexmask.long 0x00 0.--31. 1. " GP_REGISTER5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x18++0x03 line.long 0x00 "GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6" hexmask.long 0x00 0.--31. 1. " GP_REGISTER6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x1C++0x03 line.long 0x00 "GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7" hexmask.long 0x00 0.--31. 1. " GP_REGISTER7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x20++0x03 line.long 0x00 "GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8" hexmask.long 0x00 0.--31. 1. " GP_REGISTER8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x24++0x03 line.long 0x00 "GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9" hexmask.long 0x00 0.--31. 1. " GP_REGISTER9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x28++0x03 line.long 0x00 "GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10" hexmask.long 0x00 0.--31. 1. " GP_REGISTER10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x2C++0x03 line.long 0x00 "GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11" hexmask.long 0x00 0.--31. 1. " GP_REGISTER11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x30++0x03 line.long 0x00 "GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12" hexmask.long 0x00 0.--31. 1. " GP_REGISTER12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x34++0x03 line.long 0x00 "GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13" hexmask.long 0x00 0.--31. 1. " GP_REGISTER13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x38++0x03 line.long 0x00 "GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14" hexmask.long 0x00 0.--31. 1. " GP_REGISTER14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x3C++0x03 line.long 0x00 "GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15" hexmask.long 0x00 0.--31. 1. " GP_REGISTER15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x40++0x03 line.long 0x00 "GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16" hexmask.long 0x00 0.--31. 1. " GP_REGISTER16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x44++0x03 line.long 0x00 "GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17" hexmask.long 0x00 0.--31. 1. " GP_REGISTER17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x48++0x03 line.long 0x00 "GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18" hexmask.long 0x00 0.--31. 1. " GP_REGISTER18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x4C++0x03 line.long 0x00 "GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19" hexmask.long 0x00 0.--31. 1. " GP_REGISTER19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x50++0x03 line.long 0x00 "GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20" hexmask.long 0x00 0.--31. 1. " GP_REGISTER20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x54++0x03 line.long 0x00 "GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21" hexmask.long 0x00 0.--31. 1. " GP_REGISTER21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x58++0x03 line.long 0x00 "GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22" hexmask.long 0x00 0.--31. 1. " GP_REGISTER22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x5C++0x03 line.long 0x00 "GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23" hexmask.long 0x00 0.--31. 1. " GP_REGISTER23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x60++0x03 line.long 0x00 "GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24" hexmask.long 0x00 0.--31. 1. " GP_REGISTER24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x64++0x03 line.long 0x00 "GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25" hexmask.long 0x00 0.--31. 1. " GP_REGISTER25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x68++0x03 line.long 0x00 "GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26" hexmask.long 0x00 0.--31. 1. " GP_REGISTER26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x6C++0x03 line.long 0x00 "GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27" hexmask.long 0x00 0.--31. 1. " GP_REGISTER27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x70++0x03 line.long 0x00 "GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28" hexmask.long 0x00 0.--31. 1. " GP_REGISTER28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x74++0x03 line.long 0x00 "GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29" hexmask.long 0x00 0.--31. 1. " GP_REGISTER29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x78++0x03 line.long 0x00 "GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30" hexmask.long 0x00 0.--31. 1. " GP_REGISTER30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile." group.long 0x7C++0x03 line.long 0x00 "GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31" hexmask.long 0x00 0.--31. 1. " GPREG31 ," group.long 0x80++0x03 line.long 0x00 "CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0" hexmask.long 0x00 0.--31. 1. " CT_REGISTER0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x84++0x03 line.long 0x00 "CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1" hexmask.long 0x00 0.--31. 1. " CT_REGISTER1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x88++0x03 line.long 0x00 "CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2" hexmask.long 0x00 0.--31. 1. " CT_REGISTER2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x8C++0x03 line.long 0x00 "CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3" hexmask.long 0x00 0.--31. 1. " CT_REGISTER3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x90++0x03 line.long 0x00 "CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4" hexmask.long 0x00 0.--31. 1. " CT_REGISTER4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x94++0x03 line.long 0x00 "CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5" hexmask.long 0x00 0.--31. 1. " CT_REGISTER5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x98++0x03 line.long 0x00 "CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6" hexmask.long 0x00 0.--31. 1. " CT_REGISTER6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0x9C++0x03 line.long 0x00 "CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7" hexmask.long 0x00 0.--31. 1. " CT_REGISTER7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA0++0x03 line.long 0x00 "CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8" hexmask.long 0x00 0.--31. 1. " CT_REGISTER8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA4++0x03 line.long 0x00 "CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9" hexmask.long 0x00 0.--31. 1. " CT_REGISTER9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xA8++0x03 line.long 0x00 "CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10" hexmask.long 0x00 0.--31. 1. " CT_REGISTER10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xAC++0x03 line.long 0x00 "CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11" hexmask.long 0x00 0.--31. 1. " CT_REGISTER11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB0++0x03 line.long 0x00 "CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12" hexmask.long 0x00 0.--31. 1. " CT_REGISTER12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB4++0x03 line.long 0x00 "CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13" hexmask.long 0x00 0.--31. 1. " CT_REGISTER13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xB8++0x03 line.long 0x00 "CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14" hexmask.long 0x00 0.--31. 1. " CT_REGISTER14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xBC++0x03 line.long 0x00 "CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15" hexmask.long 0x00 0.--31. 1. " CT_REGISTER15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC0++0x03 line.long 0x00 "CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16" hexmask.long 0x00 0.--31. 1. " CT_REGISTER16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC4++0x03 line.long 0x00 "CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17" hexmask.long 0x00 0.--31. 1. " CT_REGISTER17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xC8++0x03 line.long 0x00 "CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18" hexmask.long 0x00 0.--31. 1. " CT_REGISTER18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xCC++0x03 line.long 0x00 "CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19" hexmask.long 0x00 0.--31. 1. " CT_REGISTER19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD0++0x03 line.long 0x00 "CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20" hexmask.long 0x00 0.--31. 1. " CT_REGISTER20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD4++0x03 line.long 0x00 "CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21" hexmask.long 0x00 0.--31. 1. " CT_REGISTER21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xD8++0x03 line.long 0x00 "CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22" hexmask.long 0x00 0.--31. 1. " CT_REGISTER22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xDC++0x03 line.long 0x00 "CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23" hexmask.long 0x00 0.--31. 1. " CT_REGISTER23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.long 0xE0++0x03 line.long 0x00 "CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24" hexmask.long 0x00 0.--31. 1. " CT_REGISTER24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xE4++0x03 line.long 0x00 "CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25" hexmask.long 0x00 0.--31. 1. " CT_REGISTER25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xE8++0x03 line.long 0x00 "CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26" hexmask.long 0x00 0.--31. 1. " CT_REGISTER26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xEC++0x03 line.long 0x00 "CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27" hexmask.long 0x00 0.--31. 1. " CT_REGISTER27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xF0++0x03 line.long 0x00 "CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28" hexmask.long 0x00 0.--31. 1. " CT_REGISTER28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xF4++0x03 line.long 0x00 "CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29" hexmask.long 0x00 0.--31. 1. " CT_REGISTER29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xF8++0x03 line.long 0x00 "CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30" hexmask.long 0x00 0.--31. 1. " CT_REGISTER30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" group.long 0xFC++0x03 line.long 0x00 "CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31" hexmask.long 0x00 0.--31. 1. " CT_REGISTER31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table" width 0xB tree.end tree "INTC (PRU-ICSS interrupt controller)" base ad:0x4A320000 width 8. group.long 0x00++0x03 line.long 0x00 "REVID,Revision ID Register" hexmask.long.byte 0x00 0.--5. 1. " REV_MINOR ,MINOR REVISION" bitfld.long 0x00 6.--7. " REV_CUSTOM ,CUSTOM REVISION" "0,1,2,3" bitfld.long 0x00 8.--10. " REV_MAJOR ,MAJOR REVISION" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11.--15. " REV_RTL ,RTL REVISIONS" "0,0x01,?..." textline " " hexmask.long.word 0x00 16.--27. 1. "REV_MODULE ,MODULE ID" bitfld.long 0x00 30.--31. " REV_SCHEME ,SCHEME" "0,1,2,3" group.long 0x04++0x03 line.long 0x00 "CR,The Control Register holds global control parameters and can forces a soft reset on the module." bitfld.long 0x00 2.--3. " NEST_MODE ,The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting " "0,1,2,3" group.long 0x10++0x03 line.long 0x00 "GER,The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable." bitfld.long 0x00 0. " ENABLE_HINT_ANY ,The current global enable value when read. Writes set the global enable." "0,1" group.long 0x1C++0x03 line.long 0x00 "GNLR,The Global Nesting Level Register allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set" hexmask.long.word 0x00 0.--8. 1. " GLB_NEST_LEVEL ,The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data." "0,1" group.long 0x20++0x03 line.long 0x00 "SISR,The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index." hexmask.long.word 0x00 0.--9. 1. " STATUS_SET_INDEX ,Writes set the status of the interrupt given in the index value. Reads return 0." group.long 0x24++0x03 line.long 0x00 "SICR,The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index." hexmask.long.word 0x00 0.--9. 1. " STATUS_CLR_INDEX ,Writes clear the status of the interrupt given in the index value. Reads return 0." group.long 0x28++0x03 line.long 0x00 "EISR,The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index." hexmask.long.word 0x00 0.--9. 1. " ENABLE_SET_INDEX ,Writes set the enable of the interrupt given in the index value. Reads return 0." group.long 0x2C++0x03 line.long 0x00 "EICR,The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index." hexmask.long.word 0x00 0.--9. 1. " ENABLE_CLR_INDEX ,Writes clear the enable of the interrupt given in the index value. Reads return 0." group.long 0x34++0x03 line.long 0x00 "HIEISR,The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled." hexmask.long.word 0x00 0.--9. 1. " HINT_ENABLE_SET_INDEX ,Writes set the enable of the host interrupt given in the index value. Reads return 0." group.long 0x38++0x03 line.long 0x00 "HIDISR,The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output." hexmask.long.word 0x00 0.--9. 1. " HINT_ENABLE_CLR_INDEX ,Writes clear the enable of the host interrupt given in the index value. Reads return 0." group.long 0x80++0x03 line.long 0x00 "GPIR,The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts." hexmask.long.word 0x00 0.--9. 1. " GLB_PRI_INTR ,The currently highest priority interrupt index pending across all the host interrupts." bitfld.long 0x00 31. " GLB_NONE ,No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending." "0,1" group.long 0x200++0x03 line.long 0x00 "SRSR0,System Interrupt Status Raw/Set Register0." hexmask.long 0x00 0.--31. 1. " RAW_STATUS_31_0 ,System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.long 0x204++0x03 line.long 0x00 "SRSR1,System Interrupt Status Raw/Set Register1" hexmask.long 0x00 0.--31. 1. " RAW_STATUS_63_32 ,System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.long 0x280++0x03 line.long 0x00 "SECR0,System Interrupt Status Enabled/Clear Register0" hexmask.long 0x00 0.--31. 1. " ENA_STATUS_31_0 ,System interrupt enabled status and clearing of the system interrupts 0 to 31" group.long 0x284++0x03 line.long 0x00 "SECR1,System Interrupt Status Enabled/Clear Register1" hexmask.long 0x00 0.--31. 1. " ENA_STATUS_63_32 ,System interrupt enabled status and clearing of the system interrupts 32 to 63" group.long 0x300++0x03 line.long 0x00 "ESR0,The System Interrupt Enable Set Register0 enables system interrupts 0 to 31 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x00 0.--31. 1. " ENABLE_SET_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.long 0x304++0x03 line.long 0x00 "ERS1,The System Interrupt Enable Set Register1 enables system interrupts 32 to 63 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x00 0.--31. 1. " ENABLE_SET_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.long 0x380++0x03 line.long 0x00 "ECR0,The System Interrupt Enable Clear Register0 disables system interrupts 0 to 31 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x00 0.--31. 1. " ENABLE_CLR_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.long 0x384++0x03 line.long 0x00 "ECR1,The System Interrupt Enable Clear Register1 disables system interrupts 32 to 63 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x00 0.--31. 1. " ENABLE_CLR_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value ( 0 = disabled, 1 = enabled). Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.long 0x400++0x03 line.long 0x00 "CMR0,The Channel Map Register0 specify the channel for the system interrupts 0 to 3. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x404++0x03 line.long 0x00 "CMR1,The Channel Map Register1 specify the channel for the system interrupts 4 to 7. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_4 ,Sets the channel for the system interrupt 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_5 ,Sets the channel for the system interrupt 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_6 ,Sets the channel for the system interrupt 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_7 ,Sets the channel for the system interrupt 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x408++0x03 line.long 0x00 "CMR2,The Channel Map Register2 specify the channel for the system interrupts 8 to 11. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_8 ,Sets the channel for the system interrupt 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_9 ,Sets the channel for the system interrupt 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_10 ,Sets the channel for the system interrupt 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_11 ,Sets the channel for the system interrupt 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40C++0x03 line.long 0x00 "CMR3,The Channel Map Register3 specify the channel for the system interrupts 12 to 15. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_12 ,Sets the channel for the system interrupt 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_13 ,Sets the channel for the system interrupt 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_14 ,Sets the channel for the system interrupt 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_15 ,Sets the channel for the system interrupt 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x410++0x03 line.long 0x00 "CMR4,The Channel Map Register4 specify the channel for the system interrupts 16 to 19. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_16 ,Sets the channel for the system interrupt 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_17 ,Sets the channel for the system interrupt 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_18 ,Sets the channel for the system interrupt 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_19 ,Sets the channel for the system interrupt 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x414++0x03 line.long 0x00 "CMR5,The Channel Map Register5 specify the channel for the system interrupts 20 to 23. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_20 ,Sets the channel for the system interrupt 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_21 ,Sets the channel for the system interrupt 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_22 ,Sets the channel for the system interrupt 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_23 ,Sets the channel for the system interrupt 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x418++0x03 line.long 0x00 "CMR6,The Channel Map Register6 specify the channel for the system interrupts 24 to 27. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_24 ,Sets the channel for the system interrupt 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_25 ,Sets the channel for the system interrupt 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_26 ,Sets the channel for the system interrupt 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_27 ,Sets the channel for the system interrupt 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x41C++0x03 line.long 0x00 "CMR7,The Channel Map Register7 specify the channel for the system interrupts 28 to 31. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_28 ,Sets the channel for the system interrupt 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_29 ,Sets the channel for the system interrupt 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_30 ,Sets the channel for the system interrupt 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_31 ,Sets the channel for the system interrupt 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x420++0x03 line.long 0x00 "CMR8,The Channel Map Register8 specify the channel for the system interrupts 32 to 35. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_32 ,Sets the channel for the system interrupt 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_33 ,Sets the channel for the system interrupt 33" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_34 ,Sets the channel for the system interrupt 34" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_35 ,Sets the channel for the system interrupt 35" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long ad:0x00000424++0x03 line.long 0x00 "CMR9,The Channel Map Register9 specify the channel for the system interrupts 36 to 39. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_36 ,Sets the channel for the system interrupt 36" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_37 ,Sets the channel for the system interrupt 37" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_38 ,Sets the channel for the system interrupt 38" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_39 ,Sets the channel for the system interrupt 39" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x428++0x03 line.long 0x00 "CMR10,The Channel Map Register10 specify the channel for the system interrupts 40 to 43. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_40 ,Sets the channel for the system interrupt 40" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_41 ,Sets the channel for the system interrupt 41" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_42 ,Sets the channel for the system interrupt 42" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_43 ,Sets the channel for the system interrupt 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x42C++0x03 line.long 0x00 "CMR11,The Channel Map Register11 specify the channel for the system interrupts 44 to 47. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_44 ,Sets the channel for the system interrupt 44" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_45 ,Sets the channel for the system interrupt 45" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_46 ,Sets the channel for the system interrupt 46" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_47 ,Sets the channel for the system interrupt 47" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x430++0x03 line.long 0x00 "CMR12,The Channel Map Register12 specify the channel for the system interrupts 48 to 51. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_48 ,Sets the channel for the system interrupt 48" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_49 ,Sets the channel for the system interrupt 49" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_50 ,Sets the channel for the system interrupt 50" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_51 ,Sets the channel for the system interrupt 51" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x434++0x03 line.long 0x00 "CMR13,The Channel Map Register13 specify the channel for the system interrupts 52 to 55. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_52 ,Sets the channel for the system interrupt 52" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_53 ,Sets the channel for the system interrupt 53" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_54 ,Sets the channel for the system interrupt 54" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_55 ,Sets the channel for the system interrupt 55" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x438++0x03 line.long 0x00 "CMR14,The Channel Map Register14 specify the channel for the system interrupts 56 to 59. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_56 ,Sets the channel for the system interrupt 56" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_57 ,Sets the channel for the system interrupt 57" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_58 ,Sets the channel for the system interrupt 58" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_59 ,Sets the channel for the system interrupt 59" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x43C++0x03 line.long 0x00 "CMR15,The Channel Map Register15 specify the channel for the system interrupts 60 to 63. There is one register per 4 system interrupts." bitfld.long 0x00 0.--3. " CH_MAP_60 ,Sets the channel for the system interrupt 60" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH_MAP_61 ,Sets the channel for the system interrupt 61" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CH_MAP_62 ,Sets the channel for the system interrupt 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " CH_MAP_63 ,Sets the channel for the system interrupt 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x03 line.long 0x00 "HMR0,The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x00 0.--3. " HINT_MAP_0 ,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " HINT_MAP_1 ,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " HINT_MAP_2 ,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " HINT_MAP_3 ,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x804++0x03 line.long 0x00 "HMR1,The Host Interrupt Map Register1 define the host interrupt for channels 4 to 7. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x00 0.--3. " HINT_MAP_4 ,HOST INTERRUPT MAP FOR CHANNEL 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " HINT_MAP_5 ,HOST INTERRUPT MAP FOR CHANNEL 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " HINT_MAP_6 ,HOST INTERRUPT MAP FOR CHANNEL 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " HINT_MAP_7 ,HOST INTERRUPT MAP FOR CHANNEL 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x808++0x03 line.long 0x00 "HMR2,The Host Interrupt Map Register2 define the host interrupt for channels 8 to 9. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x00 0.--3. " HINT_MAP_8 ,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " HINT_MAP_9 ,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x900++0x03 line.long 0x00 "HIPIR0,The Host Interrupt Prioritized Index Register0 shows the highest priority current pending interrupt for the host interrupt 0. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_0 ,HOST INT 0 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_0 ,No pending interrupt." "0,1" group.long 0x904++0x03 line.long 0x00 "HIPIR1,The Host Interrupt Prioritized Index Register1 shows the highest priority current pending interrupt for the host interrupt 1. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_1 ,HOST INT 1 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_1 ,No pending interrupt." "0,1" group.long 0x908++0x03 line.long 0x00 "HIPIR2,The Host Interrupt Prioritized Index Register2 shows the highest priority current pending interrupt for the host interrupt 2. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_2 ,HOST INT 2 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_2 ,No pending interrupt." "0,1" group.long 0x90C++0x03 line.long 0x00 "HIPIR3,The Host Interrupt Prioritized Index Register3 shows the highest priority current pending interrupt for the host interrupt 3. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_3 ,HOST INT 3 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_3 ,No pending interrupt." "0,1" group.long 0x910++0x03 line.long 0x00 "HIPIR4,The Host Interrupt Prioritized Index Register4 shows the highest priority current pending interrupt for the host interrupt 4. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_4 ,HOST INT 4 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_4 ,No pending interrupt." "0,1" group.long 0x914++0x03 line.long 0x00 "HIPIR5,The Host Interrupt Prioritized Index Register5 shows the highest priority current pending interrupt for the host interrupt 5. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_5 ,HOST INT 5 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_5 ,No pending interrupt." "0,1" group.long 0x918++0x03 line.long 0x00 "HIPIR6,The Host Interrupt Prioritized Index Register6 shows the highest priority current pending interrupt for the host interrupt 6. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_6 ,HOST INT 6 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_6 ,No pending interrupt." "0,1" group.long 0x91C++0x03 line.long 0x00 "HIPIR7,The Host Interrupt Prioritized Index Register7 shows the highest priority current pending interrupt for the host interrupt 7. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_7 ,HOST INT 7 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_7 ,No pending interrupt." "0,1" group.long 0x920++0x03 line.long 0x00 "HIPIR8,The Host Interrupt Prioritized Index Register8 shows the highest priority current pending interrupt for the host interrupt 8. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_8 ,HOST INT 8 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_8 ,No pending interrupt." "0,1" group.long 0x924++0x03 line.long 0x00 "HIPIR9,The Host Interrupt Prioritized Index Register9 shows the highest priority current pending interrupt for the host interrupt 9. There is one register per host interrupt." hexmask.long.word 0x00 0.--9. 1. " PRI_HINT_9 ,HOST INT 9 PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." bitfld.long 0x00 31. " NONE_HINT_9 ,No pending interrupt." "0,1" group.long 0xD00++0x03 line.long 0x00 "SIPR0,The System Interrupt Polarity Register0 define the polarity of the system interrupts 0 to 31. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x00 0.--31. 1. " POLARITY_31_0 ,Interrupt polarity of the system interrupts 0 to 31. 0 = active low. 1 = active high." group.long 0xD04++0x03 line.long 0x00 "SIPR1,The System Interrupt Polarity Register1 define the polarity of the system interrupts 32 to 63. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x00 0.--31. 1. " POLARITY_63_32 ,Interrupt polarity of the system interrupts 32 to 63. 0 = active low. 1 = active high." group.long 0xD80++0x03 line.long 0x00 "SITR0,The System Interrupt Type Register0 define the type of the system interrupts 0 to 31. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x00 0.--31. 1. " TYPE_31_0 ,Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.long 0xD84++0x03 line.long 0x00 "SITR1,The System Interrupt Type Register1 define the type of the system interrupts 32 to 63. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x00 0.--31. 1. " TYPE_63_32 ,Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.long 0x1100++0x03 line.long 0x00 "HINLR0,The Host Interrupt Nesting Level Register0 display and control the nesting level for host interrupt 0. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_0 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1104++0x03 line.long 0x00 "HINLR1,The Host Interrupt Nesting Level Register1 display and control the nesting level for host interrupt 1. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_1 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1108++0x03 line.long 0x00 "HINLR2,The Host Interrupt Nesting Level Register2 display and control the nesting level for host interrupt 2. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_2 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x110C++0x03 line.long 0x00 "HINLR3,The Host Interrupt Nesting Level Register3 display and control the nesting level for host interrupt 3. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_3 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1110++0x03 line.long 0x00 "HINLR4,The Host Interrupt Nesting Level Register4 display and control the nesting level for host interrupt 4. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_4 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1114++0x03 line.long 0x00 "HINLR5,The Host Interrupt Nesting Level Register5 display and control the nesting level for host interrupt 5. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_5 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1118++0x03 line.long 0x00 "HINLR6,The Host Interrupt Nesting Level Register6 display and control the nesting level for host interrupt 6. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_6 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x111C++0x03 line.long 0x00 "HINLR7,The Host Interrupt Nesting Level Register7 display and control the nesting level for host interrupt 7. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_7 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1120++0x03 line.long 0x00 "HINLR8,The Host Interrupt Nesting Level Register8 display and control the nesting level for host interrupt 8. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_8 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1124++0x03 line.long 0x00 "HINLR9,The Host Interrupt Nesting Level Register9 display and control the nesting level for host interrupt 9. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x00 0.--8. 1. " NEST_HINT_9 ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." bitfld.long 0x00 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.long 0x1500++0x03 line.long 0x00 "HIER,Host Interrupt Enable Registers" hexmask.long.word 0x00 0.--9. 1. " ENABLE_HINT ,The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled" width 0xB tree.end tree "PRU_ICSS_IEP" base ad:0x4A32E000 width 15. group.long 0x00++0x03 line.long 0x00 "GLOBAL_CFG,GLOBAL CFG" bitfld.long 0x00 0. " CNT_ENABLE ,Defines the increment value when compensation is active" "0,1" bitfld.long 0x00 4.--7. " DEFAULT_INC ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 8.--19. 1. " CMP_INC ,Counter enable 0 = Disables the counter. The counter maintains the current count. 1 = Enables the counter." group.long 0x04++0x03 line.long 0x00 "GLOBAL_STATUS,STATUS" bitfld.long 0x00 0. " CNT_OVF ,Counter overflow status. Write 1 to clear. 0 = No overflow 1 = Overflow occurred" "0,1" group.long 0x08++0x03 line.long 0x00 "COMPEN,COMPENSATION" hexmask.long.tbyte 0x00 0.--22. 1. " COMPEN_CNT ,Compensation counter" group.long 0x0C++0x03 line.long 0x00 "COUNT,COUNTER" hexmask.long 0x00 0.--31. 1. " COUNT ,32-bit count value. Increments by (DEFAULT_INC or CMP_INC) on every positive edge of iep_clk (200MHz)." group.long 0x40++0x03 line.long 0x00 "CMP_CFG,COMPARE CFG" bitfld.long 0x00 0. " CMP0_RST_CNT_EN ,Enable bit for each of the compare registers, where CMP_EN0 maps to CMP0 0 = Disables CMPn event 1 = Enables CMPn event" "0,1" hexmask.long.byte 0x00 1.--8. 1. " CMP_EN ,Enable the reset of the counter 0 = Disable 1 = Enable the reset of the counter if a CMP0 event occurs" group.long 0x44++0x03 line.long 0x00 "CMP_STATUS,COMPARE STATUS" hexmask.long.byte 0x00 0.--7. 1. " CMP_HIT ,Status bit for each of the compare registers" group.long 0x48++0x03 line.long 0x00 "CMP0,COMPARE0" hexmask.long 0x00 0.--31. 1. " CMP0 ,Compare 0 value" group.long 0x4C++0x03 line.long 0x00 "CMP1,COMPARE1" hexmask.long 0x00 0.--31. 1. " CMP1 ,Compare 1 value" group.long 0x50++0x03 line.long 0x00 "CMP2,COMPARE2" hexmask.long 0x00 0.--31. 1. " CMP2 ,Compare 2 value" group.long 0x54++0x03 line.long 0x00 "CMP3,COMPARE3" hexmask.long 0x00 0.--31. 1. " CMP3 ,Compare 3 value" group.long 0x58++0x03 line.long 0x00 "CMP4,COMPARE4" hexmask.long 0x00 0.--31. 1. " CMP4 ,Compare 4 value" group.long 0x5C++0x03 line.long 0x00 "CMP5,COMPARE5" hexmask.long 0x00 0.--31. 1. " CMP5 ,Compare 5 value" group.long 0x60++0x03 line.long 0x00 "CMP6,COMPARE6" hexmask.long 0x00 0.--31. 1. " CMP6 ,Compare 6 value" group.long 0x64++0x03 line.long 0x00 "CMP7,COMPARE7" hexmask.long 0x00 0.--31. 1. " CMP7 ,Compare 7 value" width 0xB tree.end tree "PRU_ICSS_CFG" base ad:0x4A326000 width 8. group.long 0x00++0x03 line.long 0x00 "REVID,The Revision Register contains the ID and revision information." hexmask.long 0x00 0.--31. 1. " REVID ,Revision ID" group.long 0x04++0x03 line.long 0x00 "SYSCFG,The System Configuration Register defines the power IDLE and STANDBY modes." bitfld.long 0x00 0.--1. " IDLE_MODE ,0h = Force-idle mode. 1h = No-idle mode. 2h = Smart-idle mode. 3h = Reserved." "0,1,2,3" bitfld.long 0x00 2.--3. " STANDBY_MODE ,Standby mode" "0,1,2,3" bitfld.long 0x00 4. " STANDBY_INIT ,1 = Initiate standby sequence. 0 = Enable OCP master ports." "0,1" bitfld.long 0x00 5. " SUB_MWAIT ,Status bit for wait state. 0 = Ready for Transaction 1 = Wait until 0" "0,1" group.long 0x08++0x03 line.long 0x00 "GPCFG0,The General Purpose Configuration 0 Register defines the GPI/O configuration for PRU0." bitfld.long 0x00 0.--1. " PRU0_GPI_MODE ,0h = Direct connection mode. 1h = 16-bit parallel capture mode. 2h = 28-bit shift mode. 3h = Mii_rt mode." "0,1,2,3" bitfld.long 0x00 2. " PRU0_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0 = Use the positive edge of pru0_r31_status[16] 1 = Use the negative edge of pru0_r31_status[16]" "0,1" bitfld.long 0x00 3.--7. " PRU0_GPI_DIV0 ,Divisor value (divide by PRU0_GPI_DIV0 + 1). 0h = div 1.0. 1h = div 1.5. 2h = div 2.0. .. 1eh = div 16.0. 1fh = reserved." "0,0x01,?..." bitfld.long 0x00 8.--12. " PRU0_GPI_DIV1 ,Divisor value (divide by PRU0_GPI_DIV1 + 1). 0h = div 1.0. 1h = div 1.5. 2h = div 2.0. .. 1eh = div 16.0. 1fh = reserved." "0,0x01,?..." textline " " bitfld.long 0x00 13. "PRU0_GPI_SB ,Start bit event for 28-bit shift mode" "0,1" bitfld.long 0x00 14. " PRU0_GPO_MODE ,0 = Direct output mode 1 = Serial output mode" "0,1" bitfld.long 0x00 15.--19. " PRU0_GPO_DIV0 ,Divisor value (divide by PRU0_GPO_DIV0 + 1). 0h = div 1.0. 1h = div 1.5. 2h = div 2.0. .. 1eh = div 16.0. 1fh = reserved." "0,0x01,?..." bitfld.long 0x00 20.--24. " PRU0_GPO_DIV1 ,Divisor value (divide by PRU0_GPO_DIV1 + 1). 0h = div 1.0. 1h = div 1.5. 2h = div 2.0. .. 1eh = div 16.0. 1fh = reserved." "0,0x01,?..." textline " " bitfld.long 0x00 25. "PRU0_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0 = gpo_sh0 is selected 1 = gpo_sh1 is selected" "0,1" group.long 0x0C++0x03 line.long 0x00 "GPCFG1,The General Purpose Configuration 1 Register defines the GPI/O configuration for PRU1." bitfld.long 0x00 0.--1. " PRU1_GPI_MODE ,0h = Direct connection mode. 1h = 16-bit parallel capture mode. 2h = 28-bit shift mode. 3h = Mii_rt mode." "0,1,2,3" bitfld.long 0x00 2. " PRU1_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0 = Use the positive edge of pru1_r31_status[16] 1 = Use the negative edge of pru1_r31_status[16]" "0,1" bitfld.long 0x00 3.--7. " PRU1_GPI_DIV0 ,Divisor value (divide by PRU1_GPI_DIV0 + 1). 0h = div 1.0. 1h = div 1.5. 2h = div 2.0. .. 1eh = div 16.0. 1fh = reserved." "0,0x01,?..." bitfld.long 0x00 8.--12. " PRU1_GPI_DIV1 ,Divisor value (divide by PRU1_GPI_DIV1 + 1). 0h = div 1.0. 1h = div 1.5. 2h = div 2.0. .. 1eh = div 16.0. 1fh = reserved." "0,0x01,?..." textline " " bitfld.long 0x00 13. "PRU1_GPI_SB ,28-bit shift mode start bit event" "0,1" bitfld.long 0x00 14. " PRU1_GPO_MODE ,0 = Direct output mode 1 = Serial output mode" "0,1" bitfld.long 0x00 15.--19. " PRU1_GPO_DIV0 ,Divisor value (divide by PRU1_GPO_DIV0 + 1). 0h = div 1.0. 1h = div 1.5. 2h = div 2.0. .. 1eh = div 16.0. 1fh = reserved." "0,0x01,?..." bitfld.long 0x00 20.--24. " PRU1_GPO_DIV1 ,Divisor value (divide by PRU1_GPO_DIV1 + 1). 0h = div 1.0. 1h = div 1.5. 2h = div 2.0. .. 1eh = div 16.0. 1fh = reserved." "0,0x01,?..." textline " " bitfld.long 0x00 25. "PRU1_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0 = gpo_sh0 is selected 1 = gpo_sh1 is selected" "0,1" group.long 0x10++0x03 line.long 0x00 "CGR,The Clock Gating Register controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x1." bitfld.long 0x00 0. " PRU0_CLK_STOP_REQ ,PRU0 request to stop clock. 0 = do not request to stop Clock 1 = request to stop Clock" "0,1" bitfld.long 0x00 1. " PRU0_CLK_STOP_ACK ,Acknowledgement that PRU0 clock can be stopped. 0 = Not Ready to Gate Clock 1 = Ready to Gate Clock" "0,1" bitfld.long 0x00 2. " PRU0_CLK_EN ,PRU0 clock enable. 0 = Disable Clock 1 = Enable Clock" "0,1" bitfld.long 0x00 3. " PRU1_CLK_STOP_REQ ,PRU1 request to stop clock. 0 = do not request to stop Clock 1 = request to stop Clock" "0,1" textline " " bitfld.long 0x00 4. "PRU1_CLK_STOP_ACK ,Acknowledgement that PRU1 clock can be stopped. 0 = Not Ready to Gate Clock 1 = Ready to Gate Clock" "0,1" bitfld.long 0x00 5. " PRU1_CLK_EN ,PRU1 clock enable. 0 = Disable Clock 1 = Enable Clock" "0,1" bitfld.long 0x00 6. " INTC_CLK_STOP_REQ ,INTC request to stop clock. 0 = do not request to stop Clock 1 = request to stop Clock" "0,1" bitfld.long 0x00 7. " INTC_CLK_STOP_ACK ,Acknowledgement that INTC clock can be stopped. 0 = Not Ready to Gate Clock 1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x00 8. "INTC_CLK_EN ,INTC clock enable. 0 = Disable Clock 1 = Enable Clock" "0,1" bitfld.long 0x00 9. " UART_CLK_STOP_REQ ,UART request to stop clock. 0 = do not request to stop Clock 1 = request to stop Clock" "0,1" bitfld.long 0x00 10. " UART_CLK_STOP_ACK ,Acknowledgement that UART clock can be stopped. 0 = Not Ready to Gate Clock 1 = Ready to Gate Clock" "0,1" bitfld.long 0x00 11. " UART_CLK_EN ,UART clock enable. 0 = Disable Clock 1 = Enable Clock" "0,1" textline " " bitfld.long 0x00 12. "ECAP_CLK_STOP_REQ ,ECAP request to stop clock. 0 = do not request to stop Clock 1 = request to stop Clock" "0,1" bitfld.long 0x00 13. " ECAP_CLK_STOP_ACK ,Acknowledgement that ECAP clock can be stopped. 0 = Not Ready to Gate Clock 1 = Ready to Gate Clock" "0,1" bitfld.long 0x00 14. " ECAP_CLK_EN ,ECAP clock enable. 0 = Disable Clock 1 = Enable Clock" "0,1" bitfld.long 0x00 15. " IEP_CLK_STOP_REQ ,IEP request to stop clock. 0 = do not request to stop Clock 1 = request to stop Clock" "0,1" textline " " bitfld.long 0x00 16. "IEP_CLK_STOP_ACK ,Acknowledgement that IEP clock can be stopped. 0 = Not Ready to Gate Clock 1 = Ready to Gate Clock" "0,1" bitfld.long 0x00 17. " IEP_CLK_EN ,IEP clock enable. 0 = Disable Clock 1 = Enable Clock" "0,1" group.long 0x14++0x03 line.long 0x00 "ISRP,The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRU ICSS memory parity events. The raw status is set even if the event is not enabled." bitfld.long 0x00 0.--3. " PRU0_IMEM_PE_RAW ,PRU0 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_IRAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug) ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PRU0_DMEM_PE_RAW ,PRU0 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug) ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PRU1_IMEM_PE_RAW ,PRU1 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " PRU1_DMEM_PE_RAW ,PRU1 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. "RAM_PE_RAW ,RAM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x03 line.long 0x00 "ISP,The IRQ Status Parity Register is a snapshot of the IRQ status for the PRU ICSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced." bitfld.long 0x00 0.--3. " PRU0_IMEM_PE ,PRU0 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PRU0_DMEM_PE ,PRU0 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No(enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PRU1_IMEM_PE ,PRU1 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " PRU1_DMEM_PE ,PRU1 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. "RAM_PE ,RAM Parity Error for Byte3, Byte2, Byte1, Byte0. Note RAM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x03 line.long 0x00 "IESP,The IRQ Enable Set Parity Register enables the IRQ PRU ICSS memory parity events." bitfld.long 0x00 0.--3. " PRU0_IMEM_PE_SET ,PRU0 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PRU0_DMEM_PE_SET ,PRU0 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PRU1_IMEM_PE_SET ,PRU1 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " PRU1_DMEM_PE_SET ,PRU1 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. "RAM_PE_SET ,RAM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x03 line.long 0x00 "IECP,The IRQ Enable Clear Parity Register disables the IRQ PRU ICSS memory parity events." bitfld.long 0x00 0.--3. " PRU0_IMEM_PE_CLR ,PRU0 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action . Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PRU0_DMEM_PE_CLR ,PRU0 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PRU1_IMEM_PE_CLR ,PRU1 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " PRU1_DMEM_PE_CLR ,PRU1 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28++0x03 line.long 0x00 "PMAO,The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x0000_0000." bitfld.long 0x00 0. " PMAO_PRU0 ,PRU0 OCP Master Port Address Offset Enable. 0 = Disable address offset. 1 = Enable address offset of -0x0008_0000." "0,1" bitfld.long 0x00 1. " PMAO_PRU1 ,PRU1 OCP Master Port Address Offset Enable. 0 = Disable address offset. 1 = Enable address offset of -0x0008_0000." "0,1" group.long 0x2C++0x03 line.long 0x00 "MII_RT,The MII_RT Event Enable Register enables Ethercat (or MII_RT) mode events to the PRU ICSS INTC." bitfld.long 0x00 0. " MII_RT_EVENT_EN ,Enables the MII_RT Events to the INTC. 0 = Disabled (use external events). 1 = Enabled (use MII_RT events)." "0,1" group.long 0x30++0x03 line.long 0x00 "IEPCLK,The IEP Clock Source Register defines the source of the IEP clock." bitfld.long 0x00 0. " OCP_EN ,0 = iep_clk is the source. 1 = ocp_clk is the source." "0,1" group.long 0x40++0x03 line.long 0x00 "PIN_MX,The Pin Mux Select Register defines the state of the PRU ICSS internal pinmuxing." hexmask.long.byte 0x00 0.--7. 1. " PIN_MUX_SEL ,Defines the state of PIN_MUX_SEL [1:0] for internal pinmuxing." width 0xB tree.end tree.end tree "INTC (Interrupt Controller)" base ad:0x48200000 width 19. rgroup.long 0x000++0x03 line.long 0x00 "INTC_REVISION,IP Revision Code Register" bitfld.long 0x00 4.--7. " REV_MAJOR ,IP Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV_MINOR ,IP Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x010++0x03 line.long 0x00 "INTC_SYSCONFIG,OCP Interface Control Register" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "clkfree,autoClkGate" rgroup.long 0x014++0x03 line.long 0x00 "INTC_SYSSTATUS,Module Status Information Register" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "rstOngoing,rstComp" group.long 0x040++0x03 line.long 0x00 "INTC_SIR_IRQ,Currently Active IRQ Interrupt Number Register" hexmask.long 0x00 7.--31. 1. " SPURIOUSIRQ ,Spurious IRQ flag" hexmask.long.byte 0x00 0.--6. 1. " ACTIVEIRQ ,Active IRQ number" rgroup.long 0x044++0x03 line.long 0x00 "INTC_SIR_FIQ,Currently Active FIQ Interrupt Number Register" hexmask.long 0x00 7.--31. 1. " SPURIOUSFIQ ,Spurious FIQ flag" hexmask.long.byte 0x00 0.--6. 1. " ACTIVEFIQ ,Active FIQ number" wgroup.long 0x048++0x03 line.long 0x00 "INTC_CONTROL,New Interrupt Agreement Bits Register" bitfld.long 0x00 0. " NEWIRQAGR ,New IRQ generation" "nofun_w,NewIrq_w" bitfld.long 0x00 1. " NEWFIQAGR ,Reset FIQ output and enable new FIQ generation" "nofun_w,NewFiq_w" group.long 0x04C++0x07 line.long 0x00 "INTC_PROTECTION,Protection of the Other Registers Control Register" bitfld.long 0x00 0. " PROTECTION ,Protection mode" "ProtMDis,ProtMEnb" line.long 0x04 "INTC_IDLE,Clock Auto-idle for the Functional Clock and the Input Synchronisers Control Register" bitfld.long 0x04 1. " TURBO ,Input synchroniser clock auto-gating" "SyncFree,SyncAuto" bitfld.long 0x04 0. " FUNCIDLE ,Functional clock auto-idle mode" "FuncAuto,FuncFree" rgroup.long 0x060++0x07 line.long 0x00 "INTC_IRQ_PRIORITY,Currently Active IRQ Priority Level Register" hexmask.long 0x00 7.--31. 1. " SPURIOUSIRQFLAG ,Spurious IRQ flag" hexmask.long.byte 0x00 0.--6. 1. " IRQPRIORITY ,Current IRQ priority" line.long 0x04 "INTC_FIQ_PRIORITY,Currently Active FIQ Priority Level Register" hexmask.long 0x04 7.--31. 1. " SPURIOUSFIQFLAG ,Spurious FIQ flag" hexmask.long.byte 0x04 0.--6. 1. " FIQPRIORITY ,Current FIQ priority" group.long 0x068++0x03 line.long 0x00 "INTC_THRESHOLD,Priority Threshold Regster" hexmask.long.byte 0x00 0.--7. 1. " PRIORITYTHRESHOLD ,Priority threshold" rgroup.long 0x080++0x03 line.long 0x00 "INTC_ITR0,Interrupt Status 0 Register" bitfld.long 0x00 31. " INT_31_RAW ,Interrupt 31 (eCAP0INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 30. " INT_30_RAW ,Interrupt 30 (I2C2INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 29. " INT_29_RAW ,Interrupt 29 (MMCSD2INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 28. " INT_28_RAW ,Interrupt 28 (MMCSD1INT) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INT_27_RAW ,Interrupt 27 (PRUSS1_EVTOUT7) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 26. " INT_26_RAW ,Interrupt 26 (PRUSS1_EVTOUT6) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 25. " INT_25_RAW ,Interrupt 25 (PRUSS1_EVTOUT5) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 24. " INT_24_RAW ,Interrupt 24 (PRUSS1_EVTOUT4) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INT_23_RAW ,Interrupt 23 (PRUSS1_EVTOUT3) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 22. " INT_22_RAW ,Interrupt 22 (PRUSS1_EVTOUT2) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 21. " INT_21_RAW ,Interrupt 21 (PRUSS1_EVTOUT1) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 20. " INT_20_RAW ,Interrupt 20 (PRUSS1_EVTOUT0) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INT_19_RAW ,Interrupt 19 (USBINT1) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 18. " INT_18_RAW ,Interrupt 18 (USBINT0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 17. " INT_17_RAW ,Interrupt 17 (USBSSINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 16. " INT_16_RAW ,Interrupt 16 (ADC_TSC_GENINT) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 14. " INT_14_RAW ,Interrupt 14 (EDMAERRINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 13. " INT_13_RAW ,Interrupt 13 (EDMAMPERR) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 12. " INT_12_RAW ,Interrupt 12 (EDMACOMPINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 11. " INT_11_RAW ,Interrupt 11 (PRCMINT) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " INT_10_RAW ,Interrupt 10 (L3APPINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 9. " INT_9_RAW ,Interrupt 9 (L3DEBUG) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 8. " INT_8_RAW ,Interrupt 8 (SEC_EVNT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 4. " INT_4_RAW ,Interrupt 4 (ELM_IRQ) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INT_3_RAW ,Interrupt 3 (BENCH) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 2. " INT_2_RAW ,Interrupt 2 (COMMRX) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 1. " INT_1_RAW ,Interrupt 1 (COMMTX) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 0. " INT_0_RAW ,Interrupt 0 (EMUINT) status before masking" "No interrupt,Interrupt" group.long 0x084++0x03 line.long 0x00 "INTC_MIR0,Interrupt Mask 0 Register" setclrfld.long 0x00 31. 0x08 31. 0x04 31. " INT_31_MASK_set/clr ,Interrupt 31 (eCAP0INT) mask" "Not masked,Masked" setclrfld.long 0x00 30. 0x08 30. 0x04 30. " INT_30_MASK_set/clr ,Interrupt 30 (I2C2INT) mask" "Not masked,Masked" setclrfld.long 0x00 29. 0x08 29. 0x04 29. " INT_29_MASK_set/clr ,Interrupt 29 (MMCSD2INT) mask" "Not masked,Masked" setclrfld.long 0x00 28. 0x08 28. 0x04 28. " INT_28_MASK_set/clr ,Interrupt 28 (MMCSD1INT) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 27. 0x08 27. 0x04 27. " INT_27_MASK_set/clr ,Interrupt 27 (PRUSS1_EVTOUT7) mask" "Not masked,Masked" setclrfld.long 0x00 26. 0x08 26. 0x04 26. " INT_26_MASK_set/clr ,Interrupt 26 (PRUSS1_EVTOUT6) mask" "Not masked,Masked" setclrfld.long 0x00 25. 0x08 25. 0x04 25. " INT_25_MASK_set/clr ,Interrupt 25 (PRUSS1_EVTOUT5) mask" "Not masked,Masked" setclrfld.long 0x00 24. 0x08 24. 0x04 24. " INT_24_MASK_set/clr ,Interrupt 24 (PRUSS1_EVTOUT4) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 23. 0x08 23. 0x04 23. " INT_23_MASK_set/clr ,Interrupt 23 (PRUSS1_EVTOUT3) mask" "Not masked,Masked" setclrfld.long 0x00 22. 0x08 22. 0x04 22. " INT_22_MASK_set/clr ,Interrupt 22 (PRUSS1_EVTOUT2) mask" "Not masked,Masked" setclrfld.long 0x00 21. 0x08 21. 0x04 21. " INT_21_MASK_set/clr ,Interrupt 21 (PRUSS1_EVTOUT1) mask" "Not masked,Masked" setclrfld.long 0x00 20. 0x08 20. 0x04 20. " INT_20_MASK_set/clr ,Interrupt 20 (PRUSS1_EVTOUT0) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 19. 0x08 19. 0x04 19. " INT_19_MASK_set/clr ,Interrupt 19 (USBINT1) mask" "Not masked,Masked" setclrfld.long 0x00 18. 0x08 18. 0x04 18. " INT_18_MASK_set/clr ,Interrupt 18 (USBINT0) mask" "Not masked,Masked" setclrfld.long 0x00 17. 0x08 17. 0x04 17. " INT_17_MASK_set/clr ,Interrupt 17 (USBSSINT) mask" "Not masked,Masked" setclrfld.long 0x00 16. 0x08 16. 0x04 16. " INT_16_MASK_set/clr ,Interrupt 16 (ADC_TSC_GENINT) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 14. 0x08 14. 0x04 14. " INT_14_MASK_set/clr ,Interrupt 14 (EDMAERRINT) mask" "Not masked,Masked" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " INT_13_MASK_set/clr ,Interrupt 13 (EDMAMPERR) mask" "Not masked,Masked" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " INT_12_MASK_set/clr ,Interrupt 12 (EDMACOMPINT) mask" "Not masked,Masked" setclrfld.long 0x00 11. 0x08 11. 0x04 11. " INT_11_MASK_set/clr ,Interrupt 11 (PRCMINT) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 10. 0x08 10. 0x04 10. " INT_10_MASK_set/clr ,Interrupt 10 (L3APPINT) mask" "Not masked,Masked" setclrfld.long 0x00 9. 0x08 9. 0x04 9. " INT_9_MASK_set/clr ,Interrupt 9 (L3DEBUG) mask" "Not masked,Masked" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " INT_8_MASK_set/clr ,Interrupt 8 (SEC_EVNT) mask" "Not masked,Masked" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " INT_4_MASK_set/clr ,Interrupt 4 (ELM_IRQ) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " INT_3_MASK_set/clr ,Interrupt 3 (BENCH) mask" "Not masked,Masked" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " INT_2_MASK_set/clr ,Interrupt 2 (COMMRX) mask" "Not masked,Masked" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " INT_1_MASK_set/clr ,Interrupt 1 (COMMTX) mask" "Not masked,Masked" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " INT_0_MASK_set/clr ,Interrupt 0 (EMUINT) mask" "Not masked,Masked" group.long 0x090++0x03 line.long 0x00 "INTC_ISR_SET0,Software Interrupt Status 0 Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_31_STAT_set/clr ,Software Interrupt 31 (eCAP0INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " SINT_30_STAT_set/clr ,Software Interrupt 30 (I2C2INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " SINT_29_STAT_set/clr ,Software Interrupt 29 (MMCSD2INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " SINT_28_STAT_set/clr ,Software Interrupt 28 (MMCSD1INT) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " SINT_27_STAT_set/clr ,Software Interrupt 27 (PRUSS1_EVTOUT7) status" "No interrupt,Interrupt" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " SINT_26_STAT_set/clr ,Software Interrupt 26 (PRUSS1_EVTOUT6) status" "No interrupt,Interrupt" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " SINT_25_STAT_set/clr ,Software Interrupt 25 (PRUSS1_EVTOUT5) status" "No interrupt,Interrupt" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " SINT_24_STAT_set/clr ,Software Interrupt 24 (PRUSS1_EVTOUT4) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " SINT_23_STAT_set/clr ,Software Interrupt 23 (PRUSS1_EVTOUT3) status" "No interrupt,Interrupt" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " SINT_22_STAT_set/clr ,Software Interrupt 22 (PRUSS1_EVTOUT2) status" "No interrupt,Interrupt" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " SINT_21_STAT_set/clr ,Software Interrupt 21 (PRUSS1_EVTOUT1) status" "No interrupt,Interrupt" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " SINT_20_STAT_set/clr ,Software Interrupt 20 (PRUSS1_EVTOUT0) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " SINT_19_STAT_set/clr ,Software Interrupt 19 (USBINT1) status" "No interrupt,Interrupt" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " SINT_18_STAT_set/clr ,Software Interrupt 18 (USBINT0) status" "No interrupt,Interrupt" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " SINT_17_STAT_set/clr ,Software Interrupt 17 (USBSSINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " SINT_16_STAT_set/clr ,Software Interrupt 16 (ADC_TSC_GENINT) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 14. 0x00 14. 0x04 14. " SINT_14_STAT_set/clr ,Software Interrupt 14 (EDMAERRINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " SINT_13_STAT_set/clr ,Software Interrupt 13 (EDMAMPERR) status" "No interrupt,Interrupt" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " SINT_12_STAT_set/clr ,Software Interrupt 12 (EDMACOMPINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " SINT_11_STAT_set/clr ,Software Interrupt 11 (PRCMINT) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 10. 0x00 10. 0x04 10. " SINT_10_STAT_set/clr ,Software Interrupt 10 (L3APPINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " SINT_9_STAT_set/clr ,Software Interrupt 9 (L3DEBUG) status" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " SINT_8_STAT_set/clr ,Software Interrupt 8 (SEC_EVNT) status" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SINT_4_STAT_set/clr ,Software Interrupt 4 (ELM_IRQ) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SINT_3_STAT_set/clr ,Software Interrupt 3 (BENCH) status" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " SINT_2_STAT_set/clr ,Software Interrupt 2 (COMMRX) status" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SINT_1_STAT_set/clr ,Software Interrupt 1 (COMMTX) status" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SINT_0_STAT_set/clr ,Software Interrupt 0 (EMUINT) status" "No interrupt,Interrupt" rgroup.long 0x098++0x07 line.long 0x00 "INTC_PENDING_IRQ0,IRQ Status 0 Register" bitfld.long 0x00 31. " IRQ_31_STAT ,IRQ 31 (eCAP0INT) status after masking" "Not pending,Pending" bitfld.long 0x00 30. " IRQ_30_STAT ,IRQ 30 (I2C2INT) status after masking" "Not pending,Pending" bitfld.long 0x00 29. " IRQ_29_STAT ,IRQ 29 (MMCSD2INT) status after masking" "Not pending,Pending" bitfld.long 0x00 28. " IRQ_28_STAT ,IRQ 28 (MMCSD1INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 27. " IRQ_27_STAT ,IRQ 27 (PRUSS1_EVTOUT7) status after masking" "Not pending,Pending" bitfld.long 0x00 26. " IRQ_26_STAT ,IRQ 26 (PRUSS1_EVTOUT6) status after masking" "Not pending,Pending" bitfld.long 0x00 25. " IRQ_25_STAT ,IRQ 25 (PRUSS1_EVTOUT5) status after masking" "Not pending,Pending" bitfld.long 0x00 24. " IRQ_24_STAT ,IRQ 24 (PRUSS1_EVTOUT4) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 23. " IRQ_23_STAT ,IRQ 23 (PRUSS1_EVTOUT3) status after masking" "Not pending,Pending" bitfld.long 0x00 22. " IRQ_22_STAT ,IRQ 22 (PRUSS1_EVTOUT2) status after masking" "Not pending,Pending" bitfld.long 0x00 21. " IRQ_21_STAT ,IRQ 21 (PRUSS1_EVTOUT1) status after masking" "Not pending,Pending" bitfld.long 0x00 20. " IRQ_20_STAT ,IRQ 20 (PRUSS1_EVTOUT0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 19. " IRQ_19_STAT ,IRQ 19 (USBINT1) status after masking" "Not pending,Pending" bitfld.long 0x00 18. " IRQ_18_STAT ,IRQ 18 (USBINT0) status after masking" "Not pending,Pending" bitfld.long 0x00 17. " IRQ_17_STAT ,IRQ 17 (USBSIRQ) status after masking" "Not pending,Pending" bitfld.long 0x00 16. " IRQ_16_STAT ,IRQ 16 (ADC_TSC_GENINT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 14. " IRQ_14_STAT ,IRQ 14 (EDMAERRINT) status after masking" "Not pending,Pending" bitfld.long 0x00 13. " IRQ_13_STAT ,IRQ 13 (EDMAMPERR) status after masking" "Not pending,Pending" bitfld.long 0x00 12. " IRQ_12_STAT ,IRQ 12 (EDMACOMPINT) status after masking" "Not pending,Pending" bitfld.long 0x00 11. " IRQ_11_STAT ,IRQ 11 (PRCMINT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 10. " IRQ_10_STAT ,IRQ 10 (L3APPINT) status after masking" "Not pending,Pending" bitfld.long 0x00 9. " IRQ_9_STAT ,IRQ 9 (L3DEBUG) status after masking" "Not pending,Pending" bitfld.long 0x00 8. " IRQ_8_STAT ,IRQ 8 (SEC_EVNT) status after masking" "Not pending,Pending" bitfld.long 0x00 4. " IRQ_4_STAT ,IRQ 4 (ELM_IRQ) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 3. " IRQ_3_STAT ,IRQ 3 (BENCH) status after masking" "Not pending,Pending" bitfld.long 0x00 2. " IRQ_2_STAT ,IRQ 2 (COMMRX) status after masking" "Not pending,Pending" bitfld.long 0x00 1. " IRQ_1_STAT ,IRQ 1 (COMMTX) status after masking" "Not pending,Pending" bitfld.long 0x00 0. " IRQ_0_STAT ,IRQ 0 (EMUINT) status after masking" "Not pending,Pending" line.long 0x04 "INTC_PENDING_FIQ0,FIQ Status 0 Register" bitfld.long 0x04 31. " FIQ_31_STAT ,FIQ 31 (eCAP0INT) status after masking" "Not pending,Pending" bitfld.long 0x04 30. " FIQ_30_STAT ,FIQ 30 (I2C2INT) status after masking" "Not pending,Pending" bitfld.long 0x04 29. " FIQ_29_STAT ,FIQ 29 (MMCSD2INT) status after masking" "Not pending,Pending" bitfld.long 0x04 28. " FIQ_28_STAT ,FIQ 28 (MMCSD1INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 27. " FIQ_27_STAT ,FIQ 27 (PRUSS1_EVTOUT7) status after masking" "Not pending,Pending" bitfld.long 0x04 26. " FIQ_26_STAT ,FIQ 26 (PRUSS1_EVTOUT6) status after masking" "Not pending,Pending" bitfld.long 0x04 25. " FIQ_25_STAT ,FIQ 25 (PRUSS1_EVTOUT5) status after masking" "Not pending,Pending" bitfld.long 0x04 24. " FIQ_24_STAT ,FIQ 24 (PRUSS1_EVTOUT4) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 23. " FIQ_23_STAT ,FIQ 23 (PRUSS1_EVTOUT3) status after masking" "Not pending,Pending" bitfld.long 0x04 22. " FIQ_22_STAT ,FIQ 22 (PRUSS1_EVTOUT2) status after masking" "Not pending,Pending" bitfld.long 0x04 21. " FIQ_21_STAT ,FIQ 21 (PRUSS1_EVTOUT1) status after masking" "Not pending,Pending" bitfld.long 0x04 20. " FIQ_20_STAT ,FIQ 20 (PRUSS1_EVTOUT0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 19. " FIQ_19_STAT ,FIQ 19 (USBINT1) status after masking" "Not pending,Pending" bitfld.long 0x04 18. " FIQ_18_STAT ,FIQ 18 (USBINT0) status after masking" "Not pending,Pending" bitfld.long 0x04 17. " FIQ_17_STAT ,FIQ 17 (USBSFIQ) status after masking" "Not pending,Pending" bitfld.long 0x04 16. " FIQ_16_STAT ,FIQ 16 (ADC_TSC_GENINT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 14. " FIQ_14_STAT ,FIQ 14 (EDMAERRINT) status after masking" "Not pending,Pending" bitfld.long 0x04 13. " FIQ_13_STAT ,FIQ 13 (EDMAMPERR) status after masking" "Not pending,Pending" bitfld.long 0x04 12. " FIQ_12_STAT ,FIQ 12 (EDMACOMPINT) status after masking" "Not pending,Pending" bitfld.long 0x04 11. " FIQ_11_STAT ,FIQ 11 (PRCMINT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 10. " FIQ_10_STAT ,FIQ 10 (L3APPINT) status after masking" "Not pending,Pending" bitfld.long 0x04 9. " FIQ_9_STAT ,FIQ 9 (L3DEBUG) status after masking" "Not pending,Pending" bitfld.long 0x04 8. " FIQ_8_STAT ,FIQ 8 (SEC_EVNT) status after masking" "Not pending,Pending" bitfld.long 0x04 4. " FIQ_4_STAT ,FIQ 4 (ELM_FIQ) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 3. " FIQ_3_STAT ,FIQ 3 (BENCH) status after masking" "Not pending,Pending" bitfld.long 0x04 2. " FIQ_2_STAT ,FIQ 2 (COMMRX) status after masking" "Not pending,Pending" bitfld.long 0x04 1. " FIQ_1_STAT ,FIQ 1 (COMMTX) status after masking" "Not pending,Pending" bitfld.long 0x04 0. " FIQ_0_STAT ,FIQ 0 (EMUINT) status after masking" "Not pending,Pending" rgroup.long 0x0A0++0x03 line.long 0x00 "INTC_ITR1,Interrupt Status 1 Register" bitfld.long 0x00 31. " INT_63_RAW ,Interrupt 63 (GPIOINT3B) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 30. " INT_62_RAW ,Interrupt 62 (GPIOINT3A) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 29. " INT_61_RAW ,Interrupt 61 (eCAP2INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 28. " INT_60_RAW ,Interrupt 60 (ePWM2_TZINT) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INT_59_RAW ,Interrupt 59 (ePWM1_TZINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 26. " INT_58_RAW ,Interrupt 58 (ePWM0_TZINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 25. " INT_57_RAW ,Interrupt 57 (DCAN1_PARITY) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 24. " INT_56_RAW ,Interrupt 56 (DCAN1_INT1) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INT_55_RAW ,Interrupt 55 (DCAN1_INT0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 22. " INT_54_RAW ,Interrupt 54 (DCAN0_PARITY) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 21. " INT_53_RAW ,Interrupt 53 (DCAN0_INT1) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 20. " INT_52_RAW ,Interrupt 52 (DCAN0_INT0) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INT_47_RAW ,Interrupt 47 (eCAP1INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 14. " INT_46_RAW ,Interrupt 46 (UART5INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 13. " INT_45_RAW ,Interrupt 45 (UART4INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 12. " INT_44_RAW ,Interrupt 44 (UART3INT) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INT_43_RAW ,Interrupt 43 (3PGSWMISC0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 10. " INT_42_RAW ,Interrupt 42 (3PGSWTXINT0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 9. " INT_41_RAW ,Interrupt 41 (3PGSWRXINT0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 8. " INT_40_RAW ,Interrupt 40 (3PGSWRXTHR0) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INT_39_RAW ,Interrupt 39 (ePWM2INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 5. " INT_37_RAW ,Interrupt 37 (GFXINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 4. " INT_36_RAW ,Interrupt 36 (LCDCINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 2. " INT_34_RAW ,Interrupt 34 (USBWAKEUP) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INT_33_RAW ,Interrupt 33 (GPIOINT2B) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 0. " INT_32_RAW ,Interrupt 32 (GPIOINT2A) status before masking" "No interrupt,Interrupt" group.long 0x0A4++0x03 line.long 0x00 "INTC_MIR1,Interrupt Mask 1 Register" setclrfld.long 0x00 31. 0x08 31. 0x04 31. " INT_63_MASK_set/clr ,Interrupt 63 (GPIOINT3B) mask" "Not masked,Masked" setclrfld.long 0x00 30. 0x08 30. 0x04 30. " INT_62_MASK_set/clr ,Interrupt 62 (GPIOINT3A) mask" "Not masked,Masked" setclrfld.long 0x00 29. 0x08 29. 0x04 29. " INT_61_MASK_set/clr ,Interrupt 61 (eCAP2INT) mask" "Not masked,Masked" setclrfld.long 0x00 28. 0x08 28. 0x04 28. " INT_60_MASK_set/clr ,Interrupt 60 (ePWM2_TZINT) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 27. 0x08 27. 0x04 27. " INT_59_MASK_set/clr ,Interrupt 59 (ePWM1_TZINT) mask" "Not masked,Masked" setclrfld.long 0x00 26. 0x08 26. 0x04 26. " INT_58_MASK_set/clr ,Interrupt 58 (ePWM0_TZINT) mask" "Not masked,Masked" setclrfld.long 0x00 25. 0x08 25. 0x04 25. " INT_57_MASK_set/clr ,Interrupt 57 (DCAN1_PARITY) mask" "Not masked,Masked" setclrfld.long 0x00 24. 0x08 24. 0x04 24. " INT_56_MASK_set/clr ,Interrupt 56 (DCAN1_INT1) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 23. 0x08 23. 0x04 23. " INT_55_MASK_set/clr ,Interrupt 55 (DCAN1_INT0) mask" "Not masked,Masked" setclrfld.long 0x00 22. 0x08 22. 0x04 22. " INT_54_MASK_set/clr ,Interrupt 54 (DCAN0_PARITY) mask" "Not masked,Masked" setclrfld.long 0x00 21. 0x08 21. 0x04 21. " INT_53_MASK_set/clr ,Interrupt 53 (DCAN0_INT1) mask" "Not masked,Masked" setclrfld.long 0x00 20. 0x08 20. 0x04 20. " INT_52_MASK_set/clr ,Interrupt 52 (DCAN0_INT0) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 15. 0x08 15. 0x04 15. " INT_47_MASK_set/clr ,Interrupt 47 (eCAP1INT) mask" "Not masked,Masked" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " INT_46_MASK_set/clr ,Interrupt 46 (UART5INT) mask" "Not masked,Masked" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " INT_45_MASK_set/clr ,Interrupt 45 (UART4INT) mask" "Not masked,Masked" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " INT_44_MASK_set/clr ,Interrupt 44 (UART3INT) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 11. 0x08 11. 0x04 11. " INT_43_MASK_set/clr ,Interrupt 43 (3PGSWMISC0) mask" "Not masked,Masked" setclrfld.long 0x00 10. 0x08 10. 0x04 10. " INT_42_MASK_set/clr ,Interrupt 42 (3PGSWTXINT0) mask" "Not masked,Masked" setclrfld.long 0x00 9. 0x08 9. 0x04 9. " INT_41_MASK_set/clr ,Interrupt 41 (3PGSWRXINT0) mask" "Not masked,Masked" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " INT_40_MASK_set/clr ,Interrupt 40 (3PGSWRXTHR0) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 7. 0x08 7. 0x04 7. " INT_39_MASK_set/clr ,Interrupt 39 (ePWM2INT) mask" "Not masked,Masked" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " INT_37_MASK_set/clr ,Interrupt 37 (GFXINT) mask" "Not masked,Masked" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " INT_36_MASK_set/clr ,Interrupt 36 (LCDCINT) mask" "Not masked,Masked" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " INT_34_MASK_set/clr ,Interrupt 34 (USBWAKEUP) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " INT_33_MASK_set/clr ,Interrupt 33 (GPIOINT2B) mask" "Not masked,Masked" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " INT_32_MASK_set/clr ,Interrupt 32 (GPIOINT2A) mask" "Not masked,Masked" group.long 0x0B0++0x03 line.long 0x00 "INTC_ISR_SET1,Software Interrupt Status 1 Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_63_STAT_set/clr ,Software Interrupt 63 (GPIOINT3B) status" "No interrupt,Interrupt" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " SINT_62_STAT_set/clr ,Software Interrupt 62 (GPIOINT3A) status" "No interrupt,Interrupt" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " SINT_61_STAT_set/clr ,Software Interrupt 61 (eCAP2INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " SINT_60_STAT_set/clr ,Software Interrupt 60 (ePWM2_TZINT) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " SINT_59_STAT_set/clr ,Software Interrupt 59 (ePWM1_TZINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " SINT_58_STAT_set/clr ,Software Interrupt 58 (ePWM0_TZINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " SINT_57_STAT_set/clr ,Software Interrupt 57 (DCAN1_PARITY) status" "No interrupt,Interrupt" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " SINT_56_STAT_set/clr ,Software Interrupt 56 (DCAN1_INT1) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " SINT_55_STAT_set/clr ,Software Interrupt 55 (DCAN1_INT0) status" "No interrupt,Interrupt" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " SINT_54_STAT_set/clr ,Software Interrupt 54 (DCAN0_PARITY) status" "No interrupt,Interrupt" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " SINT_53_STAT_set/clr ,Software Interrupt 53 (DCAN0_INT1) status" "No interrupt,Interrupt" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " SINT_52_STAT_set/clr ,Software Interrupt 52 (DCAN0_INT0) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " SINT_47_STAT_set/clr ,Software Interrupt 47 (eCAP1INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " SINT_46_STAT_set/clr ,Software Interrupt 46 (UART5INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " SINT_45_STAT_set/clr ,Software Interrupt 45 (UART4INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " SINT_44_STAT_set/clr ,Software Interrupt 44 (UART3INT) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " SINT_43_STAT_set/clr ,Software Interrupt 43 (3PGSWMISC0) status" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " SINT_42_STAT_set/clr ,Software Interrupt 42 (3PGSWTXINT0) status" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " SINT_41_STAT_set/clr ,Software Interrupt 41 (3PGSWRXINT0) status" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " SINT_40_STAT_set/clr ,Software Interrupt 40 (3PGSWRXTHR0) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " SINT_39_STAT_set/clr ,Software Interrupt 39 (ePWM2INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SINT_37_STAT_set/clr ,Software Interrupt 37 (GFXINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SINT_36_STAT_set/clr ,Software Interrupt 36 (LCDCINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " SINT_34_STAT_set/clr ,Software Interrupt 34 (USBWAKEUP) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SINT_33_STAT_set/clr ,Software Interrupt 33 (GPIOINT2B) status" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SINT_32_STAT_set/clr ,Software Interrupt 32 (GPIOINT2A) status" "No interrupt,Interrupt" rgroup.long 0x0B8++0x07 line.long 0x00 "INTC_PENDING_IRQ1,IRQ Status 1 Register" bitfld.long 0x00 31. " IRQ_63_STAT ,IRQ 63 (GPIOINT3B) status after masking" "Not pending,Pending" bitfld.long 0x00 30. " IRQ_62_STAT ,IRQ 62 (GPIOINT3A) status after masking" "Not pending,Pending" bitfld.long 0x00 29. " IRQ_61_STAT ,IRQ 61 (eCAP2INT) status after masking" "Not pending,Pending" bitfld.long 0x00 28. " IRQ_60_STAT ,IRQ 60 (ePWM2_TZINT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 27. " IRQ_59_STAT ,IRQ 59 (ePWM1_TZINT) status after masking" "Not pending,Pending" bitfld.long 0x00 26. " IRQ_58_STAT ,IRQ 58 (ePWM0_TZINT) status after masking" "Not pending,Pending" bitfld.long 0x00 25. " IRQ_57_STAT ,IRQ 57 (DCAN1_PARITY) status after masking" "Not pending,Pending" bitfld.long 0x00 24. " IRQ_56_STAT ,IRQ 56 (DCAN1_INT1) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 23. " IRQ_55_STAT ,IRQ 55 (DCAN1_INT0) status after masking" "Not pending,Pending" bitfld.long 0x00 22. " IRQ_54_STAT ,IRQ 54 (DCAN0_PARITY) status after masking" "Not pending,Pending" bitfld.long 0x00 21. " IRQ_53_STAT ,IRQ 53 (DCAN0_INT1) status after masking" "Not pending,Pending" bitfld.long 0x00 20. " IRQ_52_STAT ,IRQ 52 (DCAN0_INT0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 15. " IRQ_47_STAT ,IRQ 47 (eCAP1INT) status after masking" "Not pending,Pending" bitfld.long 0x00 14. " IRQ_46_STAT ,IRQ 46 (UART5INT) status after masking" "Not pending,Pending" bitfld.long 0x00 13. " IRQ_45_STAT ,IRQ 45 (UART4INT) status after masking" "Not pending,Pending" bitfld.long 0x00 12. " IRQ_44_STAT ,IRQ 44 (UART3INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 11. " IRQ_43_STAT ,IRQ 43 (3PGSWMISC0) status after masking" "Not pending,Pending" bitfld.long 0x00 10. " IRQ_42_STAT ,IRQ 42 (3PGSWTXINT0) status after masking" "Not pending,Pending" bitfld.long 0x00 9. " IRQ_41_STAT ,IRQ 41 (3PGSWRXINT0) status after masking" "Not pending,Pending" bitfld.long 0x00 8. " IRQ_40_STAT ,IRQ 40 (3PGSWRXTHR0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 7. " IRQ_39_STAT ,IRQ 39 (ePWM2INT) status after masking" "Not pending,Pending" bitfld.long 0x00 5. " IRQ_37_STAT ,IRQ 37 (GFXINT) status after masking" "Not pending,Pending" bitfld.long 0x00 4. " IRQ_36_STAT ,IRQ 36 (LCDCINT) status after masking" "Not pending,Pending" bitfld.long 0x00 2. " IRQ_34_STAT ,IRQ 34 (USBWAKEUP) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 1. " IRQ_33_STAT ,IRQ 33 (GPIOINT2B) status after masking" "Not pending,Pending" bitfld.long 0x00 0. " IRQ_32_STAT ,IRQ 32 (GPIOINT2A) status after masking" "Not pending,Pending" line.long 0x04 "INTC_PENDING_FIQ1,FIQ Status 1 Register" bitfld.long 0x04 31. " FIQ_63_STAT ,FIQ 63 (GPIOINT3B) status after masking" "Not pending,Pending" bitfld.long 0x04 30. " FIQ_62_STAT ,FIQ 62 (GPIOINT3A) status after masking" "Not pending,Pending" bitfld.long 0x04 29. " FIQ_61_STAT ,FIQ 61 (eCAP2INT) status after masking" "Not pending,Pending" bitfld.long 0x04 28. " FIQ_60_STAT ,FIQ 60 (ePWM2_TZINT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 27. " FIQ_59_STAT ,FIQ 59 (ePWM1_TZINT) status after masking" "Not pending,Pending" bitfld.long 0x04 26. " FIQ_58_STAT ,FIQ 58 (ePWM0_TZINT) status after masking" "Not pending,Pending" bitfld.long 0x04 25. " FIQ_57_STAT ,FIQ 57 (DCAN1_PARITY) status after masking" "Not pending,Pending" bitfld.long 0x04 24. " FIQ_56_STAT ,FIQ 56 (DCAN1_INT1) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 23. " FIQ_55_STAT ,FIQ 55 (DCAN1_INT0) status after masking" "Not pending,Pending" bitfld.long 0x04 22. " FIQ_54_STAT ,FIQ 54 (DCAN0_PARITY) status after masking" "Not pending,Pending" bitfld.long 0x04 21. " FIQ_53_STAT ,FIQ 53 (DCAN0_INT1) status after masking" "Not pending,Pending" bitfld.long 0x04 20. " FIQ_52_STAT ,FIQ 52 (DCAN0_INT0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 15. " FIQ_47_STAT ,FIQ 47 (eCAP1INT) status after masking" "Not pending,Pending" bitfld.long 0x04 14. " FIQ_46_STAT ,FIQ 46 (UART5INT) status after masking" "Not pending,Pending" bitfld.long 0x04 13. " FIQ_45_STAT ,FIQ 45 (UART4INT) status after masking" "Not pending,Pending" bitfld.long 0x04 12. " FIQ_44_STAT ,FIQ 44 (UART3INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 11. " FIQ_43_STAT ,FIQ 43 (3PGSWMISC0) status after masking" "Not pending,Pending" bitfld.long 0x04 10. " FIQ_42_STAT ,FIQ 42 (3PGSWTXINT0) status after masking" "Not pending,Pending" bitfld.long 0x04 9. " FIQ_41_STAT ,FIQ 41 (3PGSWRXINT0) status after masking" "Not pending,Pending" bitfld.long 0x04 8. " FIQ_40_STAT ,FIQ 40 (3PGSWRXTHR0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 7. " FIQ_39_STAT ,FIQ 39 (ePWM2INT) status after masking" "Not pending,Pending" bitfld.long 0x04 5. " FIQ_37_STAT ,FIQ 37 (GFXINT) status after masking" "Not pending,Pending" bitfld.long 0x04 4. " FIQ_36_STAT ,FIQ 36 (LCDCINT) status after masking" "Not pending,Pending" bitfld.long 0x04 2. " FIQ_34_STAT ,FIQ 34 (USBWAKEUP) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 1. " FIQ_33_STAT ,FIQ 33 (GPIOINT2B) status after masking" "Not pending,Pending" bitfld.long 0x04 0. " FIQ_32_STAT ,FIQ 32 (GPIOINT2A) status after masking" "Not pending,Pending" rgroup.long 0x0C0++0x03 line.long 0x00 "INTC_ITR2,Interrupt Status 2 Register" bitfld.long 0x00 31. " INT_95_RAW ,Interrupt 95 (TINT7) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 30. " INT_94_RAW ,Interrupt 94 (TINT6) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 29. " INT_93_RAW ,Interrupt 93 (TINT5) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 28. " INT_92_RAW ,Interrupt 92 (TINT4) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INT_91_RAW ,Interrupt 91 (WDT1INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 26. " INT_90_RAW ,Interrupt 90 (DMA_INTR_PIN2) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 25. " INT_89_RAW ,Interrupt 89 (eQEP2INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 24. " INT_88_RAW ,Interrupt 88 (eQEP1INT) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INT_87_RAW ,Interrupt 87 (ePWM1INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 22. " INT_86_RAW ,Interrupt 86 (ePWM0INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 19. " INT_83_RAW ,Interrupt 83 (MCARXINT1) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 18. " INT_82_RAW ,Interrupt 82 (MCATXINT1) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INT_81_RAW ,Interrupt 81 (MCARXINT0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 16. " INT_80_RAW ,Interrupt 80 (MCATXINT0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 15. " INT_79_RAW ,Interrupt 79 (eQEP0INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 14. " INT_78_RAW ,Interrupt 78 (M3_TXEV) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INT_77_RAW ,Interrupt 77 (MBINT0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 12. " INT_76_RAW ,Interrupt 76 (RTCALARMINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 11. " INT_75_RAW ,Interrupt 75 (RTCINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 10. " INT_74_RAW ,Interrupt 74 (UART2INT) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INT_73_RAW ,Interrupt 73 (UART1INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 8. " INT_72_RAW ,Interrupt 72 (UART0INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 7. " INT_71_RAW ,Interrupt 71 (I2C1INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 6. " INT_70_RAW ,Interrupt 70 (I2C0INT) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INT_69_RAW ,Interrupt 69 (TINT3) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 4. " INT_68_RAW ,Interrupt 68 (TINT2) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 3. " INT_67_RAW ,Interrupt 67 (TINT1_1MS) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 2. " INT_66_RAW ,Interrupt 66 (TINT0) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INT_65_RAW ,Interrupt 65 (McSPI0INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 0. " INT_64_RAW ,Interrupt 64 (MMCSD0INT) status before masking" "No interrupt,Interrupt" group.long 0x0C4++0x03 line.long 0x00 "INTC_MIR2,Interrupt Mask 2 Register" setclrfld.long 0x00 31. 0x08 31. 0x04 31. " INT_95_MASK_set/clr ,Interrupt 95 (TINT7) mask" "Not masked,Masked" setclrfld.long 0x00 30. 0x08 30. 0x04 30. " INT_94_MASK_set/clr ,Interrupt 94 (TINT6) mask" "Not masked,Masked" setclrfld.long 0x00 29. 0x08 29. 0x04 29. " INT_93_MASK_set/clr ,Interrupt 93 (TINT5) mask" "Not masked,Masked" setclrfld.long 0x00 28. 0x08 28. 0x04 28. " INT_92_MASK_set/clr ,Interrupt 92 (TINT4) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 27. 0x08 27. 0x04 27. " INT_91_MASK_set/clr ,Interrupt 91 (WDT1INT) mask" "Not masked,Masked" setclrfld.long 0x00 26. 0x08 26. 0x04 26. " INT_90_MASK_set/clr ,Interrupt 90 (DMA_INTR_PIN2) mask" "Not masked,Masked" setclrfld.long 0x00 25. 0x08 25. 0x04 25. " INT_89_MASK_set/clr ,Interrupt 89 (eQEP2INT) mask" "Not masked,Masked" setclrfld.long 0x00 24. 0x08 24. 0x04 24. " INT_88_MASK_set/clr ,Interrupt 88 (eQEP1INT) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 23. 0x08 23. 0x04 23. " INT_87_MASK_set/clr ,Interrupt 87 (ePWM1INT) mask" "Not masked,Masked" setclrfld.long 0x00 22. 0x08 22. 0x04 22. " INT_86_MASK_set/clr ,Interrupt 86 (ePWM0INT) mask" "Not masked,Masked" setclrfld.long 0x00 21. 0x08 21. 0x04 21. " INT_85_MASK_set/clr ,Interrupt 85 () mask" "Not masked,Masked" setclrfld.long 0x00 20. 0x08 20. 0x04 20. " INT_84_MASK_set/clr ,Interrupt 84 () mask" "Not masked,Masked" textline " " setclrfld.long 0x00 19. 0x08 19. 0x04 19. " INT_83_MASK_set/clr ,Interrupt 83 (MCARXINT1) mask" "Not masked,Masked" setclrfld.long 0x00 18. 0x08 18. 0x04 18. " INT_82_MASK_set/clr ,Interrupt 82 (MCATXINT1) mask" "Not masked,Masked" setclrfld.long 0x00 17. 0x08 17. 0x04 17. " INT_81_MASK_set/clr ,Interrupt 81 (MCARXINT0) mask" "Not masked,Masked" setclrfld.long 0x00 16. 0x08 16. 0x04 16. " INT_80_MASK_set/clr ,Interrupt 80 (MCATXINT0) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 15. 0x08 15. 0x04 15. " INT_79_MASK_set/clr ,Interrupt 79 (eQEP0INT) mask" "Not masked,Masked" setclrfld.long 0x00 14. 0x08 14. 0x04 14. " INT_78_MASK_set/clr ,Interrupt 78 (M3_TXEV) mask" "Not masked,Masked" setclrfld.long 0x00 13. 0x08 13. 0x04 13. " INT_77_MASK_set/clr ,Interrupt 77 (MBINT0) mask" "Not masked,Masked" setclrfld.long 0x00 12. 0x08 12. 0x04 12. " INT_76_MASK_set/clr ,Interrupt 76 (RTCALARMINT) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 11. 0x08 11. 0x04 11. " INT_75_MASK_set/clr ,Interrupt 75 (RTCINT) mask" "Not masked,Masked" setclrfld.long 0x00 10. 0x08 10. 0x04 10. " INT_74_MASK_set/clr ,Interrupt 74 (UART2INT) mask" "Not masked,Masked" setclrfld.long 0x00 9. 0x08 9. 0x04 9. " INT_73_MASK_set/clr ,Interrupt 73 (UART1INT) mask" "Not masked,Masked" setclrfld.long 0x00 8. 0x08 8. 0x04 8. " INT_72_MASK_set/clr ,Interrupt 72 (UART0INT) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 7. 0x08 7. 0x04 7. " INT_71_MASK_set/clr ,Interrupt 71 (I2C1INT) mask" "Not masked,Masked" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " INT_70_MASK_set/clr ,Interrupt 70 (I2C0INT) mask" "Not masked,Masked" setclrfld.long 0x00 5. 0x08 5. 0x04 5. " INT_69_MASK_set/clr ,Interrupt 69 (TINT3) mask" "Not masked,Masked" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " INT_68_MASK_set/clr ,Interrupt 68 (TINT2) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " INT_67_MASK_set/clr ,Interrupt 67 (TINT1_1MS) mask" "Not masked,Masked" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " INT_66_MASK_set/clr ,Interrupt 66 (TINT0) mask" "Not masked,Masked" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " INT_65_MASK_set/clr ,Interrupt 65 (McSPI0INT) mask" "Not masked,Masked" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " INT_64_MASK_set/clr ,Interrupt 64 (MMCSD0INT) mask" "Not masked,Masked" group.long 0x0D0++0x03 line.long 0x00 "INTC_ISR_SET2,Software Interrupt Status 2 Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_95_STAT_set/clr ,Software Interrupt 95 (TINT7) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_94_STAT_set/clr ,Software Interrupt 94 (TINT6) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_93_STAT_set/clr ,Software Interrupt 93 (TINT5) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_92_STAT_set/clr ,Software Interrupt 92 (TINT4) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_91_STAT_set/clr ,Software Interrupt 91 (WDT1INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_90_STAT_set/clr ,Software Interrupt 90 (DMA_INTR_PIN2) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_89_STAT_set/clr ,Software Interrupt 89 (eQEP2INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_88_STAT_set/clr ,Software Interrupt 88 (eQEP1INT) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_87_STAT_set/clr ,Software Interrupt 87 (ePWM1INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_86_STAT_set/clr ,Software Interrupt 86 (ePWM0INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_83_STAT_set/clr ,Software Interrupt 83 (MCARXINT1) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_82_STAT_set/clr ,Software Interrupt 82 (MCATXINT1) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_81_STAT_set/clr ,Software Interrupt 81 (MCARXINT0) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_80_STAT_set/clr ,Software Interrupt 80 (MCATXINT0) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_79_STAT_set/clr ,Software Interrupt 79 (eQEP0INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_78_STAT_set/clr ,Software Interrupt 78 (M3_TXEV) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_77_STAT_set/clr ,Software Interrupt 77 (MBINT0) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_76_STAT_set/clr ,Software Interrupt 76 (RTCALARMINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_75_STAT_set/clr ,Software Interrupt 75 (RTCINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_74_STAT_set/clr ,Software Interrupt 74 (UART2INT) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_73_STAT_set/clr ,Software Interrupt 73 (UART1INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_72_STAT_set/clr ,Software Interrupt 72 (UART0INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_71_STAT_set/clr ,Software Interrupt 71 (I2C1INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_70_STAT_set/clr ,Software Interrupt 70 (I2C0INT) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_69_STAT_set/clr ,Software Interrupt 69 (TINT3) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_68_STAT_set/clr ,Software Interrupt 68 (TINT2) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_67_STAT_set/clr ,Software Interrupt 67 (TINT1_1MS) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_66_STAT_set/clr ,Software Interrupt 66 (TINT0) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_65_STAT_set/clr ,Software Interrupt 65 (McSPI0INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SINT_64_STAT_set/clr ,Software Interrupt 64 (MMCSD0INT) status" "No interrupt,Interrupt" rgroup.long 0x0D8++0x07 line.long 0x00 "INTC_PENDING_IRQ2,IRQ Status 2 Register" bitfld.long 0x00 31. " IRQ_95_STAT ,IRQ 95 (TINT7) status after masking" "Not pending,Pending" bitfld.long 0x00 30. " IRQ_94_STAT ,IRQ 94 (TINT6) status after masking" "Not pending,Pending" bitfld.long 0x00 29. " IRQ_93_STAT ,IRQ 93 (TINT5) status after masking" "Not pending,Pending" bitfld.long 0x00 28. " IRQ_92_STAT ,IRQ 92 (TINT4) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 27. " IRQ_91_STAT ,IRQ 91 (WDT1INT) status after masking" "Not pending,Pending" bitfld.long 0x00 26. " IRQ_90_STAT ,IRQ 90 (DMA_INTR_PIN2) status after masking" "Not pending,Pending" bitfld.long 0x00 25. " IRQ_89_STAT ,IRQ 89 (eQEP2INT) status after masking" "Not pending,Pending" bitfld.long 0x00 24. " IRQ_88_STAT ,IRQ 88 (eQEP1INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 23. " IRQ_87_STAT ,IRQ 87 (ePWM1INT) status after masking" "Not pending,Pending" bitfld.long 0x00 22. " IRQ_86_STAT ,IRQ 86 (ePWM0INT) status after masking" "Not pending,Pending" bitfld.long 0x00 19. " IRQ_83_STAT ,IRQ 83 (MCARXINT1) status after masking" "Not pending,Pending" bitfld.long 0x00 18. " IRQ_82_STAT ,IRQ 82 (MCATXINT1) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 17. " IRQ_81_STAT ,IRQ 81 (MCARXINT0) status after masking" "Not pending,Pending" bitfld.long 0x00 16. " IRQ_80_STAT ,IRQ 80 (MCATXINT0) status after masking" "Not pending,Pending" bitfld.long 0x00 15. " IRQ_79_STAT ,IRQ 79 (eQEP0INT) status after masking" "Not pending,Pending" bitfld.long 0x00 14. " IRQ_78_STAT ,IRQ 78 (M3_TXEV) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 13. " IRQ_77_STAT ,IRQ 77 (MBINT0) status after masking" "Not pending,Pending" bitfld.long 0x00 12. " IRQ_76_STAT ,IRQ 76 (RTCALARMINT) status after masking" "Not pending,Pending" bitfld.long 0x00 11. " IRQ_75_STAT ,IRQ 75 (RTCINT) status after masking" "Not pending,Pending" bitfld.long 0x00 10. " IRQ_74_STAT ,IRQ 74 (UART2INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 9. " IRQ_73_STAT ,IRQ 73 (UART1INT) status after masking" "Not pending,Pending" bitfld.long 0x00 8. " IRQ_72_STAT ,IRQ 72 (UART0INT) status after masking" "Not pending,Pending" bitfld.long 0x00 7. " IRQ_71_STAT ,IRQ 71 (I2C1INT) status after masking" "Not pending,Pending" bitfld.long 0x00 6. " IRQ_70_STAT ,IRQ 70 (I2C0INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 5. " IRQ_69_STAT ,IRQ 69 (TINT3) status after masking" "Not pending,Pending" bitfld.long 0x00 4. " IRQ_68_STAT ,IRQ 68 (TINT2) status after masking" "Not pending,Pending" bitfld.long 0x00 3. " IRQ_67_STAT ,IRQ 67 (TINT1_1MS) status after masking" "Not pending,Pending" bitfld.long 0x00 2. " IRQ_66_STAT ,IRQ 66 (TINT0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 1. " IRQ_65_STAT ,IRQ 65 (McSPI0INT) status after masking" "Not pending,Pending" bitfld.long 0x00 0. " IRQ_64_STAT ,IRQ 64 (MMCSD0INT) status after masking" "Not pending,Pending" line.long 0x04 "INTC_PENDING_FIQ2,FIQ Status 2 Register" bitfld.long 0x04 31. " FIQ_95_STAT ,FIQ 95 (TINT7) status after masking" "Not pending,Pending" bitfld.long 0x04 30. " FIQ_94_STAT ,FIQ 94 (TINT6) status after masking" "Not pending,Pending" bitfld.long 0x04 29. " FIQ_93_STAT ,FIQ 93 (TINT5) status after masking" "Not pending,Pending" bitfld.long 0x04 28. " FIQ_92_STAT ,FIQ 92 (TINT4) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 27. " FIQ_91_STAT ,FIQ 91 (WDT1INT) status after masking" "Not pending,Pending" bitfld.long 0x04 26. " FIQ_90_STAT ,FIQ 90 (DMA_INTR_PIN2) status after masking" "Not pending,Pending" bitfld.long 0x04 25. " FIQ_89_STAT ,FIQ 89 (eQEP2INT) status after masking" "Not pending,Pending" bitfld.long 0x04 24. " FIQ_88_STAT ,FIQ 88 (eQEP1INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 23. " FIQ_87_STAT ,FIQ 87 (ePWM1INT) status after masking" "Not pending,Pending" bitfld.long 0x04 22. " FIQ_86_STAT ,FIQ 86 (ePWM0INT) status after masking" "Not pending,Pending" bitfld.long 0x04 19. " FIQ_83_STAT ,FIQ 83 (MCARXINT1) status after masking" "Not pending,Pending" bitfld.long 0x04 18. " FIQ_82_STAT ,FIQ 82 (MCATXINT1) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 17. " FIQ_81_STAT ,FIQ 81 (MCARXINT0) status after masking" "Not pending,Pending" bitfld.long 0x04 16. " FIQ_80_STAT ,FIQ 80 (MCATXINT0) status after masking" "Not pending,Pending" bitfld.long 0x04 15. " FIQ_79_STAT ,FIQ 79 (eQEP0INT) status after masking" "Not pending,Pending" bitfld.long 0x04 14. " FIQ_78_STAT ,FIQ 78 (M3_TXEV) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 13. " FIQ_77_STAT ,FIQ 77 (MBINT0) status after masking" "Not pending,Pending" bitfld.long 0x04 12. " FIQ_76_STAT ,FIQ 76 (RTCALARMINT) status after masking" "Not pending,Pending" bitfld.long 0x04 11. " FIQ_75_STAT ,FIQ 75 (RTCINT) status after masking" "Not pending,Pending" bitfld.long 0x04 10. " FIQ_74_STAT ,FIQ 74 (UART2INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 9. " FIQ_73_STAT ,FIQ 73 (UART1INT) status after masking" "Not pending,Pending" bitfld.long 0x04 8. " FIQ_72_STAT ,FIQ 72 (UART0INT) status after masking" "Not pending,Pending" bitfld.long 0x04 7. " FIQ_71_STAT ,FIQ 71 (I2C1INT) status after masking" "Not pending,Pending" bitfld.long 0x04 6. " FIQ_70_STAT ,FIQ 70 (I2C0INT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 5. " FIQ_69_STAT ,FIQ 69 (TINT3) status after masking" "Not pending,Pending" bitfld.long 0x04 4. " FIQ_68_STAT ,FIQ 68 (TINT2) status after masking" "Not pending,Pending" bitfld.long 0x04 3. " FIQ_67_STAT ,FIQ 67 (TINT1_1MS) status after masking" "Not pending,Pending" bitfld.long 0x04 2. " FIQ_66_STAT ,FIQ 66 (TINT0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 1. " FIQ_65_STAT ,FIQ 65 (McSPI0INT) status after masking" "Not pending,Pending" bitfld.long 0x04 0. " FIQ_64_STAT ,FIQ 64 (MMCSD0INT) status after masking" "Not pending,Pending" rgroup.long 0x0E0++0x03 line.long 0x00 "INTC_ITR3,Interrupt Status 3 Register" bitfld.long 0x00 29. " INT_125_RAW ,Interrupt 125 (McSPI1INT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 28. " INT_124_RAW ,Interrupt 124 (DMA_INTR_PIN1) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INT_123_RAW ,Interrupt 123 (DMA_INTR_PIN0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 25. " INT_121_RAW ,Interrupt 121 (SMRFLX_Core) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 24. " INT_120_RAW ,Interrupt 120 (SMRFLX_MPU) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 19. " INT_115_RAW ,Interrupt 115 (ADC_TSC_PENINT) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 18. " INT_114_RAW ,Interrupt 114 (TCERRINT2) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 17. " INT_113_RAW ,Interrupt 113 (TCERRINT1) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 16. " INT_112_RAW ,Interrupt 112 (TCERRINT0) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 5. " INT_101_RAW ,Interrupt 101 (DDRERR0) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " INT_100_RAW ,Interrupt 100 (GPMCINT) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 3. " INT_99_RAW ,Interrupt 99 (GPIOINT1B) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 2. " INT_98_RAW ,Interrupt 98 (GPIOINT1A) status before masking" "No interrupt,Interrupt" bitfld.long 0x00 1. " INT_97_RAW ,Interrupt 97 (GPIOINT0B) status before masking" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " INT_96_RAW ,Interrupt 96 (GPIOINT0A) status before masking" "No interrupt,Interrupt" group.long 0x0E4++0x03 line.long 0x00 "INTC_MIR3,Interrupt Mask 3 Register" setclrfld.long 0x00 29. 0x08 29. 0x04 29. " INT_125_MASK_set/clr ,Interrupt 125 (McSPI1INT) mask" "Not masked,Masked" setclrfld.long 0x00 28. 0x08 28. 0x04 28. " INT_124_MASK_set/clr ,Interrupt 124 (DMA_INTR_PIN1) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 27. 0x08 27. 0x04 27. " INT_123_MASK_set/clr ,Interrupt 123 (DMA_INTR_PIN0) mask" "Not masked,Masked" setclrfld.long 0x00 25. 0x08 25. 0x04 25. " INT_121_MASK_set/clr ,Interrupt 121 (SMRFLX_Core) mask" "Not masked,Masked" setclrfld.long 0x00 24. 0x08 24. 0x04 24. " INT_120_MASK_set/clr ,Interrupt 120 (SMRFLX_MPU) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 19. 0x08 19. 0x04 19. " INT_115_MASK_set/clr ,Interrupt 115 (ADC_TSC_PENINT) mask" "Not masked,Masked" setclrfld.long 0x00 18. 0x08 18. 0x04 18. " INT_114_MASK_set/clr ,Interrupt 114 (TCERRINT2) mask" "Not masked,Masked" setclrfld.long 0x00 17. 0x08 17. 0x04 17. " INT_113_MASK_set/clr ,Interrupt 113 (TCERRINT1) mask" "Not masked,Masked" setclrfld.long 0x00 16. 0x08 16. 0x04 16. " INT_112_MASK_set/clr ,Interrupt 112 (TCERRINT0) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " INT_101_MASK_set/clr ,Interrupt 101 (DDRERR0) mask" "Not masked,Masked" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " INT_100_MASK_set/clr ,Interrupt 100 (GPMCINT) mask" "Not masked,Masked" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " INT_99_MASK_set/clr ,Interrupt 99 (GPIOINT1B) mask" "Not masked,Masked" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " INT_98_MASK_set/clr ,Interrupt 98 (GPIOINT1A) mask" "Not masked,Masked" setclrfld.long 0x00 1. 0x08 1. 0x04 1. " INT_97_MASK_set/clr ,Interrupt 97 (GPIOINT0B) mask" "Not masked,Masked" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " INT_96_MASK_set/clr ,Interrupt 96 (GPIOINT0A) mask" "Not masked,Masked" group.long 0x0F0++0x03 line.long 0x00 "INTC_ISR_SET3,Software Interrupt Status 3 Register" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " SINT_125_STAT_set/clr ,Software Interrupt 125 (McSPI1INT) status" "No interrupt,Interrupt" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " SINT_124_STAT_set/clr ,Software Interrupt 124 (DMA_INTR_PIN1) status" "No interrupt,Interrupt" setclrfld.long 0x00 27. 0x00 27. 0x04 27. " SINT_123_STAT_set/clr ,Software Interrupt 123 (DMA_INTR_PIN0) status" "No interrupt,Interrupt" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " SINT_121_STAT_set/clr ,Software Interrupt 121 (SMRFLX_Core) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " SINT_120_STAT_set/clr ,Software Interrupt 120 (SMRFLX_MPU) status" "No interrupt,Interrupt" setclrfld.long 0x00 19. 0x00 19. 0x04 19. " SINT_115_STAT_set/clr ,Software Interrupt 115 (ADC_TSC_PENINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " SINT_114_STAT_set/clr ,Software Interrupt 114 (TCERRINT2) status" "No interrupt,Interrupt" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " SINT_113_STAT_set/clr ,Software Interrupt 113 (TCERRINT1) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 16. 0x00 16. 0x04 16. " SINT_112_STAT_set/clr ,Software Interrupt 112 (TCERRINT0) status" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SINT_101_STAT_set/clr ,Software Interrupt 101 (DDRERR0) status" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SINT_100_STAT_set/clr ,Software Interrupt 100 (GPMCINT) status" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SINT_99_STAT_set/clr ,Software Interrupt 99 (GPIOINT1B) status" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x00 2. 0x04 2. " SINT_98_STAT_set/clr ,Software Interrupt 98 (GPIOINT1A) status" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SINT_97_STAT_set/clr ,Software Interrupt 97 (GPIOINT0B) status" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SINT_96_STAT_set/clr ,Software Interrupt 96 (GPIOINT0A) status" "No interrupt,Interrupt" rgroup.long 0x0F8++0x07 line.long 0x00 "INTC_PENDING_IRQ3,IRQ Status 3 Register" bitfld.long 0x00 29. " IRQ_125_STAT ,IRQ 125 (McSPI1INT) status after masking" "Not pending,Pending" bitfld.long 0x00 28. " IRQ_124_STAT ,IRQ 124 (DMA_INTR_PIN1) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 27. " IRQ_123_STAT ,IRQ 123 (DMA_INTR_PIN0) status after masking" "Not pending,Pending" bitfld.long 0x00 25. " IRQ_121_STAT ,IRQ 121 (SMRFLX_Core) status after masking" "Not pending,Pending" bitfld.long 0x00 24. " IRQ_120_STAT ,IRQ 120 (SMRFLX_MPU) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 19. " IRQ_115_STAT ,IRQ 115 (ADC_TSC_PENINT) status after masking" "Not pending,Pending" bitfld.long 0x00 18. " IRQ_114_STAT ,IRQ 114 (TCERRINT2) status after masking" "Not pending,Pending" bitfld.long 0x00 17. " IRQ_113_STAT ,IRQ 113 (TCERRINT1) status after masking" "Not pending,Pending" bitfld.long 0x00 16. " IRQ_112_STAT ,IRQ 112 (TCERRINT0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 5. " IRQ_101_STAT ,IRQ 101 (DDRERR0) status after masking" "Not pending,Pending" bitfld.long 0x00 4. " IRQ_100_STAT ,IRQ 100 (GPMCINT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x00 3. " IRQ_99_STAT ,IRQ 99 (GPIOINT1B) status after masking" "Not pending,Pending" bitfld.long 0x00 2. " IRQ_98_STAT ,IRQ 98 (GPIOINT1A) status after masking" "Not pending,Pending" bitfld.long 0x00 1. " IRQ_97_STAT ,IRQ 97 (GPIOINT0B) status after masking" "Not pending,Pending" bitfld.long 0x00 0. " IRQ_96_STAT ,IRQ 96 (GPIOINT0A) status after masking" "Not pending,Pending" line.long 0x04 "INTC_PENDING_FIQ3,FIQ Status 3 Register" bitfld.long 0x04 29. " FIQ_125_STAT ,FIQ 125 (McSPI1INT) status after masking" "Not pending,Pending" bitfld.long 0x04 28. " FIQ_124_STAT ,FIQ 124 (DMA_INTR_PIN1) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 27. " FIQ_123_STAT ,FIQ 123 (DMA_INTR_PIN0) status after masking" "Not pending,Pending" bitfld.long 0x04 25. " FIQ_121_STAT ,FIQ 121 (SMRFLX_Core) status after masking" "Not pending,Pending" bitfld.long 0x04 24. " FIQ_120_STAT ,FIQ 120 (SMRFLX_MPU) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 19. " FIQ_115_STAT ,FIQ 115 (ADC_TSC_PENINT) status after masking" "Not pending,Pending" bitfld.long 0x04 18. " FIQ_114_STAT ,FIQ 114 (TCERRINT2) status after masking" "Not pending,Pending" bitfld.long 0x04 17. " FIQ_113_STAT ,FIQ 113 (TCERRINT1) status after masking" "Not pending,Pending" bitfld.long 0x04 16. " FIQ_112_STAT ,FIQ 112 (TCERRINT0) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 5. " FIQ_101_STAT ,FIQ 101 (DDRERR0) status after masking" "Not pending,Pending" bitfld.long 0x04 4. " FIQ_100_STAT ,FIQ 100 (GPMCINT) status after masking" "Not pending,Pending" textline " " bitfld.long 0x04 3. " FIQ_99_STAT ,FIQ 99 (GPIOINT1B) status after masking" "Not pending,Pending" bitfld.long 0x04 2. " FIQ_98_STAT ,FIQ 98 (GPIOINT1A) status after masking" "Not pending,Pending" bitfld.long 0x04 1. " FIQ_97_STAT ,FIQ 97 (GPIOINT0B) status after masking" "Not pending,Pending" bitfld.long 0x04 0. " FIQ_96_STAT ,FIQ 96 (GPIOINT0A) status after masking" "Not pending,Pending" group.long 0x100++0x03 line.long 0x00 "INTC_ILR0,Priority and FIQ/IRQ Interrupt 0 (EMUINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 0 (EMUINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 0 (EMUINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x104++0x03 line.long 0x00 "INTC_ILR1,Priority and FIQ/IRQ Interrupt 1 (COMMTX) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 1 (COMMTX) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 1 (COMMTX) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x108++0x03 line.long 0x00 "INTC_ILR2,Priority and FIQ/IRQ Interrupt 2 (COMMRX) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 2 (COMMRX) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 2 (COMMRX) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x10C++0x03 line.long 0x00 "INTC_ILR3,Priority and FIQ/IRQ Interrupt 3 (BENCH) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 3 (BENCH) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 3 (BENCH) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x110++0x03 line.long 0x00 "INTC_ILR4,Priority and FIQ/IRQ Interrupt 4 (ELM_IRQ) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 4 (ELM_IRQ) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 4 (ELM_IRQ) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x120++0x03 line.long 0x00 "INTC_ILR8,Priority and FIQ/IRQ Interrupt 8 (SEC_EVNT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 8 (SEC_EVNT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 8 (SEC_EVNT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x124++0x03 line.long 0x00 "INTC_ILR9,Priority and FIQ/IRQ Interrupt 9 (L3DEBUG) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 9 (L3DEBUG) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 9 (L3DEBUG) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x128++0x03 line.long 0x00 "INTC_ILR10,Priority and FIQ/IRQ Interrupt 10 (L3APPINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 10 (L3APPINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 10 (L3APPINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x12C++0x03 line.long 0x00 "INTC_ILR11,Priority and FIQ/IRQ Interrupt 11 (PRCMINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 11 (PRCMINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 11 (PRCMINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x130++0x03 line.long 0x00 "INTC_ILR12,Priority and FIQ/IRQ Interrupt 12 (EDMACOMPINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 12 (EDMACOMPINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 12 (EDMACOMPINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x134++0x03 line.long 0x00 "INTC_ILR13,Priority and FIQ/IRQ Interrupt 13 (EDMAMPERR) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 13 (EDMAMPERR) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 13 (EDMAMPERR) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x138++0x03 line.long 0x00 "INTC_ILR14,Priority and FIQ/IRQ Interrupt 14 (EDMAERRINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 14 (EDMAERRINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 14 (EDMAERRINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x140++0x03 line.long 0x00 "INTC_ILR16,Priority and FIQ/IRQ Interrupt 16 (ADC_TSC_GENINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 16 (ADC_TSC_GENINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 16 (ADC_TSC_GENINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x144++0x03 line.long 0x00 "INTC_ILR17,Priority and FIQ/IRQ Interrupt 17 (USBSSINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 17 (USBSSINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 17 (USBSSINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x148++0x03 line.long 0x00 "INTC_ILR18,Priority and FIQ/IRQ Interrupt 18 (USBINT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 18 (USBINT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 18 (USBINT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x14C++0x03 line.long 0x00 "INTC_ILR19,Priority and FIQ/IRQ Interrupt 19 (USBINT1) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 19 (USBINT1) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 19 (USBINT1) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x150++0x03 line.long 0x00 "INTC_ILR20,Priority and FIQ/IRQ Interrupt 20 (PRUSS1_EVTOUT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 20 (PRUSS1_EVTOUT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 20 (PRUSS1_EVTOUT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x154++0x03 line.long 0x00 "INTC_ILR21,Priority and FIQ/IRQ Interrupt 21 (PRUSS1_EVTOUT1) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 21 (PRUSS1_EVTOUT1) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 21 (PRUSS1_EVTOUT1) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x158++0x03 line.long 0x00 "INTC_ILR22,Priority and FIQ/IRQ Interrupt 22 (PRUSS1_EVTOUT2) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 22 (PRUSS1_EVTOUT2) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 22 (PRUSS1_EVTOUT2) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x15C++0x03 line.long 0x00 "INTC_ILR23,Priority and FIQ/IRQ Interrupt 23 (PRUSS1_EVTOUT3) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 23 (PRUSS1_EVTOUT3) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 23 (PRUSS1_EVTOUT3) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x160++0x03 line.long 0x00 "INTC_ILR24,Priority and FIQ/IRQ Interrupt 24 (PRUSS1_EVTOUT4) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 24 (PRUSS1_EVTOUT4) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 24 (PRUSS1_EVTOUT4) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x164++0x03 line.long 0x00 "INTC_ILR25,Priority and FIQ/IRQ Interrupt 25 (PRUSS1_EVTOUT5) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 25 (PRUSS1_EVTOUT5) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 25 (PRUSS1_EVTOUT5) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x168++0x03 line.long 0x00 "INTC_ILR26,Priority and FIQ/IRQ Interrupt 26 (PRUSS1_EVTOUT6) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 26 (PRUSS1_EVTOUT6) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 26 (PRUSS1_EVTOUT6) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x16C++0x03 line.long 0x00 "INTC_ILR27,Priority and FIQ/IRQ Interrupt 27 (PRUSS1_EVTOUT7) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 27 (PRUSS1_EVTOUT7) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 27 (PRUSS1_EVTOUT7) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x170++0x03 line.long 0x00 "INTC_ILR28,Priority and FIQ/IRQ Interrupt 28 (MMCSD1INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 28 (MMCSD1INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 28 (MMCSD1INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x174++0x03 line.long 0x00 "INTC_ILR29,Priority and FIQ/IRQ Interrupt 29 (MMCSD2INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 29 (MMCSD2INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 29 (MMCSD2INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x178++0x03 line.long 0x00 "INTC_ILR30,Priority and FIQ/IRQ Interrupt 30 (I2C2INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 30 (I2C2INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 30 (I2C2INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x17C++0x03 line.long 0x00 "INTC_ILR31,Priority and FIQ/IRQ Interrupt 31 (eCAP0INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 31 (eCAP0INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 31 (eCAP0INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x180++0x03 line.long 0x00 "INTC_ILR32,Priority and FIQ/IRQ Interrupt 32 (GPIOINT2A) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 32 (GPIOINT2A) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 32 (GPIOINT2A) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x184++0x03 line.long 0x00 "INTC_ILR33,Priority and FIQ/IRQ Interrupt 33 (GPIOINT2B) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 33 (GPIOINT2B) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 33 (GPIOINT2B) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x188++0x03 line.long 0x00 "INTC_ILR34,Priority and FIQ/IRQ Interrupt 34 (USBWAKEUP) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 34 (USBWAKEUP) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 34 (USBWAKEUP) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x190++0x03 line.long 0x00 "INTC_ILR36,Priority and FIQ/IRQ Interrupt 36 (LCDCINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 36 (LCDCINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 36 (LCDCINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x194++0x03 line.long 0x00 "INTC_ILR37,Priority and FIQ/IRQ Interrupt 37 (GFXINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 37 (GFXINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 37 (GFXINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x19C++0x03 line.long 0x00 "INTC_ILR39,Priority and FIQ/IRQ Interrupt 39 (ePWM2INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 39 (ePWM2INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 39 (ePWM2INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1A0++0x03 line.long 0x00 "INTC_ILR40,Priority and FIQ/IRQ Interrupt 40 (3PGSWRXTHR0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 40 (3PGSWRXTHR0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 40 (3PGSWRXTHR0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1A4++0x03 line.long 0x00 "INTC_ILR41,Priority and FIQ/IRQ Interrupt 41 (3PGSWRXINT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 41 (3PGSWRXINT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 41 (3PGSWRXINT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1A8++0x03 line.long 0x00 "INTC_ILR42,Priority and FIQ/IRQ Interrupt 42 (3PGSWTXINT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 42 (3PGSWTXINT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 42 (3PGSWTXINT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1AC++0x03 line.long 0x00 "INTC_ILR43,Priority and FIQ/IRQ Interrupt 43 (3PGSWMISC0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 43 (3PGSWMISC0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 43 (3PGSWMISC0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1B0++0x03 line.long 0x00 "INTC_ILR44,Priority and FIQ/IRQ Interrupt 44 (UART3INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 44 (UART3INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 44 (UART3INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1B4++0x03 line.long 0x00 "INTC_ILR45,Priority and FIQ/IRQ Interrupt 45 (UART4INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 45 (UART4INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 45 (UART4INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1B8++0x03 line.long 0x00 "INTC_ILR46,Priority and FIQ/IRQ Interrupt 46 (UART5INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 46 (UART5INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 46 (UART5INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1BC++0x03 line.long 0x00 "INTC_ILR47,Priority and FIQ/IRQ Interrupt 47 (eCAP1INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 47 (eCAP1INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 47 (eCAP1INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1D0++0x03 line.long 0x00 "INTC_ILR52,Priority and FIQ/IRQ Interrupt 52 (DCAN0_INT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 52 (DCAN0_INT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 52 (DCAN0_INT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1D4++0x03 line.long 0x00 "INTC_ILR53,Priority and FIQ/IRQ Interrupt 53 (DCAN0_INT1) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 53 (DCAN0_INT1) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 53 (DCAN0_INT1) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1D8++0x03 line.long 0x00 "INTC_ILR54,Priority and FIQ/IRQ Interrupt 54 (DCAN0_PARITY) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 54 (DCAN0_PARITY) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 54 (DCAN0_PARITY) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1DC++0x03 line.long 0x00 "INTC_ILR55,Priority and FIQ/IRQ Interrupt 55 (DCAN1_INT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 55 (DCAN1_INT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 55 (DCAN1_INT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1E0++0x03 line.long 0x00 "INTC_ILR56,Priority and FIQ/IRQ Interrupt 56 (DCAN1_INT1) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 56 (DCAN1_INT1) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 56 (DCAN1_INT1) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1E4++0x03 line.long 0x00 "INTC_ILR57,Priority and FIQ/IRQ Interrupt 57 (DCAN1_PARITY) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 57 (DCAN1_PARITY) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 57 (DCAN1_PARITY) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1E8++0x03 line.long 0x00 "INTC_ILR58,Priority and FIQ/IRQ Interrupt 58 (ePWM0_TZINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 58 (ePWM0_TZINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 58 (ePWM0_TZINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1EC++0x03 line.long 0x00 "INTC_ILR59,Priority and FIQ/IRQ Interrupt 59 (ePWM1_TZINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 59 (ePWM1_TZINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 59 (ePWM1_TZINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1F0++0x03 line.long 0x00 "INTC_ILR60,Priority and FIQ/IRQ Interrupt 60 (ePWM2_TZINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 60 (ePWM2_TZINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 60 (ePWM2_TZINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1F4++0x03 line.long 0x00 "INTC_ILR61,Priority and FIQ/IRQ Interrupt 61 (eCAP2INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 61 (eCAP2INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 61 (eCAP2INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1F8++0x03 line.long 0x00 "INTC_ILR62,Priority and FIQ/IRQ Interrupt 62 (GPIOINT3A) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 62 (GPIOINT3A) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 62 (GPIOINT3A) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x1FC++0x03 line.long 0x00 "INTC_ILR63,Priority and FIQ/IRQ Interrupt 63 (GPIOINT3B) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 63 (GPIOINT3B) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 63 (GPIOINT3B) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x200++0x03 line.long 0x00 "INTC_ILR64,Priority and FIQ/IRQ Interrupt 64 (MMCSD0INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 64 (MMCSD0INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 64 (MMCSD0INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x204++0x03 line.long 0x00 "INTC_ILR65,Priority and FIQ/IRQ Interrupt 65 (McSPI0INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 65 (McSPI0INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 65 (McSPI0INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x208++0x03 line.long 0x00 "INTC_ILR66,Priority and FIQ/IRQ Interrupt 66 (TINT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 66 (TINT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 66 (TINT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x20C++0x03 line.long 0x00 "INTC_ILR67,Priority and FIQ/IRQ Interrupt 67 (TINT1_1MS) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 67 (TINT1_1MS) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 67 (TINT1_1MS) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x210++0x03 line.long 0x00 "INTC_ILR68,Priority and FIQ/IRQ Interrupt 68 (TINT2) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 68 (TINT2) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 68 (TINT2) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x214++0x03 line.long 0x00 "INTC_ILR69,Priority and FIQ/IRQ Interrupt 69 (TINT3) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 69 (TINT3) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 69 (TINT3) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x218++0x03 line.long 0x00 "INTC_ILR70,Priority and FIQ/IRQ Interrupt 70 (I2C0INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 70 (I2C0INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 70 (I2C0INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x21C++0x03 line.long 0x00 "INTC_ILR71,Priority and FIQ/IRQ Interrupt 71 (I2C1INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 71 (I2C1INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 71 (I2C1INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x220++0x03 line.long 0x00 "INTC_ILR72,Priority and FIQ/IRQ Interrupt 72 (UART0INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 72 (UART0INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 72 (UART0INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x224++0x03 line.long 0x00 "INTC_ILR73,Priority and FIQ/IRQ Interrupt 73 (UART1INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 73 (UART1INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 73 (UART1INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x228++0x03 line.long 0x00 "INTC_ILR74,Priority and FIQ/IRQ Interrupt 74 (UART2INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 74 (UART2INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 74 (UART2INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x22C++0x03 line.long 0x00 "INTC_ILR75,Priority and FIQ/IRQ Interrupt 75 (RTCINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 75 (RTCINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 75 (RTCINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x230++0x03 line.long 0x00 "INTC_ILR76,Priority and FIQ/IRQ Interrupt 76 (RTCALARMINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 76 (RTCALARMINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 76 (RTCALARMINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x234++0x03 line.long 0x00 "INTC_ILR77,Priority and FIQ/IRQ Interrupt 77 (MBINT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 77 (MBINT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 77 (MBINT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x238++0x03 line.long 0x00 "INTC_ILR78,Priority and FIQ/IRQ Interrupt 78 (M3_TXEV) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 78 (M3_TXEV) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 78 (M3_TXEV) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x23C++0x03 line.long 0x00 "INTC_ILR79,Priority and FIQ/IRQ Interrupt 79 (eQEP0INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 79 (eQEP0INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 79 (eQEP0INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x240++0x03 line.long 0x00 "INTC_ILR80,Priority and FIQ/IRQ Interrupt 80 (MCATXINT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 80 (MCATXINT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 80 (MCATXINT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x244++0x03 line.long 0x00 "INTC_ILR81,Priority and FIQ/IRQ Interrupt 81 (MCARXINT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 81 (MCARXINT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 81 (MCARXINT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x248++0x03 line.long 0x00 "INTC_ILR82,Priority and FIQ/IRQ Interrupt 82 (MCATXINT1) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 82 (MCATXINT1) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 82 (MCATXINT1) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x24C++0x03 line.long 0x00 "INTC_ILR83,Priority and FIQ/IRQ Interrupt 83 (MCARXINT1) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 83 (MCARXINT1) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 83 (MCARXINT1) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x258++0x03 line.long 0x00 "INTC_ILR86,Priority and FIQ/IRQ Interrupt 86 (ePWM0INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 86 (ePWM0INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 86 (ePWM0INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x25C++0x03 line.long 0x00 "INTC_ILR87,Priority and FIQ/IRQ Interrupt 87 (ePWM1INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 87 (ePWM1INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 87 (ePWM1INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x260++0x03 line.long 0x00 "INTC_ILR88,Priority and FIQ/IRQ Interrupt 88 (eQEP1INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 88 (eQEP1INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 88 (eQEP1INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x264++0x03 line.long 0x00 "INTC_ILR89,Priority and FIQ/IRQ Interrupt 89 (eQEP2INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 89 (eQEP2INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 89 (eQEP2INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x268++0x03 line.long 0x00 "INTC_ILR90,Priority and FIQ/IRQ Interrupt 90 (DMA_INTR_PIN2) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 90 (DMA_INTR_PIN2) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 90 (DMA_INTR_PIN2) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x26C++0x03 line.long 0x00 "INTC_ILR91,Priority and FIQ/IRQ Interrupt 91 (WDT1INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 91 (WDT1INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 91 (WDT1INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x270++0x03 line.long 0x00 "INTC_ILR92,Priority and FIQ/IRQ Interrupt 92 (TINT4) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 92 (TINT4) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 92 (TINT4) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x274++0x03 line.long 0x00 "INTC_ILR93,Priority and FIQ/IRQ Interrupt 93 (TINT5) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 93 (TINT5) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 93 (TINT5) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x278++0x03 line.long 0x00 "INTC_ILR94,Priority and FIQ/IRQ Interrupt 94 (TINT6) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 94 (TINT6) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 94 (TINT6) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x27C++0x03 line.long 0x00 "INTC_ILR95,Priority and FIQ/IRQ Interrupt 95 (TINT7) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 95 (TINT7) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 95 (TINT7) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x280++0x03 line.long 0x00 "INTC_ILR96,Priority and FIQ/IRQ Interrupt 96 (GPIOINT0A) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 96 (GPIOINT0A) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 96 (GPIOINT0A) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x284++0x03 line.long 0x00 "INTC_ILR97,Priority and FIQ/IRQ Interrupt 97 (GPIOINT0B) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 97 (GPIOINT0B) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 97 (GPIOINT0B) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x288++0x03 line.long 0x00 "INTC_ILR98,Priority and FIQ/IRQ Interrupt 98 (GPIOINT1A) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 98 (GPIOINT1A) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 98 (GPIOINT1A) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x28C++0x03 line.long 0x00 "INTC_ILR99,Priority and FIQ/IRQ Interrupt 99 (GPIOINT1B) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 99 (GPIOINT1B) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 99 (GPIOINT1B) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x290++0x03 line.long 0x00 "INTC_ILR100,Priority and FIQ/IRQ Interrupt 100 (GPMCINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 100 (GPMCINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 100 (GPMCINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x294++0x03 line.long 0x00 "INTC_ILR101,Priority and FIQ/IRQ Interrupt 101 (DDRERR0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 101 (DDRERR0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 101 (DDRERR0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x2C0++0x03 line.long 0x00 "INTC_ILR112,Priority and FIQ/IRQ Interrupt 112 (TCERRINT0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 112 (TCERRINT0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 112 (TCERRINT0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x2C4++0x03 line.long 0x00 "INTC_ILR113,Priority and FIQ/IRQ Interrupt 113 (TCERRINT1) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 113 (TCERRINT1) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 113 (TCERRINT1) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x2C8++0x03 line.long 0x00 "INTC_ILR114,Priority and FIQ/IRQ Interrupt 114 (TCERRINT2) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 114 (TCERRINT2) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 114 (TCERRINT2) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x2CC++0x03 line.long 0x00 "INTC_ILR115,Priority and FIQ/IRQ Interrupt 115 (ADC_TSC_PENINT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 115 (ADC_TSC_PENINT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 115 (ADC_TSC_PENINT) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x2E0++0x03 line.long 0x00 "INTC_ILR120,Priority and FIQ/IRQ Interrupt 120 (SMRFLX_MPU) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 120 (SMRFLX_MPU) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 120 (SMRFLX_MPU) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x2E4++0x03 line.long 0x00 "INTC_ILR121,Priority and FIQ/IRQ Interrupt 121 (SMRFLX_Core) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 121 (SMRFLX_Core) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 121 (SMRFLX_Core) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x2EC++0x03 line.long 0x00 "INTC_ILR123,Priority and FIQ/IRQ Interrupt 123 (DMA_INTR_PIN0) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 123 (DMA_INTR_PIN0) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 123 (DMA_INTR_PIN0) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x2F0++0x03 line.long 0x00 "INTC_ILR124,Priority and FIQ/IRQ Interrupt 124 (DMA_INTR_PIN1) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 124 (DMA_INTR_PIN1) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 124 (DMA_INTR_PIN1) IRQ FiQ mapping" "IntIRQ,IntFIQ" group.long 0x2F4++0x03 line.long 0x00 "INTC_ILR125,Priority and FIQ/IRQ Interrupt 125 (McSPI1INT) Steering Register" hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt 125 (McSPI1INT) priority" bitfld.long 0x00 0. " FIQNIRQ ,Interrupt 125 (McSPI1INT) IRQ FiQ mapping" "IntIRQ,IntFIQ" width 11. tree.end tree "GPMC (General Purpose Memory Controller)" base ad:0x50000000 width 23. tree "Miscellaneous Registers" rgroup.long 0x00++0x3 line.long 0x00 "GPMC_REVISION,IP Revision Code" hexmask.long.byte 0x00 0.--7. 1. " REV ,IP revision" group.long 0x10++0x3 sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||cpuis("AM389*")||cpuis("AM335*")||cpuis("C6A816*")||cpuis("AM387*")||cpuis("DRA6*")||cpu()=="DM8148"||cpu()=="DM8147"||cpu()=="C6A8148"||cpu()=="C6A8147"||cpu()=="C6A8143"||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP")) line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The OCP Interface" bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..." else line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The Interconnect Control" bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..." endif textline " " bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied" rgroup.long 0x14++0x3 line.long 0x00 "GPMC_SYSSTATUS,Status Information About The Module" bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed" group.long 0x18++0x7 line.long 0x00 "GPMC_IRQSTATUS,Interrupt Status Register" sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")) eventfld.long 0x00 11. " WAIT3EDGEDETECTIONSTATUS ,Status of the Wait3 Edge Detection interrupt" "Not detected,Detected" textline " " eventfld.long 0x00 10. " WAIT2EDGEDETECTIONSTATUS ,Status of the Wait2 Edge Detection interrupt" "Not detected,Detected" textline " " endif eventfld.long 0x00 9. " WAIT1EDGEDETECTIONSTATUS ,Status of the Wait1 Edge Detection interrupt" "Not detected,Detected" textline " " eventfld.long 0x00 8. " WAIT0EDGEDETECTIONSTATUS ,Status of the Wait0 Edge Detection interrupt" "Not detected,Detected" textline " " eventfld.long 0x00 1. " TERMINALCOUNTSTATUS ,Status of the TerminalCountEvent interrupt (COUNTVALUE)" ">0,=0" textline " " eventfld.long 0x00 0. " FIFOEVENTSTATUS ,Status of the FIFOEvent interrupt" "FIFOTHRESHOLD" textline " " hexmask.long.word 0x00 0.--13. 1. " COUNTVALUE ,Number of remaining bytes to be read/write" group.long 0x1f4++0x0b line.long 0x00 "GPMC_ECC_CONFIG,ECC Configuration" bitfld.long 0x00 16. " ECCALGORITHM ,ECC algorithm used" "Hamming,BCH" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*")||(cpuis("AM335*"))||cpuis("C6A816*"))||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 12.--13. " ECCBCHTSEL ,Error correction capability used for BCH" "t=4,t=8,t=16,?..." else bitfld.long 0x00 12. " ECCBCHT8 ,Error correction capability used for BCH" "t=4,t=8" endif textline " " bitfld.long 0x00 8.--11. " ECCWRAPMODE ,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " ECC16B ,Selects an ECC calculated on 16 columns" "8 columns,16 columns" textline " " bitfld.long 0x00 4.--6. " ECCTOPSECTOR ,Number of sectors to process with the BCH algorithm" "1,2,3,4,5,6,7,8" textline " " sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")) bitfld.long 0x00 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,?..." else bitfld.long 0x00 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,Chip-select 6,Chip-select 7" endif textline " " bitfld.long 0x00 0. " ECCENABLE ,Enables the ECC feature" "Disabled,Enabled" line.long 0x04 "GPMC_ECC_CONTROL,ECC Control" eventfld.long 0x04 8. " ECCCLEAR ,Clear all ECC result registers" "No effect,Clear" textline " " bitfld.long 0x04 0.--3. " ECCPOINTER ,ECC result register" "ECC engine disabled,ECC result register 1,ECC result register 2,ECC result register 3,ECC result register 4,ECC result register 5,ECC result register 6,ECC result register 7,ECC result register 8,ECC result register 9,?..." line.long 0x08 "GPMC_ECC_SIZE_CONFIG,ECC Size" hexmask.long.byte 0x08 22.--29. 1. " ECCSIZE1 ,Defines ECC size 1" hexmask.long.byte 0x08 12.--19. 1. " ECCSIZE0 ,Defines ECC size 0" textline " " bitfld.long 0x08 8. " ECC9RESULTSIZE ,Selects ECC size for ECC 9 result register" "ECCSize0,ECCSize1" bitfld.long 0x08 7. " ECC8RESULTSIZE ,Selects ECC size for ECC 8 result register" "ECCSize0,ECCSize1" textline " " bitfld.long 0x08 6. " ECC7RESULTSIZE ,Selects ECC size for ECC 7 result register" "ECCSize0,ECCSize1" bitfld.long 0x08 5. " ECC6RESULTSIZE ,Selects ECC size for ECC 6 result register" "ECCSize0,ECCSize1" textline " " bitfld.long 0x08 4. " ECC5RESULTSIZE ,Selects ECC size for ECC 5 result register" "ECCSize0,ECCSize1" bitfld.long 0x08 3. " ECC4RESULTSIZE ,Selects ECC size for ECC 4 result register" "ECCSize0,ECCSize1" textline " " bitfld.long 0x08 2. " ECC3RESULTSIZE ,Selects ECC size for ECC 3 result register" "ECCSize0,ECCSize1" bitfld.long 0x08 1. " ECC2RESULTSIZE ,Selects ECC size for ECC 2 result register" "ECCSize0,ECCSize1" textline " " bitfld.long 0x08 0. " ECC1RESULTSIZE ,Selects ECC size for ECC 1 result register" "ECCSize0,ECCSize1" group.long 0x2D0++0x3 line.long 0x00 "GPMC_BCH_SWDATA,Pass Data To The BCH ECC Calculator" hexmask.long.word 0x00 0.--15. 1. " BCH_DATA ,Data to be included in the BCH calculation" tree.end tree "Chip Select #0" group.long 0x60++0x3 line.long 0x00 "GPMC_CONFIG1_CS0,Signal Control Parameters Per Chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported" textline " " bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..." textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..." textline " " bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..." else bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3" endif textline " " bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..." textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..." else bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies" textline " " sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*")) bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4" else bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8" endif group.long (0x60+0x04)++0x3 line.long 0x00 "GPMC_CONFIG2_CS0,Chip-select Signal Timing Parameter Configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,0CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " CSRDOFFTIME ,0CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " CSEXTRADELAY ,0CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,0CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x60+0x08)++0x3 line.long 0x00 "GPMC_CONFIG3_CS0,0ADV Signal Timing Parameter Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,0ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,0ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 16.--20. " ADVWROFFTIME ,0ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,0ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " ADVEXTRADELAY ,0ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,0ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " ADVONTIME ,0ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x60+0x0C)++0x3 line.long 0x00 "GPMC_CONFIG4_CS0,0WE and 0OE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,0WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 23. " WEEXTRADELAY ,0WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 16.--19. " WEONTIME ,0WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,0OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 8.--12. " OEOFFTIME ,0OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " OEEXTRADELAY ,0OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,0OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " OEONTIME ,0OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x60+0x10)++0x3 line.long 0x00 "GPMC_CONFIG5_CS0,ACCESSTIME And CYCLETIME Timing Parameters Configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x60+0x14)++0x3 line.long 0x00 "GPMC_CONFIG6_CS0,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay" textline " " bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay" textline " " bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x60+0x18)++0x3 line.long 0x00 "GPMC_CONFIG7_CS0,Chip-select Address Mapping Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" else bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" endif textline " " bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address" wgroup.long (0x60+0x1C)++0x3 line.long 0x00 "GPMC_NAND_COMMAND_CS0,Address Location" wgroup.long (0x60+0x20)++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_CS0,Address Location" group.long (0x60+0x24)++0x3 line.long 0x00 "GPMC_NAND_DATA_CS0,Address Location" tree.end tree "Chip Select #1" group.long 0x90++0x3 line.long 0x00 "GPMC_CONFIG1_CS1,Signal Control Parameters Per Chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported" textline " " bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..." textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..." textline " " bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..." else bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3" endif textline " " bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..." textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..." else bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies" textline " " sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*")) bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4" else bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8" endif group.long (0x90+0x04)++0x3 line.long 0x00 "GPMC_CONFIG2_CS1,Chip-select Signal Timing Parameter Configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,1CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " CSRDOFFTIME ,1CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " CSEXTRADELAY ,1CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,1CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x90+0x08)++0x3 line.long 0x00 "GPMC_CONFIG3_CS1,1ADV Signal Timing Parameter Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,1ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,1ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 16.--20. " ADVWROFFTIME ,1ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,1ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " ADVEXTRADELAY ,1ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,1ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " ADVONTIME ,1ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x90+0x0C)++0x3 line.long 0x00 "GPMC_CONFIG4_CS1,1WE and 1OE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,1WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 23. " WEEXTRADELAY ,1WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 16.--19. " WEONTIME ,1WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,1OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 8.--12. " OEOFFTIME ,1OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " OEEXTRADELAY ,1OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,1OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " OEONTIME ,1OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x90+0x10)++0x3 line.long 0x00 "GPMC_CONFIG5_CS1,ACCESSTIME And CYCLETIME Timing Parameters Configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x90+0x14)++0x3 line.long 0x00 "GPMC_CONFIG6_CS1,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay" textline " " bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay" textline " " bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x90+0x18)++0x3 line.long 0x00 "GPMC_CONFIG7_CS1,Chip-select Address Mapping Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" else bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" endif textline " " bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address" wgroup.long (0x90+0x1C)++0x3 line.long 0x00 "GPMC_NAND_COMMAND_CS1,Address Location" wgroup.long (0x90+0x20)++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_CS1,Address Location" group.long (0x90+0x24)++0x3 line.long 0x00 "GPMC_NAND_DATA_CS1,Address Location" tree.end tree "Chip Select #2" group.long 0xC0++0x3 line.long 0x00 "GPMC_CONFIG1_CS2,Signal Control Parameters Per Chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported" textline " " bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..." textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..." textline " " bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..." else bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3" endif textline " " bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..." textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..." else bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies" textline " " sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*")) bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4" else bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8" endif group.long (0xC0+0x04)++0x3 line.long 0x00 "GPMC_CONFIG2_CS2,Chip-select Signal Timing Parameter Configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,2CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " CSRDOFFTIME ,2CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " CSEXTRADELAY ,2CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,2CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xC0+0x08)++0x3 line.long 0x00 "GPMC_CONFIG3_CS2,2ADV Signal Timing Parameter Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,2ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,2ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 16.--20. " ADVWROFFTIME ,2ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,2ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " ADVEXTRADELAY ,2ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,2ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " ADVONTIME ,2ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xC0+0x0C)++0x3 line.long 0x00 "GPMC_CONFIG4_CS2,2WE and 2OE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,2WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 23. " WEEXTRADELAY ,2WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 16.--19. " WEONTIME ,2WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,2OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 8.--12. " OEOFFTIME ,2OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " OEEXTRADELAY ,2OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,2OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " OEONTIME ,2OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xC0+0x10)++0x3 line.long 0x00 "GPMC_CONFIG5_CS2,ACCESSTIME And CYCLETIME Timing Parameters Configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0xC0+0x14)++0x3 line.long 0x00 "GPMC_CONFIG6_CS2,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay" textline " " bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay" textline " " bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xC0+0x18)++0x3 line.long 0x00 "GPMC_CONFIG7_CS2,Chip-select Address Mapping Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" else bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" endif textline " " bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address" wgroup.long (0xC0+0x1C)++0x3 line.long 0x00 "GPMC_NAND_COMMAND_CS2,Address Location" wgroup.long (0xC0+0x20)++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_CS2,Address Location" group.long (0xC0+0x24)++0x3 line.long 0x00 "GPMC_NAND_DATA_CS2,Address Location" tree.end tree "Chip Select #3" group.long 0xF0++0x3 line.long 0x00 "GPMC_CONFIG1_CS3,Signal Control Parameters Per Chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported" textline " " bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..." textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..." textline " " bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..." else bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3" endif textline " " bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..." textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..." else bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies" textline " " sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*")) bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4" else bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8" endif group.long (0xF0+0x04)++0x3 line.long 0x00 "GPMC_CONFIG2_CS3,Chip-select Signal Timing Parameter Configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,3CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " CSRDOFFTIME ,3CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " CSEXTRADELAY ,3CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,3CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xF0+0x08)++0x3 line.long 0x00 "GPMC_CONFIG3_CS3,3ADV Signal Timing Parameter Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,3ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,3ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 16.--20. " ADVWROFFTIME ,3ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,3ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " ADVEXTRADELAY ,3ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,3ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " ADVONTIME ,3ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xF0+0x0C)++0x3 line.long 0x00 "GPMC_CONFIG4_CS3,3WE and 3OE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,3WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 23. " WEEXTRADELAY ,3WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 16.--19. " WEONTIME ,3WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,3OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 8.--12. " OEOFFTIME ,3OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " OEEXTRADELAY ,3OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,3OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " OEONTIME ,3OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xF0+0x10)++0x3 line.long 0x00 "GPMC_CONFIG5_CS3,ACCESSTIME And CYCLETIME Timing Parameters Configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0xF0+0x14)++0x3 line.long 0x00 "GPMC_CONFIG6_CS3,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay" textline " " bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay" textline " " bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0xF0+0x18)++0x3 line.long 0x00 "GPMC_CONFIG7_CS3,Chip-select Address Mapping Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" else bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" endif textline " " bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address" wgroup.long (0xF0+0x1C)++0x3 line.long 0x00 "GPMC_NAND_COMMAND_CS3,Address Location" wgroup.long (0xF0+0x20)++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_CS3,Address Location" group.long (0xF0+0x24)++0x3 line.long 0x00 "GPMC_NAND_DATA_CS3,Address Location" tree.end tree "Chip Select #4" group.long 0x120++0x3 line.long 0x00 "GPMC_CONFIG1_CS4,Signal Control Parameters Per Chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported" textline " " bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..." textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..." textline " " bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..." else bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3" endif textline " " bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..." textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..." else bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies" textline " " sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*")) bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4" else bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8" endif group.long (0x120+0x04)++0x3 line.long 0x00 "GPMC_CONFIG2_CS4,Chip-select Signal Timing Parameter Configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,4CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " CSRDOFFTIME ,4CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " CSEXTRADELAY ,4CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,4CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x120+0x08)++0x3 line.long 0x00 "GPMC_CONFIG3_CS4,4ADV Signal Timing Parameter Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,4ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,4ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 16.--20. " ADVWROFFTIME ,4ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,4ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " ADVEXTRADELAY ,4ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,4ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " ADVONTIME ,4ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x120+0x0C)++0x3 line.long 0x00 "GPMC_CONFIG4_CS4,4WE and 4OE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,4WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 23. " WEEXTRADELAY ,4WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 16.--19. " WEONTIME ,4WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,4OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 8.--12. " OEOFFTIME ,4OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " OEEXTRADELAY ,4OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,4OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " OEONTIME ,4OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x120+0x10)++0x3 line.long 0x00 "GPMC_CONFIG5_CS4,ACCESSTIME And CYCLETIME Timing Parameters Configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x120+0x14)++0x3 line.long 0x00 "GPMC_CONFIG6_CS4,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay" textline " " bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay" textline " " bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x120+0x18)++0x3 line.long 0x00 "GPMC_CONFIG7_CS4,Chip-select Address Mapping Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" else bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" endif textline " " bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address" wgroup.long (0x120+0x1C)++0x3 line.long 0x00 "GPMC_NAND_COMMAND_CS4,Address Location" wgroup.long (0x120+0x20)++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_CS4,Address Location" group.long (0x120+0x24)++0x3 line.long 0x00 "GPMC_NAND_DATA_CS4,Address Location" tree.end tree "Chip Select #5" group.long 0x150++0x3 line.long 0x00 "GPMC_CONFIG1_CS5,Signal Control Parameters Per Chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported" textline " " bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..." textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..." textline " " bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..." else bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3" endif textline " " bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..." textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..." else bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies" textline " " sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*")) bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4" else bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8" endif group.long (0x150+0x04)++0x3 line.long 0x00 "GPMC_CONFIG2_CS5,Chip-select Signal Timing Parameter Configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,5CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " CSRDOFFTIME ,5CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " CSEXTRADELAY ,5CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,5CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x150+0x08)++0x3 line.long 0x00 "GPMC_CONFIG3_CS5,5ADV Signal Timing Parameter Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,5ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,5ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 16.--20. " ADVWROFFTIME ,5ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,5ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " ADVEXTRADELAY ,5ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,5ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " ADVONTIME ,5ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x150+0x0C)++0x3 line.long 0x00 "GPMC_CONFIG4_CS5,5WE and 5OE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,5WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 23. " WEEXTRADELAY ,5WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 16.--19. " WEONTIME ,5WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,5OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 8.--12. " OEOFFTIME ,5OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " OEEXTRADELAY ,5OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,5OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " OEONTIME ,5OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x150+0x10)++0x3 line.long 0x00 "GPMC_CONFIG5_CS5,ACCESSTIME And CYCLETIME Timing Parameters Configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x150+0x14)++0x3 line.long 0x00 "GPMC_CONFIG6_CS5,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay" textline " " bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay" textline " " bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x150+0x18)++0x3 line.long 0x00 "GPMC_CONFIG7_CS5,Chip-select Address Mapping Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" else bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" endif textline " " bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address" wgroup.long (0x150+0x1C)++0x3 line.long 0x00 "GPMC_NAND_COMMAND_CS5,Address Location" wgroup.long (0x150+0x20)++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_CS5,Address Location" group.long (0x150+0x24)++0x3 line.long 0x00 "GPMC_NAND_DATA_CS5,Address Location" tree.end tree "Chip Select #6" group.long 0x180++0x3 line.long 0x00 "GPMC_CONFIG1_CS6,Signal Control Parameters Per Chip-select" bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported" textline " " bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple" textline " " bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous" textline " " bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..." textline " " bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..." textline " " bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored" textline " " bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..." else bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3" endif textline " " bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..." textline " " bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..." textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..." else bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled" endif textline " " bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies" textline " " sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*")) bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4" else bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8" endif group.long (0x180+0x04)++0x3 line.long 0x00 "GPMC_CONFIG2_CS6,Chip-select Signal Timing Parameter Configuration" bitfld.long 0x00 16.--20. " CSWROFFTIME ,6CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " CSRDOFFTIME ,6CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " CSEXTRADELAY ,6CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 0.--3. " CSONTIME ,6CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x180+0x08)++0x3 line.long 0x00 "GPMC_CONFIG3_CS6,6ADV Signal Timing Parameter Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,6ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,6ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 16.--20. " ADVWROFFTIME ,6ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,6ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " ADVEXTRADELAY ,6ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,6ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " ADVONTIME ,6ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x180+0x0C)++0x3 line.long 0x00 "GPMC_CONFIG4_CS6,6WE and 6OE signals timing parameter configuration" bitfld.long 0x00 24.--28. " WEOFFTIME ,6WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 23. " WEEXTRADELAY ,6WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " bitfld.long 0x00 16.--19. " WEONTIME ,6WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,6OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 8.--12. " OEOFFTIME ,6OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 7. " OEEXTRADELAY ,6OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed" textline " " sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,6OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7" textline " " endif bitfld.long 0x00 0.--3. " OEONTIME ,6OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x180+0x10)++0x3 line.long 0x00 "GPMC_CONFIG5_CS6,ACCESSTIME And CYCLETIME Timing Parameters Configuration" bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long (0x180+0x14)++0x3 line.long 0x00 "GPMC_CONFIG6_CS6,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration" bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay" textline " " bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay" textline " " bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x180+0x18)++0x3 line.long 0x00 "GPMC_CONFIG7_CS6,Chip-select Address Mapping Configuration" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" else bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB" endif textline " " bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address" wgroup.long (0x180+0x1C)++0x3 line.long 0x00 "GPMC_NAND_COMMAND_CS6,Address Location" wgroup.long (0x180+0x20)++0x3 line.long 0x00 "GPMC_NAND_ADDRESS_CS6,Address Location" group.long (0x180+0x24)++0x3 line.long 0x00 "GPMC_NAND_DATA_CS6,Address Location" tree.end tree "Result Registers" width 19. sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rgroup.long 0x200++0x23 line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register" bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register" bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register" bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register" bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register" bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register" bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register" bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register" bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register" bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1" else group.long 0x200++0x23 line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register" bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register" bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register" bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register" bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register" bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register" bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register" bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register" bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1" line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register" bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1" bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1" bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1" bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1" textline " " bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1" bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1" bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1" bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1" textline " " bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1" bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1" bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1" bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1" bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1" bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1" textline " " bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1" bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1" bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1" bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1" textline " " bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1" bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1" bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1" bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1" endif group.long 0x240++0xF line.long 0x00 "GPMC_BCH_RESULT0_0,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_0,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_0,BCH ECC result (bits 64 to 95)" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 127)" else line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 103)" hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)" endif sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") group.long (0x240+0xc0)++0xb line.long 0x00 "GPMC_BCH_RESULT4_0,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_0,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_0,BCH ECC result (bits 192 to 207)" sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*"))) hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_0 ,BCH ECC result (bits 192 to 207)" endif endif group.long 0x250++0xF line.long 0x00 "GPMC_BCH_RESULT0_1,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_1,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_1,BCH ECC result (bits 64 to 95)" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 127)" else line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 103)" hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)" endif sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") group.long (0x250+0xc0)++0xb line.long 0x00 "GPMC_BCH_RESULT4_1,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_1,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_1,BCH ECC result (bits 192 to 207)" sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*"))) hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_1 ,BCH ECC result (bits 192 to 207)" endif endif group.long 0x260++0xF line.long 0x00 "GPMC_BCH_RESULT0_2,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_2,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_2,BCH ECC result (bits 64 to 95)" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 127)" else line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 103)" hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)" endif sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") group.long (0x260+0xc0)++0xb line.long 0x00 "GPMC_BCH_RESULT4_2,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_2,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_2,BCH ECC result (bits 192 to 207)" sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*"))) hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_2 ,BCH ECC result (bits 192 to 207)" endif endif group.long 0x270++0xF line.long 0x00 "GPMC_BCH_RESULT0_3,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_3,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_3,BCH ECC result (bits 64 to 95)" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 127)" else line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 103)" hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)" endif sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") group.long (0x270+0xc0)++0xb line.long 0x00 "GPMC_BCH_RESULT4_3,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_3,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_3,BCH ECC result (bits 192 to 207)" sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*"))) hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_3 ,BCH ECC result (bits 192 to 207)" endif endif group.long 0x280++0xF line.long 0x00 "GPMC_BCH_RESULT0_4,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_4,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_4,BCH ECC result (bits 64 to 95)" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 127)" else line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 103)" hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)" endif sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") group.long (0x280+0xc0)++0xb line.long 0x00 "GPMC_BCH_RESULT4_4,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_4,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_4,BCH ECC result (bits 192 to 207)" sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*"))) hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_4 ,BCH ECC result (bits 192 to 207)" endif endif group.long 0x290++0xF line.long 0x00 "GPMC_BCH_RESULT0_5,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_5,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_5,BCH ECC result (bits 64 to 95)" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 127)" else line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 103)" hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)" endif sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") group.long (0x290+0xc0)++0xb line.long 0x00 "GPMC_BCH_RESULT4_5,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_5,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_5,BCH ECC result (bits 192 to 207)" sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*"))) hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_5 ,BCH ECC result (bits 192 to 207)" endif endif group.long 0x2A0++0xF line.long 0x00 "GPMC_BCH_RESULT0_6,BCH ECC result (bits 0 to 31)" line.long 0x04 "GPMC_BCH_RESULT1_6,BCH ECC result (bits 32 to 63)" line.long 0x08 "GPMC_BCH_RESULT2_6,BCH ECC result (bits 64 to 95)" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") line.long 0x0C "GPMC_BCH_RESULT3_6,BCH ECC result (bits 96 to 127)" else line.long 0x0C "GPMC_BCH_RESULT3_6,BCH ECC result (bits 96 to 103)" hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)" endif sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") group.long (0x2A0+0xc0)++0xb line.long 0x00 "GPMC_BCH_RESULT4_6,BCH ECC result (bits 128 to 159)" line.long 0x04 "GPMC_BCH_RESULT5_6,BCH ECC result (bits 160 to 191)" line.long 0x08 "GPMC_BCH_RESULT6_6,BCH ECC result (bits 192 to 207)" sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*"))) hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_6 ,BCH ECC result (bits 192 to 207)" endif endif tree.end width 0xb tree.end tree "EMIF" base ad:0x4C000000 width 24. rgroup.long 0x00++0x07 line.long 0x00 "EMIF_MOD_ID_REV,EMIF Module ID and Revision Register" bitfld.long 0x00 30.--31. " REG_SCHEME ,Distinguish between old and current revision schemes" "Old,New,?..." hexmask.long.word 0x00 16.--27. 1. " REG_MODULE_ID ,EMIF module ID" textline " " hexmask.long.byte 0x00 11.--15. 1. " REG_RTL_VERSION ,RTL Version" hexmask.long.byte 0x00 8.--10. 1. " REG_MAJOR_REVISION ,Major Revision" textline " " hexmask.long.byte 0x00 0.--5. 1. " REG_MINOR_REVISION ,Minor Revision" line.long 0x04 "STATUS,SDRAM Status Register" bitfld.long 0x04 31. " REG_BE ,Big Endian" "Big,Little" bitfld.long 0x04 30. " REG_DUAL_CLK_MODE ,Dual Clock mode" "Disabled,Enabled" textline " " bitfld.long 0x04 29. " REG_FAST_INIT ,Fast Initialization" "Disabled,Enabled" bitfld.long 0x04 2. " REG_PHY_DLL_READY ,DDR PHY Ready" "Not ready,Ready" if (((data.long(ad:0x4C000000+0x08))&0xe0000000)==0x00) group.long 0x08++0x03 line.long 0x00 "SDRAM_CONFIG,SDRAM Configuration Register" bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection" "DDR1,LPDDR1,DDR2,DDR3,LPDDR2,?..." bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position" "0,1,2,3" textline " " bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select" "No,Yes" bitfld.long 0x00 18.--19. " REG_SDRAM_DRIVE ,SDRAM drive strength" "Normal,Weak,?..." textline " " bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width (bit)" "32,16,?..." bitfld.long 0x00 10.--13. " REG_CL ,CAS Latency" "Reserved,Reserved,2,3,Reserved,1.5,2.5,?..." textline " " bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup" "1,2,4,8,?..." textline " " bitfld.long 0x00 3. " REG_EBANK ,External chip select setup" "pad_cs_o_n[0],?..." bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size" "256,512,1024,2048,?..." elif (((data.long(ad:0x4C000000+0x08))&0xe0000000)==0x20000000) group.long 0x08++0x03 line.long 0x00 "SDRAM_CONFIG,SDRAM Configuration Register" bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection" "DDR1,LPDDR1,DDR2,DDR3,LPDDR2,?..." bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position" "0,1,2,3" textline " " bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select" "No,Yes" bitfld.long 0x00 18.--19. " REG_SDRAM_DRIVE ,SDRAM drive strength" "Full,1/2,1/4,1/8" textline " " bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width (bit)" "32,16,?..." bitfld.long 0x00 10.--13. " REG_CL ,CAS Latency" "Reserved,Reserved,2,3,?..." textline " " bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup" "1,2,4,8,?..." textline " " bitfld.long 0x00 3. " REG_EBANK ,External chip select setup" "pad_cs_o_n[0],?..." bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size" "256,512,1024,2048,?..." elif (((data.long(ad:0x4C000000+0x08))&0xe0000000)==0x40000000) group.long 0x08++0x03 line.long 0x00 "SDRAM_CONFIG,SDRAM Configuration Register" bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection" "DDR1,LPDDR1,DDR2,DDR3,LPDDR2,?..." bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position" "0,1,2,3" textline " " bitfld.long 0x00 24.--26. " REG_DDR_TERM ,DDR2 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..." bitfld.long 0x00 23. " REG_DDR2_DDQS ,DDR2 differential DQS enable" "Single ended,Differential" textline " " bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select" "No,Yes" bitfld.long 0x00 18.--19. " REG_SDRAM_DRIVE ,SDRAM drive strength" "Full,Reduced,?..." textline " " bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width (bit)" "32,16,?..." bitfld.long 0x00 10.--13. " REG_CL ,CAS Latency" "Reserved,Reserved,2,3,4,5,?..." textline " " bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup" "1,2,4,8,?..." textline " " bitfld.long 0x00 3. " REG_EBANK ,External chip select setup" "pad_cs_o_n[0],?..." bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size" "256,512,1024,2048,?..." elif (((data.long(ad:0x4C000000+0x08))&0xe0000000)==0x60000000) group.long 0x08++0x03 line.long 0x00 "SDRAM_CONFIG,SDRAM Configuration Register" bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection" "DDR1,LPDDR1,DDR2,DDR3,LPDDR2,?..." bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position" "0,1,2,3" textline " " bitfld.long 0x00 24.--26. " REG_DDR_TERM ,DDR3 termination resistor value" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,?..." bitfld.long 0x00 21.--22. " REG_DYN_ODT ,DDR3 Dynamic ODT" "Disabled,RZQ/4,RZQ/2,?..." textline " " bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select" "No,Yes" bitfld.long 0x00 18.--19. " REG_SDRAM_DRIVE ,SDRAM drive strength" "RZQ/6,RZQ/7,?..." textline " " bitfld.long 0x00 16.--17. " REG_CWL ,SDDR3 CAS Write latency" "5,6,7,8" bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width (bit)" "32,16,?..." textline " " bitfld.long 0x00 10.--13. " REG_CL ,CAS Latency" "Reserved,Reserved,5,Reserved,6,Reserved,7,Reserved,8,Reserved,9,Reserved,10,Reserved,11,?..." bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup" "1,2,4,8,?..." bitfld.long 0x00 3. " REG_EBANK ,External chip select setup" "pad_cs_o_n[0],?..." textline " " bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size" "256,512,1024,2048,?..." elif (((data.long(ad:0x4C000000+0x08))&0xe0000000)==0x80000000) group.long 0x08++0x03 line.long 0x00 "SDRAM_CONFIG,SDRAM Configuration Register" bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection" "DDR1,LPDDR1,DDR2,DDR3,LPDDR2,?..." bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position" "0,1,2,3" textline " " bitfld.long 0x00 23. " REG_DDR2_DDQS ,DDR2 differential DQS enable" "Single ended,Differential" bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select" "No,Yes" textline " " bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width (bit)" "32,16,?..." bitfld.long 0x00 10.--13. " REG_CL ,CAS Latency" "Reserved,Reserved,Reserved,3,4,5,6,7,8,?..." textline " " bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup" "1,2,4,8,?..." textline " " bitfld.long 0x00 3. " REG_EBANK ,External chip select setup" "pad_cs_o_n[0],pad_cs_o_n[1:0]" bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size" "256,512,1024,2048,?..." else group.long 0x08++0x03 line.long 0x00 "SDRAM_CONFIG,SDRAM Configuration Register" bitfld.long 0x00 29.--31. " REG_SDRAM_TYPE ,SDRAM Type selection" "DDR1,LPDDR1,DDR2,DDR3,LPDDR2,?..." bitfld.long 0x00 27.--28. " REG_IBANK_POS ,Internal bank position" "0,1,2,3" textline " " bitfld.long 0x00 24.--26. " REG_DDR_TERM ,DDR2 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..." bitfld.long 0x00 23. " REG_DDR2_DDQS ,DDR2 differential DQS enable" "Single ended,Differential" textline " " bitfld.long 0x00 20. " REG_DDR_DISABLE_DLL ,Disable DLL select" "No,Yes" bitfld.long 0x00 14.--15. " REG_NARROW_MODE ,SDRAM data bus width (bit)" "32,16,?..." textline " " bitfld.long 0x00 7.--9. " REG_ROWSIZE ,Row Size" "9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--6. " REG_IBANK ,Internal Bank setup" "1,2,4,8,?..." textline " " bitfld.long 0x00 3. " REG_EBANK ,External chip select setup" "pad_cs_o_n[0],pad_cs_o_n[1:0]" bitfld.long 0x00 0.--2. " REG_PAGESIZE ,Page Size" "256,512,1024,2048,?..." endif group.long 0x0C++0x3 line.long 0x00 "SDRAM_CONFIG_2,SDRAM Configuration 2 Register" sif (!cpuis("AM335*")) bitfld.long 0x00 30. " REG_CS1NVMEN ,CS1 LPDDR2-NVM enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 27. " REG_EBANK_POS ,External bank position" "Lower,Higher" sif (!cpuis("AM335*")) textline " " bitfld.long 0x00 4.--5. " REG_RDBNUM ,Row Buffer setup" "1 row,2 row,4 row,8 row" bitfld.long 0x00 0.--2. " REG_RDBSIZE ,Row Data Buffer Size" "32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes" endif if (((data.long(ad:0x4C000000+0x08))&0xe0000000)==0x20000000) group.long 0x10++0x03 line.long 0x00 "SDRAM_REF_CTRL,SDRAM Refresh Control Register" bitfld.long 0x00 31. " REG_INITREF_DIS ,Initialization and Refresh disable" "No,Yes" bitfld.long 0x00 24.--26. " REG_PASR ,Partial Array Self Refresh" "Full,1/2,1/4,Reserved,Reserved,1/8,1/16,?..." hexmask.long.word 0x00 0.--15. 1. " REG_REFRESH_RATE ,Refresh Rate" elif (((data.long(ad:0x4C000000+0x08))&0xe0000000)==0x60000000) group.long 0x10++0x03 line.long 0x00 "SDRAM_REF_CTRL,SDRAM Refresh Control Register" bitfld.long 0x00 31. " REG_INITREF_DIS ,Initialization and Refresh disable" "No,Yes" bitfld.long 0x00 29. " REG_SRT ,DDR3 Self Refresh temperature range" "Normal,Extended" textline " " bitfld.long 0x00 28. " REG_ASR ,DDR3 Auto Self Refresh enable" "Disabled,Enabled" bitfld.long 0x00 24.--26. " REG_PASR ,Partial Array Self Refresh" "Full,1/2,1/4,1/8,3/4,1/2,1/4,1/8" textline " " hexmask.long.word 0x00 0.--15. 1. " REG_REFRESH_RATE ,Refresh Rate" else group.long 0x10++0x03 line.long 0x00 "SDRAM_REF_CTRL,SDRAM Refresh Control Register" bitfld.long 0x00 31. " REG_INITREF_DIS ,Initialization and Refresh disable" "No,Yes" hexmask.long.word 0x00 0.--15. 1. " REG_REFRESH_RATE ,Refresh Rate" endif group.long 0x14++0x1B line.long 0x00 "SDRAM_REF_CTRL_SHDW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x00 0.--15. 1. " REG_REFRESH_RATE_SHDW ,Shadow field for reg_refresh_rate" line.long 0x04 "SDRAM_TIM_1,SDRAM Timing 1 Register" bitfld.long 0x04 25.--28. " REG_T_RP ,Minimum number of m_clk cycles from Precharge to Activate or Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 21.--24. " REG_T_RCD ,Minimum number of m_clk cycles from Activate to Read or Write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 17.--20. " REG_T_WR ,Minimum number of m_clk cycles from last Write transfer to Pre-charge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 12.--16. " REG_T_RAS ,Minimum number of m_clk cycles from Activate to Pre-charge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 6.--11. " REG_T_RC ,Minimum number of m_clk cycles from Activate to Activate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 3.--5. " REG_T_RRD ,Minimum number of m_clk cycles from Activate to Activate for a different bank" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 0.--2. " REG_T_WTR ,Minimum number of m_clk cycles from last Write to Read" "0,1,2,3,4,5,6,7" line.long 0x08 "SDRAM_TIM_1_SHDW,SDRAM Timing 1 Shadow Register" bitfld.long 0x08 25.--28. " REG_T_RP_SHDW ,Shadow field for reg_t_rp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 21.--24. " REG_T_RCD_SHDW ,Shadow field for reg_t_rcd" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 17.--20. " REG_T_WR_SHDW ,Shadow field for reg_t_wr" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 12.--16. " REG_T_RAS_SHDW ,Shadow field for reg_t_ras" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 6.--11. " REG_T_RC_SHDW ,Shadow field for reg_t_rc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x08 3.--5. " REG_T_RRD_SHDW ,Shadow field for reg_t_rrd" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 0.--2. " REG_T_WTR_SHDW ,Shadow field for reg_t_wtr" "0,1,2,3,4,5,6,7" line.long 0x0C "SDRAM_TIM_2,SDRAM Timing 2 Register" bitfld.long 0x0C 28.--30. " REG_T_XP ,Minimum number of m_clk cycles from Power-Down exit to any command other than a Read command" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 25.--27. " REG_T_ODT ,Minimum number of m_clk cycles from ODT enable to write data driven for DDR2" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0C 16.--24. 1. " REG_T_XSNR ,Minimum number of m_clk cycles from Self-Refresh exit to any command other than a Read command" textline " " hexmask.long.word 0x0C 6.--15. 1. " REG_T_XSRD ,Minimum number of m_clk cycles from Self-Refresh exit to a Read command" bitfld.long 0x0C 3.--5. " REG_T_RTP ,Minimum number of m_clk cycles from the last Read command to a Pre-charge command for DDR2" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--2. " REG_T_CKE ,Minimum number of m_clk cycles between pad_cke_o changes" "0,1,2,3,4,5,6,7" line.long 0x10 "SDRAM_TIM_2_SHDW,SDRAM Timing 2 Shadow Register" bitfld.long 0x10 28.--30. " REG_T_XP_SHDW ,Shadow field for reg_t_xp" "0,1,2,3,4,5,6,7" bitfld.long 0x10 25.--27. " REG_T_ODT_SHDW ,Shadow field for reg_t_odt" "0,1,2,3,4,5,6,7" hexmask.long.word 0x10 16.--24. 1. " REG_T_XSNR_SHDW ,Shadow field for reg_t_xsnr" textline " " hexmask.long.word 0x10 6.--15. 1. " REG_T_XSRD_SHDW ,Shadow field for reg_t_xsrd" bitfld.long 0x10 3.--5. " REG_T_RTP_SHDW ,Shadow field for reg_t_rtp" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. " REG_T_CKE_SHDW ,Shadow field for reg_t_cke" "0,1,2,3,4,5,6,7" line.long 0x14 "SDRAM_TIM_3,SDRAM Timing 3 Register" sif (!cpuis("AM335*")) bitfld.long 0x14 21.--23. " REG_T_CKESR ,Minimum number of m_clk cycles for which LPDDR2 must remain in Self Refresh" "0,1,2,3,4,5,6,7" textline " " endif hexmask.long.byte 0x14 15.--20. 1. " REG_ZQ_ZQCS ,Number of m_clk clock cycles for a ZQCS command" sif (!cpuis("AM335*")) textline " " bitfld.long 0x14 13.--14. " REG_T_TDQSCKMAX ,Number of m_clk that satisfies tDQSCKmax for LPDDR2" "0,1,2,3" endif textline " " hexmask.long.word 0x14 4.--12. 1. " REG_T_RFC ,Minimum number of m_clk cycles from Refresh or Load Mode to Refresh or Activate" bitfld.long 0x14 0.--3. " REG_T_RAS_MAX ,Maximum number of reg_refresh_rate intervals from Activate to Precharge command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "SDRAM_TIM_3_SHDW,SDRAM Timing 3 Shadow Register" sif (!cpuis("AM335*")) bitfld.long 0x18 21.--23. " REG_T_CKESR_SHDW ,Shadow field for reg_t_ckesr" "0,1,2,3,4,5,6,7" textline " " endif hexmask.long.byte 0x18 15.--20. 1. " REG_ZQ_ZQCS_SHDW ,Shadow field for reg_zq_zqcs" sif (!cpuis("AM335*")) textline " " bitfld.long 0x18 13.--14. " REG_T_TDQSCKMAX_SHDW ,Shadow field for reg_t_dqsckmax" "0,1,2,3" endif textline " " hexmask.long.word 0x18 4.--12. 1. " REG_T_RFC_SHDW ,Shadow field for reg_t_rfc" bitfld.long 0x18 0.--3. " REG_T_RAS_MAX_SHDW ,Shadow field for reg_t_ras_max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("AM335*")) group.long 0x30++0x07 line.long 0x00 "LPDDR2_NVM_TIM,LPDDR2 NVM Timing Register" bitfld.long 0x00 28.--30. " REG_NVM_T_XP ,Minimum number of m_clk cycles from Powerdown exit to any command" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " REG_NVM_T_WTR ,Minimum number of m_clk cycles from last Write to Read" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " REG_NVM_T_RP ,Minimum number of m_clk cycles from Preactive to Activate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 16.--19. " REG_NVM_T_WRA ,Minimum number of m_clk cycles from last Write transfer to Activate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 8.--15. 1. " REG_NVM_T_RRD ,Minimum number of m_clk cycles from Activate to Activate for a different bank" hexmask.long.byte 0x00 0.--7. 1. " REG_NVM_T_RCDMIN ,Minimum number of m_clk cycles from Activate to Read or Write" line.long 0x04 "LPDDR2_NVM_TIM_SHDW,LPDDR2 NVM Timing Shadow Register" bitfld.long 0x04 28.--30. " REG_NVM_T_XP_SHDW ,Shadow field for reg_nvm_t_xp" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. " REG_NVM_T_WTR_SHDW ,Shadow field for reg_nvm_t_wtr" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--23. " REG_NVM_T_RP_SHDW ,Shadow field for reg_nvm_t_rp" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 16.--19. " REG_NVM_T_WRA_SHDW ,Shadow field for reg_nvm_t_wra" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 8.--15. 1. " REG_NVM_T_RRD_SHDW ,Shadow field for reg_nvm_t_rrd" hexmask.long.byte 0x04 0.--7. 1. " REG_NVM_T_RCDMIN_SHDW ,Shadow field for reg_nvm_t_rcdmin" endif group.long 0x38++0x07 line.long 0x00 "PWR_MGMT_CTRL,Power Management Control Register" bitfld.long 0x00 12.--15. " REG_PD_TIM ,Power Mangement timer for Power-Down (clocks)" "Immediately,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144" bitfld.long 0x00 11. " REG_DPD_EN ,Deep Power-Down enable" "Disabled,Enabled" bitfld.long 0x00 8.--10. " REG_LP_MODE ,Automatic Power Management enable" "Disabled,Clock Stop,Self Refresh,Disabled,Power-Down,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 4.--7. " REG_SR_TIM ,Power Management timer for Self Refresh (clocks)" "Immediately,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144" bitfld.long 0x00 0.--3. " REG_CS_TIM ,Power Management timer for Clock Stop (clocks)" "Immediately,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144" line.long 0x04 "PWR_MGMT_CTRL_SHDW,Power Management Control Shadow Register" bitfld.long 0x04 8.--11. " REG_PD_TIM_SHDW ,Shadow field for reg_pd_tim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4.--7. " REG_SR_TIM_SHDW ,Shadow field for reg_sr_tim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " REG_CS_TIM_SHDW ,Shadow field for reg_cs_tim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (!cpuis("AM335*")) group.long 0x40++0x3 line.long 0x0 "LPDDR2_MODE_REG_DATA,LPDDR2 Mode Register Data Register" hexmask.long.byte 0x0 0.--6. 1. " REG_VALUE_0 ,Mode register value" group.long 0x50++0x07 line.long 0x00 "LPDDR2_MODE_REG_CFG,LPDDR2 Mode Register Configuration Register" bitfld.long 0x00 31. " REG_CS ,Chip select to issue mode register command" "CS0,CS1" bitfld.long 0x00 30. " REG_REFRESH_EN ,Refresh Enable after MRW write" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " REG_ADDRESS ,Mode register address" line.long 0x04 "OCP_CONFIG,OCP Configuration Register" bitfld.long 0x04 24.--27. " REG_SYS_THRESH_MAX ,System OCP Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--19. " REG_LL_THRESH_MAX ,Low-latency OCP Threshold Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 0.--7. 1. " REG_PR_OLD_COUNT ,Priority Raise Old Counter" rgroup.long 0x58++0x07 line.long 0x00 "OCP_CFG_VAL_1,OCP Configuration Value 1 Register" bitfld.long 0x00 30.--31. " REG_SYS_BUS_WIDTH ,L3 OCP data bus width for a particular configuration (bit)" "32,64,128,256" bitfld.long 0x00 28.--29. " REG_LL_BUS_WIDTH ,Low-latency OCP data bus width for a particular configuration (bit)" "32,64,128,256" hexmask.long.byte 0x00 8.--15. 1. " REG_WR_FIFO_DEPTH ,Write Data FIFO depth for a particular configuration" textline " " hexmask.long.byte 0x00 0.--7. 1. " REG_CMD_FIFO_DEPTH ,Command FIFO depth for a particular configuration" line.long 0x04 "OCP_CFG_VAL_2,OCP Configuration Value 2 Register" hexmask.long.byte 0x04 16.--23. 1. " REG_RREG_FIFO_DEPTH ,Register Read Data FIFO depth for a particular configuration" hexmask.long.byte 0x04 8.--15. 1. " REG_RSD_FIFO_DEPTH ,SDRAM Read Data FIFO depth for a particular configuration" hexmask.long.byte 0x04 0.--7. 1. " REG_RCMD_FIFO_DEPTH ,Read Command FIFO depth for a particular configuration" group.long 0x60++0x03 line.long 0x00 "IODFT_TLGC,ODFT Test Logic Global Control Register" hexmask.long.word 0x00 16.--31. 1. " REG_TLEC ,IODFT Test Logic Execution Counter" textline " " bitfld.long 0x00 14. " REG_MT ,MISR on/off trigger command" "Inactive/no affect,MISR capture/Pattern generator" textline " " bitfld.long 0x00 13. " REG_ACT_CAP_EN ,Active cycles capture enable" "Disabled,Enabled" bitfld.long 0x00 12. " REG_OPG_LD ,Load pattern generators' initial value" "Not loaded,Loaded" textline " " bitfld.long 0x00 10. " REG_RESET_PHY ,Reset DDR PHY" "No reset,Reset" bitfld.long 0x00 8. " REG_MMS ,Chooses the source of the MISR input" "Output,Input" textline " " bitfld.long 0x00 4.--5. " REG_MC ,MISR state" "Download results,Current value,Load from pc,Enabled" bitfld.long 0x00 1.--3. " REG_PC ,Pattern code (pattern generator output / input )" "Functional,Random XOR/Reserved,Random XNOR/Reserved,8 bit shifter/Reserved,Current register value,Reserved/Random XOR,Reserved/Random XNOR,Reserved/8 bit shifter" textline " " bitfld.long 0x00 0. " REG_TM ,Functional mode enable" "IODFT,Functional" rgroup.long 0x64++0x13 line.long 0x00 "IODFT_CTRL_MISR_RSLT,IODFT Test Logic Control MISR Result Register" hexmask.long.word 0x00 16.--25. 1. " REG_DQM_TLMR ,MISR result signature for the control signals" hexmask.long.word 0x00 0.--10. 1. " REG_CTL_TLMR ,MISR result signature for the control signals" line.long 0x04 "IODFT_ADDR_MISR_RSLT,ODFT Test Logic Address MISR Result Register" hexmask.long.tbyte 0x04 0.--20. 1. " REG_ADDR_TLMR ,MISR result signature for the address signals" line.long 0x08 "IODFT_DATA_MISR_RSLT_1,IODFT Test Logic Data MISR Result 1 Register" line.long 0x0c "IODFT_DATA_MISR_RSLT_2,IODFT Test Logic Data MISR Result 2 Register" line.long 0x10 "IODFT_DATA_MISR_RSLT_3,IODFT Test Logic Data MISR Result 3 Register" bitfld.long 0x10 0.--2. " REG_DATA_TLMR_66_64 ,Most significant bits of the MISR result signature for data bus" "0,1,2,3,4,5,6,7" endif width 21. rgroup.long 0x80++0x07 line.long 0x00 "PERF_CNT_1,Performance Counter 1 Register" line.long 0x04 "PERF_CNT_2,Performance Counter 2 Register" group.long 0x88++0x07 line.long 0x00 "PERF_CNT_CFG,Performance Counter Configuration Register" bitfld.long 0x00 31. " REG_CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register" "Disabled,Enabled" bitfld.long 0x00 30. " REG_CNTR2_REGION_EN ,Chip Select filter enable for Performance Counter 2 register" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " REG_CNTR2_CFG ,Filter configuration for Performance Counter 2" "Total SDRAM accesses,Total SDRAM activates,Total reads,Total writes,Num. of Command FIFO is full,Num. of Write Data FIFO is full,Num. of Read Data FIFO is full,Num. of Return Command FIFO is full,Num. of priority elevations,Num. of m_clk cycles that command pending,Num. of m_clk cycles for which memory data bus Tx,?..." textline " " bitfld.long 0x00 15. " REG_CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register" "Disabled,Enabled" bitfld.long 0x00 14. " REG_CNTR1_REGION_EN ,Chip Select filter enable for Performance Counter 1 register" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " REG_CNTR1_CFG ,Filter configuration for Performance Counter 1" "Total SDRAM accesses,Total SDRAM activates,Total reads,Total writes,Num. of Command FIFO is full,Num. of Write Data FIFO is full,Num. of Read Data FIFO is full,Num. of Return Command FIFO is full,Num. of priority elevations,Num. of m_clk cycles that command pending,Num. of m_clk cycles for which memory data bus Tx,?..." line.long 0x04 "PERF_CNT_SEL,Performance Counter Master Region Select Register" hexmask.long.byte 0x04 24.--31. 1. " REG_MCONNID2 ,MConnID for Performance Counter 2 register" bitfld.long 0x04 16.--17. " REG_REGION_SEL2 ,MAddrSpace for Performance Counter 2 register" "0,1,2,3" textline " " hexmask.long.byte 0x04 8.--15. 1. " REG_MCONNID1 ,MConnID for Performance Counter 1 register" bitfld.long 0x04 0.--1. " REG_REGION_SEL1 ,MAddrSpace for Performance Counter 1 register" "0,1,2,3" rgroup.long 0x90++0x03 line.long 0x00 "PERF_CNT_TIM,Performance Counter Time Register" group.long 0x98++0x07 line.long 0x00 "READ_IDLE_CTRL,Read Idle Control Register" bitfld.long 0x00 16.--19. " REG_READ_IDLE_LEN ,Read Idle Length field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--8. 1. " REG_READ_IDLE_INTERVAL ,Read Idle Interval field" line.long 0x04 "READ_IDLE_CTRL_SHDW,Read Idle Control Shadow Register" bitfld.long 0x04 16.--19. " REG_READ_IDLE_LEN_SHDW ,Shadow field for reg_read_idle_len" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x04 0.--8. 1. " REG_READ_IDLE_INTERVAL_SHDW ,Shadow field for reg_read_idle_interval" sif (!cpuis("AM335*")) group.long 0xa0++0x03 line.long 0x00 "IRQ_EOI,End of Interrupt Register" bitfld.long 0x00 0. " REG_EOI ,Software End Of Interrupt (EOI) control" "Disabled,Enabled" endif width 21. group.long 0xa4++0x03 line.long 0x00 "IRQSTATUS_RAW_SYS,System OCP Interrupt Raw Status Register" sif (!cpuis("AM335*")) bitfld.long 0x00 2. " REG_DNV_SYS ,Raw status of system OCP interrupt for LPDDR2 NVM data not valid" "No interrupt,Interrupt" textline "" endif bitfld.long 0x00 1. " REG_TA_SYS ,Raw status of system OCP interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " REG_ERR_SYS ,Raw status of system OCP interrupt" "No interrupt,Interrupt" sif (!cpuis("AM335*")) group.long 0xa8++0x03 line.long 0x00 "IRQSTATUS_RAW_LL,Low-latency OCP Interrupt Raw Status Register" bitfld.long 0x00 2. " REG_DNV_LL ,Raw status of low-latency OCP interrupt for LPDDR2 NVM data not valid" "No interrupt,Interrupt" bitfld.long 0x00 1. " REG_TA_LL ,Raw status of low-latency OCP interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " REG_ERR_LL ,Raw status of low-latency OCP interrupt" "No interrupt,Interrupt" endif group.long 0xaC++0x03 line.long 0x00 "IRQSTATUS_SYS,System OCP Interrupt Status Register" sif (!cpuis("AM335*")) bitfld.long 0x00 2. " REG_DNV_SYS ,Enabled status of system OCP interrupt for LPDDR2 NVM data not valid" "No interrupt,Interrupt" textline "" endif bitfld.long 0x00 1. " REG_TA_SYS ,Enabled status of system OCP interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " REG_ERR_SYS ,Enabled status of system OCP interrupt" "No interrupt,Interrupt" sif (!cpuis("AM335*")) group.long 0xb0++0x03 line.long 0x00 "IRQSTATUS_LL,Low-latency OCP Interrupt Status Register" bitfld.long 0x00 2. " REG_DNV_LL ,Enabled status of low-latency OCP interrupt for LPDDR2 NVM data not valid" "No interrupt,Interrupt" bitfld.long 0x00 1. " REG_TA_LL ,Enabled status of low-latency OCP interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " REG_ERR_LL ,Enabled status of low-latency OCP interrupt" "No interrupt,Interrupt" endif group.long 0xb4++0x03 line.long 0x00 "IRQENABLE_SET_SYS,System OCP Interrupt Enable Set Register" sif (!cpuis("AM335*")) bitfld.long 0x00 2. " REG_EN_DNV_SYS ,Enable set for system OCP interrupt for LPDDR2 NVM data not valid" "No effect,Enable" textline "" endif bitfld.long 0x00 1. " REG_EN_TA_SYS ,Enable set for system OCP interrupt" "No effect,Enable" bitfld.long 0x00 0. " REG_EN_ERR_SYS ,Enable set for system OCP interrupt" "No effect,Enable" sif (!cpuis("AM335*")) group.long 0xb8++0x03 line.long 0x00 "IRQENABLE_SET_LL,Low-latency OCP Interrupt Enable Set Register" bitfld.long 0x00 2. " REG_EN_DNV_LL ,Enable set for low-latency OCP interrupt for LPDDR2 NVM data not valid" "No effect,Enable" bitfld.long 0x00 1. " REG_EN_TA_LL ,Enable set for low-latency OCP interrupt" "No effect,Enable" bitfld.long 0x00 0. " REG_EN_ERR_LL ,Enable set for low-latency OCP interrupt" "No effect,Enable" endif group.long 0xbc++0x03 line.long 0x00 "IRQENABLE_CLR_SYS,System OCP Interrupt Enable Clear Register" sif (!cpuis("AM335*")) bitfld.long 0x00 2. " REG_EN_DNV_SYS ,Enable clear for system OCP interrupt for LPDDR2 NVM data not valid" "No effect,Disable" textline "" endif bitfld.long 0x00 1. " REG_EN_TA_SYS ,Enable clear for system OCP interrupt" "No effect,Disable" bitfld.long 0x00 0. " REG_EN_ERR_SYS ,Enable clear for system OCP interrupt" "No effect,Disable" sif (!cpuis("AM335*")) group.long 0xc0++0x03 line.long 0x00 "IRQENABLE_CLR_LL,Low-latency OCP Interrupt Enable Clear Register" bitfld.long 0x00 2. " REG_EN_DNV_LL ,Enable clear for low-latency OCP interrupt for LPDDR2 NVM data not valid" "No effect,Disable" bitfld.long 0x00 1. " REG_EN_TA_LL ,Enable clear for low-latency OCP interrupt" "No effect,Disable" bitfld.long 0x00 0. " REG_EN_ERR_LL ,Enable clear for low-latency OCP interrupt" "No effect,Disable" endif group.long 0xC8++0x03 line.long 0x00 "ZQ_CONFIG,ZQ Configuration Register" bitfld.long 0x00 31. " REG_ZQ_CS1EN ,Enables ZQ calibration for CS1" "Disabled,Enabled" bitfld.long 0x00 30. " REG_ZQ_CS0EN ,Enables ZQ calibration for CS0" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " REG_ZQ_DUALCALEN ,ZQ Dual Calibration enable" "Disabled,Enabled" bitfld.long 0x00 28. " REG_ZQ_SFEXITEN ,ZQCL on Self Refresh Active Power-Down and Precharge Power-Down exit enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18.--19. " REG_ZQ_ZQINIT_MULT ,Indicates the number of ZQCL intervals that make up a ZQINIT interval minus one" "0,1,2,3" bitfld.long 0x00 16.--17. " REG_ZQ_ZQCL_MULT ,Indicates the number of ZQCS intervals that make up a ZQCL interval minus one" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--15. 1. " REG_ZQ_REFINTERVAL ,Number of refresh periods between ZQCS commans" sif (!cpuis("AM335*")) group.long 0xCC++0x03 line.long 0x00 "TEMP_ALERT_CONFIG,Temperature Alert Configuration Register" bitfld.long 0x00 31. " REG_TA_CS1EN ,Enables temperature alert polling for CS1" "Disabled,Enabled" bitfld.long 0x00 30. " REG_TA_CS0EN ,Enables temperature alert polling for CS0" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " REG_TA_SFEXITEN ,ZQCL on Self Refresh Active Power-Down and Precharge Power-Down exit enable" "Disabled,Enabled" bitfld.long 0x00 26.--27. " REG_TA_DEVWDT ,Indicates the number of ZQCL intervals that make up a ZQINIT interval minus one" "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " REG_TA_DEVCNT ,Temperature Alert Poll on Self-Refresh, Active Power-Down and Precharge Power-Down exit enable" "0,1,2,3" hexmask.long.tbyte 0x00 0.--21. 1. " REG_TA_REFINTERVAL ,Number of refresh periods between temperature alert polls" rgroup.long 0xd0++0x03 line.long 0x00 "OCP_ERR_LOG,OCP Error Log Register" bitfld.long 0x00 14.--15. " REG_MADDRSPACE ,Address space of the first errored transaction" "0,1,2,3" bitfld.long 0x00 11.--13. " REG_MBURSTSEQ ,Addressing mode of the first errored transaction" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--10. " REG_MCMD ,Command type of the first errored transaction" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " REG_MCONNID ,Connection ID of the first errored transaction" endif group.long 0xe4++0x07 line.long 0x00 "DDR_PHY_CTRL_1,DDR PHY Control 1 Register" sif (cpuis("AM335*")) bitfld.long 0x00 20. " REG_PHY_EN_DYN_PWRDN ,Enable power to PHY data macros" "Disabled,Enabled" bitfld.long 0x00 15. " REG_PHY_RST_N ,Hold the PHY macros in reset" "Not reset,Reset" textline " " bitfld.long 0x00 12.--13. " REG_PHY_IDLE_L_ODT ,Value to drive on the 2-bit local_odt PHY outputs when reg_phy_dynamic_pwrdn_enable is asserted" "0,1,2,3" bitfld.long 0x00 10.--11. " REG_PHY_WR_L_ODT ,Controls the value assigned to the reg_phy_wr_local_odt input on the data macros" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " REG_PHY_RD_L_ODT ,Enable termination at the desired strength for read usage" "0,1,2,3" bitfld.long 0x00 0.--4. " REG_READ_LATENCY ,Latency for the read data from DDR SDRAM in number of m_clk cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hexmask.long 0x00 4.--31. 1. " REG_DDR_PHY_CTRL_1 ,DDR PHY Control" bitfld.long 0x00 0.--3. " REG_READ_LATENCY ,Latency for the read data from SDRAM in number of m_clk cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif line.long 0x04 "DDR_PHY_CTRL_1_SHDW,DDR PHY Control 1 Shadow Register" sif (cpuis("AM335*")) bitfld.long 0x04 20. " REG_PHY_EN_DYN_PWRDN ,Shadow field" "Disabled,Enabled" bitfld.long 0x04 15. " REG_PHY_RST_N ,Shadow field" "Not reset,Reset" textline " " bitfld.long 0x04 12.--13. " REG_PHY_IDLE_L_ODT ,Shadow field" "0,1,2,3" bitfld.long 0x04 10.--11. " REG_PHY_WR_L_ODT ,Shadow field" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " REG_PHY_RD_L_ODT ,Shadow field" "0,1,2,3" bitfld.long 0x04 0.--4. " REG_READ_LATENCY ,Shadow field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else hexmask.long 0x04 4.--31. 1. " REG_DDR_PHY_CTRL_1_SHDW ,Shadow field for REG_DDR_PHY_CTRL_1" bitfld.long 0x04 0.--3. " REG_READ_LATENCY_SHDW ,Shadow field for REG_READ_LATENCY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif sif (!cpuis("AM335*")) group.long 0xeC++0x03 line.long 0x00 "DDR_PHY_CTRL_2,DDR PHY Control 2 Register" endif width 0xb tree.end tree "DDR2/3/mDDR Memory Controller" base ad:0x44E12000 width 38. group.long 0x1C++0x03 line.long 0x00 "CMD0_REG_PHY_CTRL_SLAVE_RATIO_0,DDR PHY Command 0 Address/Command Slave Ratio Register" hexmask.long.word 0x00 0.--9. 1. " CMD_SLAVE_RATIO ,Ratio value for address/command launch timing in DDR PHY macro" group.long (0x1C+0x0c)++0x03 line.long 0x00 "CMD0_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Command 0 Address/Command DLL Lock Difference Register" bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Max number of delay line taps variation allowed while maintaining the master DLL l" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x1C+0x10)++0x03 line.long 0x00 "CMD0_REG_PHY_INVERT_CLKOUT_0,DDR PHY Command 0 Invert Clockout Selection Register" bitfld.long 0x00 0. " INVERT_CLK_SEL ,Inverts the polarity of DRAM clock" "Not inverted,Inverted" group.long 0x50++0x03 line.long 0x00 "CMD1_REG_PHY_CTRL_SLAVE_RATIO_0,DDR PHY Command 1 Address/Command Slave Ratio Register" hexmask.long.word 0x00 0.--9. 1. " CMD_SLAVE_RATIO ,Ratio value for address/command launch timing in DDR PHY macro" group.long (0x50+0x0c)++0x03 line.long 0x00 "CMD1_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Command 1 Address/Command DLL Lock Difference Register" bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Max number of delay line taps variation allowed while maintaining the master DLL l" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x50+0x10)++0x03 line.long 0x00 "CMD1_REG_PHY_INVERT_CLKOUT_0,DDR PHY Command 1 Invert Clockout Selection Register" bitfld.long 0x00 0. " INVERT_CLK_SEL ,Inverts the polarity of DRAM clock" "Not inverted,Inverted" group.long 0x84++0x03 line.long 0x00 "CMD2_REG_PHY_CTRL_SLAVE_RATIO_0,DDR PHY Command 2 Address/Command Slave Ratio Register" hexmask.long.word 0x00 0.--9. 1. " CMD_SLAVE_RATIO ,Ratio value for address/command launch timing in DDR PHY macro" group.long (0x84+0x0c)++0x03 line.long 0x00 "CMD2_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Command 2 Address/Command DLL Lock Difference Register" bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Max number of delay line taps variation allowed while maintaining the master DLL l" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long (0x84+0x10)++0x03 line.long 0x00 "CMD2_REG_PHY_INVERT_CLKOUT_0,DDR PHY Command 2 Invert Clockout Selection Register" bitfld.long 0x00 0. " INVERT_CLK_SEL ,Inverts the polarity of DRAM clock" "Not inverted,Inverted" group.long 0xC8++0x03 line.long 0x00 "DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0,DDR PHY Data Macro 0 Read DQS Slave Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1" endif hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0" group.long (0xC8+0x14)++0x03 line.long 0x00 "DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0,DDR PHY Data Macro 0 Write DQS Slave Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1" endif hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0" group.long (0xC8+0x28)++0x03 line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_RATIO_0,DDR PHY Data Macro 0 Write Leveling Init Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,Init Ratio used by write leveling" endif hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,Init Ratio used by write leveling" group.long (0xC8+0x30)++0x07 line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_MODE_0,DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register" bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM" "Based on write leveling,Based on WLRV_INIT_RATIO_0 reg" line.long 0x04 "DATA0_REG_PHY_GATELVL_INIT_RATIO_0,DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x04 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,Programmable init ratio used by DQS Gate" endif hexmask.long.word 0x04 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,Programmable init ratio used by DQS Gate" group.long (0xC8+0x3c)++0x03 line.long 0x00 "DATA0_REG_PHY_GATELVL_INIT_MODE_0,DDR PHY Data Macro 0 DQS Gate Training Init Mode Ratio Selection Register" bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM" "Based on write leveling,Based on PHY_GATE_LVL_RATIO_INIT_0 reg" group.long (0xC8+0x40)++0x03 line.long 0x00 "DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0,DDR PHY Data Macro 0 DQS Gate Slave Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Programmable init ratio used by DQS Gate" endif hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for fifo we for CS0" group.long (0xC8+0x54)++0x07 line.long 0x00 "DATA0_REG_PHY_DQ_OFFSET_0,Offset Value from DQS to DQ for data macro 0" sif (cpuis("AM335*")) hexmask.long.byte 0x00 0.--6. 1. " DQ_OFFSET_0 ,DQ_OFFSET_0" endif line.long 0x04 "DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0,DDR PHY Data Macro 0 Write Data Slave Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x04 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1" endif hexmask.long.word 0x04 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0" group.long (0xC8+0x6c)++0x07 line.long 0x00 "DATA0_REG_PHY_USE_RANK0_DELAYS,DDR PHY Data Macro 0 Delay Selection Register" bitfld.long 0x00 0. " PHY_USE_RANK_0_DELAYS_0 ,Delay Selection" "Low,High" line.long 0x04 "DATA0_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 0 DLL Lock Difference Register" sif (cpuis("AM335*")) bitfld.long 0x04 0.--3. " DLL_LOCK_DIFF_0 ,Max number of delay line taps variation allowed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x16C++0x03 line.long 0x00 "DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0,DDR PHY Data Macro 1 Read DQS Slave Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1" endif hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0" group.long (0x16C+0x14)++0x03 line.long 0x00 "DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0,DDR PHY Data Macro 1 Write DQS Slave Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1" endif hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0" group.long (0x16C+0x28)++0x03 line.long 0x00 "DATA1_REG_PHY_WRLVL_INIT_RATIO_0,DDR PHY Data Macro 1 Write Leveling Init Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,Init Ratio used by write leveling" endif hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,Init Ratio used by write leveling" group.long (0x16C+0x30)++0x07 line.long 0x00 "DATA1_REG_PHY_WRLVL_INIT_MODE_0,DDR PHY Data Macro 1 Write Leveling Init Mode Ratio Selection Register" bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM" "Based on write leveling,Based on WLRV_INIT_RATIO_0 reg" line.long 0x04 "DATA1_REG_PHY_GATELVL_INIT_RATIO_0,DDR PHY Data Macro 1 DQS Gate Training Init Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x04 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,Programmable init ratio used by DQS Gate" endif hexmask.long.word 0x04 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,Programmable init ratio used by DQS Gate" group.long (0x16C+0x3c)++0x03 line.long 0x00 "DATA1_REG_PHY_GATELVL_INIT_MODE_0,DDR PHY Data Macro 1 DQS Gate Training Init Mode Ratio Selection Register" bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM" "Based on write leveling,Based on PHY_GATE_LVL_RATIO_INIT_0 reg" group.long (0x16C+0x40)++0x03 line.long 0x00 "DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0,DDR PHY Data Macro 1 DQS Gate Slave Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Programmable init ratio used by DQS Gate" endif hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for fifo we for CS0" group.long (0x16C+0x54)++0x07 line.long 0x00 "DATA1_REG_PHY_DQ_OFFSET_0,Offset Value from DQS to DQ for data macro 1" sif (cpuis("AM335*")) hexmask.long.byte 0x00 0.--6. 1. " DQ_OFFSET_1 ,DQ_OFFSET_1" endif line.long 0x04 "DATA1_REG_PHY_WR_DATA_SLAVE_RATIO_0,DDR PHY Data Macro 1 Write Data Slave Ratio Register" sif (!cpuis("AM335*")) hexmask.long.word 0x04 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1" endif hexmask.long.word 0x04 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0" group.long (0x16C+0x6c)++0x07 line.long 0x00 "DATA1_REG_PHY_USE_RANK0_DELAYS,DDR PHY Data Macro 1 Delay Selection Register" bitfld.long 0x00 0. " PHY_USE_RANK_0_DELAYS_0 ,Delay Selection" "Low,High" line.long 0x04 "DATA1_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 1 DLL Lock Difference Register" sif (cpuis("AM335*")) bitfld.long 0x04 0.--3. " DLL_LOCK_DIFF_1 ,Max number of delay line taps variation allowed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0xb tree.end tree "ELM (Error Location Module)" base ad:0x48080000 width 21. rgroup.long 0x000++0x03 line.long 0x00 "ELM_REVISION,ELM Revision Register" group.long 0x010++0x03 line.long 0x00 "ELM_SYSCONFIG,ELM System Configuration Register" bitfld.long 0x00 8. " CLOCKACTIVITYOCP ,OCP Clock activity when module is in IDLE mode" "OFF,ON" bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management (IDLE req/ack control)" "Force idle,No idle,Smart idle,?..." bitfld.long 0x00 1. " SOFTRESET ,Module Software Reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " AUTOGATING ,Internal OCP clock gating strategy" "Free-running,Auto-gating" rgroup.long 0x014++0x03 line.long 0x00 "ELM_SYSSTATUS,ELM System Status Register" bitfld.long 0x00 0. " RESETDONE ,Internal Reset monitoring (OCP domain)" "On-going,Completed" group.long 0x018++0x03 line.long 0x00 "ELM_IRQSTATUS,ELM Interrupt Status Register" eventfld.long 0x00 8. " PAGE_VALID ,Error location status for a full page" "Invalid,Valid" eventfld.long 0x00 7. " LOC_VALID_7 ,Error location status for syndrome polynomial 7" "In progress,Completed" eventfld.long 0x00 6. " LOC_VALID_6 ,Error location status for syndrome polynomial 6" "In progress,Completed" textline " " eventfld.long 0x00 5. " LOC_VALID_5 ,Error location status for syndrome polynomial 5" "In progress,Completed" eventfld.long 0x00 4. " LOC_VALID_4 ,Error location status for syndrome polynomial 4" "In progress,Completed" eventfld.long 0x00 3. " LOC_VALID_3 ,Error location status for syndrome polynomial 3" "In progress,Completed" textline " " eventfld.long 0x00 2. " LOC_VALID_2 ,Error location status for syndrome polynomial 2" "In progress,Completed" eventfld.long 0x00 1. " LOC_VALID_1 ,Error location status for syndrome polynomial 1" "In progress,Completed" eventfld.long 0x00 0. " LOC_VALID_0 ,Error location status for syndrome polynomial 0" "In progress,Completed" group.long 0x01C++0x03 line.long 0x00 "ELM_IRQENABLE,ELM Interrupt Enable Register" bitfld.long 0x00 8. " PAGE_MASK ,Error location interrupt enable for a full page" "Disabled,Enabled" bitfld.long 0x00 7. " LOCATION_MASK_7 ,Error location interrupt enable for syndrome polynomial 7" "Disabled,Enabled" bitfld.long 0x00 6. " LOCATION_MASK_6 ,Error location interrupt enable for syndrome polynomial 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " LOCATION_MASK_5 ,Error location interrupt enable for syndrome polynomial 5" "Disabled,Enabled" bitfld.long 0x00 4. " LOCATION_MASK_4 ,Error location interrupt enable for syndrome polynomial 4" "Disabled,Enabled" bitfld.long 0x00 3. " LOCATION_MASK_3 ,Error location interrupt enable for syndrome polynomial 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LOCATION_MASK_2 ,Error location interrupt enable for syndrome polynomial 2" "Disabled,Enabled" bitfld.long 0x00 1. " LOCATION_MASK_1 ,Error location interrupt enable for syndrome polynomial 1" "Disabled,Enabled" bitfld.long 0x00 0. " LOCATION_MASK_0 ,Error location interrupt enable for syndrome polynomial 0" "Disabled,Enabled" group.long 0x020++0x03 line.long 0x00 "ELM_LOCATION_CONFIG,ELM Location Configuration Register" hexmask.long.word 0x00 16.--26. 1. " ECC_SIZE ,Maximum size of the buffers (number of nibbles)" bitfld.long 0x00 0.--1. " ECC_BCH_LEVEL ,Error correction level" "4 bits,8 bits,16 bits,?..." group.long 0x080++0x03 line.long 0x00 "ELM_PAGE_CTRL,ELM Page Definition Register" bitfld.long 0x00 7. " SECTOR_7 ,Syndrome polynomial 7 is part of the page in page mode" "Not used,Used" bitfld.long 0x00 6. " SECTOR_6 ,Syndrome polynomial 6 is part of the page in page mode" "Not used,Used" bitfld.long 0x00 5. " SECTOR_5 ,Syndrome polynomial 5 is part of the page in page mode" "Not used,Used" textline " " bitfld.long 0x00 4. " SECTOR_4 ,Syndrome polynomial 4 is part of the page in page mode" "Not used,Used" bitfld.long 0x00 3. " SECTOR_3 ,Syndrome polynomial 3 is part of the page in page mode" "Not used,Used" bitfld.long 0x00 2. " SECTOR_2 ,Syndrome polynomial 2 is part of the page in page mode" "Not used,Used" textline " " bitfld.long 0x00 1. " SECTOR_1 ,Syndrome polynomial 1 is part of the page in page mode" "Not used,Used" bitfld.long 0x00 0. " SECTOR_0 ,Syndrome polynomial 0 is part of the page in page mode" "Not used,Used" width 27. tree "Syndrome Polynomial 0" group.long (0x400+0x0)++0x1b line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_0,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_0,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_0,Input syndrome polynomial bits 64 to 95" line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_0,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_0,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_0,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_0,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid" hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" rgroup.long (0x800+0x0)++0x03 line.long 0x00 "ELM_LOCATION_STATUS_0,Error Location Status Register" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x880+0x0)++0x3f line.long 0x00 "ELM_ERROR_LOCATION_0_0,Error Location Register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x04 "ELM_ERROR_LOCATION_1_0,Error Location Register" hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x08 "ELM_ERROR_LOCATION_2_0,Error Location Register" hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x0c "ELM_ERROR_LOCATION_3_0,Error Location Register" hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x10 "ELM_ERROR_LOCATION_4_0,Error Location Register" hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x14 "ELM_ERROR_LOCATION_5_0,Error Location Register" hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x18 "ELM_ERROR_LOCATION_6_0,Error Location Register" hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x1c "ELM_ERROR_LOCATION_7_0,Error Location Register" hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x20 "ELM_ERROR_LOCATION_8_0,Error Location Register" hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x24 "ELM_ERROR_LOCATION_9_0,Error Location Register" hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x28 "ELM_ERROR_LOCATION_10_0,Error Location Register" hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x2c "ELM_ERROR_LOCATION_11_0,Error Location Register" hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x30 "ELM_ERROR_LOCATION_12_0,Error Location Register" hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x34 "ELM_ERROR_LOCATION_13_0,Error Location Register" hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x38 "ELM_ERROR_LOCATION_14_0,Error Location Register" hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x3c "ELM_ERROR_LOCATION_15_0,Error Location Register" hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" tree.end tree "Syndrome Polynomial 1" group.long (0x400+0x40)++0x1b line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_1,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_1,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_1,Input syndrome polynomial bits 64 to 95" line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_1,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_1,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_1,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_1,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid" hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" rgroup.long (0x800+0x100)++0x03 line.long 0x00 "ELM_LOCATION_STATUS_1,Error Location Status Register" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x880+0x100)++0x3f line.long 0x00 "ELM_ERROR_LOCATION_0_1,Error Location Register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x04 "ELM_ERROR_LOCATION_1_1,Error Location Register" hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x08 "ELM_ERROR_LOCATION_2_1,Error Location Register" hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x0c "ELM_ERROR_LOCATION_3_1,Error Location Register" hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x10 "ELM_ERROR_LOCATION_4_1,Error Location Register" hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x14 "ELM_ERROR_LOCATION_5_1,Error Location Register" hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x18 "ELM_ERROR_LOCATION_6_1,Error Location Register" hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x1c "ELM_ERROR_LOCATION_7_1,Error Location Register" hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x20 "ELM_ERROR_LOCATION_8_1,Error Location Register" hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x24 "ELM_ERROR_LOCATION_9_1,Error Location Register" hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x28 "ELM_ERROR_LOCATION_10_1,Error Location Register" hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x2c "ELM_ERROR_LOCATION_11_1,Error Location Register" hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x30 "ELM_ERROR_LOCATION_12_1,Error Location Register" hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x34 "ELM_ERROR_LOCATION_13_1,Error Location Register" hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x38 "ELM_ERROR_LOCATION_14_1,Error Location Register" hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x3c "ELM_ERROR_LOCATION_15_1,Error Location Register" hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" tree.end tree "Syndrome Polynomial 2" group.long (0x400+0x80)++0x1b line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_2,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_2,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_2,Input syndrome polynomial bits 64 to 95" line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_2,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_2,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_2,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_2,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid" hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" rgroup.long (0x800+0x200)++0x03 line.long 0x00 "ELM_LOCATION_STATUS_2,Error Location Status Register" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x880+0x200)++0x3f line.long 0x00 "ELM_ERROR_LOCATION_0_2,Error Location Register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x04 "ELM_ERROR_LOCATION_1_2,Error Location Register" hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x08 "ELM_ERROR_LOCATION_2_2,Error Location Register" hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x0c "ELM_ERROR_LOCATION_3_2,Error Location Register" hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x10 "ELM_ERROR_LOCATION_4_2,Error Location Register" hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x14 "ELM_ERROR_LOCATION_5_2,Error Location Register" hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x18 "ELM_ERROR_LOCATION_6_2,Error Location Register" hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x1c "ELM_ERROR_LOCATION_7_2,Error Location Register" hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x20 "ELM_ERROR_LOCATION_8_2,Error Location Register" hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x24 "ELM_ERROR_LOCATION_9_2,Error Location Register" hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x28 "ELM_ERROR_LOCATION_10_2,Error Location Register" hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x2c "ELM_ERROR_LOCATION_11_2,Error Location Register" hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x30 "ELM_ERROR_LOCATION_12_2,Error Location Register" hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x34 "ELM_ERROR_LOCATION_13_2,Error Location Register" hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x38 "ELM_ERROR_LOCATION_14_2,Error Location Register" hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x3c "ELM_ERROR_LOCATION_15_2,Error Location Register" hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" tree.end tree "Syndrome Polynomial 3" group.long (0x400+0xC0)++0x1b line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_3,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_3,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_3,Input syndrome polynomial bits 64 to 95" line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_3,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_3,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_3,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_3,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid" hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" rgroup.long (0x800+0x300)++0x03 line.long 0x00 "ELM_LOCATION_STATUS_3,Error Location Status Register" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x880+0x300)++0x3f line.long 0x00 "ELM_ERROR_LOCATION_0_3,Error Location Register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x04 "ELM_ERROR_LOCATION_1_3,Error Location Register" hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x08 "ELM_ERROR_LOCATION_2_3,Error Location Register" hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x0c "ELM_ERROR_LOCATION_3_3,Error Location Register" hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x10 "ELM_ERROR_LOCATION_4_3,Error Location Register" hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x14 "ELM_ERROR_LOCATION_5_3,Error Location Register" hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x18 "ELM_ERROR_LOCATION_6_3,Error Location Register" hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x1c "ELM_ERROR_LOCATION_7_3,Error Location Register" hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x20 "ELM_ERROR_LOCATION_8_3,Error Location Register" hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x24 "ELM_ERROR_LOCATION_9_3,Error Location Register" hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x28 "ELM_ERROR_LOCATION_10_3,Error Location Register" hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x2c "ELM_ERROR_LOCATION_11_3,Error Location Register" hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x30 "ELM_ERROR_LOCATION_12_3,Error Location Register" hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x34 "ELM_ERROR_LOCATION_13_3,Error Location Register" hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x38 "ELM_ERROR_LOCATION_14_3,Error Location Register" hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x3c "ELM_ERROR_LOCATION_15_3,Error Location Register" hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" tree.end tree "Syndrome Polynomial 4" group.long (0x400+0x100)++0x1b line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_4,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_4,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_4,Input syndrome polynomial bits 64 to 95" line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_4,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_4,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_4,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_4,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid" hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" rgroup.long (0x800+0x400)++0x03 line.long 0x00 "ELM_LOCATION_STATUS_4,Error Location Status Register" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x880+0x400)++0x3f line.long 0x00 "ELM_ERROR_LOCATION_0_4,Error Location Register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x04 "ELM_ERROR_LOCATION_1_4,Error Location Register" hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x08 "ELM_ERROR_LOCATION_2_4,Error Location Register" hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x0c "ELM_ERROR_LOCATION_3_4,Error Location Register" hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x10 "ELM_ERROR_LOCATION_4_4,Error Location Register" hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x14 "ELM_ERROR_LOCATION_5_4,Error Location Register" hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x18 "ELM_ERROR_LOCATION_6_4,Error Location Register" hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x1c "ELM_ERROR_LOCATION_7_4,Error Location Register" hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x20 "ELM_ERROR_LOCATION_8_4,Error Location Register" hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x24 "ELM_ERROR_LOCATION_9_4,Error Location Register" hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x28 "ELM_ERROR_LOCATION_10_4,Error Location Register" hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x2c "ELM_ERROR_LOCATION_11_4,Error Location Register" hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x30 "ELM_ERROR_LOCATION_12_4,Error Location Register" hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x34 "ELM_ERROR_LOCATION_13_4,Error Location Register" hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x38 "ELM_ERROR_LOCATION_14_4,Error Location Register" hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x3c "ELM_ERROR_LOCATION_15_4,Error Location Register" hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" tree.end tree "Syndrome Polynomial 5" group.long (0x400+0x140)++0x1b line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_5,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_5,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_5,Input syndrome polynomial bits 64 to 95" line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_5,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_5,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_5,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_5,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid" hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" rgroup.long (0x800+0x500)++0x03 line.long 0x00 "ELM_LOCATION_STATUS_5,Error Location Status Register" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x880+0x500)++0x3f line.long 0x00 "ELM_ERROR_LOCATION_0_5,Error Location Register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x04 "ELM_ERROR_LOCATION_1_5,Error Location Register" hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x08 "ELM_ERROR_LOCATION_2_5,Error Location Register" hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x0c "ELM_ERROR_LOCATION_3_5,Error Location Register" hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x10 "ELM_ERROR_LOCATION_4_5,Error Location Register" hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x14 "ELM_ERROR_LOCATION_5_5,Error Location Register" hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x18 "ELM_ERROR_LOCATION_6_5,Error Location Register" hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x1c "ELM_ERROR_LOCATION_7_5,Error Location Register" hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x20 "ELM_ERROR_LOCATION_8_5,Error Location Register" hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x24 "ELM_ERROR_LOCATION_9_5,Error Location Register" hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x28 "ELM_ERROR_LOCATION_10_5,Error Location Register" hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x2c "ELM_ERROR_LOCATION_11_5,Error Location Register" hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x30 "ELM_ERROR_LOCATION_12_5,Error Location Register" hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x34 "ELM_ERROR_LOCATION_13_5,Error Location Register" hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x38 "ELM_ERROR_LOCATION_14_5,Error Location Register" hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x3c "ELM_ERROR_LOCATION_15_5,Error Location Register" hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" tree.end tree "Syndrome Polynomial 6" group.long (0x400+0x180)++0x1b line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_6,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_6,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_6,Input syndrome polynomial bits 64 to 95" line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_6,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_6,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_6,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_6,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid" hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" rgroup.long (0x800+0x600)++0x03 line.long 0x00 "ELM_LOCATION_STATUS_6,Error Location Status Register" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x880+0x600)++0x3f line.long 0x00 "ELM_ERROR_LOCATION_0_6,Error Location Register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x04 "ELM_ERROR_LOCATION_1_6,Error Location Register" hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x08 "ELM_ERROR_LOCATION_2_6,Error Location Register" hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x0c "ELM_ERROR_LOCATION_3_6,Error Location Register" hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x10 "ELM_ERROR_LOCATION_4_6,Error Location Register" hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x14 "ELM_ERROR_LOCATION_5_6,Error Location Register" hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x18 "ELM_ERROR_LOCATION_6_6,Error Location Register" hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x1c "ELM_ERROR_LOCATION_7_6,Error Location Register" hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x20 "ELM_ERROR_LOCATION_8_6,Error Location Register" hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x24 "ELM_ERROR_LOCATION_9_6,Error Location Register" hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x28 "ELM_ERROR_LOCATION_10_6,Error Location Register" hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x2c "ELM_ERROR_LOCATION_11_6,Error Location Register" hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x30 "ELM_ERROR_LOCATION_12_6,Error Location Register" hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x34 "ELM_ERROR_LOCATION_13_6,Error Location Register" hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x38 "ELM_ERROR_LOCATION_14_6,Error Location Register" hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x3c "ELM_ERROR_LOCATION_15_6,Error Location Register" hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" tree.end tree "Syndrome Polynomial 7" group.long (0x400+0x1C0)++0x1b line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_7,Input syndrome polynomial bits 0 to 31" line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_7,Input syndrome polynomial bits 32 to 63" line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_7,Input syndrome polynomial bits 64 to 95" line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_7,Input syndrome polynomial bits 96 to 127" line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_7,Input syndrome polynomial bits 128 to 159" line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_7,Input syndrome polynomial bits 160 to 191" line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_7,Input syndrome polynomial bits 192 to 207" bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid" hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" rgroup.long (0x800+0x700)++0x03 line.long 0x00 "ELM_LOCATION_STATUS_7,Error Location Status Register" bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful" bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long (0x880+0x700)++0x3f line.long 0x00 "ELM_ERROR_LOCATION_0_7,Error Location Register" hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x04 "ELM_ERROR_LOCATION_1_7,Error Location Register" hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x08 "ELM_ERROR_LOCATION_2_7,Error Location Register" hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x0c "ELM_ERROR_LOCATION_3_7,Error Location Register" hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x10 "ELM_ERROR_LOCATION_4_7,Error Location Register" hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x14 "ELM_ERROR_LOCATION_5_7,Error Location Register" hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x18 "ELM_ERROR_LOCATION_6_7,Error Location Register" hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x1c "ELM_ERROR_LOCATION_7_7,Error Location Register" hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x20 "ELM_ERROR_LOCATION_8_7,Error Location Register" hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x24 "ELM_ERROR_LOCATION_9_7,Error Location Register" hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x28 "ELM_ERROR_LOCATION_10_7,Error Location Register" hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x2c "ELM_ERROR_LOCATION_11_7,Error Location Register" hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x30 "ELM_ERROR_LOCATION_12_7,Error Location Register" hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x34 "ELM_ERROR_LOCATION_13_7,Error Location Register" hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x38 "ELM_ERROR_LOCATION_14_7,Error Location Register" hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" line.long 0x3c "ELM_ERROR_LOCATION_15_7,Error Location Register" hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address" tree.end width 11. tree.end tree.open "PRCM (Power Management and Clock Module)" tree "CM (Clock Module Registers)" tree "CM_PER" base ad:0x44E00000 width 28. group.long 0x000++0x03 line.long 0x00 "CM_PER_L4LS_CLKSTCTRL,L4LS Clock State Control Register" bitfld.long 0x00 28. " CLKACTIVITY_TIMER6_GCLK ,State of the TIMER6 CLKTIMER clock in the domain" "Gated,Active" bitfld.long 0x00 27. " CLKACTIVITY_TIMER5_GCLK ,State of the TIMER5 CLKTIMER clock in the domain" "Gated,Active" bitfld.long 0x00 26. " CLKACTIVITY_GPIO_5_GDBCLK ,State of the GPIO DBCLK clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 25. " CLKACTIVITY_SPI_GCLK ,State of the SPI_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 24. " CLKACTIVITY_I2C_FCLK ,State of the I2C _FCLK clock in the domain" "Gated,Active" bitfld.long 0x00 22. " CLKACTIVITY_GPIO_4_GDBCLK ,State of the GPIO4_GDBCLK clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 21. " CLKACTIVITY_GPIO_3_GDBCLK ,State of the GPIO3_GDBCLK clock in the domain" "Gated,Active" bitfld.long 0x00 20. " CLKACTIVITY_GPIO_2_GDBCLK ,State of the GPIO2_GDBCLK clock in the domain" "Gated,Active" bitfld.long 0x00 19. " CLKACTIVITY_GPIO_1_GDBCLK ,State of the GPIO1_GDBCLK clock in the domain" "Gated,Active" textline " " sif (!cpuis("AM335*")) bitfld.long 0x00 18. " CLKACTIVITY_GPIO_6_GDBCLK ,State of the GPIO6_GDBCLK clock in the domain" "Gated,Active" bitfld.long 0x00 17. " CLKACTIVITY_LCDC_GCLK ,State of the LCD clock in the domain" "Gated,Active" else bitfld.long 0x00 17. " CLKACTIVITY_LCDC_GCLK ,State of the LCD clock in the domain" "Gated,Active" endif bitfld.long 0x00 16. " CLKACTIVITY_TIMER4_GCLK ,State of the TIMER4 CLKTIMER clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 15. " CLKACTIVITY_TIMER3_GCLK ,State of the TIMER3 CLKTIMER clock in the domain" "Gated,Active" bitfld.long 0x00 14. " CLKACTIVITY_TIMER2_GCLK ,State of the TIMER2 CLKTIMER clock in the domain" "Gated,Active" bitfld.long 0x00 13. " CLKACTIVITY_TIMER7_GCLK ,State of the TIMER7 CLKTIMER clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 11. " CLKACTIVITY_CAN_CLK ,State of the CAN_CLK clock in the domain" "Gated,Active" bitfld.long 0x00 10. " CLKACTIVITY_UART_GFCLK ,State of the UART_GFCLK clock in the domain" "Gated,Active" bitfld.long 0x00 8. " CLKACTIVITY_L4LS_GCLK ,State of the L4LS_GCLK clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4 SLOW clock domain in PER power domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x004++0x03 line.long 0x00 "CM_PER_L3S_CLKSTCTRL,L3S Clock State Control Register" bitfld.long 0x00 3. " CLKACTIVITY_L3S_GCLK ,State of the L3S_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3 Slow clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x008++0x03 line.long 0x00 "CM_PER_L4FW_CLKSTCTRL,L4FW Clock State Control Register" bitfld.long 0x00 8. " CLKACTIVITY_L4FW_GCLK ,state of the L4FW clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4 Firewall clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x00C++0x03 line.long 0x00 "CM_PER_L3_CLKSTCTRL,L3 Clock State Control Register" bitfld.long 0x00 7. " CLKACTIVITY_MCASP_GCLK ,State of the MCASP_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 6. " CLKACTIVITY_CPTS_RFT_GCLK ,State of the CLKACTIVITY_CPTS_RFT_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 4. " CLKACTIVITY_L3_GCLK ,State of the L3_GCLK clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 3. " CLKACTIVITY_MMC_FCLK ,State of the MMC_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 2. " CLKACTIVITY_EMIF_GCLK ,State of the EMIF_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3 clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" sif (!cpuis("AM335*")) group.long 0x010++0x03 line.long 0x00 "CM_PER_PCIE_CLKCTRL,PCIE Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." endif group.long 0x014++0x03 line.long 0x00 "CM_PER_CPGMAC0_CLKCTRL,CPSW Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x018++0x03 line.long 0x00 "CM_PER_LCDC_CLKCTRL,LCD Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x01C++0x03 line.long 0x00 "CM_PER_USB0_CLKCTRL,USB Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." sif (!cpuis("AM335*")) group.long 0x020++0x03 line.long 0x00 "CM_PER_MLB_CLKCTRL,MLB Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." endif group.long 0x024++0x03 line.long 0x00 "CM_PER_TPTC0_CLKCTRL,TPTC Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x028++0x03 line.long 0x00 "CM_PER_EMIF_CLKCTRL,EMIF Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x02C++0x03 line.long 0x00 "CM_PER_OCMCRAM_CLKCTRL,OCMC Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x030++0x03 line.long 0x00 "CM_PER_GPMC_CLKCTRL,GPMC Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x034++0x03 line.long 0x00 "CM_PER_MCASP0_CLKCTRL,MCASP0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x038++0x03 line.long 0x00 "CM_PER_UART5_CLKCTRL,UART5 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x03C++0x03 line.long 0x00 "CM_PER_MMC0_CLKCTRL,MMC0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x040++0x03 line.long 0x00 "CM_PER_ELM_CLKCTRL,ELM Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x044++0x03 line.long 0x00 "CM_PER_I2C2_CLKCTRL,I2C2 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x048++0x03 line.long 0x00 "CM_PER_I2C1_CLKCTRL,I2C1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x04C++0x03 line.long 0x00 "CM_PER_SPI0_CLKCTRL,SPI0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x050++0x03 line.long 0x00 "CM_PER_SPI1_CLKCTRL,SPI1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." sif (!cpuis("AM335*")) group.long 0x054++0x03 line.long 0x00 "CM_PER_SPI2_CLKCTRL,SPI2 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x058++0x03 line.long 0x00 "CM_PER_SPI3_CLKCTRL,SPI3 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." endif group.long 0x060++0x03 line.long 0x00 "CM_PER_L4LS_CLKCTRL,L4LS Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x064++0x03 line.long 0x00 "CM_PER_L4FW_CLKCTRL,L4FW Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x068++0x03 line.long 0x00 "CM_PER_MCASP1_CLKCTRL,MCASP1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x06C++0x03 line.long 0x00 "CM_PER_UART1_CLKCTRL,IART1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x070++0x03 line.long 0x00 "CM_PER_UART2_CLKCTRL,UART2 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x074++0x03 line.long 0x00 "CM_PER_UART3_CLKCTRL,UART3 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x078++0x03 line.long 0x00 "CM_PER_UART4_CLKCTRL,UART4 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x07C++0x03 line.long 0x00 "CM_PER_TIMER7_CLKCTRL,TIMER7 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x080++0x03 line.long 0x00 "CM_PER_TIMER2_CLKCTRL,TIMER2 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x084++0x03 line.long 0x00 "CM_PER_TIMER3_CLKCTRL,TIMER3 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x088++0x03 line.long 0x00 "CM_PER_TIMER4_CLKCTRL,TIMER4 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." sif (!cpuis("AM335*")) group.long 0x08C++0x03 line.long 0x00 "CM_PER_MCASP2_CLKCTRL,MCASP2 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x090++0x03 line.long 0x00 "CM_PER_RNG_CLKCTRL,RNG Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x094++0x03 line.long 0x00 "CM_PER_AES0_CLKCTRL,AES0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x098++0x03 line.long 0x00 "CM_PER_AES1_CLKCTRL,AES1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x09C++0x03 line.long 0x00 "CM_PER_DES_CLKCTRL,DES Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0A0++0x03 line.long 0x00 "CM_PER_SHA0_CLKCTRL,SHA0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0A4++0x03 line.long 0x00 "CM_PER_PKA_CLKCTRL,PKA Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0A8++0x03 line.long 0x00 "CM_PER_GPIO6_CLKCTRL,GPIO6 Clocks Control Register" bitfld.long 0x00 18. " OPTFCLKEN_GPIO_6_GDBCLK ,Optional functional clock control" "FCLK_DIS,FCLK_EN" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." endif group.long 0x0AC++0x03 line.long 0x00 "CM_PER_GPIO1_CLKCTRL,GPIO1 Clocks Control Register" bitfld.long 0x00 18. " OPTFCLKEN_GPIO_1_GDBCLK ,Optional functional clock control" "FCLK_DIS,FCLK_EN" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0B0++0x03 line.long 0x00 "CM_PER_GPIO2_CLKCTRL,GPIO2 Clocks Control Register" bitfld.long 0x00 18. " OPTFCLKEN_GPIO_2_GDBCLK ,Optional functional clock control" "FCLK_DIS,FCLK_EN" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0B4++0x03 line.long 0x00 "CM_PER_GPIO3_CLKCTRL,GPIO3 Clocks Control Register" bitfld.long 0x00 18. " OPTFCLKEN_GPIO_3_GDBCLK ,Optional functional clock control" "FCLK_DIS,FCLK_EN" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." sif (!cpuis("AM335*")) group.long 0x0B8++0x03 line.long 0x00 "CM_PER_GPIO4_CLKCTRL,GPIO4 Clocks Control Register" bitfld.long 0x00 18. " OPTFCLKEN_GPIO_4_GDBCLK ,Optional functional clock control" "FCLK_DIS,FCLK_EN" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." endif group.long 0x0BC++0x03 line.long 0x00 "CM_PER_TPCC_CLKCTRL,TPCC Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0C0++0x03 line.long 0x00 "CM_PER_DCAN0_CLKCTRL,DCAN0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0C4++0x03 line.long 0x00 "CM_PER_DCAN1_CLKCTRL,DCAN1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." ; group.long 0x0C8++0x03 ; line.long 0x00 "CM_PER_SPARE_CLKCTRL,This register is reserved" ; bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" ; bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" ; bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0CC++0x03 line.long 0x00 "CM_PER_EPWMSS1_CLKCTRL,PWMSS1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0D0++0x03 line.long 0x00 "CM_PER_EMIF_FW_CLKCTRL,EMIF Firewall Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0D4++0x03 line.long 0x00 "CM_PER_EPWMSS0_CLKCTRL,PWMSS0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0D8++0x03 line.long 0x00 "CM_PER_EPWMSS2_CLKCTRL,PWMSS2 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0DC++0x03 line.long 0x00 "CM_PER_L3_INSTR_CLKCTRL,L3 INSTR Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0E0++0x03 line.long 0x00 "CM_PER_L3_CLKCTRL,L3 Interconnect Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0E4++0x03 line.long 0x00 "CM_PER_IEEE5000_CLKCTRL,IEEE1500 Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0EC++0x03 line.long 0x00 "CM_PER_TIMER5_CLKCTRL,TIMER5 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0F0++0x03 line.long 0x00 "CM_PER_TIMER6_CLKCTRL,TIMER6 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0F4++0x03 line.long 0x00 "CM_PER_MMC1_CLKCTRL,MMC1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0F8++0x03 line.long 0x00 "CM_PER_MMC2_CLKCTRL,MMC2 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x0FC++0x03 line.long 0x00 "CM_PER_TPTC1_CLKCTRL,TPTC1 Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x100++0x03 line.long 0x00 "CM_PER_TPTC2_CLKCTRL,TPTC2 Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." sif (!cpuis("AM335*")) group.long 0x104++0x03 line.long 0x00 "CM_PER_GPIO5_CLKCTRL,GPIO5 Clocks Control Register" bitfld.long 0x00 18. " OPTFCLKEN_GPIO_5_GDBCLK ,Optional functional clock control" "FCLK_DIS,FCLK_EN" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." endif group.long 0x10C++0x03 line.long 0x00 "CM_PER_SPINLOCK_CLKCTRL,SPINLOCK Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x110++0x03 line.long 0x00 "CM_PER_MAILBOX0_CLKCTRL,MAILBOX0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x11C++0x03 line.long 0x00 "CM_PER_L4HS_CLKSTCTRL,L4HS Clock State Control Register" bitfld.long 0x00 6. " CLKACTIVITY_CPSW_5MHZ_GCLK ,State of the CPSW_5MHZ_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 5. " CLKACTIVITY_CPSW_50MHZ_GCLK ,State of the CPSW_50MHZ_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 4. " CLKACTIVITY_CPSW_250MHZ_GCLK ,State of the CPSW_250MHZ_GCLK clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 3. " CLKACTIVITY_L4HS_GCLK ,State of the L4HS_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4 Fast clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x120++0x03 line.long 0x00 "CM_PER_L4HS_CLKCTRL,L4 Fast Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." sif (!cpuis("AM335*")) group.long 0x124++0x03 line.long 0x00 "CM_PER_MSTR_EXPS_CLKCTRL,Master Expansion Port Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x128++0x03 line.long 0x00 "CM_PER_SLV_EXPS_CLKCTRL,Slave Expansion Port Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." endif group.long 0x12C++0x03 line.long 0x00 "CM_PER_OCPWP_L3_CLKSTCTRL,OCPWP L3 Clock State Control Register" bitfld.long 0x00 5. " CLKACTIVITY_OCPWP_L4_GCLK ,State of the OCPWP L4 clock in the domain" "Gated,Active" bitfld.long 0x00 4. " CLKACTIVITY_OCPWP_L3_GCLK ,State of the OCPWP L3 clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the OCPWP clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x130++0x03 line.long 0x00 "CM_PER_OCPWP_CLKCTRL,OCPWP Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." sif (!cpuis("AM335*")) group.long 0x134++0x03 line.long 0x00 "CM_PER_MAILBOX1_CLKCTRL,Mailbox1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x138++0x03 line.long 0x00 "CM_PER_SPARE0_CLKCTRL,Spare0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x13C++0x03 line.long 0x00 "CM_PER_SPARE1_CLKCTRL,Spare1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." endif group.long 0x144++0x03 line.long 0x00 "CM_PER_CPSW_CLKSTCTRL,CPSW Clock State Control Register" bitfld.long 0x00 4. " CLKACTIVITY_CPSW_125MHz_GCLK ,State of the CPSW 125 MHz OCP clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the CPSW OCP clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x148++0x03 line.long 0x00 "CM_PER_LCDC_CLKSTCTRL,LCDC Clock State Control Register" bitfld.long 0x00 5. " CLKACTIVITY_LCDC_L4_OCP_GCLK ,State of the LCDC L4 OCP clock in the domain" "Gated,Active" bitfld.long 0x00 4. " CLKACTIVITY_LCDC_L3_OCP_GCLK ,State of the LCDC L3 OCP clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the LCDC OCP clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0x14C++0x03 line.long 0x00 "CM_PER_CLKDIV32K_CLKCTRL,CLKDIV32K Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." group.long 0x150++0x03 line.long 0x00 "CM_PER_CLK_24MHZ_CLKSTCTRL,CLK 24MHz Clock State Control Register" bitfld.long 0x00 4. " CLKACTIVITY_CLK_24MHZ_GCLK ,State of the 24MHz clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the 24MHz clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" width 11. tree.end tree "CM_WKUP" base ad:0x44E00000 width 30. group.long 0x400++0x0B line.long 0x00 "CM_WKUP_CLKSTCTRL,WKUP Clock State Control Register" bitfld.long 0x00 14. " CLKACTIVITY_ADC_FCLK ,State of the ADC clock in the domain" "Gated,Active" bitfld.long 0x00 13. " CLKACTIVITY_TIMER1_GCLK ,State of the TIMER1 clock in the domain" "Gated,Active" bitfld.long 0x00 12. " CLKACTIVITY_UART0_GFCLK ,State of the UART0 clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 11. " CLKACTIVITY_I2C0_GFCLK ,State of the I2C0 clock in the domain" "Gated,Active" bitfld.long 0x00 10. " CLKACTIVITY_TIMER0_GCLK ,State of the WKUPTIMER_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 8. " CLKACTIVITY_GPIO0_GDBCLK ,State of the WKUPGPIO_DBGICLK clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 4. " CLKACTIVITY_WDT1_GCLK ,State of the WDT1_GCLK clock in the domain" "Gated,Active" bitfld.long 0x00 3. " CLKACTIVITY_SR_SYSCLK ,State of the SMARTREFGLEX SYSCLK clock in the domain" "Gated,Active" bitfld.long 0x00 2. " CLKACTIVITY_L4_WKUP_GCLK ,State of the L4_WKUP clock in the domain" "Gated,Active" textline " " bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the always on clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" line.long 0x04 "CM_WKUP_CONTROL_CLKCTRL,Control Module Clocks Control Register" bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x04 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x08 "CM_WKUP_GPIO0_CLKCTRL,GPIO0 Clocks Control Register" bitfld.long 0x08 18. " OPTFCLKEN_GPIO0_GDBCLK ,Optional functional clock control" "FCLK_DIS,FCLK_EN" bitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x08 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." rgroup.long 0x40C++0x03 line.long 0x00 "CM_WKUP_L4WKUP_CLKCTRL,L4WKUP Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "0,1,2,3" group.long 0x410++0x0F line.long 0x00 "CM_WKUP_TIMER0_CLKCTRL,TIMER0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x04 "CM_WKUP_DEBUGSS_CLKCTRL,DEBUGSS Clocks Control Register" bitfld.long 0x04 30. " OPTCLK_DEBUG_CLKA ,OPTCLK_DEBUG_CLKA" "0,1" bitfld.long 0x04 27.--29. " STM_PMD_CLKDIVSEL ,STM_PMD_CLKDIVSEL" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. " TRC_PMD_CLKDIVSEL ,TRC_PMD_CLKDIVSEL" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 22.--23. " STM_PMD_CLKSEL ,STM_PMD_CLKSEL" "0,1,2,3" bitfld.long 0x04 20.--21. " TRC_PMD_CLKSEL ,TRC_PMD_CLKSEL" "0,1,2,3" bitfld.long 0x04 19. " OPTFCLKEN_DBGSYSCLK ,Optional functional clock control" "FCLK_DIS,FCLK_EN" textline " " bitfld.long 0x04 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x04 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x08 "CM_L3_AON_CLKSTCTRL,L3 AON Clock State Control Register" bitfld.long 0x08 4. " CLKACTIVITY_DEBUG_CLKA ,State of the Debugss CLKA clock in the domain" "0,1" bitfld.long 0x08 3. " CLKACTIVITY_L3_AON_GCLK ,State of the L3_AON clock in the domain" "Gated,Active" textline " " bitfld.long 0x08 2. " CLKACTIVITY_DBGSYSCLK ,State of the Debugss sysclk clock in the domain" "Gated,Active" bitfld.long 0x08 0.--1. " CLKTRCTRL ,Controls the clock state transition of the l3 AON clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" line.long 0x0C "CM_AUTOIDLE_DPLL_MPU,DPLL Automatic Activity Contorol Regster" bitfld.long 0x0C 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control" "AUTO_CTL_DISABLE,AUTO_LP_STOP,Reserved,Reserved,Reserved,AUTO_LP_BYP,?..." rgroup.long 0x420++0x03 line.long 0x00 "CM_IDLEST_DPLL_MPU,MPU Master Clock Activity Monitoring Register" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "NO_MNBYPASS,MN_BYPASS" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "DPLL_UNLOCKED,DPLL_LOCKED" group.long 0x424++0x0F line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_MPU,MPU DeltaMStep Parameter for Spread Spectrum Clocking Control Register" sif (cpuis("AM335*")) bitfld.long 0x00 18.--19. " DELTAMSTEP_INTEGER ,Integer part for DeltaM coefficient" "0,1,2,3" hexmask.long.tbyte 0x00 0.--17. 1. " DELTAMSTEP_FRACTION ,Fractional setting for DeltaMStep parameter" else hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" endif line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_MPU,MPU Modulation Frequency for Spread Spectrum Clocking Control Register" bitfld.long 0x04 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_CLKSEL_DPLL_MPU,MPU DPLL Control Register" bitfld.long 0x08 23. " DPLL_BYP_CLKSEL ,Selects CLKINP or CLKINPULOW as Bypass Clock" "Sel0,Sel1" hexmask.long.word 0x08 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor" hexmask.long.byte 0x08 0.--6. 1. " DPLL_DIV ,DPLL divider factor" line.long 0x0C "CM_AUTOIDLE_DPLL_DDR,DDR DPLL Automatic Activity Control Register" bitfld.long 0x0C 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control" "AUTO_CTL_DISABLE,AUTO_LP_STOP,Reserved,Reserved,Reserved,AUTO_LP_BYP,?..." rgroup.long 0x434++0x03 line.long 0x00 "CM_IDLEST_DPLL_DDR,DDR Master Clock Activity Monitoring Register" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "NO_MNBYPASS,MN_BYPASS" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "DPLL_UNLOCKED,DPLL_LOCKED" group.long 0x438++0x0F line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_DDR,DDR DeltaMStep Parameter for Spread Spectrum Clocking Control Register" sif (cpuis("AM335*")) bitfld.long 0x00 18.--19. " DELTAMSTEP_INTEGER ,Integer part for DeltaM coefficient" "0,1,2,3" hexmask.long.tbyte 0x00 0.--17. 1. " DELTAMSTEP_FRACTION ,Fractional setting for DeltaMStep parameter" else hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" endif line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_DDR,DDR Modulation Frequency for Spread Spectrum Clocking Control Register" bitfld.long 0x04 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_CLKSEL_DPLL_DDR,DDR DPLL Control Register" bitfld.long 0x08 23. " DPLL_BYP_CLKSEL ,Select CLKINP orr CLKINPULOW as bypass clock" "Sel0,Sel1" hexmask.long.word 0x08 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor" hexmask.long.byte 0x08 0.--6. 1. " DPLL_DIV ,DPLL divider factor" line.long 0x0C "CM_AUTOIDLE_DPLL_DISP,DISP DPLL Automatic Activity Control Register" bitfld.long 0x0C 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control" "AUTO_CTL_DISABLE,AUTO_LP_STOP,Reserved,Reserved,Reserved,AUTO_LP_BYP,?..." rgroup.long 0x448++0x03 line.long 0x00 "CM_IDLEST_DPLL_DISP,DISP Master Clock Activity Monitoring Register" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "NO_MNBYPASS,MN_BYPASS" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "DPLL_UNLOCKED,DPLL_LOCKED" group.long 0x44C++0x0F line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_DISP,DISP DeltaMStep Parameter for Spread Spectrum Clocking Control Register" sif (cpuis("AM335*")) bitfld.long 0x00 18.--19. " DELTAMSTEP_INTEGER ,Integer part for DeltaM coefficient" "0,1,2,3" hexmask.long.tbyte 0x00 0.--17. 1. " DELTAMSTEP_FRACTION ,Fractional setting for DeltaMStep parameter" else hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" endif line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_DISP,DISP Modulation Frequency for Spread Spectrum Clocking Control Register" bitfld.long 0x04 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_CLKSEL_DPLL_DISP,DISP DPLL Control Register" bitfld.long 0x08 23. " DPLL_BYP_CLKSEL ,Select CLKINP or CLKINPULOW as bypass clock" "Sel0,Sel1" hexmask.long.word 0x08 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor" hexmask.long.byte 0x08 0.--6. 1. " DPLL_DIV ,DPLL divider factor" line.long 0x0C "CM_AUTOIDLE_DPLL_CORE,CORE DPLL Automatic Activity Control Register" bitfld.long 0x0C 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control" "AUTO_CTL_DISABLE,AUTO_LP_STOP,Reserved,Reserved,Reserved,AUTO_LP_BYP,?..." rgroup.long 0x45C++0x03 line.long 0x00 "CM_IDLEST_DPLL_CORE,CORE Master Clock Activity Monitoring Register" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "NO_MNBYPASS,MN_BYPASS" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "DPLL_UNLOCKED,DPLL_LOCKED" group.long 0x460++0x0F line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_CORE,CORE DeltaMStep Parameter for Spread Spectrum Clocking Control Register" hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_CORE,CORE Modulation Frequency for Spread Spectrum Clocking Control Register" bitfld.long 0x04 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_CLKSEL_DPLL_CORE,CORE DPLL Control Register" hexmask.long.word 0x08 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor" hexmask.long.byte 0x08 0.--6. 1. " DPLL_DIV ,DPLL divider factor" line.long 0x0C "CM_AUTOIDLE_DPLL_PER,PER DPLL Automatic Activity Control Register" bitfld.long 0x0C 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control" "AUTO_CTL_DISABLE,AUTO_LP_STOP,Reserved,Reserved,Reserved,AUTO_LP_BYP,?..." rgroup.long 0x470++0x03 line.long 0x00 "CM_IDLEST_DPLL_PER,PER Master Clock Activity Monitoring Register" bitfld.long 0x00 8. " ST_MN_BYPASS ,DPLL MN_BYPASS status" "NO_MNBYPASS,MN_BYPASS" bitfld.long 0x00 0. " ST_DPLL_CLK ,DPLL clock activity" "DPLL_UNLOCKED,DPLL_LOCKED" group.long 0x474++0x3B line.long 0x00 "CM_SSC_DELTAMSTEP_DPLL_PER,PER DeltaMStep Parameter for Spread Spectrum Clocking Control Register" sif (cpuis("AM335*")) bitfld.long 0x00 18.--19. " DELTAMSTEP_INTEGER ,Integer part for DeltaM coefficient" "0,1,2,3" hexmask.long.tbyte 0x00 0.--17. 1. " DELTAMSTEP_FRACTION ,Fractional setting for DeltaMStep parameter" else hexmask.long.tbyte 0x00 0.--19. 1. " DELTAMSTEP ,Fractional setting for DeltaMStep parameter" endif line.long 0x04 "CM_SSC_MODFREQDIV_DPLL_PER,PER Modulation Frequency for Spread Spectrum Clocking Control Register" bitfld.long 0x04 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x04 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" line.long 0x08 "CM_CLKDCOLDO_DPLL_PER,Digitally Controlled Oscillator Output of the PER DPLL Control Register" bitfld.long 0x08 12. " DPLL_CLKDCOLDO_PWDN ,Automatic power down for CLKDCOLDO o/p when it is gated" "ALWAYS_ACTIVE,AUTO_PWDN" bitfld.long 0x08 9. " ST_DPLL_CLKDCOLDO ,DPLL CLKDCOLDO status" "CLK_ENABLED,CLK_GATED" bitfld.long 0x08 8. " DPLL_CLKDCOLDO_GATE_CTRL ,Control gating of DPLL CLKDCOLDO" "CLK_AUTOGATE,CLK_ENABLE" line.long 0x0C "CM_DIV_M4_DPLL_CORE,CLKOUT1 o/p of the HSDIVIDER Control Register" bitfld.long 0x0C 12. " HSDIVIDER_CLKOUT1_PWDN ,Automatic power down for HSDIVIDER M4 divider and hence CLKOUT1 output when the o/p clock is gated" "ALWAYS_ACTIVE,AUTO_PWDN" bitfld.long 0x0C 9. " ST_HSDIVIDER_CLKOUT1 ,HSDIVIDER CLKOUT1 status" "CLK_ENABLED,CLK_GATED" bitfld.long 0x0C 8. " HSDIVIDER_CLKOUT1_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT1" "CLK_AUTOGATE,CLK_ENABLE" textline " " bitfld.long 0x0C 5. " HSDIVIDER_CLKOUT1_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1" bitfld.long 0x0C 0.--4. " HSDIVIDER_CLKOUT1_DIV ,DPLL post-divider factor M4 for internal clock generation" "Reserved,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31" line.long 0x10 "CM_DIV_M5_DPLL_CORE,CLKOUT2 o/p of the HSDIVIDER Control Register" bitfld.long 0x10 12. " HSDIVIDER_CLKOUT2_PWDN ,Automatic power down for HSDIVIDER M5 divider and hence CLKOUT2 output when the o/p clock is gated" "ALWAYS_ACTIVE,AUTO_PWDN" bitfld.long 0x10 9. " ST_HSDIVIDER_CLKOUT2 ,HSDIVIDER CLKOUT2 status" "CLK_ENABLED,CLK_GATED" bitfld.long 0x10 8. " HSDIVIDER_CLKOUT2_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT2" "CLK_AUTOGATE,CLK_ENABLE" textline " " bitfld.long 0x10 5. " HSDIVIDER_CLKOUT2_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1" bitfld.long 0x10 0.--4. " HSDIVIDER_CLKOUT2_DIV ,DPLL post-divider factor M5 for internal clock generation" "Reserved,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31" line.long 0x14 "CM_CLKMODE_DPLL_MPU,MPU DPLL Clock Modes Control Register" bitfld.long 0x14 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square" bitfld.long 0x14 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "FULL_SPREAD,LOW_SPREAD" bitfld.long 0x14 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "Disabled,Enabled" textline " " bitfld.long 0x14 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" bitfld.long 0x14 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL" "Disabled,Enabled" bitfld.long 0x14 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode" "Disabled,Enabled" textline " " bitfld.long 0x14 9. " DPLL_RELOCK_RAMP_EN ,Clock ramping relock process enable" "Disabled,Enabled" bitfld.long 0x14 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "Diasbled,Enabled" bitfld.long 0x14 5.--7. " DPLL_RAMP_RATE ,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "REFCLKx2,REFCLKx4,REFCLKx8,REFCLKx16,REFCLKx32,REFCLKx64,REFCLKx128,REFCLKx512" textline " " bitfld.long 0x14 3.--4. " DPLL_RAMP_LEVEL ,Enable and select the algorithm used for clock ramping" "RAMP_DISABLE,RAMP_ALGO1,RAMP_ALGO2,?..." bitfld.long 0x14 0.--2. " DPLL_EN ,DPLL control" "Reserved,Reserved,Reserved,Reserved,DPLL_MN_BYP_MODE,DPLL_LP_BYP_MODE,DPLL_FR_BYP_MODE,DPLL_LOCK_MODE" line.long 0x18 "CM_CLKMODE_DPLL_PER,PER DPLL Clock Modes Control Register" bitfld.long 0x18 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square" bitfld.long 0x18 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "FULL_SPREAD,LOW_SPREAD" bitfld.long 0x18 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "Disabled,Enabled" textline " " bitfld.long 0x18 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" bitfld.long 0x18 0.--2. " DPLL_EN ,DPLL control" "Reserved,DPLL_LP_STP_MODE,Reserved,Reserved,DPLL_MN_BYP_MODE,DPLL_LP_BYP_MODE,Reserved,DPLL_LOCK_MODE" line.long 0x1C "CM_CLKMODE_DPLL_CORE,CORE DPLL Clock Modes Control Register" bitfld.long 0x1C 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square" bitfld.long 0x1C 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "FULL_SPREAD,LOW_SPREAD" bitfld.long 0x1C 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "Disabled,Enabled" textline " " bitfld.long 0x1C 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" bitfld.long 0x1C 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL" "Disabled,Enabled" bitfld.long 0x1C 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode" "Disabled,Enabled" textline " " bitfld.long 0x1C 9. " DPLL_RELOCK_RAMP_EN ,Clock ramping relock process enable" "Disabled,Enabled" bitfld.long 0x1C 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "Diasbled,Enabled" bitfld.long 0x1C 5.--7. " DPLL_RAMP_RATE ,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "REFCLKx2,REFCLKx4,REFCLKx8,REFCLKx16,REFCLKx32,REFCLKx64,REFCLKx128,REFCLKx512" textline " " bitfld.long 0x1C 3.--4. " DPLL_RAMP_LEVEL ,Enable and select the algorithm used for clock ramping" "RAMP_DISABLE,RAMP_ALGO1,RAMP_ALGO2,?..." bitfld.long 0x1C 0.--2. " DPLL_EN ,DPLL control" "Reserved,Reserved,Reserved,Reserved,DPLL_MN_BYP_MODE,DPLL_LP_BYP_MODE,DPLL_FR_BYP_MODE,DPLL_LOCK_MODE" line.long 0x20 "CM_CLKMODE_DPLL_DDR,DRR DPLL Clock Modes Control Register" bitfld.long 0x20 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square" bitfld.long 0x20 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "FULL_SPREAD,LOW_SPREAD" bitfld.long 0x20 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "Disabled,Enabled" textline " " bitfld.long 0x20 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" bitfld.long 0x20 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL" "Disabled,Enabled" bitfld.long 0x20 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode" "Disabled,Enabled" textline " " bitfld.long 0x20 9. " DPLL_RELOCK_RAMP_EN ,Clock ramping relock process enable" "Disabled,Enabled" bitfld.long 0x20 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "Diasbled,Enabled" bitfld.long 0x20 5.--7. " DPLL_RAMP_RATE ,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "REFCLKx2,REFCLKx4,REFCLKx8,REFCLKx16,REFCLKx32,REFCLKx64,REFCLKx128,REFCLKx512" textline " " bitfld.long 0x20 3.--4. " DPLL_RAMP_LEVEL ,Enable and select the algorithm used for clock ramping" "RAMP_DISABLE,RAMP_ALGO1,RAMP_ALGO2,?..." bitfld.long 0x20 0.--2. " DPLL_EN ,DPLL control" "Reserved,Reserved,Reserved,Reserved,DPLL_MN_BYP_MODE,DPLL_LP_BYP_MODE,DPLL_FR_BYP_MODE,DPLL_LOCK_MODE" line.long 0x24 "CM_CLKMODE_DPLL_DISP,DISP DPLL Clock Modes Control Register" bitfld.long 0x24 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "Triangular,Square" bitfld.long 0x24 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "FULL_SPREAD,LOW_SPREAD" bitfld.long 0x24 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "Disabled,Enabled" textline " " bitfld.long 0x24 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "Disabled,Enabled" bitfld.long 0x24 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL" "Disabled,Enabled" bitfld.long 0x24 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode" "Disabled,Enabled" textline " " bitfld.long 0x24 9. " DPLL_RELOCK_RAMP_EN ,Clock ramping relock process enable" "Disabled,Enabled" bitfld.long 0x24 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL" "Diasbled,Enabled" bitfld.long 0x24 5.--7. " DPLL_RAMP_RATE ,Selects the time in terms of DPLL REFCLKs spent at each stage of the clock ramping process" "REFCLKx2,REFCLKx4,REFCLKx8,REFCLKx16,REFCLKx32,REFCLKx64,REFCLKx128,REFCLKx512" textline " " bitfld.long 0x24 3.--4. " DPLL_RAMP_LEVEL ,Enable and select the algorithm used for clock ramping" "RAMP_DISABLE,RAMP_ALGO1,RAMP_ALGO2,?..." bitfld.long 0x24 0.--2. " DPLL_EN ,DPLL control" "Reserved,Reserved,Reserved,Reserved,DPLL_MN_BYP_MODE,DPLL_LP_BYP_MODE,DPLL_FR_BYP_MODE,DPLL_LOCK_MODE" line.long 0x28 "CM_CLKSEL_DPLL_PERIPH,PERIPH DPLL Clock Select Register" hexmask.long.byte 0x28 24.--31. 1. " DPLL_SD_DIV ,Sigma-Delta divider select" hexmask.long.word 0x28 8.--19. 1. " DPLL_MULT ,DPLL multiplier factor" hexmask.long.byte 0x28 0.--7. 1. " DPLL_DIV ,DPLL divider factor" line.long 0x2C "CM_DIV_M2_DPLL_DDR,DDR M2 divider of the DPLL Control Register" bitfld.long 0x2C 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status" "CLK_GATED,CLK_ENABLED" bitfld.long 0x2C 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT" "CLK_AUTOGATE,CLK_ENABLE" bitfld.long 0x2C 5. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "0,1" textline " " bitfld.long 0x2C 0.--4. " DPLL_CLKOUT_DIV ,DPLL M2 post-divider factor (1 to 31)" "Reserved,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31" line.long 0x30 "CM_DIV_M2_DPLL_DISP,DISP M2 divider of the DPLL Control Register" bitfld.long 0x30 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status" "CLK_GATED,CLK_ENABLED" bitfld.long 0x30 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT" "CLK_AUTOGATE,CLK_ENABLE" bitfld.long 0x30 5. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "0,1" textline " " bitfld.long 0x30 0.--4. " DPLL_CLKOUT_DIV ,DPLL M2 post-divider factor (1 to 31)" "Reserved,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31" line.long 0x34 "CM_DIV_M2_DPLL_MPU,MPU M2 divider of the DPLL Control Register" bitfld.long 0x34 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status" "CLK_GATED,CLK_ENABLED" bitfld.long 0x34 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT" "CLK_AUTOGATE,CLK_ENABLE" bitfld.long 0x34 5. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "0,1" textline " " bitfld.long 0x34 0.--4. " DPLL_CLKOUT_DIV ,DPLL M2 post-divider factor (1 to 31)" "Reserved,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31" line.long 0x38 "CM_DIV_M2_DPLL_PER,PER M2 divider of the DPLL Control Register" bitfld.long 0x38 9. " ST_DPLL_CLKOUT ,DPLL CLKOUT status" "CLK_GATED,CLK_ENABLED" bitfld.long 0x38 8. " DPLL_CLKOUT_GATE_CTRL ,Control gating of DPLL CLKOUT" "CLK_AUTOGATE,CLK_ENABLE" bitfld.long 0x38 7. " DPLL_CLKOUT_DIVCHACK ,Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect" "0,1" textline " " hexmask.long.byte 0x38 0.--6. 1. " DPLL_CLKOUT_DIV ,DPLL M2 post-divider factor" rgroup.long 0x4B0++0x03 line.long 0x00 "CM_WKUP_WKUP_M3_CLKCTRL,WKUP M3 clocks" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "0,1,2,3" group.long 0x4B4++0x17 line.long 0x00 "CM_WKUP_UART0_CLKCTRL,UART0 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x04 "CM_WKUP_I2C0_CLKCTRL,I2C0 Clocks Control Register" bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x04 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x08 "CM_WKUP_ADC_TSC_CLKCTRL,ADC Clocks Control Register" bitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x08 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x0C "CM_WKUP_SMARTREFLEX0_CLKCTRL,SmartReflex0 Clocks Control Register" bitfld.long 0x0C 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x0C 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x10 "CM_WKUP_TIMER1_CLKCTRL,TIMER1 Clocks Control Register" bitfld.long 0x10 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x10 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x14 "CM_WKUP_SMARTREFLEX1_CLKCTRL,SmartReflex1 Clocks Control Register" bitfld.long 0x14 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x14 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." rgroup.long 0x4CC++0x03 line.long 0x00 "CM_L4_WKUP_AON_CLKSTCTRL,L4 WKUP Clock State Control Register" bitfld.long 0x00 2. " CLKACTIVITY_L4_WKUP_AON_GCLK ,State of the L4_WKUP clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the always on L4 clock domain" "0,1,2,3" group.long 0x4D4++0x07 line.long 0x00 "CM_WKUP_WDT1_CLKCTRL,WDT1 Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x04 "CM_DIV_M6_DPLL_CORE,CLKOUT3 o/p of the HSDIVIDER Control Register" bitfld.long 0x04 12. " HSDIVIDER_CLKOUT3_PWDN ,Automatic power down for HSDIVIDER M6 divider and hence CLKOUT3 output when the o/p clock is gated" "ALWAYS_ACTIVE,AUTO_PWDN" bitfld.long 0x04 9. " ST_HSDIVIDER_CLKOUT3 ,HSDIVIDER CLKOUT3 status" "CLK_ENABLED,CLK_GATED" bitfld.long 0x04 8. " HSDIVIDER_CLKOUT3_GATE_CTRL ,Control gating of HSDIVIDER CLKOUT3" "CLK_AUTOGATE,CLK_ENABLE" textline " " bitfld.long 0x04 5. " HSDIVIDER_CLKOUT3_DIVCHACK ,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1" bitfld.long 0x04 0.--4. " HSDIVIDER_CLKOUT3_DIV ,DPLL post-divider factor M6 for internal clock generation" "Reserved,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31" width 11. tree.end base ad:0x44E00000 tree "CM_DPLL" width 23. group.long 0x504++0x03 line.long 0x00 "CLKSEL_TIMER7_CLK,Mux Select Line for TIMER7 Clock Register" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER7 clock" "TCLKIN clock,CLK_M_OSC clock,CLK_32KHZ clock,?..." group.long 0x508++0x03 line.long 0x00 "CLKSEL_TIMER2_CLK,Mux Select Line TIMER2 Clock Register" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER2 clock" "TCLKIN clock,CLK_M_OSC clock,CLK_32KHZ clock,?..." group.long 0x50C++0x03 line.long 0x00 "CLKSEL_TIMER3_CLK,Mux Select Line TIMER3 Clock Register" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER3 clock" "TCLKIN clock,CLK_M_OSC clock,CLK_32KHZ clock,?..." group.long 0x510++0x03 line.long 0x00 "CLKSEL_TIMER4_CLK,Mux Select Line TIMER4 Clock Register" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER4 clock" "TCLKIN clock,CLK_M_OSC clock,CLK_32KHZ clock,?..." group.long 0x514++0x03 line.long 0x00 "CM_MAC_CLKSEL,Clock Divide Ration for MII Clock Register" bitfld.long 0x00 2. " MII_CLK_SEL ,MII Clock Divider Selection" "1/2,1/5" group.long 0x518++0x03 line.long 0x00 "CLKSEL_TIMER5_CLK,Mux Select Line TIMER5 Clock Register" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER5 clock" "TCLKIN clock,CLK_M_OSC clock,CLK_32KHZ clock,?..." group.long 0x51C++0x03 line.long 0x00 "CLKSEL_TIMER6_CLK,Mux Select Line TIMER6 Clock Register" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for TIMER6 clock" "TCLKIN clock,CLK_M_OSC clock,CLK_32KHZ clock,?..." group.long 0x520++0x03 line.long 0x00 "CM_CPTS_RFT_CLKSEL,Mux Select Line for CPTS RFT Clock Register" bitfld.long 0x00 0. " CLKSEL ,Selects the Mux select line for cpgmac rft clock" "SYSCLK20,SYSCLK21" group.long 0x528++0x03 line.long 0x00 "CLKSEL_TIMER1MS_CLK,Mux Select Line TIMER1 Clock Register" bitfld.long 0x00 0.--2. " CLKSEL ,Selects the Mux select line for DMTIMER_1MS clock" "CLK_M_OSC clock,CLK_32KHZ clock,TCLKIN clock,CLK_RC32K clock,CLK_32768 clock,?..." group.long 0x52C++0x03 line.long 0x00 "CLKSEL_GFX_FCLK,Divider Value for GFX Clock Register" bitfld.long 0x00 1. " CLKSEL_GFX_FCLK ,Selects the clock on gfx fclk" "CORE PLL,PER PLL" textline " " bitfld.long 0x00 0. " CLKDIV_SEL_GFX_FCLK ,Selects the divider value on gfx fclk" "L3 Clock or 192MHz,L3 Clock/2 or 192Mhz/2" group.long 0x534++0x03 line.long 0x00 "CLKSEL_LCDC_PIXEL_CLK,Mux Select Line for LCDC PIXEL Clock Register" bitfld.long 0x00 0.--1. " CLKSEL ,Controls the Mux Select of LCDC PIXEL clock" "DISP PLL CLKOUTM2,CORE PLL CLKOUTM5,PER PLL CLKOUTM2,?..." group.long 0x538++0x03 line.long 0x00 "CLKSEL_WDT1_CLK,Mux Select Line Watchdog1 Clock Register" bitfld.long 0x00 0. " CLKSEL ,Selects the Mux select line for WDT1 clock" "RC Oscillator,32K Clock divider" group.long 0x53C++0x03 line.long 0x00 "CLKSEL_GPIO0_DBCLK,Selects the Mux Select Line for GPIO0 debounce Clock Register" bitfld.long 0x00 0.--1. " CLKSEL ,Selects the Mux select line for GPIO0 debounce clock" "RC Oscillator,32K Crystal Oscillator,Clock Divider,?..." tree.end tree "CM_MPU" width 20. group.long 0x600++0x07 line.long 0x00 "CM_MPU_CLKSTCTRL,MPU Clock State Control Register" bitfld.long 0x00 2. " CLKACTIVITY_MPU_CLK ,This field indicates the state of the MPU Clock" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the MPU clock domains" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" line.long 0x04 "CM_MPU_MPU_CLKCTRL,MPU Clocks Control Register" bitfld.long 0x04 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x04 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." tree.end tree "CM_DEVICE" width 16. group.long 0x700++0x03 line.long 0x00 "CM_CLKOUT_CTRL,CLKOUT1 and CLKOUT2 Output Control Register" bitfld.long 0x00 7. " CLKOUT2EN ,External clock activity" "Disabled,Enabled" bitfld.long 0x00 3.--5. " CLKOUT2DIV ,External clock divison factor" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 0.--2. " CLKOUT2SOURCE ,External output clock source" "32KHz Oscillator O/P,L3 Clock,DDR PHY Clock,PER PLL 192Mhz Clock,LCD Pixel Clock,?..." tree.end tree "CM_RTC" width 20. group.long 0x800++0x07 line.long 0x00 "CM_RTC_RTC_CLKCTRL,RTC Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x04 "CM_RTC_CLKSTCTRL,RTC Clock State Control Register" bitfld.long 0x04 9. " CLKACTIVITY_RTC_32KCLK ,32K RTC clock in the domain state" "Gated,Active" bitfld.long 0x04 8. " CLKACTIVITY_L4_RTC_GCLK ,4 RTC clock in the domain state" "Gated,Active" bitfld.long 0x04 0.--1. " CLKTRCTRL ,Controls the clock state transition of the RTC clock domains" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" tree.end tree "CM_GFX" width 27. group.long 0x900++0x7 line.long 0x00 "CM_GFX_L3_CLKSTCTRL,GFX L3 Clock State Control Register" bitfld.long 0x00 9. " CLKACTIVITY_GFX_FCLK ,GFX_GCLK clock in the domain state" "Gated,Active" bitfld.long 0x00 8. " CLKACTIVITY_GFX_L3_GCLK ,GFX_L3_GCLK clock in the domain state" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the GFX clock domain in GFX power domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" line.long 0x04 "CM_GFX_GFX_CLKCTRL,GFX Clocks Control Register" bitfld.long 0x04 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x04 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." sif (!cpuis("AM335*")) group.long 0x908++0x3 line.long 0x00 "CM_GFX_BITBLT_CLKCTRL,BITBLIT Clocks Control Register" bitfld.long 0x00 18. " STBYST ,Module standby status" "Func,Standby" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." endif group.long 0x90C++0xb line.long 0x00 "CM_GFX_L4LS_GFX_CLKSTCTRL,GFX L4LS Clock State Control Register" bitfld.long 0x00 8. " CLKACTIVITY_L4LS_GFX_GCLK ,This field indicates the state of the L4_LS clock in the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4LS clock domain in GFX power domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" line.long 0x04 "CM_GFX_MMUCFG_CLKCTRL,MMU CFG Clocks Control Register" bitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x04 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." line.long 0x08 "CM_GFX_MMUDATA_CLKCTRL,MMU Clocks Control Register" bitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x08 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." tree.end tree "CM_CEFUSE" width 26. group.long 0xA00++0x03 line.long 0x00 "CM_CEFUSE_CLKSTCTRL,CEFUSE Clock State Control Register" bitfld.long 0x00 9. " CLKACTIVITY_CUST_EFUSE_SYS_CLK ,This field indicates the state of the Cust_Efuse_SYSCLK clock input of the domain" "Gated,Active" bitfld.long 0x00 8. " CLKACTIVITY_L4_CEFUSE_GICLK ,This field indicates the state of the L4_CEFUSE_GCLK clock input of the domain" "Gated,Active" bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the clock domain in customer efuse power domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO" group.long 0xA20++0x03 line.long 0x00 "CM_CEFUSE_CEFUSE_CLKCTRL,CEFUSE Clocks Control Register" bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Func,Trans,Idle,Disabled" bitfld.long 0x00 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed" "Disabled,Reserved,Enabled,?..." tree.end width 11. tree.end tree "PM (Power Management Registers)" base ad:0x44E00000 tree "PRM_PER" width 18. sif (cpuis("AM335*")) group.long 0x0C00++0x03 line.long 0x00 "RM_PER_RSTCTRL,PER Resets Control Register" bitfld.long 0x00 1. " PRUSS_LRST ,PER domain PRUSS local reset control" "Cleared,Asserted" textline " " else group.long 0x0C00++0x07 line.long 0x00 "RM_PER_RSTCTRL,PER Resets Control Register" bitfld.long 0x00 0. " PCI_LRST ,PER domain PCIE local reset control" "Cleared,Asserted" line.long 0x04 "RM_PER_RSTST,PER Resets Status Register" bitfld.long 0x04 5. " PCI_LRST ,PCIE has been reset upon SW reset" "No reset,Reset" endif rgroup.long 0x0C08++0x03 line.long 0x00 "PM_PER_PWRSTST,PER Power Domain State Register" sif (cpu()=="AM3359"||cpu()=="AM3358"||cpu()=="AM3357"||cpu()=="AM3356") bitfld.long 0x00 23.--24. " PRUSS_MEM_STATEST ,PRUSS memory state status" "Mem_off,Reserved,Reserved,Mem_on" textline " " endif bitfld.long 0x00 21.--22. " RAM_MEM_STATEST ,OCMC RAM memory state status" "Mem_off,Reserved,Reserved,Mem_on" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No,Ongoing" textline " " bitfld.long 0x00 17.--18. " PER_MEM_STATEST ,PER domain memory state status" "Mem_off,Reserved,Reserved,Mem_on" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,RET,Reserved,ON" group.long 0x0C0C++0x03 line.long 0x00 "PM_PER_PWRSTCTRL,PER Power Domain Control Register" bitfld.long 0x00 30.--31. " RAM_MEM_ONSTATE ,OCMC RAM memory on state" "OFF,RET,Reserved,ON" bitfld.long 0x00 29. " PER_MEM_RETSTATE ,Other memories in PER Domain RET state" "OFF,RET" bitfld.long 0x00 27. " RAM_MEM_RETSTATE ,OCMC RAM memory RET state" "OFF,RET" textline " " bitfld.long 0x00 25.--26. " PER_MEM_ONSTATE ,Other memories in PER Domain ON state" "Reserved,Reserved,Reserved,ON" sif (cpu()=="AM3359"||cpu()=="AM3358"||cpu()=="AM3357"||cpu()=="AM3356") textline " " bitfld.long 0x00 7. " PRUSS_MEM_RETSTATE ,PRUSS memory RET state" "OFF,RET" bitfld.long 0x00 5.--6. " PRUSS_MEM_ONSTATE ,PRUSS memory ON state" "Reserved,Reserved,Reserved,ON" endif textline " " bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Disabled,Enabled" bitfld.long 0x00 3. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "logic_off,logic_ret" bitfld.long 0x00 0.--1. " POWERSTATE ,PER domain power state control" "OFF,RET,Reserved,ON" tree.end tree "PRM_WKUP" width 19. group.long 0x0D00++0x07 line.long 0x00 "RM_WKUP_RSTCTRL,ALWAYS ON Domain Resets Control Register" bitfld.long 0x00 3. " WKUP_M3_LRST ,Assert Reset to WKUP_M3" "Cleared,Asserted" line.long 0x04 "PM_WKUP_PWRSTCTRL,WKUP Power Domain Control Register" bitfld.long 0x04 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Disabled,Enabled" bitfld.long 0x04 3. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "logic_off,logic_ret" rgroup.long 0x0D08++0x03 line.long 0x00 "PM_WKUP_PWRSTST,WKUP Power Domain State Register" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No,Ongoing" bitfld.long 0x00 17.--18. " DEBUGSS_MEM_STATEST ,WKUP domain memory state status" "Mem_off,1,Reserved,Mem_on" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON" group.long 0x0D0C++0x03 line.long 0x00 "RM_WKUP_RSTST,WKUP Resets Status Register" bitfld.long 0x00 7. " ICECRUSHER_M3_RST ,M3 Processor has been reset due to M3 ICECRUSHER1 reset event" "No reset,Reset" bitfld.long 0x00 6. " EMULATION_M3_RST ,M3 Processor has been reset due to emulation reset source" "No reset,Reset" bitfld.long 0x00 5. " WKUP_M3_LRST ,M3 Processor has been reset" "No reset,Reset" tree.end tree "PRM_MPU" width 18. group.long 0x0E00++0x03 line.long 0x00 "PM_MPU_PWRSTCTRL,MPU Power Domain Control Register" bitfld.long 0x00 24. " MPU_RAM_RETSTATE ,Default power domain memory(ram) retention state when power domain is in retention" "0,1" bitfld.long 0x00 23. " MPU_L2_RETSTATE ,Default power domain memory(L2) retention state when power domain is in retention" "0,1" bitfld.long 0x00 22. " MPU_L1_RETSTATE ,Default power domain memory(L1) retention state when power domain is in retention" "0,1" textline " " bitfld.long 0x00 20.--21. " MPU_L2_ONSTATE ,Default power domain memory state when domain is ON" "Reserved,Reserved,Reserved,Mem_on" bitfld.long 0x00 18.--19. " MPU_L1_ONState ,Default power domain memory state when domain is ON" "Reserved,Reserved,Reserved,Mem_on" bitfld.long 0x00 16.--17. " MPU_RAM_ONSTATE ,Default power domain memory state when domain is ON" "Mem_off,Reserved,Reserved,Mem_on" textline " " bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Disabled,Enabled" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "logic_off,logic_ret" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,RET,Reserved,ON" rgroup.long 0x0E04++0x03 line.long 0x00 "PM_MPU_PWRSTST,MPU Power Domain State Register" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No,Ongoing" bitfld.long 0x00 8.--9. " MPU_L2_StateSt ,MPU L2 memory state status" "Mem_off,Reserved,Reserved,Mem_on" bitfld.long 0x00 6.--7. " MPU_L1_StateSt ,MPU L1 memory state status" "Mem_off,Reserved,Reserved,Mem_on" textline " " bitfld.long 0x00 4.--5. " MPU_RAM_StateSt ,MPU_RAM memory state status" "Mem_off,Reserved,Reserved,Mem_on" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON" bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,RET,Reserved,ON" group.long 0x0E08++0x03 line.long 0x00 "RM_MPU_RSTST,MPU Resets Status Register" bitfld.long 0x00 6. " ICECRUSHER_MPU_RST ,MPU Processor has been reset due to MPU ICECRUSHER1 reset event" "No reset,Reset" bitfld.long 0x00 5. " EMULATION_MPU_RST ,MPU Processor has been reset due to emulation reset source" "No reset,Reset" tree.end tree "PRM_DEVICE" width 25. group.long 0x0F00++0x03 line.long 0x00 "PRM_RSTCTRL,Global Software Cold and Warm Reset Control Register" bitfld.long 0x00 1. " RST_GLOBAL_COLD_SW ,Global COLD software reset control" "No reset,Reset" bitfld.long 0x00 0. " RST_GLOBAL_WARM_SW ,Global WARM software reset control" "No reset,Reset" group.long 0x0F04++0x03 line.long 0x00 "PRM_RSTTIME,Reset Duration Control Register" bitfld.long 0x00 8.--12. " RSTTIME2 ,Power domain reset duration 2 (cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--7. 1. " RSTTIME1 ,Global reset duration 1" group.long 0x0F08++0x03 line.long 0x00 "PRM_RSTST,Global Reset Sources Status Register" bitfld.long 0x00 9. " ICEPICK_RST ,IcePick reset event" "No reset,Reset" bitfld.long 0x00 5. " EXTERNAL_WARM_RST ,External warm reset event" "No reset,Reset" bitfld.long 0x00 4. " WDT1_RST ,Watchdog1 timer reset event" "No reset,Reset" textline " " sif (!cpuis("AM335*")) bitfld.long 0x00 3. " WDT0_RST ,Watchdog0 timer reset event" "No reset,Reset" textline " " endif bitfld.long 0x00 2. " MPU_SECURITY_VIOL_RST ,Security violation reset event triggered by Security State Machine inside MPUSS" "No reset,Reset" bitfld.long 0x00 1. " GLOBAL_WARM_SW_RST ,Global warm software reset event" "No reset,Reset" textline " " bitfld.long 0x00 0. " GLOBAL_COLD_RST ,Power-on (cold) reset event" "No reset,Reset" group.long 0x0F0C++0x03 line.long 0x00 "PRM_SRAM_COUNT,SRAM LDO Transition Counters Setup Register" hexmask.long.byte 0x00 24.--31. 1. " STARTUP_COUNT ,Determines the start-up duration of SRAM and ABB LDO" hexmask.long.byte 0x00 16.--23. 1. " SLPCNT_VALUE ,Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high" hexmask.long.byte 0x00 8.--15. 1. " VSETUPCNT_VALUE ,SRAM LDO rampup time from retention to active mode" textline " " hexmask.long.byte 0x00 0.--5. 1. " PCHARGECNT_VALUE ,Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good" group.long 0x0F10++0x03 line.long 0x00 "PRM_LDO_SRAM_CORE_SETUP,SRAM LDO for CORE Voltage Domain Setup Register" bitfld.long 0x00 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO" "No_Override,Override" bitfld.long 0x00 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO" "One_step,Two_step" bitfld.long 0x00 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO" "Ext_clock,No_ext_clock" textline " " bitfld.long 0x00 5. " ENFUNC3_EXPORT ,ENFUNC3 input of SRAM LDO" "Sub_regul_disabled,Sub_regul_enabled" bitfld.long 0x00 4. " ENFUNC2_EXPORT ,ENFUNC2 input of SRAM LDO" "Ext_cap,No_ext_cap" bitfld.long 0x00 3. " ENFUNC1_EXPORT ,ENFUNC1 input of SRAM LDO" "Short_prot_disabled,Short_prot_enabled" textline " " bitfld.long 0x00 2. " ABBOFF_SLEEP_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "SRAMNW_SLP_VDDS,SRAMNW_SLP_VDDAR" bitfld.long 0x00 1. " ABBOFF_ACT_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "SRAMNW_ACT_VDDS,SRAMNW_ACT_VDDAR" bitfld.long 0x00 0. " DISABLE_RTA_EXPORT ,Control for HD memory RTA feature" "RTA_ENABLED,RTA_DISABLED" group.long 0x0F14++0x03 line.long 0x00 "PRM_LDO_SRAM_CORE_CTRL,SRAM LDO for CORE Voltage Domain Control and Status Register" bitfld.long 0x00 8. " SRAMLDO_STATUS ,SRAMLDO status" "ACTIVE,RETENTION" bitfld.long 0x00 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state" "IDLE,IN_TRANSITION" bitfld.long 0x00 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not" "Disabled,Enabled" group.long 0x0F18++0x03 line.long 0x00 "PRM_LDO_SRAM_MPU_SETUP,SRAM LDO for MPU Voltage Domain Setup Register" bitfld.long 0x00 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO" "No_Override,Override" bitfld.long 0x00 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO" "One_step,Two_step" bitfld.long 0x00 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO" "Ext_clock,No_ext_clock" textline " " bitfld.long 0x00 5. " ENFUNC3_EXPORT ,ENFUNC3 input of SRAM LDO" "Sub_regul_disabled,Sub_regul_enabled" bitfld.long 0x00 4. " ENFUNC2_EXPORT ,ENFUNC2 input of SRAM LDO" "Ext_cap,No_ext_cap" bitfld.long 0x00 3. " ENFUNC1_EXPORT ,ENFUNC1 input of SRAM LDO" "Short_prot_disabled,Short_prot_enabled" textline " " bitfld.long 0x00 2. " ABBOFF_SLEEP_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep" "SRAMNW_SLP_VDDS,SRAMNW_SLP_VDDAR" bitfld.long 0x00 1. " ABBOFF_ACT_EXPORT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode" "SRAMNW_ACT_VDDS,SRAMNW_ACT_VDDAR" bitfld.long 0x00 0. " DISABLE_RTA_EXPORT ,Control for HD memory RTA feature" "RTA_ENABLED,RTA_DISABLED" group.long 0x0F1C++0x03 line.long 0x00 "PRM_LDO_SRAM_MPU_CTRL,SRAM LDO for MPU Voltage Domain Control and Status Register" bitfld.long 0x00 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state" "IDLE,IN_TRANSITION" bitfld.long 0x00 8. " SRAMLDO_STATUS ,SRAMLDO status" "ACTIVE,RETENTION" bitfld.long 0x00 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not" "Disabled,Enabled" tree.end tree "PRM_RTC" width 18. group.long 0x1000++0x03 line.long 0x00 "PM_RTC_PWRSTCTRL,RTC Power State Control Register" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Disabled,Enabled" bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "logic_off,logic_ret" rgroup.long 0x1004++0x03 line.long 0x00 "PM_RTC_PWRSTST,RTC Power Domain State Register" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No,Ongoing" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON" tree.end tree "PRM_GFX" width 18. group.long 0x1100++0x07 line.long 0x00 "PM_GFX_PWRSTCTRL,GFX Power State Control Register" bitfld.long 0x00 17.--18. " GFX_MEM_ONSTATE ,GFX memory state when domain is ON" "Reserved,Reserved,Reserved,Mem_on" bitfld.long 0x00 6. " GFX_MEM_RETSTATE ,Memory retention state" "OFF,RET" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "logic_off,logic_ret" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,RET,Reserved,ON" line.long 0x04 "RM_GFX_RSTCTRL,GFX Domain Resets Control Register" bitfld.long 0x04 0. " GFX_RST ,GFX domain local reset control" "Cleared,Asserted" rgroup.long 0x1110++0x03 line.long 0x00 "PM_GFX_PWRSTST,GFX Power Domain State Register" bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No,Ongoing" bitfld.long 0x00 4.--5. " GFX_MEM_STATEST ,GFX memory state status" "Mem_off,1,Reserved,Mem_on" bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON" textline " " bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,RET,Reserved,ON" group.long 0x1114++0x03 line.long 0x00 "RM_GFX_RSTST,GFX Reset Sources Status Register" bitfld.long 0x00 0. " GFX_RST ,GFX Domain Logic Reset" "No reset,Reset" tree.end tree "PRM_CEFUSE" width 21. group.long 0x1200++0x07 line.long 0x00 "PM_CEFUSE_PWRSTCTRL,CEFUSE Power State Control Register" bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition" "Disabled,Enabled" bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,INACT,ON" line.long 0x04 "PM_CEFUSE_PWRSTST,CEFUSE Power State Status Register" bitfld.long 0x04 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered" "OFF,ON,?..." bitfld.long 0x04 20. " INTRANSITION ,Domain transition status" "No,Ongoing" textline " " bitfld.long 0x04 2. " LOGICSTATEST ,Logic state status" "OFF,ON" bitfld.long 0x04 0.--1. " POWERSTATEST ,Current power state status" "OFF,RET,INACTIVE,ON" tree.end tree.end tree.end tree "Control Module" base ad:0x44E10000 width 31. rgroup.long 0x000++0x03 line.long 0x00 "CONTROL_REVISION,Control Revision Register" bitfld.long 0x00 30.--31. " IP_REV_SCHEME ,Scheme" "0,New,2,3" hexmask.long.word 0x00 16.--27. 1. " IP_REV_FUNC ,Function indicates a software compatible module family" bitfld.long 0x00 11.--15. " IP_REV_RTL ,RTL Version (R) maintained by IP design owner." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " IP_REV_MAJOR ,Major Revision (X) maintained by IP specification owner" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " IP_REV_CUSTOM ,Indicates a special version for a particular device" "Standard,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " IP_REV_MINOR ,Minor Revision (Y) maintained by IP specification owner" rgroup.long 0x600++0x03 line.long 0x00 "DEVICE_ID,Device ID Register" bitfld.long 0x00 28.--31. " DEVREV ,Device revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 12.--27. 1. " PARTNUM ,Device part number (unique JTAG ID)" hexmask.long.word 0x00 1.--11. 1. " MFGR ,Manufacturer JTAG ID" rgroup.long 0x004++0x03 line.long 0x00 "CONTROL_HWINFO,Control HW Info Register" hexmask.long 0x00 0.--31. 1. " IP_HWINFO ,IP Module dependent" group.long 0x010++0x03 line.long 0x00 "CONTROL_SYSCONFIG,Control System Configure Register" bitfld.long 0x00 4.--5. " STANDBY ,Configure local initiator state management" "Force Standby,No Standby,Smart Standby,Smart Standby wakeup capable" bitfld.long 0x00 2.--3. " IDLEMODE ,Configure local target state management" "Forced,No idle,Smart,Smart wakeup capable" rbitfld.long 0x00 1. " FREEEMU ,Sensitivity to Emulation suspend input" "Sensitive,Not sensitive" group.long 0x040++0x03 line.long 0x00 "CONTROL_STATUS,Control Status Register" bitfld.long 0x00 22.--23. " SYSBOOT1 ,Used to select crystal clock frequency" "19.2 MHz,24 MHz,25 MHz,26 MHz" bitfld.long 0x00 20.--21. " TESTMD ,Set to 00b" "0,1,2,3" bitfld.long 0x00 18.--19. " ADMUX ,GPMC CS0 Default Address Muxing" "No Addr/Data Muxing,Addr/Addr/Data Muxing,Addr/Data Muxing,?..." textline " " bitfld.long 0x00 17. " WAITEN ,GPMC CS0 Default Wait Enable" "Disabled,Enabled" bitfld.long 0x00 16. " BW ,GPMC CS0 Default Bus Width" "8-bit,16-bit" rbitfld.long 0x00 8.--10. " DEVTYPE ,Device type select" "Test Device,Emulation Device (EMU),High Security Device (HS),General Purpose Device (GP),?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SYSBOOT0 ,Selected boot mode" if (((data.long(ad:0x44E10000+0x110))&0xe0000000)==0x20000000) group.long 0x110++0x03 line.long 0x00 "SECURE_EMIF_SDRAM_CONFIG,Secure EMIF SDRAM Configuration Register" bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type selection" "Reserved,LPDDR1,DDR2,DDR3 (AA only),?..." bitfld.long 0x00 27.--28. " IBANK_POS ,Internal bank position" "All addr column,Addr[1:0] column/Addr[2] row,Addr[0] column/Addr[2:1] row,All addr row" bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM drive strength" "Normal,Weak,?..." textline " " bitfld.long 0x00 14.--15. " NARROW_MODE ,SDRAM data bus width" "64-bit,32-bit,16-bit,?..." bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,Reserved,1.5,2.5,?..." bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" textline " " bitfld.long 0x00 4.--6. " IBANK ,Internal Bank setup" "1 bank,2 banks,4 banks,8 banks,?..." bitfld.long 0x00 3. " EBANK ,External chip select setup" "pad_cs_o_n[0],pad_cs_o_n[1:0]" bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size" "256-word,512-word,1024-word,2048-word,?..." elif (((data.long(ad:0x44E10000+0x110))&0xe0000000)==0x40000000) group.long 0x110++0x03 line.long 0x00 "SECURE_EMIF_SDRAM_CONFIG,Secure EMIF SDRAM Configuration Register" bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type selection" "Reserved,LPDDR1,DDR2,DDR3 (AA only),?..." bitfld.long 0x00 27.--28. " IBANK_POS ,Internal bank position" "All addr column,Addr[1:0] column/Addr[2] row,Addr[0] column/Addr[2:1] row,All addr row" bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 and DDR3 termination resistor value" "Disabled,75 ohm,150 ohm,50 ohm,?..." textline " " bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM drive strength" "Normal,Weak,?..." textline " " bitfld.long 0x00 14.--15. " NARROW_MODE ,SDRAM data bus width" "64-bit,32-bit,16-bit,?..." bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,4,5,?..." bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" textline " " bitfld.long 0x00 4.--6. " IBANK ,Internal Bank setup" "1 bank,2 banks,4 banks,8 banks,?..." bitfld.long 0x00 3. " EBANK ,External chip select setup" "pad_cs_o_n[0],pad_cs_o_n[1:0]" bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size" "256-word,512-word,1024-word,2048-word,?..." elif (((data.long(ad:0x44E10000+0x110))&0xe0000000)==0x60000000) group.long 0x110++0x03 line.long 0x00 "SECURE_EMIF_SDRAM_CONFIG,Secure EMIF SDRAM Configuration Register" bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type selection" "Reserved,LPDDR1,DDR2,DDR3 (AA only),?..." bitfld.long 0x00 27.--28. " IBANK_POS ,Internal bank position" "All addr column,Addr[1:0] column/Addr[2] row,Addr[0] column/Addr[2:1] row,All addr row" bitfld.long 0x00 24.--26. " DDR_TERM ,DDR2 and DDR3 termination resistor value" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,?..." textline " " bitfld.long 0x00 21.--22. " DYN_ODT ,DDR3 Dynamic ODT" "Disabled,RZQ/4,RZQ/2,?..." bitfld.long 0x00 18.--19. " SDRAM_DRIVE ,SDRAM drive strength" "RZQ/6,RZQ/7,?..." bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write latency" "5,6,7,8" textline " " bitfld.long 0x00 14.--15. " NARROW_MODE ,SDRAM data bus width" "64-bit,32-bit,16-bit,?..." bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,5,Reserved,6,Reserved,7,Reserved,8,Reserved,9,Reserved,10,Reserved,11,?..." bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" textline " " bitfld.long 0x00 4.--6. " IBANK ,Internal Bank setup" "1 bank,2 banks,4 banks,8 banks,?..." bitfld.long 0x00 3. " EBANK ,External chip select setup" "pad_cs_o_n[0],pad_cs_o_n[1:0]" bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size" "256-word,512-word,1024-word,2048-word,?..." else group.long 0x110++0x03 line.long 0x00 "SECURE_EMIF_SDRAM_CONFIG,Secure EMIF SDRAM Configuration Register" bitfld.long 0x00 29.--31. " SDRAM_TYPE ,SDRAM Type selection" "Reserved,LPDDR1,DDR2,DDR3 (AA only),?..." bitfld.long 0x00 27.--28. " IBANK_POS ,Internal bank position" "All addr column,Addr[1:0] column/Addr[2] row,Addr[0] column/Addr[2:1] row,All addr row" bitfld.long 0x00 14.--15. " NARROW_MODE ,SDRAM data bus width" "64-bit,32-bit,16-bit,?..." textline " " bitfld.long 0x00 7.--9. " ROWSIZE ,Row Size" "9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits" bitfld.long 0x00 4.--6. " IBANK ,Internal Bank setup" "1 bank,2 banks,4 banks,8 banks,?..." bitfld.long 0x00 3. " EBANK ,External chip select setup" "pad_cs_o_n[0],pad_cs_o_n[1:0]" textline " " bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size" "256-word,512-word,1024-word,2048-word,?..." endif group.long 0x428++0x07 line.long 0x00 "CORE_SLDO_CTRL,CORE SLDO Control Register" hexmask.long.word 0x00 16.--25. 1. " VSET ,Trims VDDAR" line.long 0x04 "MPU_SLDO_CTRL,MPU SLDO Control Register" hexmask.long.word 0x04 16.--25. 1. " VSET ,Trims VDDAR" group.long 0x444++0x03 line.long 0x00 "CLK32KDIVRATIO_CTRL,Clock 32kHz Divider Ratio Control Register" bitfld.long 0x00 0. " CLKDIVOPP50_EN ,Operation Divider mode select" "OPP100,OPP50" group.long 0x448++0x07 line.long 0x00 "BANDGAP_CTRL,BANDGAP Control Register" hexmask.long.byte 0x00 8.--15. 1. " DTEMP ,Temperature data from ADC" bitfld.long 0x00 7. " CBIASSEL ,Reference select" "Bandgap voltage,Resistor divider" bitfld.long 0x00 6. " BGROFF ,Bandgap mode" "On,Off" textline " " bitfld.long 0x00 5. " TMPSOFF ,Temperature sensor and thermal shutdown mode" "On,Off" bitfld.long 0x00 4. " SOC ,ADC start of conversion" "Stopped,Started" bitfld.long 0x00 3. " CLRZ ,0: Resets the digital outputs" "No reset,Reset" textline " " bitfld.long 0x00 2. " CONTCONV ,ADC conversion mode" "Single,Continuous" rbitfld.long 0x00 1. " ECOZ ,ADC end of conversion" "Occurred,Not occurred" rbitfld.long 0x00 0. " TSHUT ,Thermal shutdown event" "Not occurred,Occurred" line.long 0x04 "BANDGAP_TRIM,BANDGAP Trim Register" hexmask.long.byte 0x04 24.--31. 1. " DTRBGAPC ,Trim the output voltage of bandgap" hexmask.long.byte 0x04 16.--23. 1. " DTRBGAPV ,Trim the output voltage of bandgap" hexmask.long.byte 0x04 8.--15. 1. " DTRTEMPS ,Trim the temperature sensor" textline " " hexmask.long.byte 0x04 0.--7. 1. " DTRTEMPSC ,Trim the temperature sensor" group.long 0x458++0x03 line.long 0x00 "PLL_CLKINPULOW_CTRL,PLL CLKINPULOW Control Register" bitfld.long 0x00 2. " DDR_PLL_CLKINPULOW_SEL ,DDR CLKINPULOW clock select" "CORE_CLKOUT_M6,PER_CLKOUT_M2" bitfld.long 0x00 1. " DISP_PLL_CLKINPULOW_SEL ,DISP CLKINPULOW clock select" "CORE_CLKOUT_M6,PER_CLKOUT_M2" bitfld.long 0x00 0. " MPU_DPLL_CLKINPULOW_SEL ,MPU CLKINPULOW clock select" "CORE_CLKOUT_M6,PER_CLKOUT_M2" group.long 0x468++0x0B line.long 0x00 "MOSC_CTRL,MOSC Control Register" bitfld.long 0x00 0. " RESSELECT ,Internal resistor connection between padxi and padxo for oscillator bias status" "Connected,Disconnected" line.long 0x04 "RCOSC_CTRL,RCOSC Control Register" bitfld.long 0x04 0. " STOPOSC ,Oscillator disable" "No,Yes" line.long 0x08 "DEEPSLEEP_CTRL,Deep Sleep Control Register" bitfld.long 0x08 17. " DSENABLE ,Deep sleep enable" "Disabled,Enabled" hexmask.long.word 0x08 0.--15. 1. " DSCOUNT ,Programmable count of how many OSC clocks needs to be seen before exiting deep sleep mode" rgroup.long 0x604++0x03 line.long 0x00 "DEV_FEATURE,Device Feature Register" bitfld.long 0x00 29. " SGX ,SGX enable" "Enabled,Disabled" textline " " bitfld.long 0x00 17. " ICSS_FEA1 ,TX_AUTO_SEQUENCE enable" "Enabled,Disabled" bitfld.long 0x00 16. " ICSS_FEA0 ,EtherCAT functionality and ODD_NIBBLE enable" "Enabled,Disabled" textline " " bitfld.long 0x00 7. " DCAN ,DCAN0 DCAN1 IPs enable" "Disabled,Enabled" bitfld.long 0x00 1. " CPSW ,CP Switch IP (Ethernet) enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PRU_ICSS ,PRU-ICS enable" "Disabled,Enabled" group.long 0x608++0x03 line.long 0x00 "INIT_PRIORITY_0,Initiator Priority 0 Register" bitfld.long 0x00 26.--27. " TCWR2 ,TPTC 2 Write Port initiator priority" "0,1,2,3" bitfld.long 0x00 24.--25. " TCRD2 ,TPTC 2 Read Port initiator priority" "0,1,2,3" bitfld.long 0x00 22.--23. " TCWR1 ,TPTC 1 Write Port initiator priority" "0,1,2,3" textline " " bitfld.long 0x00 20.--21. " TCRD1 ,TPTC 1 Read Port initiator priority" "0,1,2,3" bitfld.long 0x00 18.--19. " TCWR0 ,TPTC 0 Write Port initiator priority" "0,1,2,3" bitfld.long 0x00 16.--17. " TCRD0 ,TPTC 0 Read Port initiator priority" "0,1,2,3" textline " " bitfld.long 0x00 14.--15. " P1500 ,P1500 Port Initiator priority" "0,1,2,3" bitfld.long 0x00 6.--7. " MMU ,System MMU initiator priority" "0,1,2,3" bitfld.long 0x00 4.--5. " PRU_ICSS ,PRU-ICSS initiator priority" "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " HOST_ARM ,Host Cortex A8 initiator priority" "0,1,2,3" group.long 0x60C++0x0B line.long 0x00 "INIT_PRIORITY_1,Initiator Priority 1 Register" bitfld.long 0x00 24.--25. " DEBUG ,Debug Subsystem initiator priority" "0,1,2,3" bitfld.long 0x00 22.--23. " LCD ,LCD initiator priority" "0,1,2,3" textline " " bitfld.long 0x00 20.--21. " SGX ,SGX initiator priority" "0,1,2,3" bitfld.long 0x00 6.--7. " USB_QMGR ,USB Queue Manager initiator priority" "0,1,2,3" textline " " bitfld.long 0x00 4.--5. " USB_DMA ,USB DMA port initiator priority" "0,1,2,3" bitfld.long 0x00 0.--1. " CPSW ,CPSW initiator priority" "0,1,2,3" line.long 0x04 "MMU_CFG,MMU Configuration Register" bitfld.long 0x04 15. " MMU_ABORT ,MMU abort operation" "Not aborted,Aborted" bitfld.long 0x04 7. " MMU_DISABLE ,MMU Disable" "No,Yes" line.long 0x08 "TPTC_CFG,TPTC Configuration Register" bitfld.long 0x08 4.--5. " TC2DBS ,TPTC2 Default Burst Size" "16 byte,32 byte,64 byte,128 byte" bitfld.long 0x08 2.--3. " TC1DBS ,TPTC1 Default Burst Size" "16 byte,32 byte,64 byte,128 byte" bitfld.long 0x08 0.--1. " TC0DBS ,TPTC0 Default Burst Size" "16 byte,32 byte,64 byte,128 byte" group.long 0x620++0x03 line.long 0x00 "USB_CTRL0,USB Control 0 Register" bitfld.long 0x00 23. " DATAPOLARITY_INV ,Data Polarity Invert" "DP/DM,DM/DP" bitfld.long 0x00 20. " OTGSESSENDEN ,Session End Detect Enable" "Disabled,Enabled" bitfld.long 0x00 19. " OTGVDET_EN ,VBUS Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " DMGPIO_PD ,Pulldown on DM in GPIO Mode" "Enabled,Disabled" bitfld.long 0x00 17. " DPGPIO_PD ,Pulldown on DP in GPIO Mode" "Enabled,Disabled" bitfld.long 0x00 14. " GPIO_SIG_CROSS ,UART TX->DM UART RX->DP" "Enabled,Disabled" textline " " bitfld.long 0x00 13. " GPIO_SIG_INV ,UART TX->Invert->DP UART RX->Invert->DM" "Not inverted,Inverted" bitfld.long 0x00 12. " GPIOMODE ,GPIO Mode" "USB Mode,GPIO Mode" bitfld.long 0x00 10. " CDET_EXTCTL ,Bypass the charger detection state machine" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 9. " DPPULLUP ,Pullup on DP line" "Disabled,Enabled" bitfld.long 0x00 8. " DMPULLUP ,Pullup on DM line" "Disabled,Enabled" bitfld.long 0x00 7. " CHGVSRC_EN ,Enable VSRC on DP line (Host Charger case)" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CHGISINK_EN ,Enable ISINK on DM line (Host Charger case)" "Disabled,Enabled" bitfld.long 0x00 5. " SINKONDP ,Sink on DP" "Disabled,Enabled" bitfld.long 0x00 4. " SRCONDM ,Source on DM" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CHGDET_RSTRT ,Restart Charger Detect" "No reset,Reset" bitfld.long 0x00 2. " CHGDET_DIS ,Charger Detect Disable" "No,Yes" bitfld.long 0x00 1. " OTG_PWRDN ,Power down the USB OTG PHY" "Normal,Powered down" textline " " bitfld.long 0x00 0. " CM_PWRDN ,Power down the USB CM PHY" "Normal,Powered down" rgroup.long 0x624++0x03 line.long 0x00 "USB_STS0,USB Status 0 Register" bitfld.long 0x00 5.--7. " CHGDETSTS ,Charge Detection Status" "Wait State,No Contact,PS/2,Unknown error,Dedicated charger,HOST charger,PC,Interrupt" bitfld.long 0x00 4. " CDET_DMDET ,DM Comparator Output" "Low,High" bitfld.long 0x00 3. " CDET_DPDET ,DP Comparator Output" "Low,High" textline " " bitfld.long 0x00 2. " CDET_DATADET ,Charger Comparator Output" "Low,High" bitfld.long 0x00 1. " CHGDETECT ,Charger Detection Status" "Not detected,Detected" bitfld.long 0x00 0. " CHGDETDONE ,Charger Detection Protocol Done" "Not done,Done" group.long 0x628++0x03 line.long 0x00 "USB_CTRL1,USB Control 1 Register" bitfld.long 0x00 23. " DATAPOLARITY_INV ,Data Polarity Invert" "DP/DM,DM/DP" bitfld.long 0x00 20. " OTGSESSENDEN ,Session End Detect Enable" "Disabled,Enabled" bitfld.long 0x00 19. " OTGVDET_EN ,VBUS Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " DMGPIO_PD ,Pulldown on DM in GPIO Mode" "Enabled,Disabled" bitfld.long 0x00 17. " DPGPIO_PD ,Pulldown on DP in GPIO Mode" "Enabled,Disabled" bitfld.long 0x00 14. " GPIO_SIG_CROSS ,UART TX->DM UART RX->DP" "Enabled,Disabled" textline " " bitfld.long 0x00 13. " GPIO_SIG_INV ,UART TX->Invert->DP UART RX->Invert->DM" "Not inverted,Inverted" bitfld.long 0x00 12. " GPIOMODE ,GPIO Mode" "USB Mode,GPIO Mode" bitfld.long 0x00 10. " CDET_EXTCTL ,Bypass the charger detection state machine" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 9. " DPPULLUP ,Pullup on DP line" "Disabled,Enabled" bitfld.long 0x00 8. " DMPULLUP ,Pullup on DM line" "Disabled,Enabled" bitfld.long 0x00 7. " CHGVSRC_EN ,Enable VSRC on DP line (Host Charger case)" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CHGISINK_EN ,Enable ISINK on DM line (Host Charger case)" "Disabled,Enabled" bitfld.long 0x00 5. " SINKONDP ,Sink on DP" "Disabled,Enabled" bitfld.long 0x00 4. " SRCONDM ,Source on DM" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CHGDET_RSTRT ,Restart Charger Detect" "No reset,Reset" bitfld.long 0x00 2. " CHGDET_DIS ,Charger Detect Disable" "No,Yes" bitfld.long 0x00 1. " OTG_PWRDN ,Power down the USB OTG PHY" "Normal,Powered down" textline " " bitfld.long 0x00 0. " CM_PWRDN ,Power down the USB CM PHY" "Normal,Powered down" rgroup.long 0x62C++0x13 line.long 0x00 "USB_STS1,USB Status 1 Register" bitfld.long 0x00 5.--7. " CHGDETSTS ,Charge Detection Status" "Wait State,No Contact,PS/2,Unknown error,Dedicated charger,HOST charger,PC,Interrupt" bitfld.long 0x00 4. " CDET_DMDET ,DM Comparator Output" "Low,High" bitfld.long 0x00 3. " CDET_DPDET ,DP Comparator Output" "Low,High" textline " " bitfld.long 0x00 2. " CDET_DATADET ,Charger Comparator Output" "Low,High" bitfld.long 0x00 1. " CHGDETECT ,Charger Detection Status" "Not detected,Detected" bitfld.long 0x00 0. " CHGDETDONE ,Charger Detection Protocol Done" "Not done,Done" line.long 0x04 "MAC_ID0_LO,MAC ID0 Low Address Register" hexmask.long.byte 0x04 8.--15. 1. " MACADDR_7_0 ,MAC0 Address - Byte 0" hexmask.long.byte 0x04 0.--7. 1. " MACADDR_15_8 ,MAC0 Address - Byte 1" line.long 0x08 "MAC_ID0_HI,MAC ID0 High Address Register" hexmask.long.byte 0x08 24.--31. 1. " MACADDR_23_16 ,MAC0 Address - Byte 2" hexmask.long.byte 0x08 16.--23. 1. " MACADDR_31_24 ,MAC0 Address - Byte 3" hexmask.long.byte 0x08 8.--15. 1. " MACADDR_39_32 ,MAC0 Address - Byte 4" textline " " hexmask.long.byte 0x08 0.--7. 1. " MACADDR_47_40 ,MAC0 Address - Byte 5" line.long 0x0C "MAC_ID1_LO,MAC ID1 Low Address Register" hexmask.long.byte 0x0C 8.--15. 1. " MACADDR_7_0 ,MAC0 Address - Byte 0" hexmask.long.byte 0x0C 0.--7. 1. " MACADDR_15_8 ,MAC0 Address - Byte 1" line.long 0x10 "MAC_ID1_HI,MAC ID1 High Address Register" hexmask.long.byte 0x10 24.--31. 1. " MACADDR_23_16 ,MAC0 Address - Byte 2" hexmask.long.byte 0x10 16.--23. 1. " MACADDR_31_24 ,MAC0 Address - Byte 3" textline " " hexmask.long.byte 0x10 8.--15. 1. " MACADDR_39_32 ,MAC0 Address - Byte 4" hexmask.long.byte 0x10 0.--7. 1. " macaddr_47_40 ,MAC0 Address - Byte 5" group.long 0x644++0x07 line.long 0x00 "DCAN_RAMINIT,DCAN RAM Initialization Register" eventfld.long 0x00 9. " DCAN1_RAMINIT_DONE ,DCAN1 RAM Initialization status" "Not complete,Complete" eventfld.long 0x00 8. " DCAN0_RAMINIT_DONE ,DCAN0 RAM Initialization status" "Not complete,Complete" textline " " bitfld.long 0x00 1. " DCAN1_RAMINIT_START ,A transition from 0 to 1 will start DCAN1 RAM initialization sequence" "Stopped,Started" bitfld.long 0x00 0. " DCAN0_RAMINIT_START ,A transition from 0 to 1 will start DCAN1 RAM initialization sequence" "Stopped,Started" line.long 0x04 "USB_WKUP_CTRL,USB WKUP Control Register" bitfld.long 0x04 8. " PHY1_WUEN ,PHY1 Wakeup Enable" "Disabled,Enabled" bitfld.long 0x04 0. " PHY0_WUEN ,PHY0 Wakeup Enable" "Disabled,Enabled" group.long 0x650++0x03 line.long 0x00 "GMII_SEL,GMII Selection Rgister" bitfld.long 0x00 7. " RMII2_IO_CLK_EN ,RMII Port 2 clock sourced from chip pin enable" "Disabled,Enabled" bitfld.long 0x00 6. " RMII1_IO_CLK_EN ,RMII Port 1 clock sourced from chip pin enable" "Disabled,Enabled" bitfld.long 0x00 5. " RGMII2_IDMOE ,RGMII2 Internal Delay Mode" "Delay,No delay" textline " " bitfld.long 0x00 4. " RGMII1_IDMODE ,RGMII1 Internal Delay Mode" "Delay,No delay" bitfld.long 0x00 2.--3. " GMII2_SEL ,GMII Port 2 Mode Select" "GMII/MII,RMII,RGMII Mode,Not used" bitfld.long 0x00 0.--1. " GMII1_SEL ,GMII Port 1 Mode Select" "GMII/MII,RMII,RGMII Mode,Not used" group.long 0x664++0x03 line.long 0x00 "PWMSS_CTRL,PWMSS Control Register" bitfld.long 0x00 2. " PWMSS2_TBCLKEN ,Timebase clock enable for PWMSS2" "Low,High" bitfld.long 0x00 1. " PWMSS1_TBCLKEN ,Timebase clock enable for PWMSS1" "Low,High" bitfld.long 0x00 0. " PWMSS0_TBCLKEN ,Timebase clock enable for PWMSS0" "Low,High" group.long 0x670++0x07 line.long 0x00 "MREQPRIO_0,MREQ Priority 0 Register" bitfld.long 0x00 24.--26. " SGX ,MReqPriority for SGX Initiator OCP Interface" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24.--26. " USB1 ,MReqPriority for USB1 Initiator OCP Interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " USB0 ,MReqPriority for USB0 Initiator OCP Interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " CPSW ,MReqPriority for CPSW Initiator OCP Interface" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--10. " PRU_ICSS_PRU0 ,MReqPriority for PRU-ICSS PRU0 Initiator OCP Interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " SAB_INIT1 ,MReqPriority for MPU Initiator 1 OCP Interface" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " SAB_INIT0 ,MReqPriority for MPU Initiator 0 OCP Interface" "0,1,2,3,4,5,6,7" line.long 0x04 "MREQPRIO_1,MREQ Priority 1 Register" bitfld.long 0x04 0.--2. " EXP ,MReqPriority for Expansion Initiator OCP Interface" "0,1,2,3,4,5,6,7" group.long 0x690++0x0F line.long 0x00 "HW_EVENT_SEL_GRP1,HW Event Selection Group 1 Register" hexmask.long.byte 0x00 24.--31. 1. " EVENT4 ,Select 4th trace event from group 1" hexmask.long.byte 0x00 16.--23. 1. " EVENT3 ,Select 3rd trace event from group 1" hexmask.long.byte 0x00 8.--15. 1. " EVENT2 ,Select 2nd trace event from group 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " EVENT1 ,Select 1st trace event from group 1" line.long 0x04 "HW_EVENT_SEL_GRP2,HW Event Selection Group 2 Register" hexmask.long.byte 0x04 24.--31. 1. " EVENT8 ,Select 8th trace event from group 2" hexmask.long.byte 0x04 16.--23. 1. " EVENT7 ,Select 7th trace event from group 2" hexmask.long.byte 0x04 8.--15. 1. " EVENT6 ,Select 6th trace event from group 2" textline " " hexmask.long.byte 0x04 0.--7. 1. " EVENT5 ,Select 5th trace event from group 2" line.long 0x08 "HW_EVENT_SEL_GRP3,HW Event Selection Group 3 Register" hexmask.long.byte 0x08 24.--31. 1. " EVENT12 ,Select 12th trace event from group 3" hexmask.long.byte 0x08 16.--23. 1. " EVENT11 ,Select 11th trace event from group 3" hexmask.long.byte 0x08 8.--15. 1. " EVENT10 ,Select 10th trace event from group 3" textline " " hexmask.long.byte 0x08 0.--7. 1. " EVENT9 ,Select 9th trace event from group 3" line.long 0x0C "HW_EVENT_SEL_GRP4,HW Event Selection Group 4 Register" hexmask.long.byte 0x0C 24.--31. 1. " EVENT16 ,Select 16th trace event from group 4" hexmask.long.byte 0x0C 16.--23. 1. " EVENT15 ,Select 15th trace event from group 4" hexmask.long.byte 0x0C 8.--15. 1. " EVENT14 ,Select 14th trace event from group 4" textline " " hexmask.long.byte 0x0C 0.--7. 1. " EVENT13 ,Select 13th trace event from group 4" group.long 0x6A0++0x07 line.long 0x00 "SMRT_CTRL,SMRT Control Register" bitfld.long 0x00 1. " SR1_SLEEP ,Enable sensor" "Disabled,Enabled" bitfld.long 0x00 0. " SR0_SLEEP ,Enable sensor" "Disabled,Enabled" line.long 0x04 "MPUSS_HW_DEBUG_SEL,MPUSS HW Debug Select Register" bitfld.long 0x04 9. " HW_DBG_GATE_EN ,MPUSS_HW_DBG_INFO gate enable" "Disabled,Enabled" bitfld.long 0x04 0.--3. " HW_DBG_SEL ,Selects which Group of signals are sent out to the MODENA_HW_DBG_INFO register" "Group 0,Group 1,Group 2,Group 3,Group 4,Group 5,Group 6,Group 7,?..." rgroup.long 0x6A8++0x03 line.long 0x00 "MPUSS_HW_DBG_INFO,MPUSS HW Debug Info Register" hexmask.long 0x00 0.--31. 1. " HW_DBG_INFO ,Hardware Debug Info from MPU" rgroup.long 0x770++0x0F line.long 0x00 "VDD_MPU_OPP_050,VDD MPU OPP50 Register" hexmask.long.tbyte 0x00 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domain OPP50" line.long 0x04 "VDD_MPU_OPP_100,VDD MPU OPP100 Register" hexmask.long.tbyte 0x04 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domain OPP100" line.long 0x08 "VDD_MPU_OPP_120,VDD MPU OPP120 Register" hexmask.long.tbyte 0x08 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domain OPP120" line.long 0x0C "VDD_MPU_OPP_TURBO,VDD MPU OPPTURBO Register" hexmask.long.tbyte 0x0C 0.--23. 1. " NTARGET ,Ntarget value for MPU Voltage domain OPPTURBO" rgroup.long 0x7B8++0x07 line.long 0x00 "VDD_CORE_OPP_050,VDD CORE OPP50 Register" hexmask.long.tbyte 0x00 0.--23. 1. " NTARGET ,Ntarget value for CORE Voltage domain OPP50" line.long 0x04 "VDD_CORE_OPP_100,VDD CORE OPP100 Register" hexmask.long.tbyte 0x04 0.--23. 1. " NTARGET ,Ntarget value for CORE Voltage domain OPP100" rgroup.long 0x7D0++0x03 line.long 0x00 "BB_SCALE,BBIAS Scale Register" bitfld.long 0x00 8.--11. " SCALE ,Dynamic core voltage scaling for class 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " BBIAS ,BBIAS value from Efuse" "0,1,2,3" rgroup.long 0x7F4++0x03 line.long 0x00 "USB_VID_PID,USB VID PID Register" hexmask.long.word 0x00 16.--31. 1. " USB_VID ,USB Vendor ID" hexmask.long.word 0x00 0.--15. 1. " USB_PID ,USB Product ID" tree "Pin Mux Configuration Registers" width 24. group.long 0x800++0x9F line.long 0x0 "CONF_GPMC_AD0,GPMC AD0 Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_GPMC_AD1,GPMC AD1 Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_GPMC_AD2,GPMC AD2 Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_GPMC_AD3,GPMC AD3 Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x10 "CONF_GPMC_AD4,GPMC AD4 Configuration Register" bitfld.long 0x10 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x10 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x10 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x10 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x10 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x14 "CONF_GPMC_AD5,GPMC AD5 Configuration Register" bitfld.long 0x14 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x14 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x14 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x14 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x14 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x18 "CONF_GPMC_AD6,GPMC AD6 Configuration Register" bitfld.long 0x18 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x18 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x18 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x18 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x18 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x1C "CONF_GPMC_AD7,GPMC AD7 Configuration Register" bitfld.long 0x1C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x1C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x1C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x1C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x1C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x20 "CONF_GPMC_AD8,GPMC AD8 Configuration Register" bitfld.long 0x20 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x20 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x20 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x20 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x20 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x24 "CONF_GPMC_AD9,GPMC AD9 Configuration Register" bitfld.long 0x24 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x24 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x24 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x24 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x24 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x28 "CONF_GPMC_AD10,GPMC AD10 Configuration Register" bitfld.long 0x28 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x28 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x28 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x28 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x28 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x2C "CONF_GPMC_AD11,GPMC AD11 Configuration Register" bitfld.long 0x2C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x2C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x2C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x2C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x2C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x30 "CONF_GPMC_AD12,GPMC AD12 Configuration Register" bitfld.long 0x30 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x30 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x30 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x30 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x30 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x34 "CONF_GPMC_AD13,GPMC AD13 Configuration Register" bitfld.long 0x34 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x34 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x34 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x34 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x34 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x38 "CONF_GPMC_AD14,GPMC AD14 Configuration Register" bitfld.long 0x38 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x38 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x38 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x38 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x38 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x3C "CONF_GPMC_AD15,GPMC AD15 Configuration Register" bitfld.long 0x3C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x3C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x3C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x3C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x3C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x40 "CONF_GPMC_A0,GPMC A0 Configuration Register" bitfld.long 0x40 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x40 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x40 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x40 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x40 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x44 "CONF_GPMC_A1,GPMC A1 Configuration Register" bitfld.long 0x44 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x44 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x44 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x44 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x44 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x48 "CONF_GPMC_A2,GPMC A2 Configuration Register" bitfld.long 0x48 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x48 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x48 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x48 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x48 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4C "CONF_GPMC_A3,GPMC A3 Configuration Register" bitfld.long 0x4C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x50 "CONF_GPMC_A4,GPMC A4 Configuration Register" bitfld.long 0x50 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x50 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x50 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x50 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x50 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x54 "CONF_GPMC_A5,GPMC A5 Configuration Register" bitfld.long 0x54 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x54 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x54 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x54 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x54 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x58 "CONF_GPMC_A6,GPMC A6 Configuration Register" bitfld.long 0x58 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x58 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x58 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x58 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x58 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x5C "CONF_GPMC_A7,GPMC A7 Configuration Register" bitfld.long 0x5C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x5C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x5C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x5C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x5C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x60 "CONF_GPMC_A8,GPMC A8 Configuration Register" bitfld.long 0x60 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x60 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x60 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x60 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x60 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x64 "CONF_GPMC_A9,GPMC A9 Configuration Register" bitfld.long 0x64 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x64 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x64 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x64 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x64 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x68 "CONF_GPMC_A10,GPMC A10 Configuration Register" bitfld.long 0x68 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x68 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x68 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x68 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x68 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x6C "CONF_GPMC_A11,GPMC A11 Configuration Register" bitfld.long 0x6C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x6C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x6C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x6C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x6C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x70 "CONF_GPMC_WAIT0,GPMC WAIT0 Configuration Register" bitfld.long 0x70 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x70 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x70 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x70 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x70 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x74 "CONF_GPMC_WPN,GPMC WPN Configuration Register" bitfld.long 0x74 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x74 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x74 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x74 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x74 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x78 "CONF_GPMC_BE1N,GPMC BE1N Configuration Register" bitfld.long 0x78 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x78 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x78 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x78 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x78 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x7C "CONF_GPMC_CSN0,GPMC CSN0 Configuration Register" bitfld.long 0x7C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x7C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x7C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x7C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x7C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x80 "CONF_GPMC_CSN1,GPMC CSN1 Configuration Register" bitfld.long 0x80 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x80 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x80 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x80 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x80 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x84 "CONF_GPMC_CSN2,GPMC CSN2 Configuration Register" bitfld.long 0x84 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x84 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x84 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x84 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x84 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x88 "CONF_GPMC_CSN3,GPMC CSN3 Configuration Register" bitfld.long 0x88 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x88 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x88 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x88 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x88 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8C "CONF_GPMC_CLK,GPMC CLK Configuration Register" bitfld.long 0x8C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x90 "CONF_GPMC_ADVN_ALE,GPMC ADVN_ALE Configuration Register" bitfld.long 0x90 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x90 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x90 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x90 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x90 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x94 "CONF_GPMC_OEN_REN,GPMC OEN_REN Configuration Register" bitfld.long 0x94 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x94 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x94 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x94 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x94 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x98 "CONF_GPMC_WEN,GPMC WEN Configuration Register" bitfld.long 0x98 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x98 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x98 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x98 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x98 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x9C "CONF_GPMC_BE0N_CLE,GPMC BE0N_CLE Configuration Register" bitfld.long 0x9C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x9C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x9C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x9C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x9C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x8A0++0x4F line.long 0x0 "CONF_LCD_DATA0,LCD DATA0 Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_LCD_DATA1,LCD DATA1 Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_LCD_DATA2,LCD DATA2 Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_LCD_DATA3,LCD DATA3 Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x10 "CONF_LCD_DATA4,LCD DATA4 Configuration Register" bitfld.long 0x10 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x10 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x10 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x10 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x10 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x14 "CONF_LCD_DATA5,LCD DATA5 Configuration Register" bitfld.long 0x14 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x14 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x14 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x14 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x14 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x18 "CONF_LCD_DATA6,LCD DATA6 Configuration Register" bitfld.long 0x18 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x18 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x18 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x18 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x18 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x1C "CONF_LCD_DATA7,LCD DATA7 Configuration Register" bitfld.long 0x1C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x1C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x1C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x1C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x1C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x20 "CONF_LCD_DATA8,LCD DATA8 Configuration Register" bitfld.long 0x20 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x20 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x20 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x20 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x20 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x24 "CONF_LCD_DATA9,LCD DATA9 Configuration Register" bitfld.long 0x24 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x24 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x24 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x24 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x24 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x28 "CONF_LCD_DATA10,LCD DATA10 Configuration Register" bitfld.long 0x28 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x28 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x28 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x28 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x28 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x2C "CONF_LCD_DATA11,LCD DATA11 Configuration Register" bitfld.long 0x2C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x2C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x2C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x2C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x2C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x30 "CONF_LCD_DATA12,LCD DATA12 Configuration Register" bitfld.long 0x30 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x30 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x30 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x30 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x30 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x34 "CONF_LCD_DATA13,LCD DATA13 Configuration Register" bitfld.long 0x34 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x34 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x34 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x34 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x34 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x38 "CONF_LCD_DATA14,LCD DATA14 Configuration Register" bitfld.long 0x38 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x38 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x38 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x38 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x38 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x3C "CONF_LCD_DATA15,LCD DATA15 Configuration Register" bitfld.long 0x3C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x3C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x3C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x3C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x3C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x40 "CONF_LCD_VSYNC,LCD VSYNC Configuration Register" bitfld.long 0x40 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x40 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x40 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x40 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x40 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x44 "CONF_LCD_HSYNC,LCD HSYNC Configuration Register" bitfld.long 0x44 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x44 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x44 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x44 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x44 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x48 "CONF_LCD_PCLK,LCD PCLK Configuration Register" bitfld.long 0x48 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x48 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x48 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x48 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x48 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4C "CONF_LCD_AC_BIAS_EN,LCD AC_BIAS_EN Configuration Register" bitfld.long 0x4C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x8F0++0x17 line.long 0x0 "CONF_MMC0_DAT3,MMC0 DAT3 Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_MMC0_DAT2,MMC0 DAT2 Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_MMC0_DAT1,MMC0 DAT1 Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_MMC0_DAT0,MMC0 DAT0 Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x10 "CONF_MMC0_CLK,MMC0 CLK Configuration Register" bitfld.long 0x10 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x10 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x10 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x10 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x10 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x14 "CONF_MMC0_CMD,MMC0 CMD Configuration Register" bitfld.long 0x14 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x14 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x14 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x14 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x14 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x908++0x3B line.long 0x0 "CONF_MII1_COL,MII1 COL Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_MII1_CRS,MII1 CRS Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_MII1_RXERR,MII1 RXERR Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_MII1_TXEN,MII1 TXEN Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x10 "CONF_MII1_RXDV,MII1 RXDV Configuration Register" bitfld.long 0x10 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x10 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x10 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x10 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x10 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x14 "CONF_MII1_TXD3,MII1 TXD3 Configuration Register" bitfld.long 0x14 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x14 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x14 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x14 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x14 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x18 "CONF_MII1_TXD2,MII1 TXD2 Configuration Register" bitfld.long 0x18 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x18 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x18 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x18 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x18 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x1C "CONF_MII1_TXD1,MII1 TXD1 Configuration Register" bitfld.long 0x1C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x1C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x1C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x1C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x1C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x20 "CONF_MII1_TXD0,MII1 TXD0 Configuration Register" bitfld.long 0x20 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x20 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x20 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x20 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x20 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x24 "CONF_MII1_TXCLK,MII1 TXCLK Configuration Register" bitfld.long 0x24 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x24 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x24 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x24 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x24 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x28 "CONF_MII1_RXCLK,MII1 RXCLK Configuration Register" bitfld.long 0x28 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x28 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x28 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x28 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x28 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x2C "CONF_MII1_RXD3,MII1 RXD3 Configuration Register" bitfld.long 0x2C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x2C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x2C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x2C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x2C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x30 "CONF_MII1_RXD2,MII1 RXD2 Configuration Register" bitfld.long 0x30 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x30 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x30 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x30 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x30 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x34 "CONF_MII1_RXD1,MII1 RXD1 Configuration Register" bitfld.long 0x34 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x34 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x34 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x34 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x34 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x38 "CONF_MII1_RXD0,MII1 RXD0 Configuration Register" bitfld.long 0x38 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x38 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x38 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x38 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x38 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x944++0x3 line.long 0x00 "CONF_RMII1_REFCLK,RMII1 REFCLK Configuration Register" bitfld.long 0x00 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x00 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x00 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x00 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x948++0x07 line.long 0x0 "CONF_MDIO_DATA,MDIO DATA Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_MDIO_CLK,MDIO CLK Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x950++0x13 line.long 0x0 "CONF_SPI0_SCLK,SPI0 SCLK Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_SPI0_D0,SPI0 D0 Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_SPI0_D1,SPI0 D1 Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_SPI0_CS0,SPI0 CS0 Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x10 "CONF_SPI0_CS1,SPI0 CS1 Configuration Register" bitfld.long 0x10 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x10 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x10 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x10 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x10 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x964++0x3 line.long 0x00 "CONF_ECAP0_IN_PWM0_OUT,ECAP0 IN_PWM0_OUT Configuration Register" bitfld.long 0x00 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x00 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x00 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x00 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x00 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x968++0x0F line.long 0x0 "CONF_UART0_CTSN,UART0 CTSN Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_UART0_RTSN,UART0 RTSN Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_UART0_RXD,UART0 RXD Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_UART0_TXD,UART0 TXD Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x978++0x0F line.long 0x0 "CONF_UART1_CTSN,UART1 CTSN Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_UART1_RTSN,UART1 RTSN Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_UART1_RXD,UART1 RXD Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_UART1_TXD,UART1 TXD Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x988++0x07 line.long 0x0 "CONF_I2C0_SDA,I2C0 SDA Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_I2C0_SCL,I2C0 SCL Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x990++0x1F line.long 0x0 "CONF_MCASP0_ACLKX,MCASP0 ACLKX Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_MCASP0_FSX,MCASP0 FSX Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_MCASP0_AXR0,MCASP0 AXR0 Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_MCASP0_AHCLKR,MCASP0 AHCLKR Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x10 "CONF_MCASP0_ACLKR,MCASP0 ACLKR Configuration Register" bitfld.long 0x10 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x10 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x10 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x10 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x10 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x14 "CONF_MCASP0_FSR,MCASP0 FSR Configuration Register" bitfld.long 0x14 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x14 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x14 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x14 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x14 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x18 "CONF_MCASP0_AXR1,MCASP0 AXR1 Configuration Register" bitfld.long 0x18 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x18 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x18 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x18 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x18 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x1C "CONF_MCASP0_AHCLKX,MCASP0 AHCLKX Configuration Register" bitfld.long 0x1C 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x1C 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x1C 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x1C 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x1C 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x9B0++0x07 line.long 0x0 "CONF_XDMA_EVENT_INTR0,XDMA EVENT_INTR0 Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_XDMA_EVENT_INTR1,XDMA EVENT_INTR1 Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x9B8++0x0B line.long 0x0 "CONF_NRESETIN_OUT,NRESETIN_OUT Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_PORZ,PORZ Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_NNMI,NNMI Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x9C4++0x0B line.long 0x0 "CONF_OSC0_IN,OSC0 IN Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_OSC0_OUT,OSC0 OUT Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_OSC0_VSS,OSC0 VSS Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x9D0++0x1B line.long 0x0 "CONF_TMS,TMS Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_TDI,TDI Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_TDO,TDO Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_TCK,TCK Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x10 "CONF_NTRST,NTRST Configuration Register" bitfld.long 0x10 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x10 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x10 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x10 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x10 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x14 "CONF_EMU0,EMU0 Configuration Register" bitfld.long 0x14 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x14 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x14 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x14 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x14 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x18 "CONF_EMU1,EMU1 Configuration Register" bitfld.long 0x18 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x18 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x18 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x18 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x18 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x9EC++0x07 line.long 0x0 "CONF_RTC_XTALIN,OSC1 IN Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_RTC_XTALOUT,OSC1 OUT Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0x9F8++0x0F line.long 0x0 "CONF_RTC_PWRONRSTN,RTC_PWRONRSTN Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_PMIC_POWER_EN,PMIC_POWER_EN Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_EXT_WAKEUP,EXT_WAKEUP Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_ENZ_KALDO_1P8V,ENZ_KALDO_1P8V Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0xA08++0x17 line.long 0x0 "CONF_USB0_DM,USB0 DM Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_USB0_DP,USB0 DP Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_USB0_CE,USB0 CE Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_USB0_D,USB0 D Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x10 "CONF_USB0_VBUS,USB0 VBUS Configuration Register" bitfld.long 0x10 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x10 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x10 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x10 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x10 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x14 "CONF_USB0_DRVVBUS,USB0 DRVVBUS Configuration Register" bitfld.long 0x14 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x14 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x14 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x14 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x14 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" group.long 0xA20++0x17 line.long 0x0 "CONF_USB1_DM,USB1 DM Configuration Register" bitfld.long 0x0 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x0 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x0 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x0 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x0 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x4 "CONF_USB1_DP,USB1 DP Configuration Register" bitfld.long 0x4 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x4 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x4 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x4 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x4 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x8 "CONF_USB1_CE,USB1 CE Configuration Register" bitfld.long 0x8 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x8 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x8 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x8 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x8 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0xC "CONF_USB1_D,USB1 D Configuration Register" bitfld.long 0xC 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0xC 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0xC 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0xC 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0xC 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x10 "CONF_USB1_VBUS,USB1 VBUS Configuration Register" bitfld.long 0x10 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x10 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x10 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x10 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x10 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" line.long 0x14 "CONF_USB1_DRVVBUS,USB1 DRVVBUS Configuration Register" bitfld.long 0x14 6. " SLEWCTRL ,Select between faster or slower slew rate" "Fast,Slow" bitfld.long 0x14 5. " RXACTIVE ,Input enable value for the PAD" "Disabled,Enabled" bitfld.long 0x14 4. " PUTYPESEL ,Pad pullup/pulldown type selection" "Pulldown,Pullup" textline " " bitfld.long 0x14 3. " PUDEN ,Pad pullup/pulldown enable" "Enabled,Disabled" bitfld.long 0x14 0.--2. " MMODE ,Pad functional signal mux select" "0,1,2,3,4,5,6,7" tree.end textline " " width 31. rgroup.long 0xE00++0x3 line.long 0x00 "CQDETECT_STATUS,CQDETECT Status Register" bitfld.long 0x00 13. " CQERR_GENERAL ,CQDetect Mode Error Status" "No error,Error" bitfld.long 0x00 12. " CQERR_GEMAC_B ,CQDetect Mode Error Status" "No error,Error" textline " " bitfld.long 0x00 11. " CQERR_GEMAC_A ,CQDetect Mode Error Status" "No error,Error" bitfld.long 0x00 10. " CQERR_MMCSD_B ,CQDetect Mode Error Status" "No error,Error" textline " " bitfld.long 0x00 9. " CQERR_MMCSD_A ,CQDetect Mode Error Status" "No error,Error" bitfld.long 0x00 8. " CQERR_GPMC ,CQDetect Mode Error Status" "No error,Error" textline " " bitfld.long 0x00 5. " CQSTAT_GENERAL ,CQDetect IO Mode Status" "1.8V,3.3V" bitfld.long 0x00 4. " CQSTAT_GEMAC_B ,CQDetect IO Mode Status" "1.8V,3.3V" textline " " bitfld.long 0x00 3. " CQSTAT_GEMAC_A ,CQDetect IO Mode Status" "1.8V,3.3V" bitfld.long 0x00 2. " CQSTAT_MMCSD_B ,CQDetect IO Mode Status" "1.8V,3.3V" textline " " bitfld.long 0x00 1. " CQSTAT_MMCSD_A ,CQDetect IO Mode Status" "1.8V,3.3V" bitfld.long 0x00 0. " CQSTAT_GPMC ,CQDetect IO Mode Status" "1.8V,3.3V" group.long 0xE04++0x3 line.long 0x00 "DDR_IO_CTRL,DDR IO Control Register" bitfld.long 0x00 31. " DDR3_RST_DEF_VAL ,DDR3 reset default value" "No reset,Reset" bitfld.long 0x00 30. " DDR_WUCLK_DISABLE ,Disables the slow clock to WUCLKIN and ISOCLKIN of DDR emif SS and IOs" "No,Yes" bitfld.long 0x00 28. " MDDR_SEL ,MDDR Select" "DDR2,mDDR" group.long 0xE0C++0x3 line.long 0x00 "VTP_CTRL,VTP Control Register" hexmask.long.byte 0x00 16.--22. 1. " PCIN ,Default/reset values of P for the VTP controller" hexmask.long.byte 0x00 8.--14. 1. " NCIN ,Default/reset values of N for the VTP controller" bitfld.long 0x00 6. " ENABLE ,VTP mode" "Bypass,Compensation" textline " " rbitfld.long 0x00 5. " READY ,Training sequence status" "Not completed,Completed" bitfld.long 0x00 4. " LOCK ,Lock dynamic update" "Not locked,Locked" bitfld.long 0x00 1.--3. " FILTER ,Digital filter bits to prevent the controller from making excessive number of changes" "Disabled,2 requests,3 requests,4 requests,5 requests,6 requests,7 requests,8 requests" textline " " bitfld.long 0x00 0. " CLRZ ,Clears flops" "Low,High" group.long 0xE14++0x3 line.long 0x00 "VREF_CTRL,VREF Control Register" bitfld.long 0x00 3.--4. " DDR_VREF_CCAP ,Select for coupling cap for DDR" "None,VSS,VDDS,Both" bitfld.long 0x00 1.--2. " DDR_VREF_TAP ,Select for int ref for DDR" "2uA,4uA,6uA,8uA" bitfld.long 0x00 0. " DDR_VREF_EN ,Internal reference enable for DDR" "Disabled,Enabled" group.long 0xF90++0x3F line.long 0x00 "TPCC_EVT_MUX_0_3,TPCC EVT MUX 0 3 Register" bitfld.long 0x00 24.--29. " EVT_MUX_3 ,Selects 1 of 64 inputs for DMA event 3" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 16.--21. " EVT_MUX_2 ,Selects 1 of 64 inputs for DMA event 2" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 8.--13. " EVT_MUX_1 ,Selects 1 of 64 inputs for DMA event 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x00 0.--5. " EVT_MUX_0 ,Selects 1 of 64 inputs for DMA event 0" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x04 "TPCC_EVT_MUX_4_7,TPCC EVT MUX 4 7 Register" bitfld.long 0x04 24.--29. " EVT_MUX_7 ,Selects 1 of 64 inputs for DMA event 7" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x04 16.--21. " EVT_MUX_6 ,Selects 1 of 64 inputs for DMA event 6" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x04 8.--13. " EVT_MUX_5 ,Selects 1 of 64 inputs for DMA event 5" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x04 0.--5. " EVT_MUX_4 ,Selects 1 of 64 inputs for DMA event 4" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x08 "TPCC_EVT_MUX_8_11,TPCC EVT MUX 8 11 Register" bitfld.long 0x08 24.--29. " EVT_MUX_11 ,Selects 1 of 64 inputs for DMA event 11" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 16.--21. " EVT_MUX_10 ,Selects 1 of 64 inputs for DMA event 10" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 8.--13. " EVT_MUX_9 ,Selects 1 of 64 inputs for DMA event 9" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x08 0.--5. " EVT_MUX_8 ,Selects 1 of 64 inputs for DMA event 8" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x0C "TPCC_EVT_MUX_12_15,TPCC EVT MUX 12 15 Register" bitfld.long 0x0C 24.--29. " EVT_MUX_15 ,Selects 1 of 64 inputs for DMA event 15" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x0C 16.--21. " EVT_MUX_14 ,Selects 1 of 64 inputs for DMA event 14" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x0C 8.--13. " EVT_MUX_13 ,Selects 1 of 64 inputs for DMA event 13" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x0C 0.--5. " EVT_MUX_12 ,Selects 1 of 64 inputs for DMA event 12" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x10 "TPCC_EVT_MUX_16_19,TPCC EVT MUX 16 19 Register" bitfld.long 0x10 24.--29. " EVT_MUX_19 ,Selects 1 of 64 inputs for DMA event 19" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x10 16.--21. " EVT_MUX_18 ,Selects 1 of 64 inputs for DMA event 18" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x10 8.--13. " EVT_MUX_17 ,Selects 1 of 64 inputs for DMA event 17" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x10 0.--5. " EVT_MUX_16 ,Selects 1 of 64 inputs for DMA event 16" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x14 "TPCC_EVT_MUX_20_23,TPCC EVT MUX 20 23 Register" bitfld.long 0x14 24.--29. " EVT_MUX_23 ,Selects 1 of 64 inputs for DMA event 23" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x14 16.--21. " EVT_MUX_22 ,Selects 1 of 64 inputs for DMA event 22" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x14 8.--13. " EVT_MUX_21 ,Selects 1 of 64 inputs for DMA event 21" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x14 0.--5. " EVT_MUX_20 ,Selects 1 of 64 inputs for DMA event 20" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x18 "TPCC_EVT_MUX_24_27,TPCC EVT MUX 24 27 Register" bitfld.long 0x18 24.--29. " EVT_MUX_27 ,Selects 1 of 64 inputs for DMA event 27" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x18 16.--21. " EVT_MUX_26 ,Selects 1 of 64 inputs for DMA event 26" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x18 8.--13. " EVT_MUX_25 ,Selects 1 of 64 inputs for DMA event 25" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x18 0.--5. " EVT_MUX_24 ,Selects 1 of 64 inputs for DMA event 24" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x1C "TPCC_EVT_MUX_28_31,TPCC EVT MUX 28 31 Register" bitfld.long 0x1C 24.--29. " EVT_MUX_31 ,Selects 1 of 64 inputs for DMA event 31" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x1C 16.--21. " EVT_MUX_30 ,Selects 1 of 64 inputs for DMA event 30" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x1C 8.--13. " EVT_MUX_29 ,Selects 1 of 64 inputs for DMA event 29" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x1C 0.--5. " EVT_MUX_28 ,Selects 1 of 64 inputs for DMA event 28" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x20 "TPCC_EVT_MUX_32_35,TPCC EVT MUX 32 35 Register" bitfld.long 0x20 24.--29. " EVT_MUX_35 ,Selects 1 of 64 inputs for DMA event 35" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x20 16.--21. " EVT_MUX_34 ,Selects 1 of 64 inputs for DMA event 34" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x20 8.--13. " EVT_MUX_33 ,Selects 1 of 64 inputs for DMA event 33" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x20 0.--5. " EVT_MUX_32 ,Selects 1 of 64 inputs for DMA event 32" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x24 "TPCC_EVT_MUX_36_39,TPCC EVT MUX 36 39 Register" bitfld.long 0x24 24.--29. " EVT_MUX_39 ,Selects 1 of 64 inputs for DMA event 39" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x24 16.--21. " EVT_MUX_38 ,Selects 1 of 64 inputs for DMA event 38" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x24 8.--13. " EVT_MUX_37 ,Selects 1 of 64 inputs for DMA event 37" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x24 0.--5. " EVT_MUX_36 ,Selects 1 of 64 inputs for DMA event 36" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x28 "TPCC_EVT_MUX_40_43,TPCC EVT MUX 40 43 Register" bitfld.long 0x28 24.--29. " EVT_MUX_43 ,Selects 1 of 64 inputs for DMA event 43" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x28 16.--21. " EVT_MUX_42 ,Selects 1 of 64 inputs for DMA event 42" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x28 8.--13. " EVT_MUX_41 ,Selects 1 of 64 inputs for DMA event 41" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x28 0.--5. " EVT_MUX_40 ,Selects 1 of 64 inputs for DMA event 40" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x2C "TPCC_EVT_MUX_44_47,TPCC EVT MUX 44 47 Register" bitfld.long 0x2C 24.--29. " EVT_MUX_47 ,Selects 1 of 64 inputs for DMA event 47" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x2C 16.--21. " EVT_MUX_46 ,Selects 1 of 64 inputs for DMA event 46" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x2C 8.--13. " EVT_MUX_45 ,Selects 1 of 64 inputs for DMA event 45" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x2C 0.--5. " EVT_MUX_44 ,Selects 1 of 64 inputs for DMA event 44" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x30 "TPCC_EVT_MUX_48_51,TPCC EVT MUX 48 51 Register" bitfld.long 0x30 24.--29. " EVT_MUX_51 ,Selects 1 of 64 inputs for DMA event 51" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x30 16.--21. " EVT_MUX_50 ,Selects 1 of 64 inputs for DMA event 50" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x30 8.--13. " EVT_MUX_49 ,Selects 1 of 64 inputs for DMA event 49" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x30 0.--5. " EVT_MUX_48 ,Selects 1 of 64 inputs for DMA event 48" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x34 "TPCC_EVT_MUX_52_55,TPCC EVT MUX 52 55 Register" bitfld.long 0x34 24.--29. " EVT_MUX_55 ,Selects 1 of 64 inputs for DMA event 55" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x34 16.--21. " EVT_MUX_54 ,Selects 1 of 64 inputs for DMA event 54" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x34 8.--13. " EVT_MUX_53 ,Selects 1 of 64 inputs for DMA event 53" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x34 0.--5. " EVT_MUX_52 ,Selects 1 of 64 inputs for DMA event 52" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x38 "TPCC_EVT_MUX_56_59,TPCC EVT MUX 56 59 Register" bitfld.long 0x38 24.--29. " EVT_MUX_59 ,Selects 1 of 64 inputs for DMA event 59" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x38 16.--21. " EVT_MUX_58 ,Selects 1 of 64 inputs for DMA event 58" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x38 8.--13. " EVT_MUX_57 ,Selects 1 of 64 inputs for DMA event 57" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x38 0.--5. " EVT_MUX_56 ,Selects 1 of 64 inputs for DMA event 56" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x3C "TPCC_EVT_MUX_60_63,TPCC EVT MUX 60 63 Register" bitfld.long 0x3C 24.--29. " EVT_MUX_63 ,Selects 1 of 64 inputs for DMA event 63" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x3C 16.--21. " EVT_MUX_62 ,Selects 1 of 64 inputs for DMA event 62" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x3C 8.--13. " EVT_MUX_61 ,Selects 1 of 64 inputs for DMA event 61" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" textline " " bitfld.long 0x3C 0.--5. " EVT_MUX_60 ,Selects 1 of 64 inputs for DMA event 60" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" group.long 0xFD0++0x3F line.long 0x00 "TIMER_EVT_CAPT,Timer Event Capture Register" bitfld.long 0x00 16.--20. " TIMER7_EVTCAPT ,Timer 7 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " TIMER6_EVTCAPT ,Timer 6 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TIMER5_EVTCAPT ,Timer 5 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ECAP_EVT_CAPT,ECAP Event Capture Register" bitfld.long 0x04 16.--20. " ECAP2_EVTCAPT ,ECAP 2 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 8.--12. " ECAP1_EVTCAPT ,ECAP 1 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 0.--4. " ECAP0_EVTCAPT ,ECAP 0 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "ADC_EVT_CAPT,EADC Event Capture Register" bitfld.long 0x08 0.--3. " ADC_EVTCAPT ,ECAP0 event capture mux" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1000++0x03 line.long 0x00 "RESET_ISO,Reser Isolation Register" bitfld.long 0x00 0. " ISO_CONTROL ,Ethernet Switch Isolation" "Not isolated,Isolated" group.long 0x131C++0x03 line.long 0x00 "DDR_CKE_CTRL,DDR CKE Control Register" bitfld.long 0x00 0. " DDR_CKE_CTRL ,CKE from EMIF/DDRPHY is ANDed with this bit" "Gated off to zero,Normal operation" hgroup.long 0x1320++0x03 hide.long 0x00 "SMA2,SMA2 Register" group.long 0x1324++0x03 line.long 0x00 "M3_TXEV_EOI,M3 TEXV EOI Register" bitfld.long 0x00 0. " M3_TXEV_EOI ,TXEV (Event) from M3 processor" "Low,High" group.long 0x1328++0x1F line.long 0x0 "IPC_MSG_REG0,Inter Processor Messaging 0 Register" hexmask.long 0x0 0.--31. 1. " IPC_MSG_REG0 ,Inter Processor Messaging Register" line.long 0x4 "IPC_MSG_REG1,Inter Processor Messaging 1 Register" hexmask.long 0x4 0.--31. 1. " IPC_MSG_REG1 ,Inter Processor Messaging Register" line.long 0x8 "IPC_MSG_REG2,Inter Processor Messaging 2 Register" hexmask.long 0x8 0.--31. 1. " IPC_MSG_REG2 ,Inter Processor Messaging Register" line.long 0xC "IPC_MSG_REG3,Inter Processor Messaging 3 Register" hexmask.long 0xC 0.--31. 1. " IPC_MSG_REG3 ,Inter Processor Messaging Register" line.long 0x10 "IPC_MSG_REG4,Inter Processor Messaging 4 Register" hexmask.long 0x10 0.--31. 1. " IPC_MSG_REG4 ,Inter Processor Messaging Register" line.long 0x14 "IPC_MSG_REG5,Inter Processor Messaging 5 Register" hexmask.long 0x14 0.--31. 1. " IPC_MSG_REG5 ,Inter Processor Messaging Register" line.long 0x18 "IPC_MSG_REG6,Inter Processor Messaging 6 Register" hexmask.long 0x18 0.--31. 1. " IPC_MSG_REG6 ,Inter Processor Messaging Register" line.long 0x1C "IPC_MSG_REG7,Inter Processor Messaging 7 Register" hexmask.long 0x1C 0.--31. 1. " IPC_MSG_REG7 ,Inter Processor Messaging Register" group.long 0x1404++0x0B line.long 0x0 "DDR_CMD0_IOCTRL,DDR CMD0 IO Control Register" bitfld.long 0x0 31. 20. " IO_CONFIG_GP_IO10 ,Input that selects pullup or pulldown CMD0 IO 10" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 30. 19. " IO_CONFIG_GP_IO9 ,Input that selects pullup or pulldown CMD0 IO 9" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 29. 18. " IO_CONFIG_GP_IO8 ,Input that selects pullup or pulldown CMD0 IO 8" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x0 28. 17. " IO_CONFIG_GP_IO7 ,Input that selects pullup or pulldown CMD0 IO 7" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 27. 16. " IO_CONFIG_GP_IO6 ,Input that selects pullup or pulldown CMD0 IO 6" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 26. 15. " IO_CONFIG_GP_IO5 ,Input that selects pullup or pulldown CMD0 IO 5" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x0 25. 14. " IO_CONFIG_GP_IO4 ,Input that selects pullup or pulldown CMD0 IO 4" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 24. 13. " IO_CONFIG_GP_IO3 ,Input that selects pullup or pulldown CMD0 IO 3" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 23. 12. " IO_CONFIG_GP_IO2 ,Input that selects pullup or pulldown CMD0 IO 2" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x0 22. 11. " IO_CONFIG_GP_IO1 ,Input that selects pullup or pulldown CMD0 IO 1" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 21. 10. " IO_CONFIG_GP_IO0 ,Input that selects pullup or pulldown CMD0 IO 0" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 8.--9. " IO_CONFIG_SR_CLK ,2 bit to program clock IO Pads (DDR_CK/DDR_CKN) output slew rate" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " IO_CONFIG_I_CLK ,3-bit configuration input to program clock IO pads (DDR_CK/DDR_CKN) output impedance" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " IO_CONFIG_SR ,2 bit to program addr/cmd IO Pads output slew rate" "0,1,2,3" bitfld.long 0x0 0.--2. " IO_CONFIG_I ,3-bit configuration input to program addr/cmd IO output impedance" "0,1,2,3,4,5,6,7" line.long 0x4 "DDR_CMD1_IOCTRL,DDR CMD1 IO Control Register" bitfld.long 0x4 31. 20. " IO_CONFIG_GP_IO10 ,Input that selects pullup or pulldown CMD0 IO 10" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 30. 19. " IO_CONFIG_GP_IO9 ,Input that selects pullup or pulldown CMD0 IO 9" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 29. 18. " IO_CONFIG_GP_IO8 ,Input that selects pullup or pulldown CMD0 IO 8" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x4 28. 17. " IO_CONFIG_GP_IO7 ,Input that selects pullup or pulldown CMD0 IO 7" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 27. 16. " IO_CONFIG_GP_IO6 ,Input that selects pullup or pulldown CMD0 IO 6" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 26. 15. " IO_CONFIG_GP_IO5 ,Input that selects pullup or pulldown CMD0 IO 5" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x4 25. 14. " IO_CONFIG_GP_IO4 ,Input that selects pullup or pulldown CMD0 IO 4" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 24. 13. " IO_CONFIG_GP_IO3 ,Input that selects pullup or pulldown CMD0 IO 3" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 23. 12. " IO_CONFIG_GP_IO2 ,Input that selects pullup or pulldown CMD0 IO 2" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x4 22. 11. " IO_CONFIG_GP_IO1 ,Input that selects pullup or pulldown CMD0 IO 1" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 21. 10. " IO_CONFIG_GP_IO0 ,Input that selects pullup or pulldown CMD0 IO 0" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 8.--9. " IO_CONFIG_SR_CLK ,2 bit to program clock IO Pads (DDR_CK/DDR_CKN) output slew rate" "0,1,2,3" textline " " bitfld.long 0x4 5.--7. " IO_CONFIG_I_CLK ,3-bit configuration input to program clock IO pads (DDR_CK/DDR_CKN) output impedance" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3.--4. " IO_CONFIG_SR ,2 bit to program addr/cmd IO Pads output slew rate" "0,1,2,3" bitfld.long 0x4 0.--2. " IO_CONFIG_I ,3-bit configuration input to program addr/cmd IO output impedance" "0,1,2,3,4,5,6,7" line.long 0x8 "DDR_CMD2_IOCTRL,DDR CMD2 IO Control Register" bitfld.long 0x8 31. 20. " IO_CONFIG_GP_IO10 ,Input that selects pullup or pulldown CMD0 IO 10" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x8 30. 19. " IO_CONFIG_GP_IO9 ,Input that selects pullup or pulldown CMD0 IO 9" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x8 29. 18. " IO_CONFIG_GP_IO8 ,Input that selects pullup or pulldown CMD0 IO 8" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x8 28. 17. " IO_CONFIG_GP_IO7 ,Input that selects pullup or pulldown CMD0 IO 7" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x8 27. 16. " IO_CONFIG_GP_IO6 ,Input that selects pullup or pulldown CMD0 IO 6" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x8 26. 15. " IO_CONFIG_GP_IO5 ,Input that selects pullup or pulldown CMD0 IO 5" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x8 25. 14. " IO_CONFIG_GP_IO4 ,Input that selects pullup or pulldown CMD0 IO 4" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x8 24. 13. " IO_CONFIG_GP_IO3 ,Input that selects pullup or pulldown CMD0 IO 3" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x8 23. 12. " IO_CONFIG_GP_IO2 ,Input that selects pullup or pulldown CMD0 IO 2" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x8 22. 11. " IO_CONFIG_GP_IO1 ,Input that selects pullup or pulldown CMD0 IO 1" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x8 21. 10. " IO_CONFIG_GP_IO0 ,Input that selects pullup or pulldown CMD0 IO 0" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x8 8.--9. " IO_CONFIG_SR_CLK ,2 bit to program clock IO Pads (DDR_CK/DDR_CKN) output slew rate" "0,1,2,3" textline " " bitfld.long 0x8 5.--7. " IO_CONFIG_I_CLK ,3-bit configuration input to program clock IO pads (DDR_CK/DDR_CKN) output impedance" "0,1,2,3,4,5,6,7" bitfld.long 0x8 3.--4. " IO_CONFIG_SR ,2 bit to program addr/cmd IO Pads output slew rate" "0,1,2,3" bitfld.long 0x8 0.--2. " IO_CONFIG_I ,3-bit configuration input to program addr/cmd IO output impedance" "0,1,2,3,4,5,6,7" group.long 0x1440++0x07 line.long 0x0 "DDR_DATA0_IOCTRL,DDR DATA0 IO Control Register" bitfld.long 0x0 29. 19. " IO_CONFIG_DQS ,Input that selects pullup or pulldown for DQS" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 28. 18. " IO_CONFIG_DM ,Input that selects pullup or pulldown for DM" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 27. 17. " IO_CONFIG_DQ7 ,Input that selects pullup or pulldown for DQ 7" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x0 26. 16. " IO_CONFIG_DQ6 ,Input that selects pullup or pulldown for DQ 6" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 25. 25. " IO_CONFIG_DQ5 ,Input that selects pullup or pulldown for DQ 5" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 24. 14. " IO_CONFIG_DQ4 ,Input that selects pullup or pulldown for DQ 4" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x0 23. 13. " IO_CONFIG_DQ3 ,Input that selects pullup or pulldown for DQ 3" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 22. 12. " IO_CONFIG_DQ2 ,Input that selects pullup or pulldown for DQ 2" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x0 21. 11. " IO_CONFIG_DQ1 ,Input that selects pullup or pulldown for DQ 1" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x0 20. 10. " IO_CONFIG_DQ0 ,Input that selects pullup or pulldown for DQ 0" "Disabled,Weak pullup,Weak pullup,Weak keeper" bitfld.long 0x0 8.--9. " IO_CONFIG_SR_CLK ,2 bit to program clock IO Pads (DDR_DQS/DDR_DQSn) output slew rate" "0,1,2,3" bitfld.long 0x0 5.--7. " IO_CONFIG_I_CLK ,3-bit configuration input to program clock IO pads (DDR_DQS/DDR_DQSn) output impedance" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 3.--4. " IO_CONFIG_SR ,2 bit to program data IO Pads output slew rate" "0,1,2,3" bitfld.long 0x0 0.--2. " IO_CONFIG_I ,3-bit configuration input to program data IO output impedance" "0,1,2,3,4,5,6,7" line.long 0x4 "DDR_DATA1_IOCTRL,DDR DATA1 IO Control Register" bitfld.long 0x4 29. 19. " IO_CONFIG_DQS ,Input that selects pullup or pulldown for DQS" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 28. 18. " IO_CONFIG_DM ,Input that selects pullup or pulldown for DM" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 27. 17. " IO_CONFIG_DQ7 ,Input that selects pullup or pulldown for DQ 7" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x4 26. 16. " IO_CONFIG_DQ6 ,Input that selects pullup or pulldown for DQ 6" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 25. 25. " IO_CONFIG_DQ5 ,Input that selects pullup or pulldown for DQ 5" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 24. 14. " IO_CONFIG_DQ4 ,Input that selects pullup or pulldown for DQ 4" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x4 23. 13. " IO_CONFIG_DQ3 ,Input that selects pullup or pulldown for DQ 3" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 22. 12. " IO_CONFIG_DQ2 ,Input that selects pullup or pulldown for DQ 2" "Disabled,Weak pullup,Weak pulldown,Weak keeper" bitfld.long 0x4 21. 11. " IO_CONFIG_DQ1 ,Input that selects pullup or pulldown for DQ 1" "Disabled,Weak pullup,Weak pulldown,Weak keeper" textline " " bitfld.long 0x4 20. 10. " IO_CONFIG_DQ0 ,Input that selects pullup or pulldown for DQ 0" "Disabled,Weak pullup,Weak pullup,Weak keeper" bitfld.long 0x4 8.--9. " IO_CONFIG_SR_CLK ,2 bit to program clock IO Pads (DDR_DQS/DDR_DQSn) output slew rate" "0,1,2,3" bitfld.long 0x4 5.--7. " IO_CONFIG_I_CLK ,3-bit configuration input to program clock IO pads (DDR_DQS/DDR_DQSn) output impedance" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x4 3.--4. " IO_CONFIG_SR ,2 bit to program data IO Pads output slew rate" "0,1,2,3" bitfld.long 0x4 0.--2. " IO_CONFIG_I ,3-bit configuration input to program data IO output impedance" "0,1,2,3,4,5,6,7" width 11. tree.end tree.open "EDMA (Enhanced Direct-Memory-Access)" tree "EDMA TPCC (EDMA Channel Controller Control Registers)" base ad:0x49000000 tree "Global Registers" width 10. rgroup.long 0x00++0x7 line.long 0x00 "PID,Peripheral ID Register" line.long 0x04 "CCCFG,EDMA3CC Configuration Register" sif ((cpuis("AM387*"))||(cpuis("DRA62*"))) bitfld.long 0x04 25. " MP_EXIST ,Memory Protection Existence" "Reserved,Included" bitfld.long 0x04 24. " CHMAP_EXIST ,Channel Mapping Existence" "Reserved,Included" textline " " bitfld.long 0x04 20.--21. " NUM_REGN ,Number of Shadow Regions" "Reserved,Reserved,Reserved,8 regions" bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of Queues / Number of TCs" "Reserved,Reserved,Reserved,4 EDMA3TCs/Event,?..." textline " " bitfld.long 0x04 12.--14. " NUM_PAENTRY ,Number of PaRAM Sets" "Reserved,Reserved,Reserved,Reserved,Reserved,512,?..." elif (cpuis("AM335*")) bitfld.long 0x04 25. " MP_EXIST ,Memory Protection Existence" "Reserved,Included" bitfld.long 0x04 24. " CHMAP_EXIST ,Channel Mapping Existence" "Reserved,Included" textline " " bitfld.long 0x04 20.--21. " NUM_REGN ,Number of Shadow Regions" "Reserved,Reserved,4 regions,?..." bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of Queues / Number of TCs" "Reserved,Reserved,3 EDMA3TCs/Event,?..." textline " " bitfld.long 0x04 12.--14. " NUM_PAENTRY ,Number of PaRAM Sets" "Reserved,Reserved,Reserved,Reserved,256,?..." else bitfld.long 0x04 25. " MP_EXIST ,Memory Protection Existence" "Not exist,?..." bitfld.long 0x04 24. " CHMAP_EXIST ,Channel Mapping Existence" "Not exist,?..." textline " " bitfld.long 0x04 20.--21. " NUM_REGN ,Number of Shadow Regions" "Reserved,2 regions,?..." bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of Queues / Number of TCs" "Reserved,Reserved,2,?..." textline " " bitfld.long 0x04 12.--14. " NUM_PAENTRY ,Number of PaRAM Sets" "Reserved,Reserved,Reserved,128 sets,?..." endif bitfld.long 0x04 8.--10. " NUM_INTCH ,Number of Interrupt Channels" "Reserved,Reserved,Reserved,Reserved,64 channels,?..." textline " " bitfld.long 0x04 4.--6. " NUM_QDMACH ,Number of QDMA Channels" "Reserved,Reserved,Reserved,Reserved,8 channels,?..." bitfld.long 0x04 0.--2. " NUM_DMACH ,Number of DMA Channels" "Reserved,Reserved,Reserved,Reserved,Reserved,64 channels,?..." tree "DMA Channels Mapping Registers" group.long 0x100++0xFF line.long 0x0 "DCHMAP0,DMA Channel Map 0 Register" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 0" line.long 0x4 "DCHMAP1,DMA Channel Map 1 Register" hexmask.long.word 0x4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 1" line.long 0x8 "DCHMAP2,DMA Channel Map 2 Register" hexmask.long.word 0x8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 2" line.long 0xC "DCHMAP3,DMA Channel Map 3 Register" hexmask.long.word 0xC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 3" line.long 0x10 "DCHMAP4,DMA Channel Map 4 Register" hexmask.long.word 0x10 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 4" line.long 0x14 "DCHMAP5,DMA Channel Map 5 Register" hexmask.long.word 0x14 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 5" line.long 0x18 "DCHMAP6,DMA Channel Map 6 Register" hexmask.long.word 0x18 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 6" line.long 0x1C "DCHMAP7,DMA Channel Map 7 Register" hexmask.long.word 0x1C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 7" line.long 0x20 "DCHMAP8,DMA Channel Map 8 Register" hexmask.long.word 0x20 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 8" line.long 0x24 "DCHMAP9,DMA Channel Map 9 Register" hexmask.long.word 0x24 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 9" line.long 0x28 "DCHMAP10,DMA Channel Map 10 Register" hexmask.long.word 0x28 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 10" line.long 0x2C "DCHMAP11,DMA Channel Map 11 Register" hexmask.long.word 0x2C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 11" line.long 0x30 "DCHMAP12,DMA Channel Map 12 Register" hexmask.long.word 0x30 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 12" line.long 0x34 "DCHMAP13,DMA Channel Map 13 Register" hexmask.long.word 0x34 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 13" line.long 0x38 "DCHMAP14,DMA Channel Map 14 Register" hexmask.long.word 0x38 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 14" line.long 0x3C "DCHMAP15,DMA Channel Map 15 Register" hexmask.long.word 0x3C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 15" line.long 0x40 "DCHMAP16,DMA Channel Map 16 Register" hexmask.long.word 0x40 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 16" line.long 0x44 "DCHMAP17,DMA Channel Map 17 Register" hexmask.long.word 0x44 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 17" line.long 0x48 "DCHMAP18,DMA Channel Map 18 Register" hexmask.long.word 0x48 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 18" line.long 0x4C "DCHMAP19,DMA Channel Map 19 Register" hexmask.long.word 0x4C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 19" line.long 0x50 "DCHMAP20,DMA Channel Map 20 Register" hexmask.long.word 0x50 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 20" line.long 0x54 "DCHMAP21,DMA Channel Map 21 Register" hexmask.long.word 0x54 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 21" line.long 0x58 "DCHMAP22,DMA Channel Map 22 Register" hexmask.long.word 0x58 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 22" line.long 0x5C "DCHMAP23,DMA Channel Map 23 Register" hexmask.long.word 0x5C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 23" line.long 0x60 "DCHMAP24,DMA Channel Map 24 Register" hexmask.long.word 0x60 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 24" line.long 0x64 "DCHMAP25,DMA Channel Map 25 Register" hexmask.long.word 0x64 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 25" line.long 0x68 "DCHMAP26,DMA Channel Map 26 Register" hexmask.long.word 0x68 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 26" line.long 0x6C "DCHMAP27,DMA Channel Map 27 Register" hexmask.long.word 0x6C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 27" line.long 0x70 "DCHMAP28,DMA Channel Map 28 Register" hexmask.long.word 0x70 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 28" line.long 0x74 "DCHMAP29,DMA Channel Map 29 Register" hexmask.long.word 0x74 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 29" line.long 0x78 "DCHMAP30,DMA Channel Map 30 Register" hexmask.long.word 0x78 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 30" line.long 0x7C "DCHMAP31,DMA Channel Map 31 Register" hexmask.long.word 0x7C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 31" line.long 0x80 "DCHMAP32,DMA Channel Map 32 Register" hexmask.long.word 0x80 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 32" line.long 0x84 "DCHMAP33,DMA Channel Map 33 Register" hexmask.long.word 0x84 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 33" line.long 0x88 "DCHMAP34,DMA Channel Map 34 Register" hexmask.long.word 0x88 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 34" line.long 0x8C "DCHMAP35,DMA Channel Map 35 Register" hexmask.long.word 0x8C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 35" line.long 0x90 "DCHMAP36,DMA Channel Map 36 Register" hexmask.long.word 0x90 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 36" line.long 0x94 "DCHMAP37,DMA Channel Map 37 Register" hexmask.long.word 0x94 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 37" line.long 0x98 "DCHMAP38,DMA Channel Map 38 Register" hexmask.long.word 0x98 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 38" line.long 0x9C "DCHMAP39,DMA Channel Map 39 Register" hexmask.long.word 0x9C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 39" line.long 0xA0 "DCHMAP40,DMA Channel Map 40 Register" hexmask.long.word 0xA0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 40" line.long 0xA4 "DCHMAP41,DMA Channel Map 41 Register" hexmask.long.word 0xA4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 41" line.long 0xA8 "DCHMAP42,DMA Channel Map 42 Register" hexmask.long.word 0xA8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 42" line.long 0xAC "DCHMAP43,DMA Channel Map 43 Register" hexmask.long.word 0xAC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 43" line.long 0xB0 "DCHMAP44,DMA Channel Map 44 Register" hexmask.long.word 0xB0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 44" line.long 0xB4 "DCHMAP45,DMA Channel Map 45 Register" hexmask.long.word 0xB4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 45" line.long 0xB8 "DCHMAP46,DMA Channel Map 46 Register" hexmask.long.word 0xB8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 46" line.long 0xBC "DCHMAP47,DMA Channel Map 47 Register" hexmask.long.word 0xBC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 47" line.long 0xC0 "DCHMAP48,DMA Channel Map 48 Register" hexmask.long.word 0xC0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 48" line.long 0xC4 "DCHMAP49,DMA Channel Map 49 Register" hexmask.long.word 0xC4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 49" line.long 0xC8 "DCHMAP50,DMA Channel Map 50 Register" hexmask.long.word 0xC8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 50" line.long 0xCC "DCHMAP51,DMA Channel Map 51 Register" hexmask.long.word 0xCC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 51" line.long 0xD0 "DCHMAP52,DMA Channel Map 52 Register" hexmask.long.word 0xD0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 52" line.long 0xD4 "DCHMAP53,DMA Channel Map 53 Register" hexmask.long.word 0xD4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 53" line.long 0xD8 "DCHMAP54,DMA Channel Map 54 Register" hexmask.long.word 0xD8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 54" line.long 0xDC "DCHMAP55,DMA Channel Map 55 Register" hexmask.long.word 0xDC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 55" line.long 0xE0 "DCHMAP56,DMA Channel Map 56 Register" hexmask.long.word 0xE0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 56" line.long 0xE4 "DCHMAP57,DMA Channel Map 57 Register" hexmask.long.word 0xE4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 57" line.long 0xE8 "DCHMAP58,DMA Channel Map 58 Register" hexmask.long.word 0xE8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 58" line.long 0xEC "DCHMAP59,DMA Channel Map 59 Register" hexmask.long.word 0xEC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 59" line.long 0xF0 "DCHMAP60,DMA Channel Map 60 Register" hexmask.long.word 0xF0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 60" line.long 0xF4 "DCHMAP61,DMA Channel Map 61 Register" hexmask.long.word 0xF4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 61" line.long 0xF8 "DCHMAP62,DMA Channel Map 62 Register" hexmask.long.word 0xF8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 62" line.long 0xFC "DCHMAP63,DMA Channel Map 63 Register" hexmask.long.word 0xFC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 63" tree.end tree "QDMA Channels Mapping Registers" group.long 0x200++0x1f line.long 0x0 "QCHMAP0,QDMA Channel Map 0 Register" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 0" hexmask.long.byte 0x0 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY" line.long 0x4 "QCHMAP1,QDMA Channel Map 1 Register" hexmask.long.word 0x4 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 1" hexmask.long.byte 0x4 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY" line.long 0x8 "QCHMAP2,QDMA Channel Map 2 Register" hexmask.long.word 0x8 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 2" hexmask.long.byte 0x8 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY" line.long 0xC "QCHMAP3,QDMA Channel Map 3 Register" hexmask.long.word 0xC 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 3" hexmask.long.byte 0xC 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY" line.long 0x10 "QCHMAP4,QDMA Channel Map 4 Register" hexmask.long.word 0x10 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 4" hexmask.long.byte 0x10 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY" line.long 0x14 "QCHMAP5,QDMA Channel Map 5 Register" hexmask.long.word 0x14 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 5" hexmask.long.byte 0x14 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY" line.long 0x18 "QCHMAP6,QDMA Channel Map 6 Register" hexmask.long.word 0x18 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 6" hexmask.long.byte 0x18 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY" line.long 0x1C "QCHMAP7,QDMA Channel Map 7 Register" hexmask.long.word 0x1C 5.--13. 1. " PAENTRY ,PaRAM Set Number for DMA Channel 7" hexmask.long.byte 0x1C 2.--4. 1. " TRWORD ,Specific Trigger Word of the PaRAM Set Defined by PAENTRY" tree.end width 10. tree "DMA Queue Registers" group.long 0x240++0x1f line.long 0x00 "DMAQNUM0,DMA Queue Number Register 0" bitfld.long 0x00 28.--30. " E7 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 24.--26. " E6 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 20.--22. " E5 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 16.--18. " E4 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." textline " " bitfld.long 0x00 12.--14. " E3 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 8.--10. " E2 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 4.--6. " E1 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 0.--2. " E0 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." line.long 0x04 "DMAQNUM1,DMA Queue Number Register 1" bitfld.long 0x04 28.--30. " E15 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x04 24.--26. " E14 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x04 20.--22. " E13 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x04 16.--18. " E12 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." textline " " bitfld.long 0x04 12.--14. " E11 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x04 8.--10. " E10 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x04 4.--6. " E9 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x04 0.--2. " E8 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." line.long 0x08 "DMAQNUM2,DMA Queue Number Register 2" bitfld.long 0x08 28.--30. " E23 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x08 24.--26. " E22 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x08 20.--22. " E21 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x08 16.--18. " E20 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." textline " " bitfld.long 0x08 12.--14. " E19 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x08 8.--10. " E18 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x08 4.--6. " E17 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x08 0.--2. " E16 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." line.long 0x0c "DMAQNUM3,DMA Queue Number Register 3" bitfld.long 0x0c 28.--30. " E31 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x0c 24.--26. " E30 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x0c 20.--22. " E29 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x0c 16.--18. " E28 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." textline " " bitfld.long 0x0c 12.--14. " E27 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x0c 8.--10. " E26 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x0c 4.--6. " E25 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x0c 0.--2. " E24 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." line.long 0x10 "DMAQNUM4,DMA Queue Number Register 4" bitfld.long 0x10 28.--30. " E39 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x10 24.--26. " E38 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x10 20.--22. " E37 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x10 16.--18. " E36 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." textline " " bitfld.long 0x10 12.--14. " E35 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x10 8.--10. " E34 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x10 4.--6. " E33 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x10 0.--2. " E32 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." line.long 0x14 "DMAQNUM5,DMA Queue Number Register 5" bitfld.long 0x14 28.--30. " E47 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x14 24.--26. " E46 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x14 20.--22. " E45 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x14 16.--18. " E44 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." textline " " bitfld.long 0x14 12.--14. " E43 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x14 8.--10. " E42 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x14 4.--6. " E41 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x14 0.--2. " E40 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." line.long 0x18 "DMAQNUM6,DMA Queue Number Register 6" bitfld.long 0x18 28.--30. " E55 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x18 24.--26. " E54 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x18 20.--22. " E53 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x18 16.--18. " E52 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." textline " " bitfld.long 0x18 12.--14. " E51 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x18 8.--10. " E50 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x18 4.--6. " E49 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x18 0.--2. " E48 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." line.long 0x1c "DMAQNUM7,DMA Queue Number Register 7" bitfld.long 0x1c 28.--30. " E63 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x1c 24.--26. " E62 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x1c 20.--22. " E61 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x1c 16.--18. " E60 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." textline " " bitfld.long 0x1c 12.--14. " E59 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x1c 8.--10. " E58 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x1c 4.--6. " E57 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x1c 0.--2. " E56 ,DMA Queue Number" "Q0,Q1,Q2,Q3,?..." group.long 0x260++0x3 line.long 0x00 "QDMAQNUM,QDMA Channel Queue Number Register" sif (cpuis("DRA62*")) bitfld.long 0x00 28.--30. " E4 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 24.--26. " E6 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 20.--22. " E5 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 16.--18. " E4 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..." endif bitfld.long 0x00 12.--14. " E3 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 8.--10. " E2 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 4.--6. " E1 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..." bitfld.long 0x00 0.--2. " E0 ,QDMA Queue Number" "Q0,Q1,Q2,Q3,?..." group.long 0x284++0x3 line.long 0x00 "QUEPRI,Queue Priority Register" bitfld.long 0x00 12.--14. " PRIQ3 ,Priority Level for Queue 3" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRIQ2 ,Priority Level for Queue 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRIQ1 ,Priority Level for Queue 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRIQ0 ,Priority Level for Queue 0" "0,1,2,3,4,5,6,7" tree.end tree.end tree "Error Registers" width 10. rgroup.long 0x300++0x7 line.long 0x00 "EMR,Event Missed Register" bitfld.long 0x00 31. " E31 ,Channel 31 event missed" "Not missed,Missed" bitfld.long 0x00 30. " E30 ,Channel 30 event missed" "Not missed,Missed" bitfld.long 0x00 29. " E29 ,Channel 29 event missed" "Not missed,Missed" bitfld.long 0x00 28. " E28 ,Channel 28 event missed" "Not missed,Missed" textline " " bitfld.long 0x00 27. " E27 ,Channel 27 event missed" "Not missed,Missed" bitfld.long 0x00 26. " E26 ,Channel 26 event missed" "Not missed,Missed" bitfld.long 0x00 25. " E25 ,Channel 25 event missed" "Not missed,Missed" bitfld.long 0x00 24. " E24 ,Channel 24 event missed" "Not missed,Missed" textline " " bitfld.long 0x00 23. " E23 ,Channel 23 event missed" "Not missed,Missed" bitfld.long 0x00 22. " E22 ,Channel 22 event missed" "Not missed,Missed" bitfld.long 0x00 21. " E21 ,Channel 21 event missed" "Not missed,Missed" bitfld.long 0x00 20. " E20 ,Channel 20 event missed" "Not missed,Missed" textline " " bitfld.long 0x00 19. " E19 ,Channel 19 event missed" "Not missed,Missed" bitfld.long 0x00 18. " E18 ,Channel 18 event missed" "Not missed,Missed" bitfld.long 0x00 17. " E17 ,Channel 17 event missed" "Not missed,Missed" bitfld.long 0x00 16. " E16 ,Channel 16 event missed" "Not missed,Missed" textline " " bitfld.long 0x00 15. " E15 ,Channel 15 event missed" "Not missed,Missed" bitfld.long 0x00 14. " E14 ,Channel 14 event missed" "Not missed,Missed" bitfld.long 0x00 13. " E13 ,Channel 13 event missed" "Not missed,Missed" bitfld.long 0x00 12. " E12 ,Channel 12 event missed" "Not missed,Missed" textline " " bitfld.long 0x00 11. " E11 ,Channel 11 event missed" "Not missed,Missed" bitfld.long 0x00 10. " E10 ,Channel 10 event missed" "Not missed,Missed" bitfld.long 0x00 9. " E9 ,Channel 9 event missed" "Not missed,Missed" bitfld.long 0x00 8. " E8 ,Channel 8 event missed" "Not missed,Missed" textline " " bitfld.long 0x00 7. " E7 ,Channel 7 event missed" "Not missed,Missed" bitfld.long 0x00 6. " E6 ,Channel 6 event missed" "Not missed,Missed" bitfld.long 0x00 5. " E5 ,Channel 5 event missed" "Not missed,Missed" bitfld.long 0x00 4. " E4 ,Channel 4 event missed" "Not missed,Missed" textline " " bitfld.long 0x00 3. " E3 ,Channel 3 event missed" "Not missed,Missed" bitfld.long 0x00 2. " E2 ,Channel 2 event missed" "Not missed,Missed" bitfld.long 0x00 1. " E1 ,Channel 1 event missed" "Not missed,Missed" bitfld.long 0x00 0. " E0 ,Channel 0 event missed" "Not missed,Missed" line.long 0x04 "EMRH,Event Missed Register High" bitfld.long 0x04 31. " E63 ,Channel 63 event missed" "Not missed,Missed" bitfld.long 0x04 30. " E62 ,Channel 62 event missed" "Not missed,Missed" bitfld.long 0x04 29. " E61 ,Channel 61 event missed" "Not missed,Missed" bitfld.long 0x04 28. " E60 ,Channel 60 event missed" "Not missed,Missed" textline " " bitfld.long 0x04 27. " E59 ,Channel 59 event missed" "Not missed,Missed" bitfld.long 0x04 26. " E58 ,Channel 58 event missed" "Not missed,Missed" bitfld.long 0x04 25. " E57 ,Channel 57 event missed" "Not missed,Missed" bitfld.long 0x04 24. " E56 ,Channel 56 event missed" "Not missed,Missed" textline " " bitfld.long 0x04 23. " E55 ,Channel 55 event missed" "Not missed,Missed" bitfld.long 0x04 22. " E54 ,Channel 54 event missed" "Not missed,Missed" bitfld.long 0x04 21. " E53 ,Channel 53 event missed" "Not missed,Missed" bitfld.long 0x04 20. " E52 ,Channel 52 event missed" "Not missed,Missed" textline " " bitfld.long 0x04 19. " E51 ,Channel 51 event missed" "Not missed,Missed" bitfld.long 0x04 18. " E50 ,Channel 50 event missed" "Not missed,Missed" bitfld.long 0x04 17. " E49 ,Channel 49 event missed" "Not missed,Missed" bitfld.long 0x04 16. " E48 ,Channel 48 event missed" "Not missed,Missed" textline " " bitfld.long 0x04 15. " E47 ,Channel 47 event missed" "Not missed,Missed" bitfld.long 0x04 14. " E46 ,Channel 46 event missed" "Not missed,Missed" bitfld.long 0x04 13. " E45 ,Channel 45 event missed" "Not missed,Missed" bitfld.long 0x04 12. " E44 ,Channel 44 event missed" "Not missed,Missed" textline " " bitfld.long 0x04 11. " E43 ,Channel 43 event missed" "Not missed,Missed" bitfld.long 0x04 10. " E42 ,Channel 42 event missed" "Not missed,Missed" bitfld.long 0x04 9. " E41 ,Channel 41 event missed" "Not missed,Missed" bitfld.long 0x04 8. " E40 ,Channel 40 event missed" "Not missed,Missed" textline " " bitfld.long 0x04 7. " E39 ,Channel 39 event missed" "Not missed,Missed" bitfld.long 0x04 6. " E38 ,Channel 38 event missed" "Not missed,Missed" bitfld.long 0x04 5. " E37 ,Channel 37 event missed" "Not missed,Missed" bitfld.long 0x04 4. " E36 ,Channel 36 event missed" "Not missed,Missed" textline " " bitfld.long 0x04 3. " E35 ,Channel 35 event missed" "Not missed,Missed" bitfld.long 0x04 2. " E34 ,Channel 34 event missed" "Not missed,Missed" bitfld.long 0x04 1. " E33 ,Channel 33 event missed" "Not missed,Missed" bitfld.long 0x04 0. " E32 ,Channel 32 event missed" "Not missed,Missed" wgroup.long 0x308++0x7 line.long 0x00 "EMCR,Event Missed Clear Register" bitfld.long 0x00 31. " E31 ,Event missed 31 clear" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Event missed 30 clear" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Event missed 29 clear" "No effect,Clear" bitfld.long 0x00 28. " E28 ,Event missed 28 clear" "No effect,Clear" textline " " bitfld.long 0x00 27. " E27 ,Event missed 27 clear" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Event missed 26 clear" "No effect,Clear" bitfld.long 0x00 25. " E25 ,Event missed 25 clear" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Event missed 24 clear" "No effect,Clear" textline " " bitfld.long 0x00 23. " E23 ,Event missed 23 clear" "No effect,Clear" bitfld.long 0x00 22. " E22 ,Event missed 22 clear" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Event missed 21 clear" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Event missed 20 clear" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Event missed 19 clear" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Event missed 18 clear" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Event missed 17 clear" "No effect,Clear" bitfld.long 0x00 16. " E16 ,Event missed 16 clear" "No effect,Clear" textline " " bitfld.long 0x00 15. " E15 ,Event missed 15 clear" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Event missed 14 clear" "No effect,Clear" bitfld.long 0x00 13. " E13 ,Event missed 13 clear" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Event missed 12 clear" "No effect,Clear" textline " " bitfld.long 0x00 11. " E11 ,Event missed 11 clear" "No effect,Clear" bitfld.long 0x00 10. " E10 ,Event missed 10 clear" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Event missed 9 clear" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Event missed 8 clear" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Event missed 7 clear" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Event missed 6 clear" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Event missed 5 clear" "No effect,Clear" bitfld.long 0x00 4. " E4 ,Event missed 4 clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,Event missed 3 clear" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Event missed 2 clear" "No effect,Clear" bitfld.long 0x00 1. " E1 ,Event missed 1 clear" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Event missed 0 clear" "No effect,Clear" line.long 0x04 "EMCRH,Event Missed Clear Register High" bitfld.long 0x04 31. " E63 ,Event missed 63 clear" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Event missed 62 clear" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Event missed 61 clear" "No effect,Clear" bitfld.long 0x04 28. " E60 ,Event missed 60 clear" "No effect,Clear" textline " " bitfld.long 0x04 27. " E59 ,Event missed 59 clear" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Event missed 58 clear" "No effect,Clear" bitfld.long 0x04 25. " E57 ,Event missed 57 clear" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Event missed 56 clear" "No effect,Clear" textline " " bitfld.long 0x04 23. " E55 ,Event missed 55 clear" "No effect,Clear" bitfld.long 0x04 22. " E54 ,Event missed 54 clear" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Event missed 53 clear" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Event missed 52 clear" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Event missed 51 clear" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Event missed 50 clear" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Event missed 49 clear" "No effect,Clear" bitfld.long 0x04 16. " E48 ,Event missed 48 clear" "No effect,Clear" textline " " bitfld.long 0x04 15. " E47 ,Event missed 47 clear" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Event missed 46 clear" "No effect,Clear" bitfld.long 0x04 13. " E45 ,Event missed 45 clear" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Event missed 44 clear" "No effect,Clear" textline " " bitfld.long 0x04 11. " E43 ,Event missed 43 clear" "No effect,Clear" bitfld.long 0x04 10. " E42 ,Event missed 42 clear" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Event missed 41 clear" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Event missed 40 clear" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Event missed 39 clear" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Event missed 38 clear" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Event missed 37 clear" "No effect,Clear" bitfld.long 0x04 4. " E36 ,Event missed 36 clear" "No effect,Clear" textline " " bitfld.long 0x04 3. " E35 ,Event missed 35 clear" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Event missed 34 clear" "No effect,Clear" bitfld.long 0x04 1. " E33 ,Event missed 33 clear" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Event missed 32 clear" "No effect,Clear" rgroup.long 0x310++0x3 line.long 0x00 "QEMR,QDMA Event Missed Register" bitfld.long 0x00 7. " E7 ,Channel 7 QDMA event missed" "Not missed,Missed" bitfld.long 0x00 6. " E6 ,Channel 6 QDMA event missed" "Not missed,Missed" bitfld.long 0x00 5. " E5 ,Channel 5 QDMA event missed" "Not missed,Missed" bitfld.long 0x00 4. " E4 ,Channel 4 QDMA event missed" "Not missed,Missed" textline " " bitfld.long 0x00 3. " E3 ,Channel 3 QDMA event missed" "Not missed,Missed" bitfld.long 0x00 2. " E2 ,Channel 2 QDMA event missed" "Not missed,Missed" bitfld.long 0x00 1. " E1 ,Channel 1 QDMA event missed" "Not missed,Missed" bitfld.long 0x00 0. " E0 ,Channel 0 QDMA event missed" "Not missed,Missed" wgroup.long 0x314++0x3 line.long 0x00 "QEMCR,QDMA Event Missed Clear Register" bitfld.long 0x00 7. " E7 ,QDMA event missed 7 clear" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA event missed 6 clear" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA event missed 5 clear" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA event missed 4 clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA event missed 3 clear" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA event missed 2 clear" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA event missed 1 clear" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA event missed 0 clear" "No effect,Clear" rgroup.long 0x318++0x3 line.long 0x00 "CCERR,EDMA3CC Error Register" bitfld.long 0x00 16. " TCCERR ,Transfer completion code error" "Not reached,Reached" textline " " bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error for queue 3" "Not exceeded,Exceeded" textline " " bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error for queue 2" "Not exceeded,Exceeded" textline " " bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error for queue 1" "Not exceeded,Exceeded" textline " " bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error for queue 0" "Not exceeded,Exceeded" wgroup.long 0x31c++0x3 line.long 0x00 "CCERRCLR,EDMA3CC Error Clear Register" bitfld.long 0x00 16. " TCCERR ,Transfer completion code error clear" "No effect,Clear" textline " " bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error clear for queue 3" "No effect,Clear" textline " " bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error clear for queue 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error clear for queue 1" "No effect,Clear" textline " " bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error clear for queue 0" "No effect,Clear" wgroup.long 0x320++0x3 line.long 0x00 "EEVAL,Error Evaluation Register" bitfld.long 0x00 0. " EVAL ,Error interrupt evaluate" "No effect,Evaluate" tree.end tree "Region Access Enable Registers" width 8. group.long 0x340++0x7 line.long 0x00 "DRAE0,DMA Region Access Enable Register for Region 0" bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 0" "Not allowed,Allowed" bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 0" "Not allowed,Allowed" bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 0" "Not allowed,Allowed" bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 0" "Not allowed,Allowed" bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 0" "Not allowed,Allowed" bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 0" "Not allowed,Allowed" bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 0" "Not allowed,Allowed" bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 0" "Not allowed,Allowed" bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 0" "Not allowed,Allowed" bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 0" "Not allowed,Allowed" bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 0" "Not allowed,Allowed" bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 0" "Not allowed,Allowed" bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 0" "Not allowed,Allowed" bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 0" "Not allowed,Allowed" bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 0" "Not allowed,Allowed" bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 0" "Not allowed,Allowed" bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 0" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 0" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 0" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 0" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 0" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 0" "Not allowed,Allowed" line.long 0x04 "DRAEH0,DMA Region Access Enabled Register High for Region 0" bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 0" "Not allowed,Allowed" bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 0" "Not allowed,Allowed" bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 0" "Not allowed,Allowed" bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 0" "Not allowed,Allowed" bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 0" "Not allowed,Allowed" bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 0" "Not allowed,Allowed" bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 0" "Not allowed,Allowed" bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 0" "Not allowed,Allowed" bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 0" "Not allowed,Allowed" bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 0" "Not allowed,Allowed" bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 0" "Not allowed,Allowed" bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 0" "Not allowed,Allowed" bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 0" "Not allowed,Allowed" bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 0" "Not allowed,Allowed" bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 0" "Not allowed,Allowed" bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 0" "Not allowed,Allowed" bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 0" "Not allowed,Allowed" bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 0" "Not allowed,Allowed" bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 0" "Not allowed,Allowed" bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 0" "Not allowed,Allowed" bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 0" "Not allowed,Allowed" bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 0" "Not allowed,Allowed" group.long 0x348++0x7 line.long 0x00 "DRAE1,DMA Region Access Enable Register for Region 1" bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 1" "Not allowed,Allowed" bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 1" "Not allowed,Allowed" bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 1" "Not allowed,Allowed" bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 1" "Not allowed,Allowed" bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 1" "Not allowed,Allowed" bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 1" "Not allowed,Allowed" bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 1" "Not allowed,Allowed" bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 1" "Not allowed,Allowed" bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 1" "Not allowed,Allowed" bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 1" "Not allowed,Allowed" bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 1" "Not allowed,Allowed" bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 1" "Not allowed,Allowed" bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 1" "Not allowed,Allowed" bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 1" "Not allowed,Allowed" bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 1" "Not allowed,Allowed" bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 1" "Not allowed,Allowed" bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 1" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 1" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 1" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 1" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 1" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 1" "Not allowed,Allowed" line.long 0x04 "DRAEH1,DMA Region Access Enabled Register High for Region 1" bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 1" "Not allowed,Allowed" bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 1" "Not allowed,Allowed" bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 1" "Not allowed,Allowed" bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 1" "Not allowed,Allowed" bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 1" "Not allowed,Allowed" bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 1" "Not allowed,Allowed" bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 1" "Not allowed,Allowed" bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 1" "Not allowed,Allowed" bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 1" "Not allowed,Allowed" bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 1" "Not allowed,Allowed" bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 1" "Not allowed,Allowed" bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 1" "Not allowed,Allowed" bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 1" "Not allowed,Allowed" bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 1" "Not allowed,Allowed" bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 1" "Not allowed,Allowed" bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 1" "Not allowed,Allowed" bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 1" "Not allowed,Allowed" bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 1" "Not allowed,Allowed" bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 1" "Not allowed,Allowed" bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 1" "Not allowed,Allowed" bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 1" "Not allowed,Allowed" bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 1" "Not allowed,Allowed" group.long 0x350++0x7 line.long 0x00 "DRAE2,DMA Region Access Enable Register for Region 2" bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 2" "Not allowed,Allowed" bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 2" "Not allowed,Allowed" bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 2" "Not allowed,Allowed" bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 2" "Not allowed,Allowed" bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 2" "Not allowed,Allowed" bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 2" "Not allowed,Allowed" bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 2" "Not allowed,Allowed" bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 2" "Not allowed,Allowed" bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 2" "Not allowed,Allowed" bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 2" "Not allowed,Allowed" bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 2" "Not allowed,Allowed" bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 2" "Not allowed,Allowed" bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 2" "Not allowed,Allowed" bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 2" "Not allowed,Allowed" bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 2" "Not allowed,Allowed" bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 2" "Not allowed,Allowed" bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 2" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 2" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 2" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 2" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 2" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 2" "Not allowed,Allowed" line.long 0x04 "DRAEH2,DMA Region Access Enabled Register High for Region 2" bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 2" "Not allowed,Allowed" bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 2" "Not allowed,Allowed" bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 2" "Not allowed,Allowed" bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 2" "Not allowed,Allowed" bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 2" "Not allowed,Allowed" bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 2" "Not allowed,Allowed" bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 2" "Not allowed,Allowed" bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 2" "Not allowed,Allowed" bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 2" "Not allowed,Allowed" bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 2" "Not allowed,Allowed" bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 2" "Not allowed,Allowed" bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 2" "Not allowed,Allowed" bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 2" "Not allowed,Allowed" bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 2" "Not allowed,Allowed" bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 2" "Not allowed,Allowed" bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 2" "Not allowed,Allowed" bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 2" "Not allowed,Allowed" bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 2" "Not allowed,Allowed" bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 2" "Not allowed,Allowed" bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 2" "Not allowed,Allowed" bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 2" "Not allowed,Allowed" bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 2" "Not allowed,Allowed" group.long 0x358++0x7 line.long 0x00 "DRAE3,DMA Region Access Enable Register for Region 3" bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 3" "Not allowed,Allowed" bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 3" "Not allowed,Allowed" bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 3" "Not allowed,Allowed" bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 3" "Not allowed,Allowed" bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 3" "Not allowed,Allowed" bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 3" "Not allowed,Allowed" bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 3" "Not allowed,Allowed" bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 3" "Not allowed,Allowed" bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 3" "Not allowed,Allowed" bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 3" "Not allowed,Allowed" bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 3" "Not allowed,Allowed" bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 3" "Not allowed,Allowed" bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 3" "Not allowed,Allowed" bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 3" "Not allowed,Allowed" bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 3" "Not allowed,Allowed" bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 3" "Not allowed,Allowed" bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 3" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 3" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 3" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 3" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 3" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 3" "Not allowed,Allowed" line.long 0x04 "DRAEH3,DMA Region Access Enabled Register High for Region 3" bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 3" "Not allowed,Allowed" bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 3" "Not allowed,Allowed" bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 3" "Not allowed,Allowed" bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 3" "Not allowed,Allowed" bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 3" "Not allowed,Allowed" bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 3" "Not allowed,Allowed" bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 3" "Not allowed,Allowed" bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 3" "Not allowed,Allowed" bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 3" "Not allowed,Allowed" bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 3" "Not allowed,Allowed" bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 3" "Not allowed,Allowed" bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 3" "Not allowed,Allowed" bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 3" "Not allowed,Allowed" bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 3" "Not allowed,Allowed" bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 3" "Not allowed,Allowed" bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 3" "Not allowed,Allowed" bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 3" "Not allowed,Allowed" bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 3" "Not allowed,Allowed" bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 3" "Not allowed,Allowed" bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 3" "Not allowed,Allowed" bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 3" "Not allowed,Allowed" bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 3" "Not allowed,Allowed" group.long 0x360++0x7 line.long 0x00 "DRAE4,DMA Region Access Enable Register for Region 4" bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 4" "Not allowed,Allowed" bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 4" "Not allowed,Allowed" bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 4" "Not allowed,Allowed" bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 4" "Not allowed,Allowed" bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 4" "Not allowed,Allowed" bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 4" "Not allowed,Allowed" bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 4" "Not allowed,Allowed" bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 4" "Not allowed,Allowed" bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 4" "Not allowed,Allowed" bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 4" "Not allowed,Allowed" bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 4" "Not allowed,Allowed" bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 4" "Not allowed,Allowed" bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 4" "Not allowed,Allowed" bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 4" "Not allowed,Allowed" bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 4" "Not allowed,Allowed" bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 4" "Not allowed,Allowed" bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 4" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 4" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 4" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 4" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 4" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 4" "Not allowed,Allowed" line.long 0x04 "DRAEH4,DMA Region Access Enabled Register High for Region 4" bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 4" "Not allowed,Allowed" bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 4" "Not allowed,Allowed" bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 4" "Not allowed,Allowed" bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 4" "Not allowed,Allowed" bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 4" "Not allowed,Allowed" bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 4" "Not allowed,Allowed" bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 4" "Not allowed,Allowed" bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 4" "Not allowed,Allowed" bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 4" "Not allowed,Allowed" bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 4" "Not allowed,Allowed" bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 4" "Not allowed,Allowed" bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 4" "Not allowed,Allowed" bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 4" "Not allowed,Allowed" bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 4" "Not allowed,Allowed" bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 4" "Not allowed,Allowed" bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 4" "Not allowed,Allowed" bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 4" "Not allowed,Allowed" bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 4" "Not allowed,Allowed" bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 4" "Not allowed,Allowed" bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 4" "Not allowed,Allowed" bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 4" "Not allowed,Allowed" bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 4" "Not allowed,Allowed" group.long 0x368++0x7 line.long 0x00 "DRAE5,DMA Region Access Enable Register for Region 5" bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 5" "Not allowed,Allowed" bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 5" "Not allowed,Allowed" bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 5" "Not allowed,Allowed" bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 5" "Not allowed,Allowed" bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 5" "Not allowed,Allowed" bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 5" "Not allowed,Allowed" bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 5" "Not allowed,Allowed" bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 5" "Not allowed,Allowed" bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 5" "Not allowed,Allowed" bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 5" "Not allowed,Allowed" bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 5" "Not allowed,Allowed" bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 5" "Not allowed,Allowed" bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 5" "Not allowed,Allowed" bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 5" "Not allowed,Allowed" bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 5" "Not allowed,Allowed" bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 5" "Not allowed,Allowed" bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 5" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 5" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 5" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 5" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 5" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 5" "Not allowed,Allowed" line.long 0x04 "DRAEH5,DMA Region Access Enabled Register High for Region 5" bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 5" "Not allowed,Allowed" bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 5" "Not allowed,Allowed" bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 5" "Not allowed,Allowed" bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 5" "Not allowed,Allowed" bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 5" "Not allowed,Allowed" bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 5" "Not allowed,Allowed" bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 5" "Not allowed,Allowed" bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 5" "Not allowed,Allowed" bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 5" "Not allowed,Allowed" bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 5" "Not allowed,Allowed" bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 5" "Not allowed,Allowed" bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 5" "Not allowed,Allowed" bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 5" "Not allowed,Allowed" bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 5" "Not allowed,Allowed" bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 5" "Not allowed,Allowed" bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 5" "Not allowed,Allowed" bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 5" "Not allowed,Allowed" bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 5" "Not allowed,Allowed" bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 5" "Not allowed,Allowed" bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 5" "Not allowed,Allowed" bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 5" "Not allowed,Allowed" bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 5" "Not allowed,Allowed" group.long 0x370++0x7 line.long 0x00 "DRAE6,DMA Region Access Enable Register for Region 6" bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 6" "Not allowed,Allowed" bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 6" "Not allowed,Allowed" bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 6" "Not allowed,Allowed" bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 6" "Not allowed,Allowed" bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 6" "Not allowed,Allowed" bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 6" "Not allowed,Allowed" bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 6" "Not allowed,Allowed" bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 6" "Not allowed,Allowed" bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 6" "Not allowed,Allowed" bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 6" "Not allowed,Allowed" bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 6" "Not allowed,Allowed" bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 6" "Not allowed,Allowed" bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 6" "Not allowed,Allowed" bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 6" "Not allowed,Allowed" bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 6" "Not allowed,Allowed" bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 6" "Not allowed,Allowed" bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 6" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 6" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 6" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 6" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 6" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 6" "Not allowed,Allowed" line.long 0x04 "DRAEH6,DMA Region Access Enabled Register High for Region 6" bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 6" "Not allowed,Allowed" bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 6" "Not allowed,Allowed" bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 6" "Not allowed,Allowed" bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 6" "Not allowed,Allowed" bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 6" "Not allowed,Allowed" bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 6" "Not allowed,Allowed" bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 6" "Not allowed,Allowed" bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 6" "Not allowed,Allowed" bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 6" "Not allowed,Allowed" bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 6" "Not allowed,Allowed" bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 6" "Not allowed,Allowed" bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 6" "Not allowed,Allowed" bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 6" "Not allowed,Allowed" bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 6" "Not allowed,Allowed" bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 6" "Not allowed,Allowed" bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 6" "Not allowed,Allowed" bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 6" "Not allowed,Allowed" bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 6" "Not allowed,Allowed" bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 6" "Not allowed,Allowed" bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 6" "Not allowed,Allowed" bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 6" "Not allowed,Allowed" bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 6" "Not allowed,Allowed" group.long 0x378++0x7 line.long 0x00 "DRAE7,DMA Region Access Enable Register for Region 7" bitfld.long 0x00 31. " E31 ,DMA region access enable for bit channel 31 in region 7" "Not allowed,Allowed" bitfld.long 0x00 30. " E30 ,DMA region access enable for bit channel 30 in region 7" "Not allowed,Allowed" bitfld.long 0x00 29. " E29 ,DMA region access enable for bit channel 29 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 28. " E28 ,DMA region access enable for bit channel 28 in region 7" "Not allowed,Allowed" bitfld.long 0x00 27. " E27 ,DMA region access enable for bit channel 27 in region 7" "Not allowed,Allowed" bitfld.long 0x00 26. " E26 ,DMA region access enable for bit channel 26 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 25. " E25 ,DMA region access enable for bit channel 25 in region 7" "Not allowed,Allowed" bitfld.long 0x00 24. " E24 ,DMA region access enable for bit channel 24 in region 7" "Not allowed,Allowed" bitfld.long 0x00 23. " E23 ,DMA region access enable for bit channel 23 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 22. " E22 ,DMA region access enable for bit channel 22 in region 7" "Not allowed,Allowed" bitfld.long 0x00 21. " E21 ,DMA region access enable for bit channel 21 in region 7" "Not allowed,Allowed" bitfld.long 0x00 20. " E20 ,DMA region access enable for bit channel 20 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 19. " E19 ,DMA region access enable for bit channel 19 in region 7" "Not allowed,Allowed" bitfld.long 0x00 18. " E18 ,DMA region access enable for bit channel 18 in region 7" "Not allowed,Allowed" bitfld.long 0x00 17. " E17 ,DMA region access enable for bit channel 17 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " E16 ,DMA region access enable for bit channel 16 in region 7" "Not allowed,Allowed" bitfld.long 0x00 15. " E15 ,DMA region access enable for bit channel 15 in region 7" "Not allowed,Allowed" bitfld.long 0x00 14. " E14 ,DMA region access enable for bit channel 14 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 13. " E13 ,DMA region access enable for bit channel 13 in region 7" "Not allowed,Allowed" bitfld.long 0x00 12. " E12 ,DMA region access enable for bit channel 12 in region 7" "Not allowed,Allowed" bitfld.long 0x00 11. " E11 ,DMA region access enable for bit channel 11 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 10. " E10 ,DMA region access enable for bit channel 10 in region 7" "Not allowed,Allowed" bitfld.long 0x00 9. " E9 ,DMA region access enable for bit channel 9 in region 7" "Not allowed,Allowed" bitfld.long 0x00 8. " E8 ,DMA region access enable for bit channel 8 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 7. " E7 ,DMA region access enable for bit channel 7 in region 7" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,DMA region access enable for bit channel 6 in region 7" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,DMA region access enable for bit channel 5 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,DMA region access enable for bit channel 4 in region 7" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,DMA region access enable for bit channel 3 in region 7" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,DMA region access enable for bit channel 2 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,DMA region access enable for bit channel 1 in region 7" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,DMA region access enable for bit channel 0 in region 7" "Not allowed,Allowed" line.long 0x04 "DRAEH7,DMA Region Access Enabled Register High for Region 7" bitfld.long 0x04 31. " E63 ,DMA region access enable for bit channel 63 in region 7" "Not allowed,Allowed" bitfld.long 0x04 30. " E62 ,DMA region access enable for bit channel 62 in region 7" "Not allowed,Allowed" bitfld.long 0x04 29. " E61 ,DMA region access enable for bit channel 61 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 28. " E60 ,DMA region access enable for bit channel 60 in region 7" "Not allowed,Allowed" bitfld.long 0x04 27. " E59 ,DMA region access enable for bit channel 59 in region 7" "Not allowed,Allowed" bitfld.long 0x04 26. " E58 ,DMA region access enable for bit channel 58 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 25. " E57 ,DMA region access enable for bit channel 57 in region 7" "Not allowed,Allowed" bitfld.long 0x04 24. " E56 ,DMA region access enable for bit channel 56 in region 7" "Not allowed,Allowed" bitfld.long 0x04 23. " E55 ,DMA region access enable for bit channel 55 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 22. " E54 ,DMA region access enable for bit channel 54 in region 7" "Not allowed,Allowed" bitfld.long 0x04 21. " E53 ,DMA region access enable for bit channel 53 in region 7" "Not allowed,Allowed" bitfld.long 0x04 20. " E52 ,DMA region access enable for bit channel 52 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 19. " E51 ,DMA region access enable for bit channel 51 in region 7" "Not allowed,Allowed" bitfld.long 0x04 18. " E50 ,DMA region access enable for bit channel 50 in region 7" "Not allowed,Allowed" bitfld.long 0x04 17. " E49 ,DMA region access enable for bit channel 49 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 16. " E48 ,DMA region access enable for bit channel 48 in region 7" "Not allowed,Allowed" bitfld.long 0x04 15. " E47 ,DMA region access enable for bit channel 47 in region 7" "Not allowed,Allowed" bitfld.long 0x04 14. " E46 ,DMA region access enable for bit channel 46 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 13. " E45 ,DMA region access enable for bit channel 45 in region 7" "Not allowed,Allowed" bitfld.long 0x04 12. " E44 ,DMA region access enable for bit channel 44 in region 7" "Not allowed,Allowed" bitfld.long 0x04 11. " E43 ,DMA region access enable for bit channel 43 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 10. " E42 ,DMA region access enable for bit channel 42 in region 7" "Not allowed,Allowed" bitfld.long 0x04 9. " E41 ,DMA region access enable for bit channel 41 in region 7" "Not allowed,Allowed" bitfld.long 0x04 8. " E40 ,DMA region access enable for bit channel 40 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 7. " E39 ,DMA region access enable for bit channel 39 in region 7" "Not allowed,Allowed" bitfld.long 0x04 6. " E38 ,DMA region access enable for bit channel 38 in region 7" "Not allowed,Allowed" bitfld.long 0x04 5. " E37 ,DMA region access enable for bit channel 37 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 4. " E36 ,DMA region access enable for bit channel 36 in region 7" "Not allowed,Allowed" bitfld.long 0x04 3. " E35 ,DMA region access enable for bit channel 35 in region 7" "Not allowed,Allowed" bitfld.long 0x04 2. " E34 ,DMA region access enable for bit channel 34 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x04 1. " E33 ,DMA region access enable for bit channel 33 in region 7" "Not allowed,Allowed" bitfld.long 0x04 0. " E32 ,DMA region access enable for bit channel 32 in region 7" "Not allowed,Allowed" group.long 0x380++0x3 line.long 0x00 "QRAE0,QDMA Region Access Enable Register for Region 0" bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 0" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 0" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 0" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 0" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 0" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 0" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 0" "Not allowed,Allowed" group.long 0x384++0x3 line.long 0x00 "QRAE1,QDMA Region Access Enable Register for Region 1" bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 1" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 1" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 1" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 1" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 1" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 1" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 1" "Not allowed,Allowed" group.long 0x388++0x3 line.long 0x00 "QRAE2,QDMA Region Access Enable Register for Region 2" bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 2" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 2" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 2" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 2" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 2" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 2" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 2" "Not allowed,Allowed" group.long 0x38C++0x3 line.long 0x00 "QRAE3,QDMA Region Access Enable Register for Region 3" bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 3" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 3" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 3" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 3" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 3" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 3" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 3" "Not allowed,Allowed" group.long 0x390++0x3 line.long 0x00 "QRAE4,QDMA Region Access Enable Register for Region 4" bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 4" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 4" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 4" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 4" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 4" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 4" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 4" "Not allowed,Allowed" group.long 0x394++0x3 line.long 0x00 "QRAE5,QDMA Region Access Enable Register for Region 5" bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 5" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 5" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 5" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 5" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 5" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 5" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 5" "Not allowed,Allowed" group.long 0x398++0x3 line.long 0x00 "QRAE6,QDMA Region Access Enable Register for Region 6" bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 6" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 6" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 6" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 6" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 6" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 6" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 6" "Not allowed,Allowed" group.long 0x39C++0x3 line.long 0x00 "QRAE7,QDMA Region Access Enable Register for Region 7" bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit channel 7 in region 7" "Not allowed,Allowed" bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit channel 6 in region 7" "Not allowed,Allowed" bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit channel 5 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit channel 4 in region 7" "Not allowed,Allowed" bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit channel 3 in region 7" "Not allowed,Allowed" bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit channel 2 in region 7" "Not allowed,Allowed" textline " " bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit channel 1 in region 7" "Not allowed,Allowed" bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit channel 0 in region 7" "Not allowed,Allowed" tree.end tree "Status/Debug Visibility Registers" width 9. rgroup.long 0x400++0x3f "Event Queue 0 Registers" line.long 0x0 "Q0E0 ,Event Queue Entry 0 Register" bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x4 "Q0E1 ,Event Queue Entry 1 Register" bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x8 "Q0E2 ,Event Queue Entry 2 Register" bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0xC "Q0E3 ,Event Queue Entry 3 Register" bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x10 "Q0E4 ,Event Queue Entry 4 Register" bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x14 "Q0E5 ,Event Queue Entry 5 Register" bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x18 "Q0E6 ,Event Queue Entry 6 Register" bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x1C "Q0E7 ,Event Queue Entry 7 Register" bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x20 "Q0E8 ,Event Queue Entry 8 Register" bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x24 "Q0E9 ,Event Queue Entry 9 Register" bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x28 "Q0E10,Event Queue Entry 10 Register" bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x2C "Q0E11,Event Queue Entry 11 Register" bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x30 "Q0E12,Event Queue Entry 12 Register" bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x34 "Q0E13,Event Queue Entry 13 Register" bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x38 "Q0E14,Event Queue Entry 14 Register" bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x3C "Q0E15,Event Queue Entry 15 Register" bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" rgroup.long 0x440++0x3f "Event Queue 1 Registers" line.long 0x0 "Q1E0 ,Event Queue Entry 0 Register" bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x4 "Q1E1 ,Event Queue Entry 1 Register" bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x8 "Q1E2 ,Event Queue Entry 2 Register" bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0xC "Q1E3 ,Event Queue Entry 3 Register" bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x10 "Q1E4 ,Event Queue Entry 4 Register" bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x14 "Q1E5 ,Event Queue Entry 5 Register" bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x18 "Q1E6 ,Event Queue Entry 6 Register" bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x1C "Q1E7 ,Event Queue Entry 7 Register" bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x20 "Q1E8 ,Event Queue Entry 8 Register" bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x24 "Q1E9 ,Event Queue Entry 9 Register" bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x28 "Q1E10,Event Queue Entry 10 Register" bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x2C "Q1E11,Event Queue Entry 11 Register" bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x30 "Q1E12,Event Queue Entry 12 Register" bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x34 "Q1E13,Event Queue Entry 13 Register" bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x38 "Q1E14,Event Queue Entry 14 Register" bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x3C "Q1E15,Event Queue Entry 15 Register" bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" rgroup.long 0x480++0x3f "Event Queue 2 Registers" line.long 0x0 "Q2E0 ,Event Queue Entry 0 Register" bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x4 "Q2E1 ,Event Queue Entry 1 Register" bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x8 "Q2E2 ,Event Queue Entry 2 Register" bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0xC "Q2E3 ,Event Queue Entry 3 Register" bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x10 "Q2E4 ,Event Queue Entry 4 Register" bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x14 "Q2E5 ,Event Queue Entry 5 Register" bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x18 "Q2E6 ,Event Queue Entry 6 Register" bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x1C "Q2E7 ,Event Queue Entry 7 Register" bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x20 "Q2E8 ,Event Queue Entry 8 Register" bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x24 "Q2E9 ,Event Queue Entry 9 Register" bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x28 "Q2E10,Event Queue Entry 10 Register" bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x2C "Q2E11,Event Queue Entry 11 Register" bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x30 "Q2E12,Event Queue Entry 12 Register" bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x34 "Q2E13,Event Queue Entry 13 Register" bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x38 "Q2E14,Event Queue Entry 14 Register" bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x3C "Q2E15,Event Queue Entry 15 Register" bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" rgroup.long 0x4C0++0x3f "Event Queue 3 Registers" line.long 0x0 "Q3E0 ,Event Queue Entry 0 Register" bitfld.long 0x0 6.--7. " ETYPE ,Event trigger type for entry 0 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x0 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x4 "Q3E1 ,Event Queue Entry 1 Register" bitfld.long 0x4 6.--7. " ETYPE ,Event trigger type for entry 1 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x4 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x8 "Q3E2 ,Event Queue Entry 2 Register" bitfld.long 0x8 6.--7. " ETYPE ,Event trigger type for entry 2 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x8 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0xC "Q3E3 ,Event Queue Entry 3 Register" bitfld.long 0xC 6.--7. " ETYPE ,Event trigger type for entry 3 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0xC 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x10 "Q3E4 ,Event Queue Entry 4 Register" bitfld.long 0x10 6.--7. " ETYPE ,Event trigger type for entry 4 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x10 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x14 "Q3E5 ,Event Queue Entry 5 Register" bitfld.long 0x14 6.--7. " ETYPE ,Event trigger type for entry 5 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x14 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x18 "Q3E6 ,Event Queue Entry 6 Register" bitfld.long 0x18 6.--7. " ETYPE ,Event trigger type for entry 6 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x18 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x1C "Q3E7 ,Event Queue Entry 7 Register" bitfld.long 0x1C 6.--7. " ETYPE ,Event trigger type for entry 7 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x1C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x20 "Q3E8 ,Event Queue Entry 8 Register" bitfld.long 0x20 6.--7. " ETYPE ,Event trigger type for entry 8 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x20 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x24 "Q3E9 ,Event Queue Entry 9 Register" bitfld.long 0x24 6.--7. " ETYPE ,Event trigger type for entry 9 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x24 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x28 "Q3E10,Event Queue Entry 10 Register" bitfld.long 0x28 6.--7. " ETYPE ,Event trigger type for entry 10 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x28 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x2C "Q3E11,Event Queue Entry 11 Register" bitfld.long 0x2C 6.--7. " ETYPE ,Event trigger type for entry 11 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x2C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x30 "Q3E12,Event Queue Entry 12 Register" bitfld.long 0x30 6.--7. " ETYPE ,Event trigger type for entry 12 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x30 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x34 "Q3E13,Event Queue Entry 13 Register" bitfld.long 0x34 6.--7. " ETYPE ,Event trigger type for entry 13 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x34 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x38 "Q3E14,Event Queue Entry 14 Register" bitfld.long 0x38 6.--7. " ETYPE ,Event trigger type for entry 14 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x38 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" line.long 0x3C "Q3E15,Event Queue Entry 15 Register" bitfld.long 0x3C 6.--7. " ETYPE ,Event trigger type for entry 15 in the event queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER" bitfld.long 0x3C 0.--5. " ENUM ,Event number" "DMA/QDMA 0,DMA/QDMA 1,DMA/QDMQ 2,DMA/QDMA 3,DMA 4,DMA 5,DMA 6,DMA 7,DMA 8,DMA 9,DMA 10,DMA 11,DMA 12,DMA 13,DMA 14,DMA 15,DMA 16,DMA 17,DMA 18,DMA 19,DMA 20,DMA 21,DMA 22,DMA 23,DMA 24,DMA 25,DMA 26,DMA 27,DMA 28,DMA 29,DMA 30,DMA 31,DMA 32,DMA 33,DMA 34,DMA 35,DMA 36,DMA 37,DMA 38,DMA 39,DMA 40,DMA 41,DMA 42,DMA 43,DMA 44,DMA 45,DMA 46,DMA 47,DMA 48,DMA 49,DMA 50,DMA 51,DMA 52,DMA 53,DMA 54,DMA 55,DMA 56,DMA 57,DMA 58,DMA 59,DMA 60,DMA 61,DMA 62,DMA 63" width 9. rgroup.long 0x600++0xB "Queue Status Registers" line.long 0x0 "QSTAT0,Queue 0 Status Register" bitfld.long 0x0 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded" bitfld.long 0x0 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..." bitfld.long 0x0 8.--12. " NUMVAL ,Number of valid entrier in queue 0" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..." bitfld.long 0x0 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x4 "QSTAT1,Queue 1 Status Register" bitfld.long 0x4 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded" bitfld.long 0x4 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..." bitfld.long 0x4 8.--12. " NUMVAL ,Number of valid entrier in queue 1" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..." bitfld.long 0x4 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x8 "QSTAT2,Queue 2 Status Register" bitfld.long 0x8 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded" bitfld.long 0x8 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..." bitfld.long 0x8 8.--12. " NUMVAL ,Number of valid entrier in queue 2" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..." bitfld.long 0x8 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif (cpuis("DRA62*")) rgroup.long 0x60C++0x3 line.long 0x00 "QSTAT3,Queue 3 Status Register" bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded" bitfld.long 0x00 16.--20. " WM ,Watermark" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..." bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entrier in queue $2" "0(empty),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16(full),?..." bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 9. group.long 0x620++0x3 line.long 0x00 "QWMTHRA,Queue Watermark Threshold A Register" bitfld.long 0x00 24.--28. " Q3 ,Queue threshold for queue 3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..." bitfld.long 0x00 16.--20. " Q2 ,Queue threshold for queue 2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..." bitfld.long 0x00 8.--12. " Q1 ,Queue threshold for queue 1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..." bitfld.long 0x00 0.--4. " Q0 ,Queue threshold for queue 0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Disabled,?..." rgroup.long 0x640++0x3 line.long 0x00 "CCSTAT,EDMA3CC Status Register" bitfld.long 0x00 19. " QUEACTV3 ,Queue 3 active" "Not active,Active" bitfld.long 0x00 18. " QUEACTV2 ,Queue 2 active" "Not active,Active" textline " " bitfld.long 0x00 17. " QUEACTV1 ,Queue 1 active" "Not active,Active" bitfld.long 0x00 16. " QUEACTV0 ,Queue 0 active" "Not active,Active" textline " " bitfld.long 0x00 8.--13. " COMPACTV ,Completion request active" "No requests,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 4. " ACTV ,Channel controller active" "Not active,Active" textline " " bitfld.long 0x00 2. " TRACTV ,Transfer request active" "Not active,Active" bitfld.long 0x00 1. " QEVTACTV ,QDMA event active" "Not active,Active" textline " " bitfld.long 0x00 0. " EVTACTV ,DMA event active" "Not active,Active" tree.end tree "Memory Protection Address Space" width 7. rgroup.long 0x800++0x7 line.long 0x00 "MPFAR,Memory Protection Fault Address Register" line.long 0x04 "MPFSR,Memory Protection Fault Status Register" hexmask.long.byte 0x04 9.--12. 1. " FID ,Faulted identification" bitfld.long 0x04 5. " SRE ,Supervisor read error" "No error,Error" bitfld.long 0x04 4. " SWE ,Supervisor write error" "No error,Error" bitfld.long 0x04 3. " SXE ,Supervisor execute error" "No error,Error" textline " " bitfld.long 0x04 2. " URE ,User read error" "No error,Error" bitfld.long 0x04 1. " UWE ,User write error" "No error,Error" bitfld.long 0x04 0. " UXE ,User execute error" "No error,Error" wgroup.long 0x808++0x3 line.long 0x00 "MPFCR,Memory Protection Fault Command Register" bitfld.long 0x00 0. " MPFCLR ,Fault clear register" "No effect,Clear" sif (!cpuis("AM335*")) group.long 0x80C++0x03 line.long 0x00 "MPPAG,Memory Protection Page Attribute Register Global" bitfld.long 0x00 15. " AID5 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x00 14. " AID4 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x00 13. " AID3 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x00 12. " AID2 ,Allowed ID" "Not allowed,Permitted" textline " " bitfld.long 0x00 11. " AID1 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x00 10. " AID0 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x00 9. " EXT ,External allowed ID" "Not allowed,Permited" bitfld.long 0x00 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed" endif group.long 0x810++0x1f line.long 0x0 "MPPA0,Memory Protection Page Attribute Register 0" bitfld.long 0x0 15. " AID5 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x0 14. " AID4 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x0 13. " AID3 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x0 12. " AID2 ,Allowed ID" "Not allowed,Permitted" textline " " bitfld.long 0x0 11. " AID1 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x0 10. " AID0 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x0 9. " EXT ,External allowed ID" "Not allowed,Permited" bitfld.long 0x0 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x0 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x0 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x0 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x0 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x0 0. " UX ,User execute permission" "Not allowed,Allowed" line.long 0x4 "MPPA1,Memory Protection Page Attribute Register 1" bitfld.long 0x4 15. " AID5 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x4 14. " AID4 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x4 13. " AID3 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x4 12. " AID2 ,Allowed ID" "Not allowed,Permitted" textline " " bitfld.long 0x4 11. " AID1 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x4 10. " AID0 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x4 9. " EXT ,External allowed ID" "Not allowed,Permited" bitfld.long 0x4 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x4 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x4 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x4 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x4 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x4 0. " UX ,User execute permission" "Not allowed,Allowed" line.long 0x8 "MPPA2,Memory Protection Page Attribute Register 2" bitfld.long 0x8 15. " AID5 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x8 14. " AID4 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x8 13. " AID3 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x8 12. " AID2 ,Allowed ID" "Not allowed,Permitted" textline " " bitfld.long 0x8 11. " AID1 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x8 10. " AID0 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x8 9. " EXT ,External allowed ID" "Not allowed,Permited" bitfld.long 0x8 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x8 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x8 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x8 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x8 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x8 0. " UX ,User execute permission" "Not allowed,Allowed" line.long 0xC "MPPA3,Memory Protection Page Attribute Register 3" bitfld.long 0xC 15. " AID5 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0xC 14. " AID4 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0xC 13. " AID3 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0xC 12. " AID2 ,Allowed ID" "Not allowed,Permitted" textline " " bitfld.long 0xC 11. " AID1 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0xC 10. " AID0 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0xC 9. " EXT ,External allowed ID" "Not allowed,Permited" bitfld.long 0xC 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0xC 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0xC 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0xC 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0xC 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0xC 0. " UX ,User execute permission" "Not allowed,Allowed" line.long 0x10 "MPPA4,Memory Protection Page Attribute Register 4" bitfld.long 0x10 15. " AID5 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x10 14. " AID4 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x10 13. " AID3 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x10 12. " AID2 ,Allowed ID" "Not allowed,Permitted" textline " " bitfld.long 0x10 11. " AID1 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x10 10. " AID0 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x10 9. " EXT ,External allowed ID" "Not allowed,Permited" bitfld.long 0x10 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x10 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x10 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x10 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x10 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x10 0. " UX ,User execute permission" "Not allowed,Allowed" line.long 0x14 "MPPA5,Memory Protection Page Attribute Register 5" bitfld.long 0x14 15. " AID5 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x14 14. " AID4 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x14 13. " AID3 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x14 12. " AID2 ,Allowed ID" "Not allowed,Permitted" textline " " bitfld.long 0x14 11. " AID1 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x14 10. " AID0 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x14 9. " EXT ,External allowed ID" "Not allowed,Permited" bitfld.long 0x14 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x14 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x14 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x14 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x14 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x14 0. " UX ,User execute permission" "Not allowed,Allowed" line.long 0x18 "MPPA6,Memory Protection Page Attribute Register 6" bitfld.long 0x18 15. " AID5 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x18 14. " AID4 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x18 13. " AID3 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x18 12. " AID2 ,Allowed ID" "Not allowed,Permitted" textline " " bitfld.long 0x18 11. " AID1 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x18 10. " AID0 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x18 9. " EXT ,External allowed ID" "Not allowed,Permited" bitfld.long 0x18 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x18 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x18 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x18 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x18 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x18 0. " UX ,User execute permission" "Not allowed,Allowed" line.long 0x1C "MPPA7,Memory Protection Page Attribute Register 7" bitfld.long 0x1C 15. " AID5 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x1C 14. " AID4 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x1C 13. " AID3 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x1C 12. " AID2 ,Allowed ID" "Not allowed,Permitted" textline " " bitfld.long 0x1C 11. " AID1 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x1C 10. " AID0 ,Allowed ID" "Not allowed,Permitted" bitfld.long 0x1C 9. " EXT ,External allowed ID" "Not allowed,Permited" bitfld.long 0x1C 5. " SR ,Supervisor read permission" "Not allowed,Allowed" textline " " bitfld.long 0x1C 4. " SW ,Supervisor write permission" "Not allowed,Allowed" bitfld.long 0x1C 3. " SX ,Supervisor execute permission" "Not allowed,Allowed" bitfld.long 0x1C 2. " UR ,User read permission" "Not allowed,Allowed" bitfld.long 0x1C 1. " UW ,User write permission" "Not allowed,Allowed" textline " " bitfld.long 0x1C 0. " UX ,User execute permission" "Not allowed,Allowed" tree.end tree "DMA Channel Registers" width 7. group.long 0x1000++0x7 line.long 0x00 "ER,Event Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted" line.long 0x04 "ERH,Event Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted" rgroup.long 0x1018++0x7 line.long 0x00 "CER,Chained Event Register" bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized" bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized" bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized" textline " " bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized" bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized" bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized" textline " " bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized" bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized" bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized" textline " " bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized" bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized" bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized" textline " " bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized" bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized" bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized" textline " " bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized" bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized" bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized" textline " " bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized" bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized" bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized" textline " " bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized" bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized" bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized" textline " " bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized" textline " " bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized" bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized" textline " " bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized" line.long 0x04 "CERH,Chained Event Register High" bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized" bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized" bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized" textline " " bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized" bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized" bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized" textline " " bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized" bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized" bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized" textline " " bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized" bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized" bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized" textline " " bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized" bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized" bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized" textline " " bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized" bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized" bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized" textline " " bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized" bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized" bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized" textline " " bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized" bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized" bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized" textline " " bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized" bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized" bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized" textline " " bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized" bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized" bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized" textline " " bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized" bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized" group.long 0x1020++0x7 line.long 0x00 "EER,Event Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled" line.long 0x04 "EERH,Event Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled" rgroup.long 0x1038++0x7 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored" bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored" bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored" bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored" bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored" bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored" bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored" bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored" bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored" bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored" bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored" bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored" bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored" bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored" bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored" bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored" bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored" bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored" line.long 0x04 "SERH,Secondary Event Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored" bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored" bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored" bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored" bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored" bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored" bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored" bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored" bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored" bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored" bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored" bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored" bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored" bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored" bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored" bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored" bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored" bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored" bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored" bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored" bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored" bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored" wgroup.long 0x1040++0x7 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear" bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear" bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear" bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear" bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear" bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear" line.long 0x04 "SECRH,Secondary Event Clear Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear" bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear" bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear" bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear" bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear" bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear" tree.end tree "Interrupt Registers" width 7. group.long 0x1050++0x7 line.long 0x00 "IER,Interrupt Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled" line.long 0x04 "IERH,Interrupt Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " I63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " I62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " I61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " I60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " I59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " I58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " I57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " I56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " I55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " I54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " I53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " I52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " I51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " I50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " I49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " I48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " I47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " I46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " I45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " I44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " I43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " I42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " I41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " I40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " I39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " I38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " I37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " I36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " I35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " I34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " I33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " I32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled" rgroup.long 0x1068++0x7 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected" bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected" textline " " bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected" bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected" textline " " bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected" bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected" textline " " bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected" bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected" textline " " bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected" bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected" textline " " bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected" bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected" textline " " bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected" bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected" bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected" bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected" textline " " bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected" bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected" textline " " bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected" bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected" textline " " bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected" bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected" textline " " bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected" bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected" textline " " bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected" bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected" bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected" textline " " bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected" bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected" line.long 0x04 "IPRH,Interrupt Pending Register High" bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected" bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected" textline " " bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected" bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected" textline " " bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected" bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected" textline " " bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected" bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected" textline " " bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected" bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected" textline " " bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected" bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected" textline " " bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected" bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected" textline " " bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected" bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected" textline " " bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected" bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected" textline " " bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected" bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected" textline " " bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected" bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected" textline " " bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected" bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected" textline " " bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected" bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected" textline " " bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected" bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected" textline " " bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected" bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected" textline " " bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected" bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected" wgroup.long 0x1070++0x7 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear" bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear" textline " " bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear" bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear" bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear" bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear" bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear" textline " " bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear" bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear" bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear" textline " " bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear" bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear" bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear" bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear" bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear" textline " " bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear" bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear" bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear" textline " " bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear" bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear" bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear" bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear" line.long 0x04 "ICRH,Interrupt Clear Register High" bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear" bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear" textline " " bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear" bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear" textline " " bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear" bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear" bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear" textline " " bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear" bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear" textline " " bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear" bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear" bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear" textline " " bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear" bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear" textline " " bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear" bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear" bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear" textline " " bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear" bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear" textline " " bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear" bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear" bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear" textline " " bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear" bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear" textline " " bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear" bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear" bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear" wgroup.long 0x1078++0x3 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulsed" tree.end tree "QDMA Registers" rgroup.long 0x1080++0x3 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized" bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized" textline " " bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized" bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized" group.long 0x1084++0x3 line.long 0x00 "QEER,QDMA Event Enable Register" setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled" rgroup.long 0x1090++0x3 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored" bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored" bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored" wgroup.long 0x1094++0x3 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear" tree.end sif (!cpuis("AM335*")) tree "Shadow Region 0 Channel Registers" tree "DMA Channel Registers" width 7. group.long (0x2000+0x0)++0x7 line.long 0x00 "ER,Event Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted" line.long 0x04 "ERH,Event Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted" rgroup.long (0x2018+0x0)++0x7 line.long 0x00 "ECR,Chained Event Register" bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized" bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized" bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized" textline " " bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized" bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized" bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized" textline " " bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized" bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized" bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized" textline " " bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized" bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized" bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized" textline " " bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized" bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized" bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized" textline " " bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized" bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized" bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized" textline " " bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized" bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized" bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized" textline " " bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized" bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized" bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized" textline " " bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized" textline " " bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized" bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized" textline " " bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized" line.long 0x04 "ECRH,Chained Event Register High" bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized" bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized" bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized" textline " " bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized" bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized" bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized" textline " " bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized" bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized" bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized" textline " " bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized" bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized" bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized" textline " " bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized" bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized" bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized" textline " " bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized" bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized" bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized" textline " " bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized" bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized" bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized" textline " " bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized" bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized" bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized" textline " " bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized" bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized" bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized" textline " " bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized" bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized" bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized" textline " " bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized" bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized" group.long (0x2020+0x0)++0x7 line.long 0x00 "EER,Event Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled" line.long 0x04 "EERH,Event Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled" rgroup.long (0x2038+0x0)++0x7 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored" bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored" bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored" bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored" bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored" bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored" bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored" bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored" bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored" bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored" bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored" bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored" bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored" bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored" bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored" bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored" bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored" bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored" line.long 0x04 "SERH,Secondary Event Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored" bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored" bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored" bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored" bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored" bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored" bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored" bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored" bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored" bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored" bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored" bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored" bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored" bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored" bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored" bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored" bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored" bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored" bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored" bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored" bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored" bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored" wgroup.long (0x2040+0x0)++0x7 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear" bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear" bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear" bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear" bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear" bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear" line.long 0x04 "SECRH,Secondary Event Clear Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear" bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear" bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear" bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear" bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear" bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear" tree.end tree "Interrupt Registers" width 7. group.long (0x2050+0x0)++0x7 line.long 0x00 "IER,Interrupt Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled" line.long 0x04 "IERH,Interrupt Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled" rgroup.long (0x2068+0x0)++0x7 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected" bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected" textline " " bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected" bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected" textline " " bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected" bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected" textline " " bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected" bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected" textline " " bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected" bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected" textline " " bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected" bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected" textline " " bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected" bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected" bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected" bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected" textline " " bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected" bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected" textline " " bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected" bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected" textline " " bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected" bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected" textline " " bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected" bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected" textline " " bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected" bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected" bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected" textline " " bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected" bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected" line.long 0x04 "IPRH,Interrupt Pending Register High" bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected" bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected" textline " " bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected" bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected" textline " " bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected" bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected" textline " " bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected" bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected" textline " " bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected" bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected" textline " " bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected" bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected" textline " " bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected" bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected" textline " " bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected" bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected" textline " " bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected" bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected" textline " " bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected" bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected" textline " " bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected" bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected" textline " " bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected" bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected" textline " " bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected" bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected" textline " " bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected" bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected" textline " " bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected" bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected" textline " " bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected" bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected" wgroup.long (0x2070+0x0)++0x7 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear" bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear" textline " " bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear" bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear" bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear" bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear" bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear" textline " " bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear" bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear" bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear" textline " " bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear" bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear" bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear" bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear" bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear" textline " " bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear" bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear" bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear" textline " " bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear" bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear" bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear" bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear" line.long 0x04 "ICRH,Interrupt Clear Register High" bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear" bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear" textline " " bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear" bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear" textline " " bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear" bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear" bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear" textline " " bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear" bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear" textline " " bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear" bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear" bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear" textline " " bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear" bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear" textline " " bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear" bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear" bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear" textline " " bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear" bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear" textline " " bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear" bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear" bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear" textline " " bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear" bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear" textline " " bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear" bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear" bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear" wgroup.long (0x2078+0x0)++0x3 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse" tree.end tree "QDMA Registers" rgroup.long (0x2080+0x0)++0x3 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized" bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized" textline " " bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized" bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized" group.long (0x2084+0x0)++0x3 line.long 0x00 "QEER,QDMA Event Enable Register" setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled" rgroup.long (0x2090+0x0)++0x3 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored" bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored" bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored" wgroup.long (0x2094+0x0)++0x3 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear" tree.end tree.end tree "Shadow Region 1 Channel Registers" tree "DMA Channel Registers" width 7. group.long (0x2000+0x200)++0x7 line.long 0x00 "ER,Event Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted" line.long 0x04 "ERH,Event Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted" rgroup.long (0x2018+0x200)++0x7 line.long 0x00 "ECR,Chained Event Register" bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized" bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized" bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized" textline " " bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized" bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized" bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized" textline " " bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized" bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized" bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized" textline " " bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized" bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized" bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized" textline " " bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized" bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized" bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized" textline " " bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized" bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized" bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized" textline " " bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized" bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized" bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized" textline " " bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized" bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized" bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized" textline " " bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized" textline " " bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized" bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized" textline " " bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized" line.long 0x04 "ECRH,Chained Event Register High" bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized" bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized" bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized" textline " " bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized" bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized" bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized" textline " " bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized" bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized" bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized" textline " " bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized" bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized" bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized" textline " " bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized" bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized" bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized" textline " " bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized" bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized" bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized" textline " " bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized" bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized" bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized" textline " " bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized" bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized" bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized" textline " " bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized" bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized" bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized" textline " " bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized" bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized" bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized" textline " " bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized" bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized" group.long (0x2020+0x200)++0x7 line.long 0x00 "EER,Event Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled" line.long 0x04 "EERH,Event Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled" rgroup.long (0x2038+0x200)++0x7 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored" bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored" bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored" bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored" bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored" bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored" bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored" bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored" bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored" bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored" bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored" bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored" bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored" bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored" bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored" bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored" bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored" bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored" line.long 0x04 "SERH,Secondary Event Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored" bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored" bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored" bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored" bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored" bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored" bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored" bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored" bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored" bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored" bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored" bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored" bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored" bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored" bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored" bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored" bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored" bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored" bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored" bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored" bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored" bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored" wgroup.long (0x2040+0x200)++0x7 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear" bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear" bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear" bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear" bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear" bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear" line.long 0x04 "SECRH,Secondary Event Clear Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear" bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear" bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear" bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear" bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear" bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear" tree.end tree "Interrupt Registers" width 7. group.long (0x2050+0x200)++0x7 line.long 0x00 "IER,Interrupt Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled" line.long 0x04 "IERH,Interrupt Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled" rgroup.long (0x2068+0x200)++0x7 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected" bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected" textline " " bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected" bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected" textline " " bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected" bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected" textline " " bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected" bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected" textline " " bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected" bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected" textline " " bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected" bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected" textline " " bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected" bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected" bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected" bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected" textline " " bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected" bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected" textline " " bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected" bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected" textline " " bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected" bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected" textline " " bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected" bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected" textline " " bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected" bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected" bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected" textline " " bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected" bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected" line.long 0x04 "IPRH,Interrupt Pending Register High" bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected" bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected" textline " " bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected" bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected" textline " " bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected" bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected" textline " " bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected" bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected" textline " " bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected" bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected" textline " " bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected" bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected" textline " " bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected" bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected" textline " " bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected" bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected" textline " " bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected" bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected" textline " " bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected" bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected" textline " " bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected" bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected" textline " " bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected" bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected" textline " " bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected" bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected" textline " " bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected" bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected" textline " " bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected" bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected" textline " " bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected" bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected" wgroup.long (0x2070+0x200)++0x7 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear" bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear" textline " " bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear" bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear" bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear" bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear" bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear" textline " " bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear" bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear" bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear" textline " " bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear" bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear" bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear" bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear" bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear" textline " " bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear" bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear" bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear" textline " " bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear" bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear" bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear" bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear" line.long 0x04 "ICRH,Interrupt Clear Register High" bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear" bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear" textline " " bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear" bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear" textline " " bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear" bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear" bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear" textline " " bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear" bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear" textline " " bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear" bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear" bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear" textline " " bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear" bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear" textline " " bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear" bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear" bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear" textline " " bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear" bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear" textline " " bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear" bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear" bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear" textline " " bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear" bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear" textline " " bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear" bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear" bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear" wgroup.long (0x2078+0x200)++0x3 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse" tree.end tree "QDMA Registers" rgroup.long (0x2080+0x200)++0x3 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized" bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized" textline " " bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized" bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized" group.long (0x2084+0x200)++0x3 line.long 0x00 "QEER,QDMA Event Enable Register" setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled" rgroup.long (0x2090+0x200)++0x3 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored" bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored" bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored" wgroup.long (0x2094+0x200)++0x3 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear" tree.end tree.end tree "Shadow Region 2 Channel Registers" tree "DMA Channel Registers" width 7. group.long (0x2000+0x400)++0x7 line.long 0x00 "ER,Event Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted" line.long 0x04 "ERH,Event Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted" rgroup.long (0x2018+0x400)++0x7 line.long 0x00 "ECR,Chained Event Register" bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized" bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized" bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized" textline " " bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized" bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized" bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized" textline " " bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized" bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized" bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized" textline " " bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized" bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized" bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized" textline " " bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized" bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized" bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized" textline " " bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized" bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized" bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized" textline " " bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized" bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized" bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized" textline " " bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized" bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized" bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized" textline " " bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized" textline " " bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized" bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized" textline " " bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized" line.long 0x04 "ECRH,Chained Event Register High" bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized" bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized" bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized" textline " " bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized" bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized" bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized" textline " " bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized" bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized" bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized" textline " " bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized" bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized" bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized" textline " " bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized" bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized" bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized" textline " " bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized" bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized" bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized" textline " " bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized" bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized" bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized" textline " " bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized" bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized" bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized" textline " " bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized" bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized" bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized" textline " " bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized" bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized" bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized" textline " " bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized" bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized" group.long (0x2020+0x400)++0x7 line.long 0x00 "EER,Event Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled" line.long 0x04 "EERH,Event Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled" rgroup.long (0x2038+0x400)++0x7 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored" bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored" bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored" bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored" bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored" bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored" bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored" bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored" bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored" bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored" bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored" bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored" bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored" bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored" bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored" bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored" bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored" bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored" line.long 0x04 "SERH,Secondary Event Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored" bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored" bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored" bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored" bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored" bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored" bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored" bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored" bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored" bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored" bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored" bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored" bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored" bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored" bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored" bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored" bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored" bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored" bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored" bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored" bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored" bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored" wgroup.long (0x2040+0x400)++0x7 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear" bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear" bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear" bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear" bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear" bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear" line.long 0x04 "SECRH,Secondary Event Clear Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear" bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear" bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear" bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear" bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear" bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear" tree.end tree "Interrupt Registers" width 7. group.long (0x2050+0x400)++0x7 line.long 0x00 "IER,Interrupt Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled" line.long 0x04 "IERH,Interrupt Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled" rgroup.long (0x2068+0x400)++0x7 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected" bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected" textline " " bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected" bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected" textline " " bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected" bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected" textline " " bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected" bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected" textline " " bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected" bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected" textline " " bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected" bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected" textline " " bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected" bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected" bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected" bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected" textline " " bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected" bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected" textline " " bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected" bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected" textline " " bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected" bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected" textline " " bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected" bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected" textline " " bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected" bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected" bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected" textline " " bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected" bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected" line.long 0x04 "IPRH,Interrupt Pending Register High" bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected" bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected" textline " " bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected" bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected" textline " " bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected" bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected" textline " " bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected" bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected" textline " " bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected" bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected" textline " " bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected" bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected" textline " " bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected" bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected" textline " " bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected" bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected" textline " " bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected" bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected" textline " " bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected" bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected" textline " " bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected" bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected" textline " " bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected" bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected" textline " " bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected" bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected" textline " " bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected" bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected" textline " " bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected" bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected" textline " " bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected" bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected" wgroup.long (0x2070+0x400)++0x7 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear" bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear" textline " " bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear" bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear" bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear" bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear" bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear" textline " " bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear" bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear" bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear" textline " " bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear" bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear" bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear" bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear" bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear" textline " " bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear" bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear" bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear" textline " " bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear" bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear" bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear" bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear" line.long 0x04 "ICRH,Interrupt Clear Register High" bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear" bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear" textline " " bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear" bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear" textline " " bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear" bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear" bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear" textline " " bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear" bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear" textline " " bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear" bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear" bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear" textline " " bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear" bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear" textline " " bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear" bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear" bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear" textline " " bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear" bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear" textline " " bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear" bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear" bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear" textline " " bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear" bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear" textline " " bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear" bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear" bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear" wgroup.long (0x2078+0x400)++0x3 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse" tree.end tree "QDMA Registers" rgroup.long (0x2080+0x400)++0x3 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized" bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized" textline " " bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized" bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized" group.long (0x2084+0x400)++0x3 line.long 0x00 "QEER,QDMA Event Enable Register" setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled" rgroup.long (0x2090+0x400)++0x3 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored" bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored" bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored" wgroup.long (0x2094+0x400)++0x3 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear" tree.end tree.end tree "Shadow Region 3 Channel Registers" tree "DMA Channel Registers" width 7. group.long (0x2000+0x600)++0x7 line.long 0x00 "ER,Event Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted" line.long 0x04 "ERH,Event Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted" rgroup.long (0x2018+0x600)++0x7 line.long 0x00 "ECR,Chained Event Register" bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized" bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized" bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized" textline " " bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized" bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized" bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized" textline " " bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized" bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized" bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized" textline " " bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized" bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized" bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized" textline " " bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized" bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized" bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized" textline " " bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized" bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized" bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized" textline " " bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized" bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized" bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized" textline " " bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized" bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized" bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized" textline " " bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized" textline " " bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized" bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized" textline " " bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized" line.long 0x04 "ECRH,Chained Event Register High" bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized" bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized" bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized" textline " " bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized" bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized" bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized" textline " " bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized" bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized" bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized" textline " " bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized" bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized" bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized" textline " " bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized" bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized" bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized" textline " " bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized" bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized" bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized" textline " " bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized" bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized" bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized" textline " " bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized" bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized" bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized" textline " " bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized" bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized" bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized" textline " " bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized" bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized" bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized" textline " " bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized" bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized" group.long (0x2020+0x600)++0x7 line.long 0x00 "EER,Event Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled" line.long 0x04 "EERH,Event Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled" rgroup.long (0x2038+0x600)++0x7 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored" bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored" bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored" bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored" bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored" bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored" bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored" bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored" bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored" bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored" bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored" bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored" bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored" bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored" bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored" bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored" bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored" bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored" line.long 0x04 "SERH,Secondary Event Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored" bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored" bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored" bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored" bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored" bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored" bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored" bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored" bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored" bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored" bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored" bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored" bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored" bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored" bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored" bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored" bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored" bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored" bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored" bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored" bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored" bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored" wgroup.long (0x2040+0x600)++0x7 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear" bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear" bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear" bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear" bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear" bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear" line.long 0x04 "SECRH,Secondary Event Clear Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear" bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear" bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear" bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear" bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear" bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear" tree.end tree "Interrupt Registers" width 7. group.long (0x2050+0x600)++0x7 line.long 0x00 "IER,Interrupt Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled" line.long 0x04 "IERH,Interrupt Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled" rgroup.long (0x2068+0x600)++0x7 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected" bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected" textline " " bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected" bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected" textline " " bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected" bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected" textline " " bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected" bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected" textline " " bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected" bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected" textline " " bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected" bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected" textline " " bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected" bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected" bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected" bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected" textline " " bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected" bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected" textline " " bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected" bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected" textline " " bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected" bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected" textline " " bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected" bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected" textline " " bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected" bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected" bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected" textline " " bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected" bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected" line.long 0x04 "IPRH,Interrupt Pending Register High" bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected" bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected" textline " " bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected" bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected" textline " " bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected" bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected" textline " " bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected" bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected" textline " " bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected" bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected" textline " " bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected" bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected" textline " " bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected" bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected" textline " " bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected" bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected" textline " " bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected" bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected" textline " " bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected" bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected" textline " " bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected" bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected" textline " " bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected" bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected" textline " " bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected" bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected" textline " " bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected" bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected" textline " " bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected" bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected" textline " " bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected" bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected" wgroup.long (0x2070+0x600)++0x7 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear" bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear" textline " " bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear" bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear" bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear" bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear" bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear" textline " " bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear" bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear" bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear" textline " " bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear" bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear" bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear" bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear" bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear" textline " " bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear" bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear" bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear" textline " " bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear" bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear" bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear" bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear" line.long 0x04 "ICRH,Interrupt Clear Register High" bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear" bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear" textline " " bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear" bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear" textline " " bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear" bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear" bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear" textline " " bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear" bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear" textline " " bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear" bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear" bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear" textline " " bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear" bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear" textline " " bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear" bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear" bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear" textline " " bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear" bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear" textline " " bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear" bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear" bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear" textline " " bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear" bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear" textline " " bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear" bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear" bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear" wgroup.long (0x2078+0x600)++0x3 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse" tree.end tree "QDMA Registers" rgroup.long (0x2080+0x600)++0x3 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized" bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized" textline " " bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized" bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized" group.long (0x2084+0x600)++0x3 line.long 0x00 "QEER,QDMA Event Enable Register" setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled" rgroup.long (0x2090+0x600)++0x3 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored" bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored" bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored" wgroup.long (0x2094+0x600)++0x3 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear" tree.end tree.end tree "Shadow Region 4 Channel Registers" tree "DMA Channel Registers" width 7. group.long (0x2000+0x800)++0x7 line.long 0x00 "ER,Event Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted" line.long 0x04 "ERH,Event Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted" rgroup.long (0x2018+0x800)++0x7 line.long 0x00 "ECR,Chained Event Register" bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized" bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized" bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized" textline " " bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized" bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized" bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized" textline " " bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized" bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized" bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized" textline " " bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized" bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized" bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized" textline " " bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized" bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized" bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized" textline " " bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized" bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized" bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized" textline " " bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized" bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized" bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized" textline " " bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized" bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized" bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized" textline " " bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized" textline " " bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized" bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized" textline " " bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized" line.long 0x04 "ECRH,Chained Event Register High" bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized" bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized" bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized" textline " " bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized" bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized" bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized" textline " " bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized" bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized" bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized" textline " " bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized" bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized" bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized" textline " " bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized" bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized" bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized" textline " " bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized" bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized" bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized" textline " " bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized" bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized" bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized" textline " " bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized" bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized" bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized" textline " " bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized" bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized" bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized" textline " " bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized" bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized" bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized" textline " " bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized" bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized" group.long (0x2020+0x800)++0x7 line.long 0x00 "EER,Event Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled" line.long 0x04 "EERH,Event Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled" rgroup.long (0x2038+0x800)++0x7 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored" bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored" bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored" bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored" bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored" bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored" bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored" bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored" bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored" bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored" bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored" bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored" bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored" bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored" bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored" bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored" bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored" bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored" line.long 0x04 "SERH,Secondary Event Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored" bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored" bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored" bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored" bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored" bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored" bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored" bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored" bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored" bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored" bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored" bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored" bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored" bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored" bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored" bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored" bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored" bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored" bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored" bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored" bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored" bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored" wgroup.long (0x2040+0x800)++0x7 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear" bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear" bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear" bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear" bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear" bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear" line.long 0x04 "SECRH,Secondary Event Clear Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear" bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear" bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear" bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear" bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear" bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear" tree.end tree "Interrupt Registers" width 7. group.long (0x2050+0x800)++0x7 line.long 0x00 "IER,Interrupt Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled" line.long 0x04 "IERH,Interrupt Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled" rgroup.long (0x2068+0x800)++0x7 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected" bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected" textline " " bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected" bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected" textline " " bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected" bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected" textline " " bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected" bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected" textline " " bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected" bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected" textline " " bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected" bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected" textline " " bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected" bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected" bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected" bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected" textline " " bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected" bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected" textline " " bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected" bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected" textline " " bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected" bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected" textline " " bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected" bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected" textline " " bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected" bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected" bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected" textline " " bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected" bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected" line.long 0x04 "IPRH,Interrupt Pending Register High" bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected" bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected" textline " " bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected" bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected" textline " " bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected" bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected" textline " " bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected" bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected" textline " " bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected" bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected" textline " " bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected" bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected" textline " " bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected" bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected" textline " " bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected" bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected" textline " " bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected" bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected" textline " " bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected" bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected" textline " " bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected" bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected" textline " " bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected" bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected" textline " " bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected" bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected" textline " " bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected" bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected" textline " " bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected" bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected" textline " " bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected" bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected" wgroup.long (0x2070+0x800)++0x7 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear" bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear" textline " " bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear" bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear" bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear" bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear" bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear" textline " " bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear" bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear" bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear" textline " " bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear" bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear" bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear" bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear" bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear" textline " " bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear" bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear" bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear" textline " " bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear" bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear" bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear" bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear" line.long 0x04 "ICRH,Interrupt Clear Register High" bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear" bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear" textline " " bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear" bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear" textline " " bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear" bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear" bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear" textline " " bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear" bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear" textline " " bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear" bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear" bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear" textline " " bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear" bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear" textline " " bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear" bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear" bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear" textline " " bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear" bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear" textline " " bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear" bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear" bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear" textline " " bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear" bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear" textline " " bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear" bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear" bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear" wgroup.long (0x2078+0x800)++0x3 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse" tree.end tree "QDMA Registers" rgroup.long (0x2080+0x800)++0x3 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized" bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized" textline " " bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized" bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized" group.long (0x2084+0x800)++0x3 line.long 0x00 "QEER,QDMA Event Enable Register" setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled" rgroup.long (0x2090+0x800)++0x3 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored" bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored" bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored" wgroup.long (0x2094+0x800)++0x3 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear" tree.end tree.end tree "Shadow Region 5 Channel Registers" tree "DMA Channel Registers" width 7. group.long (0x2000+0xA00)++0x7 line.long 0x00 "ER,Event Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted" line.long 0x04 "ERH,Event Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted" rgroup.long (0x2018+0xA00)++0x7 line.long 0x00 "ECR,Chained Event Register" bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized" bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized" bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized" textline " " bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized" bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized" bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized" textline " " bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized" bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized" bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized" textline " " bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized" bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized" bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized" textline " " bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized" bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized" bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized" textline " " bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized" bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized" bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized" textline " " bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized" bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized" bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized" textline " " bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized" bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized" bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized" textline " " bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized" textline " " bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized" bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized" textline " " bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized" line.long 0x04 "ECRH,Chained Event Register High" bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized" bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized" bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized" textline " " bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized" bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized" bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized" textline " " bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized" bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized" bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized" textline " " bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized" bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized" bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized" textline " " bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized" bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized" bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized" textline " " bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized" bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized" bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized" textline " " bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized" bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized" bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized" textline " " bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized" bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized" bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized" textline " " bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized" bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized" bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized" textline " " bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized" bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized" bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized" textline " " bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized" bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized" group.long (0x2020+0xA00)++0x7 line.long 0x00 "EER,Event Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled" line.long 0x04 "EERH,Event Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled" rgroup.long (0x2038+0xA00)++0x7 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored" bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored" bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored" bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored" bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored" bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored" bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored" bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored" bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored" bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored" bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored" bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored" bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored" bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored" bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored" bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored" bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored" bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored" line.long 0x04 "SERH,Secondary Event Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored" bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored" bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored" bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored" bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored" bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored" bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored" bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored" bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored" bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored" bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored" bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored" bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored" bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored" bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored" bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored" bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored" bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored" bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored" bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored" bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored" bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored" wgroup.long (0x2040+0xA00)++0x7 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear" bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear" bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear" bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear" bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear" bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear" line.long 0x04 "SECRH,Secondary Event Clear Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear" bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear" bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear" bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear" bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear" bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear" tree.end tree "Interrupt Registers" width 7. group.long (0x2050+0xA00)++0x7 line.long 0x00 "IER,Interrupt Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled" line.long 0x04 "IERH,Interrupt Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled" rgroup.long (0x2068+0xA00)++0x7 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected" bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected" textline " " bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected" bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected" textline " " bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected" bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected" textline " " bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected" bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected" textline " " bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected" bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected" textline " " bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected" bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected" textline " " bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected" bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected" bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected" bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected" textline " " bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected" bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected" textline " " bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected" bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected" textline " " bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected" bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected" textline " " bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected" bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected" textline " " bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected" bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected" bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected" textline " " bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected" bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected" line.long 0x04 "IPRH,Interrupt Pending Register High" bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected" bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected" textline " " bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected" bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected" textline " " bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected" bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected" textline " " bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected" bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected" textline " " bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected" bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected" textline " " bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected" bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected" textline " " bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected" bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected" textline " " bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected" bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected" textline " " bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected" bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected" textline " " bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected" bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected" textline " " bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected" bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected" textline " " bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected" bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected" textline " " bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected" bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected" textline " " bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected" bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected" textline " " bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected" bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected" textline " " bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected" bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected" wgroup.long (0x2070+0xA00)++0x7 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear" bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear" textline " " bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear" bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear" bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear" bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear" bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear" textline " " bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear" bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear" bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear" textline " " bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear" bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear" bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear" bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear" bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear" textline " " bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear" bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear" bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear" textline " " bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear" bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear" bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear" bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear" line.long 0x04 "ICRH,Interrupt Clear Register High" bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear" bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear" textline " " bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear" bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear" textline " " bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear" bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear" bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear" textline " " bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear" bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear" textline " " bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear" bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear" bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear" textline " " bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear" bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear" textline " " bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear" bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear" bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear" textline " " bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear" bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear" textline " " bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear" bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear" bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear" textline " " bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear" bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear" textline " " bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear" bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear" bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear" wgroup.long (0x2078+0xA00)++0x3 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse" tree.end tree "QDMA Registers" rgroup.long (0x2080+0xA00)++0x3 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized" bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized" textline " " bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized" bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized" group.long (0x2084+0xA00)++0x3 line.long 0x00 "QEER,QDMA Event Enable Register" setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled" rgroup.long (0x2090+0xA00)++0x3 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored" bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored" bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored" wgroup.long (0x2094+0xA00)++0x3 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear" tree.end tree.end tree "Shadow Region 6 Channel Registers" tree "DMA Channel Registers" width 7. group.long (0x2000+0xC00)++0x7 line.long 0x00 "ER,Event Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted" line.long 0x04 "ERH,Event Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted" rgroup.long (0x2018+0xC00)++0x7 line.long 0x00 "ECR,Chained Event Register" bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized" bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized" bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized" textline " " bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized" bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized" bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized" textline " " bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized" bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized" bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized" textline " " bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized" bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized" bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized" textline " " bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized" bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized" bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized" textline " " bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized" bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized" bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized" textline " " bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized" bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized" bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized" textline " " bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized" bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized" bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized" textline " " bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized" textline " " bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized" bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized" textline " " bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized" line.long 0x04 "ECRH,Chained Event Register High" bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized" bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized" bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized" textline " " bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized" bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized" bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized" textline " " bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized" bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized" bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized" textline " " bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized" bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized" bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized" textline " " bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized" bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized" bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized" textline " " bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized" bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized" bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized" textline " " bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized" bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized" bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized" textline " " bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized" bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized" bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized" textline " " bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized" bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized" bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized" textline " " bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized" bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized" bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized" textline " " bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized" bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized" group.long (0x2020+0xC00)++0x7 line.long 0x00 "EER,Event Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled" line.long 0x04 "EERH,Event Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled" rgroup.long (0x2038+0xC00)++0x7 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored" bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored" bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored" bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored" bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored" bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored" bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored" bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored" bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored" bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored" bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored" bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored" bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored" bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored" bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored" bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored" bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored" bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored" line.long 0x04 "SERH,Secondary Event Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored" bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored" bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored" bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored" bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored" bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored" bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored" bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored" bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored" bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored" bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored" bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored" bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored" bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored" bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored" bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored" bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored" bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored" bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored" bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored" bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored" bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored" wgroup.long (0x2040+0xC00)++0x7 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear" bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear" bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear" bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear" bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear" bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear" line.long 0x04 "SECRH,Secondary Event Clear Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear" bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear" bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear" bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear" bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear" bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear" tree.end tree "Interrupt Registers" width 7. group.long (0x2050+0xC00)++0x7 line.long 0x00 "IER,Interrupt Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled" line.long 0x04 "IERH,Interrupt Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled" rgroup.long (0x2068+0xC00)++0x7 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected" bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected" textline " " bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected" bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected" textline " " bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected" bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected" textline " " bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected" bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected" textline " " bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected" bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected" textline " " bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected" bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected" textline " " bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected" bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected" bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected" bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected" textline " " bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected" bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected" textline " " bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected" bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected" textline " " bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected" bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected" textline " " bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected" bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected" textline " " bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected" bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected" bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected" textline " " bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected" bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected" line.long 0x04 "IPRH,Interrupt Pending Register High" bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected" bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected" textline " " bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected" bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected" textline " " bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected" bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected" textline " " bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected" bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected" textline " " bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected" bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected" textline " " bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected" bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected" textline " " bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected" bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected" textline " " bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected" bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected" textline " " bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected" bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected" textline " " bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected" bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected" textline " " bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected" bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected" textline " " bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected" bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected" textline " " bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected" bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected" textline " " bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected" bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected" textline " " bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected" bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected" textline " " bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected" bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected" wgroup.long (0x2070+0xC00)++0x7 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear" bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear" textline " " bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear" bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear" bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear" bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear" bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear" textline " " bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear" bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear" bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear" textline " " bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear" bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear" bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear" bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear" bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear" textline " " bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear" bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear" bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear" textline " " bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear" bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear" bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear" bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear" line.long 0x04 "ICRH,Interrupt Clear Register High" bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear" bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear" textline " " bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear" bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear" textline " " bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear" bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear" bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear" textline " " bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear" bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear" textline " " bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear" bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear" bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear" textline " " bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear" bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear" textline " " bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear" bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear" bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear" textline " " bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear" bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear" textline " " bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear" bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear" bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear" textline " " bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear" bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear" textline " " bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear" bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear" bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear" wgroup.long (0x2078+0xC00)++0x3 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse" tree.end tree "QDMA Registers" rgroup.long (0x2080+0xC00)++0x3 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized" bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized" textline " " bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized" bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized" group.long (0x2084+0xC00)++0x3 line.long 0x00 "QEER,QDMA Event Enable Register" setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled" rgroup.long (0x2090+0xC00)++0x3 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored" bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored" bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored" wgroup.long (0x2094+0xC00)++0x3 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear" tree.end tree.end tree "Shadow Channel Registers for MP Space 7" tree "DMA Channel Registers" width 7. group.long (0x2000+0xE00)++0x7 line.long 0x00 "ER,Event Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event 31" "Not asserted,Asserted" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event 30" "Not asserted,Asserted" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event 29" "Not asserted,Asserted" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event 28" "Not asserted,Asserted" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event 27" "Not asserted,Asserted" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event 26" "Not asserted,Asserted" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event 25" "Not asserted,Asserted" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event 24" "Not asserted,Asserted" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event 23" "Not asserted,Asserted" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event 22" "Not asserted,Asserted" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event 21" "Not asserted,Asserted" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event 20" "Not asserted,Asserted" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event 19" "Not asserted,Asserted" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event 18" "Not asserted,Asserted" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event 17" "Not asserted,Asserted" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event 16" "Not asserted,Asserted" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event 15" "Not asserted,Asserted" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event 14" "Not asserted,Asserted" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event 13" "Not asserted,Asserted" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event 12" "Not asserted,Asserted" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event 11" "Not asserted,Asserted" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event 10" "Not asserted,Asserted" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event 9" "Not asserted,Asserted" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event 8" "Not asserted,Asserted" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event 7" "Not asserted,Asserted" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event 6" "Not asserted,Asserted" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event 5" "Not asserted,Asserted" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event 4" "Not asserted,Asserted" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event 3" "Not asserted,Asserted" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event 2" "Not asserted,Asserted" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event 1" "Not asserted,Asserted" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event 0" "Not asserted,Asserted" line.long 0x04 "ERH,Event Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event 63" "Not asserted,Asserted" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event 62" "Not asserted,Asserted" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event 61" "Not asserted,Asserted" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event 60" "Not asserted,Asserted" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event 59" "Not asserted,Asserted" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event 58" "Not asserted,Asserted" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event 57" "Not asserted,Asserted" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event 56" "Not asserted,Asserted" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event 55" "Not asserted,Asserted" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event 54" "Not asserted,Asserted" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event 53" "Not asserted,Asserted" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event 52" "Not asserted,Asserted" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event 51" "Not asserted,Asserted" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event 50" "Not asserted,Asserted" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event 49" "Not asserted,Asserted" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event 48" "Not asserted,Asserted" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event 47" "Not asserted,Asserted" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event 46" "Not asserted,Asserted" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event 45" "Not asserted,Asserted" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event 44" "Not asserted,Asserted" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event 43" "Not asserted,Asserted" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event 42" "Not asserted,Asserted" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event 41" "Not asserted,Asserted" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event 40" "Not asserted,Asserted" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event 39" "Not asserted,Asserted" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event 38" "Not asserted,Asserted" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event 37" "Not asserted,Asserted" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event 36" "Not asserted,Asserted" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event 35" "Not asserted,Asserted" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event 34" "Not asserted,Asserted" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event 33" "Not asserted,Asserted" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event 32" "Not asserted,Asserted" rgroup.long (0x2018+0xE00)++0x7 line.long 0x00 "ECR,Chained Event Register" bitfld.long 0x00 31. " E31 ,Chained event for event 31" "No effect,Prioritized" bitfld.long 0x00 30. " E30 ,Chained event for event 30" "No effect,Prioritized" bitfld.long 0x00 29. " E29 ,Chained event for event 29" "No effect,Prioritized" textline " " bitfld.long 0x00 28. " E28 ,Chained event for event 28" "No effect,Prioritized" bitfld.long 0x00 27. " E27 ,Chained event for event 27" "No effect,Prioritized" bitfld.long 0x00 26. " E26 ,Chained event for event 26" "No effect,Prioritized" textline " " bitfld.long 0x00 25. " E25 ,Chained event for event 25" "No effect,Prioritized" bitfld.long 0x00 24. " E24 ,Chained event for event 24" "No effect,Prioritized" bitfld.long 0x00 23. " E23 ,Chained event for event 23" "No effect,Prioritized" textline " " bitfld.long 0x00 22. " E22 ,Chained event for event 22" "No effect,Prioritized" bitfld.long 0x00 21. " E21 ,Chained event for event 21" "No effect,Prioritized" bitfld.long 0x00 20. " E20 ,Chained event for event 20" "No effect,Prioritized" textline " " bitfld.long 0x00 19. " E19 ,Chained event for event 19" "No effect,Prioritized" bitfld.long 0x00 18. " E18 ,Chained event for event 18" "No effect,Prioritized" bitfld.long 0x00 17. " E17 ,Chained event for event 17" "No effect,Prioritized" textline " " bitfld.long 0x00 16. " E16 ,Chained event for event 16" "No effect,Prioritized" bitfld.long 0x00 15. " E15 ,Chained event for event 15" "No effect,Prioritized" bitfld.long 0x00 14. " E14 ,Chained event for event 14" "No effect,Prioritized" textline " " bitfld.long 0x00 13. " E13 ,Chained event for event 13" "No effect,Prioritized" bitfld.long 0x00 12. " E12 ,Chained event for event 12" "No effect,Prioritized" bitfld.long 0x00 11. " E11 ,Chained event for event 11" "No effect,Prioritized" textline " " bitfld.long 0x00 10. " E10 ,Chained event for event 10" "No effect,Prioritized" bitfld.long 0x00 9. " E9 ,Chained event for event 9" "No effect,Prioritized" bitfld.long 0x00 8. " E8 ,Chained event for event 8" "No effect,Prioritized" textline " " bitfld.long 0x00 7. " E7 ,Chained event for event 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,Chained event for event 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,Chained event for event 5" "No effect,Prioritized" textline " " bitfld.long 0x00 4. " E4 ,Chained event for event 4" "No effect,Prioritized" bitfld.long 0x00 3. " E3 ,Chained event for event 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,Chained event for event 2" "No effect,Prioritized" textline " " bitfld.long 0x00 1. " E1 ,Chained event for event 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,Chained event for event 0" "No effect,Prioritized" line.long 0x04 "ECRH,Chained Event Register High" bitfld.long 0x04 31. " E63 ,Chained event for event 63" "No effect,Prioritized" bitfld.long 0x04 30. " E62 ,Chained event for event 62" "No effect,Prioritized" bitfld.long 0x04 29. " E61 ,Chained event for event 61" "No effect,Prioritized" textline " " bitfld.long 0x04 28. " E60 ,Chained event for event 60" "No effect,Prioritized" bitfld.long 0x04 27. " E59 ,Chained event for event 59" "No effect,Prioritized" bitfld.long 0x04 26. " E58 ,Chained event for event 58" "No effect,Prioritized" textline " " bitfld.long 0x04 25. " E57 ,Chained event for event 57" "No effect,Prioritized" bitfld.long 0x04 24. " E56 ,Chained event for event 56" "No effect,Prioritized" bitfld.long 0x04 23. " E55 ,Chained event for event 55" "No effect,Prioritized" textline " " bitfld.long 0x04 22. " E54 ,Chained event for event 54" "No effect,Prioritized" bitfld.long 0x04 21. " E53 ,Chained event for event 53" "No effect,Prioritized" bitfld.long 0x04 20. " E52 ,Chained event for event 52" "No effect,Prioritized" textline " " bitfld.long 0x04 19. " E51 ,Chained event for event 51" "No effect,Prioritized" bitfld.long 0x04 18. " E50 ,Chained event for event 50" "No effect,Prioritized" bitfld.long 0x04 17. " E49 ,Chained event for event 49" "No effect,Prioritized" textline " " bitfld.long 0x04 16. " E48 ,Chained event for event 48" "No effect,Prioritized" bitfld.long 0x04 15. " E47 ,Chained event for event 47" "No effect,Prioritized" bitfld.long 0x04 14. " E46 ,Chained event for event 46" "No effect,Prioritized" textline " " bitfld.long 0x04 13. " E45 ,Chained event for event 45" "No effect,Prioritized" bitfld.long 0x04 12. " E44 ,Chained event for event 44" "No effect,Prioritized" bitfld.long 0x04 11. " E43 ,Chained event for event 43" "No effect,Prioritized" textline " " bitfld.long 0x04 10. " E42 ,Chained event for event 42" "No effect,Prioritized" bitfld.long 0x04 9. " E41 ,Chained event for event 41" "No effect,Prioritized" bitfld.long 0x04 8. " E40 ,Chained event for event 40" "No effect,Prioritized" textline " " bitfld.long 0x04 7. " E39 ,Chained event for event 39" "No effect,Prioritized" bitfld.long 0x04 6. " E38 ,Chained event for event 38" "No effect,Prioritized" bitfld.long 0x04 5. " E37 ,Chained event for event 37" "No effect,Prioritized" textline " " bitfld.long 0x04 4. " E36 ,Chained event for event 36" "No effect,Prioritized" bitfld.long 0x04 3. " E35 ,Chained event for event 35" "No effect,Prioritized" bitfld.long 0x04 2. " E34 ,Chained event for event 34" "No effect,Prioritized" textline " " bitfld.long 0x04 1. " E33 ,Chained event for event 33" "No effect,Prioritized" bitfld.long 0x04 0. " E32 ,Chained event for event 32" "No effect,Prioritized" group.long (0x2020+0xE00)++0x7 line.long 0x00 "EER,Event Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event enable 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event enable 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event enable 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event enable 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event enable 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event enable 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event enable 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event enable 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event enable 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event enable 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event enable 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event enable 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event enable 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event enable 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event enable 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event enable 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event enable 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event enable 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event enable 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event enable 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event enable 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event enable 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event enable 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event enable 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Event enable 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Event enable 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Event enable 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Event enable 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event enable 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event enable 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event enable 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event enable 0" "Disabled,Enabled" line.long 0x04 "EERH,Event Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Event enable 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Event enable 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Event enable 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Event enable 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Event enable 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Event enable 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Event enable 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Event enable 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Event enable 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Event enable 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Event enable 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Event enable 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Event enable 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Event enable 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Event enable 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Event enable 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Event enable 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Event enable 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Event enable 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Event enable 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Event enable 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Event enable 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Event enable 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Event enable 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Event enable 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Event enable 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Event enable 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Event enable 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Event enable 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Event enable 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Event enable 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Event enable 32" "Disabled,Enabled" rgroup.long (0x2038+0xE00)++0x7 line.long 0x00 "SER,Secondary Event Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "Not stored,Stored" bitfld.long 0x00 30. " E30 ,Secondary event 30" "Not stored,Stored" bitfld.long 0x00 29. " E29 ,Secondary event 29" "Not stored,Stored" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "Not stored,Stored" bitfld.long 0x00 27. " E27 ,Secondary event 27" "Not stored,Stored" bitfld.long 0x00 26. " E26 ,Secondary event 26" "Not stored,Stored" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "Not stored,Stored" bitfld.long 0x00 24. " E24 ,Secondary event 24" "Not stored,Stored" bitfld.long 0x00 23. " E23 ,Secondary event 23" "Not stored,Stored" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "Not stored,Stored" bitfld.long 0x00 21. " E21 ,Secondary event 21" "Not stored,Stored" bitfld.long 0x00 20. " E20 ,Secondary event 20" "Not stored,Stored" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "Not stored,Stored" bitfld.long 0x00 18. " E18 ,Secondary event 18" "Not stored,Stored" bitfld.long 0x00 17. " E17 ,Secondary event 17" "Not stored,Stored" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "Not stored,Stored" bitfld.long 0x00 15. " E15 ,Secondary event 15" "Not stored,Stored" bitfld.long 0x00 14. " E14 ,Secondary event 14" "Not stored,Stored" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "Not stored,Stored" bitfld.long 0x00 12. " E12 ,Secondary event 12" "Not stored,Stored" bitfld.long 0x00 11. " E11 ,Secondary event 11" "Not stored,Stored" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "Not stored,Stored" bitfld.long 0x00 9. " E9 ,Secondary event 9" "Not stored,Stored" bitfld.long 0x00 8. " E8 ,Secondary event 8" "Not stored,Stored" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,Secondary event 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,Secondary event 5" "Not stored,Stored" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "Not stored,Stored" bitfld.long 0x00 3. " E3 ,Secondary event 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,Secondary event 2" "Not stored,Stored" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,Secondary event 0" "Not stored,Stored" line.long 0x04 "SERH,Secondary Event Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "Not stored,Stored" bitfld.long 0x04 30. " E62 ,Secondary event 62" "Not stored,Stored" bitfld.long 0x04 29. " E61 ,Secondary event 61" "Not stored,Stored" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "Not stored,Stored" bitfld.long 0x04 27. " E59 ,Secondary event 59" "Not stored,Stored" bitfld.long 0x04 26. " E58 ,Secondary event 58" "Not stored,Stored" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "Not stored,Stored" bitfld.long 0x04 24. " E56 ,Secondary event 56" "Not stored,Stored" bitfld.long 0x04 23. " E55 ,Secondary event 55" "Not stored,Stored" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "Not stored,Stored" bitfld.long 0x04 21. " E53 ,Secondary event 53" "Not stored,Stored" bitfld.long 0x04 20. " E52 ,Secondary event 52" "Not stored,Stored" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "Not stored,Stored" bitfld.long 0x04 18. " E50 ,Secondary event 50" "Not stored,Stored" bitfld.long 0x04 17. " E49 ,Secondary event 49" "Not stored,Stored" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "Not stored,Stored" bitfld.long 0x04 15. " E47 ,Secondary event 47" "Not stored,Stored" bitfld.long 0x04 14. " E46 ,Secondary event 46" "Not stored,Stored" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "Not stored,Stored" bitfld.long 0x04 12. " E44 ,Secondary event 44" "Not stored,Stored" bitfld.long 0x04 11. " E43 ,Secondary event 43" "Not stored,Stored" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "Not stored,Stored" bitfld.long 0x04 9. " E41 ,Secondary event 41" "Not stored,Stored" bitfld.long 0x04 8. " E40 ,Secondary event 40" "Not stored,Stored" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "Not stored,Stored" bitfld.long 0x04 6. " E38 ,Secondary event 38" "Not stored,Stored" bitfld.long 0x04 5. " E37 ,Secondary event 37" "Not stored,Stored" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "Not stored,Stored" bitfld.long 0x04 3. " E35 ,Secondary event 35" "Not stored,Stored" bitfld.long 0x04 2. " E34 ,Secondary event 34" "Not stored,Stored" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "Not stored,Stored" bitfld.long 0x04 0. " E32 ,Secondary event 32" "Not stored,Stored" wgroup.long (0x2040+0xE00)++0x7 line.long 0x00 "SECR,Secondary Event Clear Register" bitfld.long 0x00 31. " E31 ,Secondary event 31" "No effect,Clear" bitfld.long 0x00 30. " E30 ,Secondary event 30" "No effect,Clear" bitfld.long 0x00 29. " E29 ,Secondary event 29" "No effect,Clear" textline " " bitfld.long 0x00 28. " E28 ,Secondary event 28" "No effect,Clear" bitfld.long 0x00 27. " E27 ,Secondary event 27" "No effect,Clear" bitfld.long 0x00 26. " E26 ,Secondary event 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " E25 ,Secondary event 25" "No effect,Clear" bitfld.long 0x00 24. " E24 ,Secondary event 24" "No effect,Clear" bitfld.long 0x00 23. " E23 ,Secondary event 23" "No effect,Clear" textline " " bitfld.long 0x00 22. " E22 ,Secondary event 22" "No effect,Clear" bitfld.long 0x00 21. " E21 ,Secondary event 21" "No effect,Clear" bitfld.long 0x00 20. " E20 ,Secondary event 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " E19 ,Secondary event 19" "No effect,Clear" bitfld.long 0x00 18. " E18 ,Secondary event 18" "No effect,Clear" bitfld.long 0x00 17. " E17 ,Secondary event 17" "No effect,Clear" textline " " bitfld.long 0x00 16. " E16 ,Secondary event 16" "No effect,Clear" bitfld.long 0x00 15. " E15 ,Secondary event 15" "No effect,Clear" bitfld.long 0x00 14. " E14 ,Secondary event 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " E13 ,Secondary event 13" "No effect,Clear" bitfld.long 0x00 12. " E12 ,Secondary event 12" "No effect,Clear" bitfld.long 0x00 11. " E11 ,Secondary event 11" "No effect,Clear" textline " " bitfld.long 0x00 10. " E10 ,Secondary event 10" "No effect,Clear" bitfld.long 0x00 9. " E9 ,Secondary event 9" "No effect,Clear" bitfld.long 0x00 8. " E8 ,Secondary event 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " E7 ,Secondary event 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,Secondary event 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,Secondary event 5" "No effect,Clear" textline " " bitfld.long 0x00 4. " E4 ,Secondary event 4" "No effect,Clear" bitfld.long 0x00 3. " E3 ,Secondary event 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,Secondary event 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " E1 ,Secondary event 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,Secondary event 0" "No effect,Clear" line.long 0x04 "SECRH,Secondary Event Clear Register High" bitfld.long 0x04 31. " E63 ,Secondary event 63" "No effect,Clear" bitfld.long 0x04 30. " E62 ,Secondary event 62" "No effect,Clear" bitfld.long 0x04 29. " E61 ,Secondary event 61" "No effect,Clear" textline " " bitfld.long 0x04 28. " E60 ,Secondary event 60" "No effect,Clear" bitfld.long 0x04 27. " E59 ,Secondary event 59" "No effect,Clear" bitfld.long 0x04 26. " E58 ,Secondary event 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " E57 ,Secondary event 57" "No effect,Clear" bitfld.long 0x04 24. " E56 ,Secondary event 56" "No effect,Clear" bitfld.long 0x04 23. " E55 ,Secondary event 55" "No effect,Clear" textline " " bitfld.long 0x04 22. " E54 ,Secondary event 54" "No effect,Clear" bitfld.long 0x04 21. " E53 ,Secondary event 53" "No effect,Clear" bitfld.long 0x04 20. " E52 ,Secondary event 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " E51 ,Secondary event 51" "No effect,Clear" bitfld.long 0x04 18. " E50 ,Secondary event 50" "No effect,Clear" bitfld.long 0x04 17. " E49 ,Secondary event 49" "No effect,Clear" textline " " bitfld.long 0x04 16. " E48 ,Secondary event 48" "No effect,Clear" bitfld.long 0x04 15. " E47 ,Secondary event 47" "No effect,Clear" bitfld.long 0x04 14. " E46 ,Secondary event 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " E45 ,Secondary event 45" "No effect,Clear" bitfld.long 0x04 12. " E44 ,Secondary event 44" "No effect,Clear" bitfld.long 0x04 11. " E43 ,Secondary event 43" "No effect,Clear" textline " " bitfld.long 0x04 10. " E42 ,Secondary event 42" "No effect,Clear" bitfld.long 0x04 9. " E41 ,Secondary event 41" "No effect,Clear" bitfld.long 0x04 8. " E40 ,Secondary event 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " E39 ,Secondary event 39" "No effect,Clear" bitfld.long 0x04 6. " E38 ,Secondary event 38" "No effect,Clear" bitfld.long 0x04 5. " E37 ,Secondary event 37" "No effect,Clear" textline " " bitfld.long 0x04 4. " E36 ,Secondary event 36" "No effect,Clear" bitfld.long 0x04 3. " E35 ,Secondary event 35" "No effect,Clear" bitfld.long 0x04 2. " E34 ,Secondary event 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " E33 ,Secondary event 33" "No effect,Clear" bitfld.long 0x04 0. " E32 ,Secondary event 32" "No effect,Clear" tree.end tree "Interrupt Registers" width 7. group.long (0x2050+0xE00)++0x7 line.long 0x00 "IER,Interrupt Enable Register" setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Interrupt Enable for channel 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Interrupt Enable for channel 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Interrupt Enable for channel 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Interrupt Enable for channel 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Interrupt Enable for channel 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Interrupt Enable for channel 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Interrupt Enable for channel 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Interrupt Enable for channel 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Interrupt Enable for channel 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Interrupt Enable for channel 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Interrupt Enable for channel 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Interrupt Enable for channel 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Interrupt Enable for channel 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Interrupt Enable for channel 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Interrupt Enable for channel 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Interrupt Enable for channel 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Interrupt Enable for channel 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Interrupt Enable for channel 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Interrupt Enable for channel 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Interrupt Enable for channel 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Interrupt Enable for channel 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Interrupt Enable for channel 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Interrupt Enable for channel 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Interrupt Enable for channel 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7_set/clr ,Interrupt Enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6_set/clr ,Interrupt Enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5_set/clr ,Interrupt Enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4_set/clr ,Interrupt Enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Interrupt Enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Interrupt Enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Interrupt Enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Interrupt Enable for channel 0" "Disabled,Enabled" line.long 0x04 "IERH,Interrupt Enable Register High" setclrfld.long 0x04 31. 0x14 31. 0x0c 31. " E63_set/clr ,Interrupt Enable for channel 63" "Disabled,Enabled" setclrfld.long 0x04 30. 0x14 30. 0x0c 30. " E62_set/clr ,Interrupt Enable for channel 62" "Disabled,Enabled" textline " " setclrfld.long 0x04 29. 0x14 29. 0x0c 29. " E61_set/clr ,Interrupt Enable for channel 61" "Disabled,Enabled" setclrfld.long 0x04 28. 0x14 28. 0x0c 28. " E60_set/clr ,Interrupt Enable for channel 60" "Disabled,Enabled" textline " " setclrfld.long 0x04 27. 0x14 27. 0x0c 27. " E59_set/clr ,Interrupt Enable for channel 59" "Disabled,Enabled" setclrfld.long 0x04 26. 0x14 26. 0x0c 26. " E58_set/clr ,Interrupt Enable for channel 58" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x14 25. 0x0c 25. " E57_set/clr ,Interrupt Enable for channel 57" "Disabled,Enabled" setclrfld.long 0x04 24. 0x14 24. 0x0c 24. " E56_set/clr ,Interrupt Enable for channel 56" "Disabled,Enabled" textline " " setclrfld.long 0x04 23. 0x14 23. 0x0c 23. " E55_set/clr ,Interrupt Enable for channel 55" "Disabled,Enabled" setclrfld.long 0x04 22. 0x14 22. 0x0c 22. " E54_set/clr ,Interrupt Enable for channel 54" "Disabled,Enabled" textline " " setclrfld.long 0x04 21. 0x14 21. 0x0c 21. " E53_set/clr ,Interrupt Enable for channel 53" "Disabled,Enabled" setclrfld.long 0x04 20. 0x14 20. 0x0c 20. " E52_set/clr ,Interrupt Enable for channel 52" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x14 19. 0x0c 19. " E51_set/clr ,Interrupt Enable for channel 51" "Disabled,Enabled" setclrfld.long 0x04 18. 0x14 18. 0x0c 18. " E50_set/clr ,Interrupt Enable for channel 50" "Disabled,Enabled" textline " " setclrfld.long 0x04 17. 0x14 17. 0x0c 17. " E49_set/clr ,Interrupt Enable for channel 49" "Disabled,Enabled" setclrfld.long 0x04 16. 0x14 16. 0x0c 16. " E48_set/clr ,Interrupt Enable for channel 48" "Disabled,Enabled" textline " " setclrfld.long 0x04 15. 0x14 15. 0x0c 15. " E47_set/clr ,Interrupt Enable for channel 47" "Disabled,Enabled" setclrfld.long 0x04 14. 0x14 14. 0x0c 14. " E46_set/clr ,Interrupt Enable for channel 46" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x14 13. 0x0c 13. " E45_set/clr ,Interrupt Enable for channel 45" "Disabled,Enabled" setclrfld.long 0x04 12. 0x14 12. 0x0c 12. " E44_set/clr ,Interrupt Enable for channel 44" "Disabled,Enabled" textline " " setclrfld.long 0x04 11. 0x14 11. 0x0c 11. " E43_set/clr ,Interrupt Enable for channel 43" "Disabled,Enabled" setclrfld.long 0x04 10. 0x14 10. 0x0c 10. " E42_set/clr ,Interrupt Enable for channel 42" "Disabled,Enabled" textline " " setclrfld.long 0x04 9. 0x14 9. 0x0c 9. " E41_set/clr ,Interrupt Enable for channel 41" "Disabled,Enabled" setclrfld.long 0x04 8. 0x14 8. 0x0c 8. " E40_set/clr ,Interrupt Enable for channel 40" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x14 7. 0x0c 7. " E39_set/clr ,Interrupt Enable for channel 39" "Disabled,Enabled" setclrfld.long 0x04 6. 0x14 6. 0x0c 6. " E38_set/clr ,Interrupt Enable for channel 38" "Disabled,Enabled" textline " " setclrfld.long 0x04 5. 0x14 5. 0x0c 5. " E37_set/clr ,Interrupt Enable for channel 37" "Disabled,Enabled" setclrfld.long 0x04 4. 0x14 4. 0x0c 4. " E36_set/clr ,Interrupt Enable for channel 36" "Disabled,Enabled" textline " " setclrfld.long 0x04 3. 0x14 3. 0x0c 3. " E35_set/clr ,Interrupt Enable for channel 35" "Disabled,Enabled" setclrfld.long 0x04 2. 0x14 2. 0x0c 2. " E34_set/clr ,Interrupt Enable for channel 34" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x14 1. 0x0c 1. " E33_set/clr ,Interrupt Enable for channel 33" "Disabled,Enabled" setclrfld.long 0x04 0. 0x14 0. 0x0c 0. " E32_set/clr ,Interrupt Enable for channel 32" "Disabled,Enabled" rgroup.long (0x2068+0xE00)++0x7 line.long 0x00 "IPR,Interrupt Pending Register" bitfld.long 0x00 31. " I31 ,Interrupt transfer completion code 31 detected" "Not detected,Detected" bitfld.long 0x00 30. " I30 ,Interrupt transfer completion code 30 detected" "Not detected,Detected" textline " " bitfld.long 0x00 29. " I29 ,Interrupt transfer completion code 29 detected" "Not detected,Detected" bitfld.long 0x00 28. " I28 ,Interrupt transfer completion code 28 detected" "Not detected,Detected" textline " " bitfld.long 0x00 27. " I27 ,Interrupt transfer completion code 27 detected" "Not detected,Detected" bitfld.long 0x00 26. " I26 ,Interrupt transfer completion code 26 detected" "Not detected,Detected" textline " " bitfld.long 0x00 25. " I25 ,Interrupt transfer completion code 25 detected" "Not detected,Detected" bitfld.long 0x00 24. " I24 ,Interrupt transfer completion code 24 detected" "Not detected,Detected" textline " " bitfld.long 0x00 23. " I23 ,Interrupt transfer completion code 23 detected" "Not detected,Detected" bitfld.long 0x00 22. " I22 ,Interrupt transfer completion code 22 detected" "Not detected,Detected" textline " " bitfld.long 0x00 21. " I21 ,Interrupt transfer completion code 21 detected" "Not detected,Detected" bitfld.long 0x00 20. " I20 ,Interrupt transfer completion code 20 detected" "Not detected,Detected" textline " " bitfld.long 0x00 19. " I19 ,Interrupt transfer completion code 19 detected" "Not detected,Detected" bitfld.long 0x00 18. " I18 ,Interrupt transfer completion code 18 detected" "Not detected,Detected" textline " " bitfld.long 0x00 17. " I17 ,Interrupt transfer completion code 17 detected" "Not detected,Detected" bitfld.long 0x00 16. " I16 ,Interrupt transfer completion code 16 detected" "Not detected,Detected" textline " " bitfld.long 0x00 15. " I15 ,Interrupt transfer completion code 15 detected" "Not detected,Detected" bitfld.long 0x00 14. " I14 ,Interrupt transfer completion code 14 detected" "Not detected,Detected" textline " " bitfld.long 0x00 13. " I13 ,Interrupt transfer completion code 13 detected" "Not detected,Detected" bitfld.long 0x00 12. " I12 ,Interrupt transfer completion code 12 detected" "Not detected,Detected" textline " " bitfld.long 0x00 11. " I11 ,Interrupt transfer completion code 11 detected" "Not detected,Detected" bitfld.long 0x00 10. " I10 ,Interrupt transfer completion code 10 detected" "Not detected,Detected" textline " " bitfld.long 0x00 9. " I9 ,Interrupt transfer completion code 9 detected" "Not detected,Detected" bitfld.long 0x00 8. " I8 ,Interrupt transfer completion code 8 detected" "Not detected,Detected" textline " " bitfld.long 0x00 7. " I7 ,Interrupt transfer completion code 7 detected" "Not detected,Detected" bitfld.long 0x00 6. " I6 ,Interrupt transfer completion code 6 detected" "Not detected,Detected" textline " " bitfld.long 0x00 5. " I5 ,Interrupt transfer completion code 5 detected" "Not detected,Detected" bitfld.long 0x00 4. " I4 ,Interrupt transfer completion code 4 detected" "Not detected,Detected" textline " " bitfld.long 0x00 3. " I3 ,Interrupt transfer completion code 3 detected" "Not detected,Detected" bitfld.long 0x00 2. " I2 ,Interrupt transfer completion code 2 detected" "Not detected,Detected" textline " " bitfld.long 0x00 1. " I1 ,Interrupt transfer completion code 1 detected" "Not detected,Detected" bitfld.long 0x00 0. " I0 ,Interrupt transfer completion code 0 detected" "Not detected,Detected" line.long 0x04 "IPRH,Interrupt Pending Register High" bitfld.long 0x04 31. " I63 ,Interrupt transfer completion code 63 detected" "Not detected,Detected" bitfld.long 0x04 30. " I62 ,Interrupt transfer completion code 62 detected" "Not detected,Detected" textline " " bitfld.long 0x04 29. " I61 ,Interrupt transfer completion code 61 detected" "Not detected,Detected" bitfld.long 0x04 28. " I60 ,Interrupt transfer completion code 60 detected" "Not detected,Detected" textline " " bitfld.long 0x04 27. " I59 ,Interrupt transfer completion code 59 detected" "Not detected,Detected" bitfld.long 0x04 26. " I58 ,Interrupt transfer completion code 58 detected" "Not detected,Detected" textline " " bitfld.long 0x04 25. " I57 ,Interrupt transfer completion code 57 detected" "Not detected,Detected" bitfld.long 0x04 24. " I56 ,Interrupt transfer completion code 56 detected" "Not detected,Detected" textline " " bitfld.long 0x04 23. " I55 ,Interrupt transfer completion code 55 detected" "Not detected,Detected" bitfld.long 0x04 22. " I54 ,Interrupt transfer completion code 54 detected" "Not detected,Detected" textline " " bitfld.long 0x04 21. " I53 ,Interrupt transfer completion code 53 detected" "Not detected,Detected" bitfld.long 0x04 20. " I52 ,Interrupt transfer completion code 52 detected" "Not detected,Detected" textline " " bitfld.long 0x04 19. " I51 ,Interrupt transfer completion code 51 detected" "Not detected,Detected" bitfld.long 0x04 18. " I50 ,Interrupt transfer completion code 50 detected" "Not detected,Detected" textline " " bitfld.long 0x04 17. " I49 ,Interrupt transfer completion code 49 detected" "Not detected,Detected" bitfld.long 0x04 16. " I48 ,Interrupt transfer completion code 48 detected" "Not detected,Detected" textline " " bitfld.long 0x04 15. " I47 ,Interrupt transfer completion code 47 detected" "Not detected,Detected" bitfld.long 0x04 14. " I46 ,Interrupt transfer completion code 46 detected" "Not detected,Detected" textline " " bitfld.long 0x04 13. " I45 ,Interrupt transfer completion code 45 detected" "Not detected,Detected" bitfld.long 0x04 12. " I44 ,Interrupt transfer completion code 44 detected" "Not detected,Detected" textline " " bitfld.long 0x04 11. " I43 ,Interrupt transfer completion code 43 detected" "Not detected,Detected" bitfld.long 0x04 10. " I42 ,Interrupt transfer completion code 42 detected" "Not detected,Detected" textline " " bitfld.long 0x04 9. " I41 ,Interrupt transfer completion code 41 detected" "Not detected,Detected" bitfld.long 0x04 8. " I40 ,Interrupt transfer completion code 40 detected" "Not detected,Detected" textline " " bitfld.long 0x04 7. " I39 ,Interrupt transfer completion code 39 detected" "Not detected,Detected" bitfld.long 0x04 6. " I38 ,Interrupt transfer completion code 38 detected" "Not detected,Detected" textline " " bitfld.long 0x04 5. " I37 ,Interrupt transfer completion code 37 detected" "Not detected,Detected" bitfld.long 0x04 4. " I36 ,Interrupt transfer completion code 36 detected" "Not detected,Detected" textline " " bitfld.long 0x04 3. " I35 ,Interrupt transfer completion code 35 detected" "Not detected,Detected" bitfld.long 0x04 2. " I34 ,Interrupt transfer completion code 34 detected" "Not detected,Detected" textline " " bitfld.long 0x04 1. " I33 ,Interrupt transfer completion code 33 detected" "Not detected,Detected" bitfld.long 0x04 0. " I32 ,Interrupt transfer completion code 32 detected" "Not detected,Detected" wgroup.long (0x2070+0xE00)++0x7 line.long 0x00 "ICR,Interrupt Clear Register" bitfld.long 0x00 31. " I31 ,Interrupt clear for TCC = 31" "No effect,Clear" bitfld.long 0x00 30. " I30 ,Interrupt clear for TCC = 30" "No effect,Clear" textline " " bitfld.long 0x00 29. " I29 ,Interrupt clear for TCC = 29" "No effect,Clear" bitfld.long 0x00 28. " I28 ,Interrupt clear for TCC = 28" "No effect,Clear" textline " " bitfld.long 0x00 27. " I27 ,Interrupt clear for TCC = 27" "No effect,Clear" bitfld.long 0x00 26. " I26 ,Interrupt clear for TCC = 26" "No effect,Clear" textline " " bitfld.long 0x00 25. " I25 ,Interrupt clear for TCC = 25" "No effect,Clear" bitfld.long 0x00 24. " I24 ,Interrupt clear for TCC = 24" "No effect,Clear" textline " " bitfld.long 0x00 23. " I23 ,Interrupt clear for TCC = 23" "No effect,Clear" bitfld.long 0x00 22. " I22 ,Interrupt clear for TCC = 22" "No effect,Clear" textline " " bitfld.long 0x00 21. " I21 ,Interrupt clear for TCC = 21" "No effect,Clear" bitfld.long 0x00 20. " I20 ,Interrupt clear for TCC = 20" "No effect,Clear" textline " " bitfld.long 0x00 19. " I19 ,Interrupt clear for TCC = 19" "No effect,Clear" bitfld.long 0x00 18. " I18 ,Interrupt clear for TCC = 18" "No effect,Clear" textline " " bitfld.long 0x00 17. " I17 ,Interrupt clear for TCC = 17" "No effect,Clear" bitfld.long 0x00 16. " I16 ,Interrupt clear for TCC = 16" "No effect,Clear" textline " " bitfld.long 0x00 15. " I15 ,Interrupt clear for TCC = 15" "No effect,Clear" bitfld.long 0x00 14. " I14 ,Interrupt clear for TCC = 14" "No effect,Clear" textline " " bitfld.long 0x00 13. " I13 ,Interrupt clear for TCC = 13" "No effect,Clear" bitfld.long 0x00 12. " I12 ,Interrupt clear for TCC = 12" "No effect,Clear" textline " " bitfld.long 0x00 11. " I11 ,Interrupt clear for TCC = 11" "No effect,Clear" bitfld.long 0x00 10. " I10 ,Interrupt clear for TCC = 10" "No effect,Clear" textline " " bitfld.long 0x00 9. " I9 ,Interrupt clear for TCC = 9" "No effect,Clear" bitfld.long 0x00 8. " I8 ,Interrupt clear for TCC = 8" "No effect,Clear" textline " " bitfld.long 0x00 7. " I7 ,Interrupt clear for TCC = 7" "No effect,Clear" bitfld.long 0x00 6. " I6 ,Interrupt clear for TCC = 6" "No effect,Clear" textline " " bitfld.long 0x00 5. " I5 ,Interrupt clear for TCC = 5" "No effect,Clear" bitfld.long 0x00 4. " I4 ,Interrupt clear for TCC = 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " I3 ,Interrupt clear for TCC = 3" "No effect,Clear" bitfld.long 0x00 2. " I2 ,Interrupt clear for TCC = 2" "No effect,Clear" textline " " bitfld.long 0x00 1. " I1 ,Interrupt clear for TCC = 1" "No effect,Clear" bitfld.long 0x00 0. " I0 ,Interrupt clear for TCC = 0" "No effect,Clear" line.long 0x04 "ICRH,Interrupt Clear Register High" bitfld.long 0x04 31. " I63 ,Interrupt clear for TCC = 63" "No effect,Clear" bitfld.long 0x04 30. " I62 ,Interrupt clear for TCC = 62" "No effect,Clear" textline " " bitfld.long 0x04 29. " I61 ,Interrupt clear for TCC = 61" "No effect,Clear" bitfld.long 0x04 28. " I60 ,Interrupt clear for TCC = 60" "No effect,Clear" textline " " bitfld.long 0x04 27. " I59 ,Interrupt clear for TCC = 59" "No effect,Clear" bitfld.long 0x04 26. " I58 ,Interrupt clear for TCC = 58" "No effect,Clear" textline " " bitfld.long 0x04 25. " I57 ,Interrupt clear for TCC = 57" "No effect,Clear" bitfld.long 0x04 24. " I56 ,Interrupt clear for TCC = 56" "No effect,Clear" textline " " bitfld.long 0x04 23. " I55 ,Interrupt clear for TCC = 55" "No effect,Clear" bitfld.long 0x04 22. " I54 ,Interrupt clear for TCC = 54" "No effect,Clear" textline " " bitfld.long 0x04 21. " I53 ,Interrupt clear for TCC = 53" "No effect,Clear" bitfld.long 0x04 20. " I52 ,Interrupt clear for TCC = 52" "No effect,Clear" textline " " bitfld.long 0x04 19. " I51 ,Interrupt clear for TCC = 51" "No effect,Clear" bitfld.long 0x04 18. " I50 ,Interrupt clear for TCC = 50" "No effect,Clear" textline " " bitfld.long 0x04 17. " I49 ,Interrupt clear for TCC = 49" "No effect,Clear" bitfld.long 0x04 16. " I48 ,Interrupt clear for TCC = 48" "No effect,Clear" textline " " bitfld.long 0x04 15. " I47 ,Interrupt clear for TCC = 47" "No effect,Clear" bitfld.long 0x04 14. " I46 ,Interrupt clear for TCC = 46" "No effect,Clear" textline " " bitfld.long 0x04 13. " I45 ,Interrupt clear for TCC = 45" "No effect,Clear" bitfld.long 0x04 12. " I44 ,Interrupt clear for TCC = 44" "No effect,Clear" textline " " bitfld.long 0x04 11. " I43 ,Interrupt clear for TCC = 43" "No effect,Clear" bitfld.long 0x04 10. " I42 ,Interrupt clear for TCC = 42" "No effect,Clear" textline " " bitfld.long 0x04 9. " I41 ,Interrupt clear for TCC = 41" "No effect,Clear" bitfld.long 0x04 8. " I40 ,Interrupt clear for TCC = 40" "No effect,Clear" textline " " bitfld.long 0x04 7. " I39 ,Interrupt clear for TCC = 39" "No effect,Clear" bitfld.long 0x04 6. " I38 ,Interrupt clear for TCC = 38" "No effect,Clear" textline " " bitfld.long 0x04 5. " I37 ,Interrupt clear for TCC = 37" "No effect,Clear" bitfld.long 0x04 4. " I36 ,Interrupt clear for TCC = 36" "No effect,Clear" textline " " bitfld.long 0x04 3. " I35 ,Interrupt clear for TCC = 35" "No effect,Clear" bitfld.long 0x04 2. " I34 ,Interrupt clear for TCC = 34" "No effect,Clear" textline " " bitfld.long 0x04 1. " I33 ,Interrupt clear for TCC = 33" "No effect,Clear" bitfld.long 0x04 0. " I32 ,Interrupt clear for TCC = 32" "No effect,Clear" wgroup.long (0x2078+0xE00)++0x3 line.long 0x00 "IEVAL,Interrupt Evaluate Register" bitfld.long 0x00 0. " IEVAL ,Interrupt evaluate" "No effect,Pulse" tree.end tree "QDMA Registers" rgroup.long (0x2080+0xE00)++0x3 line.long 0x00 "QER,QDMA Event Register" bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized" bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized" bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized" bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized" textline " " bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized" bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized" bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized" bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized" group.long (0x2084+0xE00)++0x3 line.long 0x00 "QEER,QDMA Event Enable Register" setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled" rgroup.long (0x2090+0xE00)++0x3 line.long 0x00 "QSER,QDMA Secondary Event Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event for channel 7" "Not stored,Stored" bitfld.long 0x00 6. " E6 ,QDMA secondary event for channel 6" "Not stored,Stored" bitfld.long 0x00 5. " E5 ,QDMA secondary event for channel 5" "Not stored,Stored" bitfld.long 0x00 4. " E4 ,QDMA secondary event for channel 4" "Not stored,Stored" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event for channel 3" "Not stored,Stored" bitfld.long 0x00 2. " E2 ,QDMA secondary event for channel 2" "Not stored,Stored" bitfld.long 0x00 1. " E1 ,QDMA secondary event for channel 1" "Not stored,Stored" bitfld.long 0x00 0. " E0 ,QDMA secondary event for channel 0" "Not stored,Stored" wgroup.long (0x2094+0xE00)++0x3 line.long 0x00 "QSECR,QDMA Secondary Event Clear Register" bitfld.long 0x00 7. " E7 ,QDMA secondary event clear for channel 7" "No effect,Clear" bitfld.long 0x00 6. " E6 ,QDMA secondary event clear for channel 6" "No effect,Clear" bitfld.long 0x00 5. " E5 ,QDMA secondary event clear for channel 5" "No effect,Clear" bitfld.long 0x00 4. " E4 ,QDMA secondary event clear for channel 4" "No effect,Clear" textline " " bitfld.long 0x00 3. " E3 ,QDMA secondary event clear for channel 3" "No effect,Clear" bitfld.long 0x00 2. " E2 ,QDMA secondary event clear for channel 2" "No effect,Clear" bitfld.long 0x00 1. " E1 ,QDMA secondary event clear for channel 1" "No effect,Clear" bitfld.long 0x00 0. " E0 ,QDMA secondary event clear for channel 0" "No effect,Clear" tree.end tree.end endif width 0x0b tree.end tree "EDMA TPTC0 (EDMA Transfer Controller Control Registers)" base ad:0x49800000 width 8. rgroup.long 0x00++0x7 line.long 0x00 "PID,Peripheral Identifier" line.long 0x04 "TCCFG,EDMA3TC Configuration Register" bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..." bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..." bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..." rgroup.long 0x100++0x3 line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register" bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3" bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..." bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy" bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy" tree "Error Registers" width 9. sif (cpuis("DRA62*")) rgroup.long 0x120++0x3 line.long 0x00 "ERRSTAT,Error Register" bitfld.long 0x00 3. " MMRAERR ,MMR address error" "Not detected,Detected" bitfld.long 0x00 2. " TRERR ,Transfer request error event" "Not detected,Detected" bitfld.long 0x00 0. " BUSERR ,Bus error event" "Not detected,Detected" group.long 0x124++0x3 line.long 0x00 "ERREN,Error Enable Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled" bitfld.long 0x00 2. " TRERR ,Interrupt enable for Transfer request error event" "Disabled,Enabled" bitfld.long 0x00 0. " BUSERR ,Interrupt enable for Bus error event" "Disabled,Enabled" wgroup.long 0x128++0x3 line.long 0x00 "ERRCLR,Error Clear Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt clear for MMR address error" "No effect,Clear" bitfld.long 0x00 2. " TRERR ,Interrupt clear for Transfer request error event" "No effect,Clear" bitfld.long 0x00 0. " BUSERR ,Interrupt clear for Bus error event" "No effect,Clear" else group.long 0x120++0x3 line.long 0x00 "ERRSTAT,Error Register" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "Not detected,Detected" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,Transfer request error event" "Not detected,Detected" setclrfld.long 0x00 0. 0x04 0. 0x04 0. " BUSERR ,Bus error event" "Not detected,Detected" endif rgroup.long 0x12c++0x3 line.long 0x00 "ERRDET,Error Details Register" bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled" bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error" wgroup.long 0x130++0x3 line.long 0x00 "ERRCMD,Error Interrupt Command Register" bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed" group.long 0x140++0x3 line.long 0x00 "RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. " RDRATE ,Read rate - number of cycles between read commands" "0 cycles,4 cycles,8 cycles,16 cycles,32 cycles,?..." tree.end tree "EDMA3TC Channel Registers" width 11. group.long 0x240++0x3 "Source Active Registers" line.long 0x00 "SAOPT,Source Active Options Register" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" rgroup.long 0x244++0x07 line.long 0x00 "SASRC,Source Active Source Address Register" line.long 0x04 "SACNT,Source Active Count Register" hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count" hgroup.long 0x24c++0x03 hide.long 0x00 "SADST,Source Active Destination Address Register" rgroup.long 0x250++0x0f line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register" hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register" bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x04 0.--3. 1. " PRIVID ,Privilege ID" line.long 0x08 "SACNTRLD,Source Active Count Reload Register" hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value" line.long 0x0c "SASRCBREF,Source Active Source Address B-Reference Register" hgroup.long 0x260++0x03 hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register" rgroup.long 0x280++0x03 "Destination FIFO Registers" line.long 0x00 "DFCNTRLD,Destination FIFO Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value" hgroup.long 0x284++0x03 hide.long 0x00 "DFSRCBREF,Destination FIFO Source Address B-Reference Register" rgroup.long 0x288++0x03 line.long 0x00 "DFDSTBREF,Destination FIFO Destination Address B-Reference Register" group.long 0x300++0x3 line.long 0x00 "DFOPT0,Destination FIFO Options Register 0" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x300+0x4)++0x3 hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0" rgroup.long (0x300+0x8)++0xF line.long 0x00 "DFCNT0,Destination FIFO Count Register 0" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST0,Destination FIFO Destination Address Register 0" line.long 0x08 "DFBIDX0,Destination FIFO B-Dimension Index Register 0" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" group.long 0x340++0x3 line.long 0x00 "DFOPT1,Destination FIFO Options Register 1" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x340+0x4)++0x3 hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1" rgroup.long (0x340+0x8)++0xF line.long 0x00 "DFCNT1,Destination FIFO Count Register 1" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST1,Destination FIFO Destination Address Register 1" line.long 0x08 "DFBIDX1,Destination FIFO B-Dimension Index Register 1" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" group.long 0x380++0x3 line.long 0x00 "DFOPT2,Destination FIFO Options Register 2" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x380+0x4)++0x3 hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2" rgroup.long (0x380+0x8)++0xF line.long 0x00 "DFCNT2,Destination FIFO Count Register 2" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST2,Destination FIFO Destination Address Register 2" line.long 0x08 "DFBIDX2,Destination FIFO B-Dimension Index Register 2" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" group.long 0x3C0++0x3 line.long 0x00 "DFOPT3,Destination FIFO Options Register 3" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x3C0+0x4)++0x3 hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3" rgroup.long (0x3C0+0x8)++0xF line.long 0x00 "DFCNT3,Destination FIFO Count Register 3" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST3,Destination FIFO Destination Address Register 3" line.long 0x08 "DFBIDX3,Destination FIFO B-Dimension Index Register 3" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" tree.end tree.end tree "EDMA TPTC1 (EDMA Transfer Controller Control Registers)" base ad:0x49900000 width 8. rgroup.long 0x00++0x7 line.long 0x00 "PID,Peripheral Identifier" line.long 0x04 "TCCFG,EDMA3TC Configuration Register" bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..." bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..." bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..." rgroup.long 0x100++0x3 line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register" bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3" bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..." bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy" bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy" tree "Error Registers" width 9. sif (cpuis("DRA62*")) rgroup.long 0x120++0x3 line.long 0x00 "ERRSTAT,Error Register" bitfld.long 0x00 3. " MMRAERR ,MMR address error" "Not detected,Detected" bitfld.long 0x00 2. " TRERR ,Transfer request error event" "Not detected,Detected" bitfld.long 0x00 0. " BUSERR ,Bus error event" "Not detected,Detected" group.long 0x124++0x3 line.long 0x00 "ERREN,Error Enable Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled" bitfld.long 0x00 2. " TRERR ,Interrupt enable for Transfer request error event" "Disabled,Enabled" bitfld.long 0x00 0. " BUSERR ,Interrupt enable for Bus error event" "Disabled,Enabled" wgroup.long 0x128++0x3 line.long 0x00 "ERRCLR,Error Clear Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt clear for MMR address error" "No effect,Clear" bitfld.long 0x00 2. " TRERR ,Interrupt clear for Transfer request error event" "No effect,Clear" bitfld.long 0x00 0. " BUSERR ,Interrupt clear for Bus error event" "No effect,Clear" else group.long 0x120++0x3 line.long 0x00 "ERRSTAT,Error Register" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "Not detected,Detected" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,Transfer request error event" "Not detected,Detected" setclrfld.long 0x00 0. 0x04 0. 0x04 0. " BUSERR ,Bus error event" "Not detected,Detected" endif rgroup.long 0x12c++0x3 line.long 0x00 "ERRDET,Error Details Register" bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled" bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error" wgroup.long 0x130++0x3 line.long 0x00 "ERRCMD,Error Interrupt Command Register" bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed" group.long 0x140++0x3 line.long 0x00 "RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. " RDRATE ,Read rate - number of cycles between read commands" "0 cycles,4 cycles,8 cycles,16 cycles,32 cycles,?..." tree.end tree "EDMA3TC Channel Registers" width 11. group.long 0x240++0x3 "Source Active Registers" line.long 0x00 "SAOPT,Source Active Options Register" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" rgroup.long 0x244++0x07 line.long 0x00 "SASRC,Source Active Source Address Register" line.long 0x04 "SACNT,Source Active Count Register" hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count" hgroup.long 0x24c++0x03 hide.long 0x00 "SADST,Source Active Destination Address Register" rgroup.long 0x250++0x0f line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register" hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register" bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x04 0.--3. 1. " PRIVID ,Privilege ID" line.long 0x08 "SACNTRLD,Source Active Count Reload Register" hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value" line.long 0x0c "SASRCBREF,Source Active Source Address B-Reference Register" hgroup.long 0x260++0x03 hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register" rgroup.long 0x280++0x03 "Destination FIFO Registers" line.long 0x00 "DFCNTRLD,Destination FIFO Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value" hgroup.long 0x284++0x03 hide.long 0x00 "DFSRCBREF,Destination FIFO Source Address B-Reference Register" rgroup.long 0x288++0x03 line.long 0x00 "DFDSTBREF,Destination FIFO Destination Address B-Reference Register" group.long 0x300++0x3 line.long 0x00 "DFOPT0,Destination FIFO Options Register 0" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x300+0x4)++0x3 hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0" rgroup.long (0x300+0x8)++0xF line.long 0x00 "DFCNT0,Destination FIFO Count Register 0" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST0,Destination FIFO Destination Address Register 0" line.long 0x08 "DFBIDX0,Destination FIFO B-Dimension Index Register 0" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" group.long 0x340++0x3 line.long 0x00 "DFOPT1,Destination FIFO Options Register 1" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x340+0x4)++0x3 hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1" rgroup.long (0x340+0x8)++0xF line.long 0x00 "DFCNT1,Destination FIFO Count Register 1" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST1,Destination FIFO Destination Address Register 1" line.long 0x08 "DFBIDX1,Destination FIFO B-Dimension Index Register 1" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" group.long 0x380++0x3 line.long 0x00 "DFOPT2,Destination FIFO Options Register 2" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x380+0x4)++0x3 hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2" rgroup.long (0x380+0x8)++0xF line.long 0x00 "DFCNT2,Destination FIFO Count Register 2" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST2,Destination FIFO Destination Address Register 2" line.long 0x08 "DFBIDX2,Destination FIFO B-Dimension Index Register 2" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" group.long 0x3C0++0x3 line.long 0x00 "DFOPT3,Destination FIFO Options Register 3" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x3C0+0x4)++0x3 hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3" rgroup.long (0x3C0+0x8)++0xF line.long 0x00 "DFCNT3,Destination FIFO Count Register 3" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST3,Destination FIFO Destination Address Register 3" line.long 0x08 "DFBIDX3,Destination FIFO B-Dimension Index Register 3" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" tree.end tree.end tree "EDMA TPTC2 (EDMA Transfer Controller Control Registers)" base ad:0x49A00000 width 8. rgroup.long 0x00++0x7 line.long 0x00 "PID,Peripheral Identifier" line.long 0x04 "TCCFG,EDMA3TC Configuration Register" bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..." bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..." bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..." rgroup.long 0x100++0x3 line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register" bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3" bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..." bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy" bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy" tree "Error Registers" width 9. sif (cpuis("DRA62*")) rgroup.long 0x120++0x3 line.long 0x00 "ERRSTAT,Error Register" bitfld.long 0x00 3. " MMRAERR ,MMR address error" "Not detected,Detected" bitfld.long 0x00 2. " TRERR ,Transfer request error event" "Not detected,Detected" bitfld.long 0x00 0. " BUSERR ,Bus error event" "Not detected,Detected" group.long 0x124++0x3 line.long 0x00 "ERREN,Error Enable Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt enable for MMR address error" "Disabled,Enabled" bitfld.long 0x00 2. " TRERR ,Interrupt enable for Transfer request error event" "Disabled,Enabled" bitfld.long 0x00 0. " BUSERR ,Interrupt enable for Bus error event" "Disabled,Enabled" wgroup.long 0x128++0x3 line.long 0x00 "ERRCLR,Error Clear Register" bitfld.long 0x00 3. " MMRAERR ,Interrupt clear for MMR address error" "No effect,Clear" bitfld.long 0x00 2. " TRERR ,Interrupt clear for Transfer request error event" "No effect,Clear" bitfld.long 0x00 0. " BUSERR ,Interrupt clear for Bus error event" "No effect,Clear" else group.long 0x120++0x3 line.long 0x00 "ERRSTAT,Error Register" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "Not detected,Detected" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,Transfer request error event" "Not detected,Detected" setclrfld.long 0x00 0. 0x04 0. 0x04 0. " BUSERR ,Bus error event" "Not detected,Detected" endif rgroup.long 0x12c++0x3 line.long 0x00 "ERRDET,Error Details Register" bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled" bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error" wgroup.long 0x130++0x3 line.long 0x00 "ERRCMD,Error Interrupt Command Register" bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Pulsed" group.long 0x140++0x3 line.long 0x00 "RDRATE,Read Rate Register" bitfld.long 0x00 0.--2. " RDRATE ,Read rate - number of cycles between read commands" "0 cycles,4 cycles,8 cycles,16 cycles,32 cycles,?..." tree.end tree "EDMA3TC Channel Registers" width 11. group.long 0x240++0x3 "Source Active Registers" line.long 0x00 "SAOPT,Source Active Options Register" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" rgroup.long 0x244++0x07 line.long 0x00 "SASRC,Source Active Source Address Register" line.long 0x04 "SACNT,Source Active Count Register" hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count" hgroup.long 0x24c++0x03 hide.long 0x00 "SADST,Source Active Destination Address Register" rgroup.long 0x250++0x0f line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register" hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register" bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x04 0.--3. 1. " PRIVID ,Privilege ID" line.long 0x08 "SACNTRLD,Source Active Count Reload Register" hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value" line.long 0x0c "SASRCBREF,Source Active Source Address B-Reference Register" hgroup.long 0x260++0x03 hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register" rgroup.long 0x280++0x03 "Destination FIFO Registers" line.long 0x00 "DFCNTRLD,Destination FIFO Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value" hgroup.long 0x284++0x03 hide.long 0x00 "DFSRCBREF,Destination FIFO Source Address B-Reference Register" rgroup.long 0x288++0x03 line.long 0x00 "DFDSTBREF,Destination FIFO Destination Address B-Reference Register" group.long 0x300++0x3 line.long 0x00 "DFOPT0,Destination FIFO Options Register 0" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x300+0x4)++0x3 hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register 0" rgroup.long (0x300+0x8)++0xF line.long 0x00 "DFCNT0,Destination FIFO Count Register 0" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST0,Destination FIFO Destination Address Register 0" line.long 0x08 "DFBIDX0,Destination FIFO B-Dimension Index Register 0" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register 0" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" group.long 0x340++0x3 line.long 0x00 "DFOPT1,Destination FIFO Options Register 1" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x340+0x4)++0x3 hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register 1" rgroup.long (0x340+0x8)++0xF line.long 0x00 "DFCNT1,Destination FIFO Count Register 1" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST1,Destination FIFO Destination Address Register 1" line.long 0x08 "DFBIDX1,Destination FIFO B-Dimension Index Register 1" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register 1" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" group.long 0x380++0x3 line.long 0x00 "DFOPT2,Destination FIFO Options Register 2" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x380+0x4)++0x3 hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register 2" rgroup.long (0x380+0x8)++0xF line.long 0x00 "DFCNT2,Destination FIFO Count Register 2" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST2,Destination FIFO Destination Address Register 2" line.long 0x08 "DFBIDX2,Destination FIFO B-Dimension Index Register 2" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register 2" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" group.long 0x3C0++0x3 line.long 0x00 "DFOPT3,Destination FIFO Options Register 3" bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled" bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled" hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code" textline " " bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..." bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST" textline " " bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST" hgroup.long (0x3C0+0x4)++0x3 hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register 3" rgroup.long (0x3C0+0x8)++0xF line.long 0x00 "DFCNT3,Destination FIFO Count Register 3" hexmask.long.word 0x00 16.--31. 1. " BCNT ,B dimension count" hexmask.long.word 0x00 0.--15. 1. " ACNT ,A dimension count" line.long 0x04 "DFDST3,Destination FIFO Destination Address Register 3" line.long 0x08 "DFBIDX3,Destination FIFO B-Dimension Index Register 3" hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays" hexmask.long.word 0x08 0.--15. 1. " SBIDX ,B-Index offset between source arrays" line.long 0x0c "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register 3" bitfld.long 0x0c 8. " PRIV ,Privilege level" "User,Supervisor" hexmask.long.byte 0x0c 0.--3. 1. " PRIVID ,Privilege ID" tree.end tree.end tree.end tree "Touchscreen Controller" base ad:0x44E0D000 width 22. rgroup.long 0x00++0x7 line.long 0x00 "REVISION,Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,R_RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" group.long 0x10++0x3 line.long 0x00 "SYSCONFIG,SYSCONFIG Register" bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode" "Force Idle,No Idle Mode,Smart-Idle Mode,Smart-Idle-Wakeup" group.long 0x20++0x23 sif (!cpuis("AM335*")) line.long 0x00 "IRQ_EOI,IRQ_EOI Register" bitfld.long 0x00 0. " LINE_NUMBER ,LINE_NUMBER" "0,1" endif line.long 0x04 "IRQSTATUS_RAW,IRQSTATUS_RAW Register" bitfld.long 0x04 10. " PEN_IRQ_SYNCHRONIZED ,PEN IRQ synchronized" "No event pending,Event pending" bitfld.long 0x04 9. " PEN_UP_EVENT ,Pen Up Event" "No event pending,Event pending" textline " " bitfld.long 0x04 8. " OUT_OF_RANGE ,Out of Range" "No event pending,Event pending" bitfld.long 0x04 7. " FIFO1_UNDERFLOW ,FIFO1 Underflow" "No event pending,Event pending" textline " " bitfld.long 0x04 6. " FIFO1_OVERRUN ,FIFO1 Overrun" "No event pending,Event pending" bitfld.long 0x04 5. " FIFO1_THRESHOLD ,FIFO1 Threshold" "No event pending,Event pending" textline " " bitfld.long 0x04 4. " FIFO0_UNDERFLOW ,FIFO0 Underflow" "No event pending,Event pending" bitfld.long 0x04 3. " FIFO0_OVERRUN ,FIFO0 Overrun" "No event pending,Event pending" textline " " bitfld.long 0x04 2. " FIFO0_THRESHOLD ,FIFO0 Threshold" "No event pending,Event pending" bitfld.long 0x04 1. " END_OF_SEQUENCE ,End of Sequence" "No event pending,Event pending" textline " " bitfld.long 0x04 0. " HW_PEN_EVENT_ASYNCHRONOUS ,HW Pen Event asynchronous" "No event pending,Event pending" line.long 0x08 "IRQSTATUS,IRQSTATUS Register" setclrfld.long 0x08 10. 0x04 10. 0x08 10. " HW_PEN_IRQ_SYNCHRONIZED_set/clr ,PEN IRQ synchronized" "No event pending,Event pending" setclrfld.long 0x08 9. 0x04 9. 0x08 9. " PEN_UP_EVENT_set/clr ,Pen Up Event" "No event pending,Event pending" textline " " setclrfld.long 0x08 8. 0x04 8. 0x08 8. " OUT_OF_RANGE_set/clr ,Out of Range" "No event pending,Event pending" setclrfld.long 0x08 7. 0x04 7. 0x08 7. " FIFO1_UNDERFLOW_set/clr ,FIFO1 Underflow" "No event pending,Event pending" textline " " setclrfld.long 0x08 6. 0x04 6. 0x08 6. " FIFO1_OVERRUN_set/clr ,FIFO1 Overrun" "No event pending,Event pending" setclrfld.long 0x08 5. 0x04 5. 0x08 5. " FIFO1_THRESHOLD_set/clr ,FIFO1 Threshold" "No event pending,Event pending" textline " " setclrfld.long 0x08 4. 0x04 4. 0x08 4. " FIFO0_UNDERFLOW_set/clr ,FIFO0 Underflow" "No event pending,Event pending" setclrfld.long 0x08 3. 0x04 3. 0x08 3. " FIFO0_OVERRUN_set/clr ,FIFO0 Overrun" "No event pending,Event pending" textline " " setclrfld.long 0x08 2. 0x04 2. 0x08 2. " FIFO0_THRESHOLD_set/clr ,FIFO0 Threshold" "No event pending,Event pending" setclrfld.long 0x08 1. 0x04 1. 0x08 1. " END_OF_SEQUENCE_set/clr ,End of Sequence" "No event pending,Event pending" textline " " setclrfld.long 0x08 0. 0x04 0. 0x08 0. " HW_PEN_EVENT_ASYNCHRONOUS_set/clr ,HW Pen Event asynchronous" "No event pending,Event pending" line.long 0x0C "IRQENABLE,IRQENABLE Register" setclrfld.long 0x0C 10. 0x0C 10. 0x10 10. " HW_PEN_IRQ_SYNCHRONIZED_set/clr ,PEN IRQ synchronized" "Disabled,Enabled" setclrfld.long 0x0C 9. 0x0C 9. 0x10 9. " PEN_UP_EVENT_set/clr ,Pen Up Event" "Disabled,Enabled" textline " " setclrfld.long 0x0C 8. 0x0C 8. 0x10 8. " OUT_OF_RANGE_set/clr ,Out of Range" "Disabled,Enabled" setclrfld.long 0x0C 7. 0x0C 7. 0x10 7. " FIFO1_UNDERFLOW_set/clr ,FIFO1 Underflow" "Disabled,Enabled" textline " " setclrfld.long 0x0C 6. 0x0C 6. 0x10 6. " FIFO1_OVERRUN_set/clr ,FIFO1 Overrun" "Disabled,Enabled" setclrfld.long 0x0C 5. 0x0C 5. 0x10 5. " FIFO1_THRESHOLD_set/clr ,FIFO1 Threshold" "Disabled,Enabled" textline " " setclrfld.long 0x0C 4. 0x0C 4. 0x10 4. " FIFO0_UNDERFLOW_set/clr ,FIFO0 Underflow" "Disabled,Enabled" setclrfld.long 0x0C 3. 0x0C 3. 0x10 3. " FIFO0_OVERRUN_set/clr ,FIFO0 Overrun" "Disabled,Enabled" textline " " setclrfld.long 0x0C 2. 0x0C 2. 0x10 2. " FIFO0_THRESHOLD_set/clr ,FIFO0 Threshold" "Disabled,Enabled" setclrfld.long 0x0C 1. 0x0C 1. 0x10 1. " END_OF_SEQUENCE_set/clr ,End of Sequence" "Disabled,Enabled" textline " " setclrfld.long 0x0C 0. 0x0C 0. 0x10 0. " HW_PEN_EVENT_ASYNCHRONOUS_set/clr ,HW Pen Event asynchronous" "Disabled,Enabled" line.long 0x14 "IRQWAKEUP,IRQWAKEUP Register" bitfld.long 0x14 0. " WAKEEN0 ,Wakeup generation for HW Pen event" "Disabled,Enabled" line.long 0x18 "DMAENABLE_SET,Per-Line DMA Set Register" bitfld.long 0x18 1. " ENABLE_1 ,Enable DMA request FIFO 1" "Disabled,Enabled" bitfld.long 0x18 0. " ENABLE_0 ,Enable DMA request FIFO 0" "Disabled,Enabled" line.long 0x1c "DMAENABLE_CLR,Per-Line DMA Clr Register" bitfld.long 0x1c 1. " ENABLE_1 ,Enable DMA request FIFO 1 read/write" "Disabled/No action,Enabled/Disable" bitfld.long 0x1c 0. " ENABLE_0 ,Enable DMA request FIFO 0 read/write" "Disabled/No action,Enabled/Disable" line.long 0x20 "CTRL,@TSC_ADC_SS Control Register" bitfld.long 0x20 9. " HW_PREEMPT ,SW steps are preempted by HW events" "Disabled,Enabled" bitfld.long 0x20 8. " HW_EVENT_MAPPING ,Map HW event" "Pen touch irq,HW event input" textline " " bitfld.long 0x20 7. " TOUCH_SCREEN_ENABLE ,Touchscreen transistors" "Disabled,Enabled" bitfld.long 0x20 6. " AFE_PEN_CTRL[1] ,AFE Pen Ctrl (Wiper touch)" "Low,High" textline " " bitfld.long 0x20 5. " AFE_PEN_CTRL[0] ,AFE Pen Ctrl(X+touch)" "Low,High" bitfld.long 0x20 4. " POWER_DOWN ,ADC Power Down control" "AFE is Up,AFE is Down" textline " " bitfld.long 0x20 3. " ADC_BIAS_SELECT ,Select Internal or External Bias to AFE" "Internal,External" bitfld.long 0x20 2. " STEPCONFIG_WRITEPROTECT_N_ACTIVE_LOW ,Step configuration registers are protected" "Enabled,Disabled" textline " " bitfld.long 0x20 1. " STEP_ID_TAG ,Step ID number with the captured ADC data in the FIFO" "0,ID tag" bitfld.long 0x20 0. " ENABLE ,TSC_ADC_SS module enable bit" "Disabled,Enabled" rgroup.long 0x44++0x03 line.long 0x00 "ADCSTAT,General Status bits @TSC_ADC_SS_Sequencer_Status Register" bitfld.long 0x00 7. " PEN_IRQ1 ,PEN_IRQ[1] status" "Not occured,Occured" bitfld.long 0x00 6. " PEN_IRQ0 ,PEN_IRQ[0] status" "Not occured,Occured" textline " " bitfld.long 0x00 5. " FSM_BUSY ,Status of OCP FSM and ADC FSM" "Idle,Busy" bitfld.long 0x00 0.--4. " STEP_ID ,Encoded values" "Step 1,Step 2,Step 3,Step 4,Step 5,Step 6,Step 7,Step 8,Step 9,Step 10,Step 11,Step 12,Step 13,Step 14,Step 15,Step 16,Idle,Charge,?..." group.long 0x48++0x1f line.long 0x00 "ADCRANGE,High and Low Range Threshold@TSC_ADC_SS_Range_Check Register" hexmask.long.word 0x00 12.--27. 1. " HIGH_RANGE_DATA ,Sampled ADC data is compared to this value" hexmask.long.word 0x00 0.--11. 1. " LOW_RANGE_DATA ,Sampled ADC data is compared to this value" line.long 0x04 "ADC_CLKDIV,ADC clock divider register@TSC_ADC_SS_Clock_Divider Register" hexmask.long.word 0x04 0.--15. 1. " ADC_CLKDIV ,The input ADC clock will be divided by this value and sent to the AFE" line.long 0x08 "ADC_MISC,AFE misc debug@TSC_ADC_SS_MISC Register" bitfld.long 0x08 4.--7. " AFE_SPARE_OUTPUT ,Connected to AFE Spare Output pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0.--3. " AFE_SPARE_INPUT ,Connected to AFE Spare Input pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0c "STEPENABLE,Step Enable Registe" bitfld.long 0x0c 16. " STEP16 ,Enable step 16" "Disabled,Enabled" bitfld.long 0x0c 15. " STEP15 ,Enable step 115" "Disabled,Enabled" textline " " bitfld.long 0x0c 14. " STEP14 ,Enable step 14" "Disabled,Enabled" bitfld.long 0x0c 13. " STEP13 ,Enable step 13" "Disabled,Enabled" textline " " bitfld.long 0x0c 12. " STEP12 ,Enable step 112" "Disabled,Enabled" bitfld.long 0x0c 11. " STEP11 ,Enable step 11" "Disabled,Enabled" textline " " bitfld.long 0x0c 10. " STEP10 ,Enable step 10" "Disabled,Enabled" bitfld.long 0x0c 9. " STEP9 ,Enable step 9" "Disabled,Enabled" textline " " bitfld.long 0x0c 8. " STEP8 ,Enable step 8" "Disabled,Enabled" bitfld.long 0x0c 7. " STEP7 ,Enable step 7" "Disabled,Enabled" textline " " bitfld.long 0x0c 6. " STEP6 ,Enable step 6" "Disabled,Enabled" bitfld.long 0x0c 5. " STEP5 ,Enable step 5" "Disabled,Enabled" textline " " bitfld.long 0x0c 4. " STEP4 ,Enable step 4" "Disabled,Enabled" bitfld.long 0x0c 3. " STEP3 ,Enable step 3" "Disabled,Enabled" textline " " bitfld.long 0x0c 2. " STEP2 ,Enable step 2" "Disabled,Enabled" bitfld.long 0x0c 1. " STEP1 ,Enable step 1" "Disabled,Enabled" textline " " bitfld.long 0x0C 0. " TS_CHARGE ,Enable TS Charge step" "Disabled,Enabled" line.long 0x10 "IDLECONFIG,Idle Step configuration@TSC_ADC_SS_IDLE_StepConfig Registerr" bitfld.long 0x10 25. " DIFF_CNTRL ,Differential Control Pin" "Single Ended,Differential Pair" bitfld.long 0x10 23.--24. " SEL_RF_MUNDER_SCORE_UNDER_SCORE_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x10 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x10 15.--18. " SEL_INM_SWM3_0 ,SEL_INM pins for neg differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x10 12.--14. " SEL_RFP_UNDER_SCORE_UNDER_SCORE_SWC_2_0 ,SEL_RFP pins SW configuration" "VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF,INTREF" bitfld.long 0x10 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x10 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x10 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x10 7. " YPPSWUNDERSCOREUNDERSCORESWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " XNNSWUNDERSCOREUNDERSCORESWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x10 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" line.long 0x14 "TS_CHARGE_STEPCONFIG,TS Charge StepConfiguration@TSC_ADC_SS_TS_Charge_StepConfig Register" bitfld.long 0x14 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" textline " " bitfld.long 0x14 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" sif (cpuis("DRA62*")) bitfld.long 0x14 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN" textline " " bitfld.long 0x14 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN,VREFN" else bitfld.long 0x14 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x14 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" endif bitfld.long 0x14 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF,INTREF" textline " " bitfld.long 0x14 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x14 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x14 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x14 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x14 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" line.long 0x18 "TS_CHARGE_DELAY,TS Charge Delay Register" hexmask.long.tbyte 0x18 0.--17. 1. " OPENDELAY ,Program the # of ADC clock cycles to wait between applying the step configuration registers and going back to the IDLE state" tree "Step Configuration & Step Delay Registers" group.long 0x64++0x7f line.long 0x0 "STEPCONFIG1,Step configuration 1" bitfld.long 0x0 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x0 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x0 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x0 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x0 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x0 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x0 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x0 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x0 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x0 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x0 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x0 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x0 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x0 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x0 "STEPDELAY1,Step Delay Register 1" hexmask.long.byte 0x04+0x0 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x0 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x8 "STEPCONFIG2,Step configuration 2" bitfld.long 0x8 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x8 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x8 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x8 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x8 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x8 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x8 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x8 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x8 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x8 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x8 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x8 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x8 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x8 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x8 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x8 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x8 "STEPDELAY2,Step Delay Register 2" hexmask.long.byte 0x04+0x8 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x8 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x10 "STEPCONFIG3,Step configuration 3" bitfld.long 0x10 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x10 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x10 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x10 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x10 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x10 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x10 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x10 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x10 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x10 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x10 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x10 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x10 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x10 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x10 "STEPDELAY3,Step Delay Register 3" hexmask.long.byte 0x04+0x10 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x10 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x18 "STEPCONFIG4,Step configuration 4" bitfld.long 0x18 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x18 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x18 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x18 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x18 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x18 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x18 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x18 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x18 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x18 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x18 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x18 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x18 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x18 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x18 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x18 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x18 "STEPDELAY4,Step Delay Register 4" hexmask.long.byte 0x04+0x18 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x18 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x20 "STEPCONFIG5,Step configuration 5" bitfld.long 0x20 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x20 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x20 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x20 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x20 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x20 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x20 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x20 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x20 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x20 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x20 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x20 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x20 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x20 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x20 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x20 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x20 "STEPDELAY5,Step Delay Register 5" hexmask.long.byte 0x04+0x20 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x20 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x28 "STEPCONFIG6,Step configuration 6" bitfld.long 0x28 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x28 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x28 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x28 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x28 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x28 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x28 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x28 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x28 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x28 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x28 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x28 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x28 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x28 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x28 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x28 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x28 "STEPDELAY6,Step Delay Register 6" hexmask.long.byte 0x04+0x28 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x28 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x30 "STEPCONFIG7,Step configuration 7" bitfld.long 0x30 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x30 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x30 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x30 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x30 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x30 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x30 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x30 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x30 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x30 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x30 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x30 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x30 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x30 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x30 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x30 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x30 "STEPDELAY7,Step Delay Register 7" hexmask.long.byte 0x04+0x30 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x30 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x38 "STEPCONFIG8,Step configuration 8" bitfld.long 0x38 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x38 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x38 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x38 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x38 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x38 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x38 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x38 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x38 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x38 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x38 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x38 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x38 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x38 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x38 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x38 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x38 "STEPDELAY8,Step Delay Register 8" hexmask.long.byte 0x04+0x38 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x38 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x40 "STEPCONFIG9,Step configuration 9" bitfld.long 0x40 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x40 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x40 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x40 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x40 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x40 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x40 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x40 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x40 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x40 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x40 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x40 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x40 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x40 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x40 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x40 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x40 "STEPDELAY9,Step Delay Register 9" hexmask.long.byte 0x04+0x40 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x40 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x48 "STEPCONFIG10,Step configuration 10" bitfld.long 0x48 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x48 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x48 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x48 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x48 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x48 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x48 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x48 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x48 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x48 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x48 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x48 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x48 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x48 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x48 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x48 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x48 "STEPDELAY10,Step Delay Register 10" hexmask.long.byte 0x04+0x48 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x48 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x50 "STEPCONFIG11,Step configuration 11" bitfld.long 0x50 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x50 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x50 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x50 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x50 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x50 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x50 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x50 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x50 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x50 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x50 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x50 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x50 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x50 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x50 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x50 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x50 "STEPDELAY11,Step Delay Register 11" hexmask.long.byte 0x04+0x50 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x50 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x58 "STEPCONFIG12,Step configuration 12" bitfld.long 0x58 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x58 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x58 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x58 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x58 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x58 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x58 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x58 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x58 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x58 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x58 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x58 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x58 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x58 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x58 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x58 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x58 "STEPDELAY12,Step Delay Register 12" hexmask.long.byte 0x04+0x58 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x58 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x60 "STEPCONFIG13,Step configuration 13" bitfld.long 0x60 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x60 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x60 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x60 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x60 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x60 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x60 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x60 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x60 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x60 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x60 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x60 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x60 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x60 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x60 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x60 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x60 "STEPDELAY13,Step Delay Register 13" hexmask.long.byte 0x04+0x60 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x60 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x68 "STEPCONFIG14,Step configuration 14" bitfld.long 0x68 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x68 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x68 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x68 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x68 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x68 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x68 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x68 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x68 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x68 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x68 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x68 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x68 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x68 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x68 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x68 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x68 "STEPDELAY14,Step Delay Register 14" hexmask.long.byte 0x04+0x68 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x68 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x70 "STEPCONFIG15,Step configuration 15" bitfld.long 0x70 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x70 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x70 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x70 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x70 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x70 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x70 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x70 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x70 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x70 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x70 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x70 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x70 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x70 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x70 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x70 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x70 "STEPDELAY15,Step Delay Register 15" hexmask.long.byte 0x04+0x70 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x70 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" line.long 0x78 "STEPCONFIG16,Step configuration 16" bitfld.long 0x78 27. " RANGE_CHECK ,Range check" "Disable,Compare ADC" bitfld.long 0x78 26. " FIFO_SELECT ,Sampled data will be stored in FIFO" "FIFO,FIFO 1" textline " " bitfld.long 0x78 25. " DIFF_CNTRL ,Differential Control Pin" "Disabled,Enabled" bitfld.long 0x78 23.--24. " SEL_RFM_SWC_1_0 ,SEL_RFM pins SW configuration" "VSSA,XNUR,YNLR,ADCREFM" textline " " bitfld.long 0x78 19.--22. " SEL_INP_SWC_3_0 ,SEL_INP pins SW configuration" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" bitfld.long 0x78 15.--18. " SEL_INM_SWM3_0 ,SEL_INP pins for negative differential" "Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM,ADCREFM" textline " " bitfld.long 0x78 12.--14. " SEL_RFP_SWC_2_0 ,SEL_RFP pins SW configuration" "Reserved,VDDA,XPUL,YPLL,ADCREFP,INTREF,INTREF,INTREF" bitfld.long 0x78 11. " WPNSW_SWC ,WPNSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x78 10. " YPNSW_SWC ,YPNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x78 9. " XNPSW_SWC ,XNPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x78 8. " YNNSW_SWC ,YNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x78 7. " YPPSW_SWC ,YPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x78 6. " XNNSW_SWC ,XNNSW pin SW configuration" "Disabled,Enabled" bitfld.long 0x78 5. " XPPSW_SWC ,XPPSW pin SW configuration" "Disabled,Enabled" textline " " bitfld.long 0x78 2.--4. " AVERAGING ,Number of samplings to average" "No average,2,4,8,16,?..." bitfld.long 0x78 0.--1. " MODE ,Mode" "SW/one-shot,SW/continuous,HW sync/one-shot,HW sync/continuous" line.long 0x04+0x78 "STEPDELAY16,Step Delay Register 16" hexmask.long.byte 0x04+0x78 24.--31. 1. " SAMPLEDELAY ,Number of ADC clock cycles to sample" hexmask.long.tbyte 0x04+0x78 0.--17. 1. " OPENDELAY ,Program the number of ADC clock cycles to wait" tree.end rgroup.long 0xE4++0x3 line.long 0x00 "FIFO0COUNT,FIFO0COUNT Register" hexmask.long.byte 0x00 0.--6. 1. " WORDS_IN_FIFO ,Number of words currently in the FIFO" group.long 0xE8++0x7 line.long 0x00 "FIFO0THRESHOLD,FIFO0 Threshold trigger@TSC_ADC_SS_FIFO0 Threshold Level Register" hexmask.long.byte 0x00 0.--5. 1. " FIFO0_THRESHOLD_LEVEL ,Program the desired FIFO0 data sample level to reach before generating interrupt to CPU" line.long 0x04 "DMA0REQ,FIFO0 DMA req0 trigger@TSC_ADC_SS_FIFO0 DMA REQUEST Register" hexmask.long.byte 0x04 0.--5. 1. " DMA_REQUEST_LEVEL ,Number of words in FIFO0 before generating a DMA request" sif (cpuis("DRA62*")||cpuis("AM335*")) rgroup.long 0xf0++0x3 line.long 0x00 "FIFO1COUNT,FIFO1COUNT Register" hexmask.long.byte 0x00 0.--6. 1. " WORDS_IN_FIFO ,FIFO1 Word Count Register" else rgroup.long 0xf0++0x3 line.long 0x00 "FIFO1COUNT,FIFO1COUNT Register" hexmask.long.byte 0x00 0.--5. 1. " WORDS_IN_FIFO ,FIFO1 Word Count Register" endif group.long 0xF4++0x7 line.long 0x00 "FIFO1THRESHOLD,FIFO1 Threshold Level Register" hexmask.long.byte 0x00 0.--5. 1. " FIFO1_THRESHOLD_LEVEL ,Program the desired FIFO1 data sample level to reach before generating interrupt to CPU" line.long 0x04 "DMA1REQ,FIFO1 DMA Request Register" hexmask.long.byte 0x04 0.--5. 1. " DMA_REQUEST_LEVEL ,Number of words in FIFO1 before generating a DMA request" rgroup.long 0x100++0x3 line.long 0x00 "FIFO0DATA,ADC_ FIFO0 _READ Data @TSC_ADC_SS_FIFO0 READ Register" hexmask.long.byte 0x00 16.--19. 1. " ADCCHNLID ,Optional ID tag of channel that captured the data" hexmask.long.word 0x00 0.--11. 1. " ADCDATA ,12 bit sampled ADC converted data value stored in FIFO 0" rgroup.long 0x200++0x3 line.long 0x00 "FIFO1DATA,ADC_ FIFO1 _READ Data @TSC_ADC_SS_FIFO1 READ Register" hexmask.long.byte 0x00 16.--19. 1. " ADCCHNLID ,Optional ID tag of channel that captured the data" hexmask.long.word 0x00 0.--11. 1. " ADCDATA ,12 bit sampled ADC converted data value stored in FIFO 1" tree.end tree "LCD Controller" base ad:0x4830E000 width 20. rgroup.long 0x00++0x03 line.long 0x00 "PID,PID Register" bitfld.long 0x00 30.--31. " SCHEME ,The scheme of the register used" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,The function of the module being used" bitfld.long 0x00 11.--15. " RTL ,The Release number for this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Release Number" bitfld.long 0x00 6.--7. " CUSTOM ,Custom IP" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Release Number" group.long 0x04++0x03 line.long 0x00 "LCD_CTRL,LCD Control Register" hexmask.long.byte 0x00 8.--15. 1. " CLKDIV ,Clock divisor" bitfld.long 0x00 1. " AUTO_UFLOW_RESTART ,Software has to restart" "Module,Next frame" bitfld.long 0x00 0. " MODESEL ,LCD mode select" "LIDD,Raster" group.long 0x0c++0x5b line.long 0x00 "LIDD_CTRL,LCD LIDD Control Register" bitfld.long 0x00 9. " DMA_CS0_CS1 ,CS0/CS1 select for LIDD DMA writes" "CS0,CS1" bitfld.long 0x00 8. " LIDD_DMA_EN ,LIDD DMA enable" "Disabled,Enabled" bitfld.long 0x00 7. " CS1_E1_POL ,Chip select 1/enable 1 (secondary) polarity control" "Not inverted,Inverted" textline " " bitfld.long 0x00 6. " CS0_E0_POL ,Chip select 0/enable 0 (primary) polarity control" "Not inverted,Inverted" bitfld.long 0x00 5. " WS_DIR_POL ,Write strobe/direction polarity control" "Not inverted,Inverted" bitfld.long 0x00 4. " RS_EN_POL ,Read strobe/enable polarity control" "Not inverted,Inverted" textline " " bitfld.long 0x00 3. " ALEPOL ,Address latch enable (ALE) polarity control" "Not inverted,Inverted" bitfld.long 0x00 0.--2. " LIDD_MODE_SEL ,LIDD mode select" "Sync MPU68,Async MPU68,Sync MPU80,Async MPU80,Hitachi,?..." line.long 0x04 "LIDD_CS0_CONF,LCD LIDD CS0 Configuration Register" bitfld.long 0x04 27.--31. " W_SU ,Write strobe set-up cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 21.--26. " W_STROBE ,Write strobe duration cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 17.--20. " W_HOLD ,Write strobe hold cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 12.--16. " R_SU ,Read strobe set-up cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 6.--11. " R_STROBE ,Read strobe duration cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 2.--5. " R_HOLD ,Read strobe hold cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 0.--1. " TA ,MCLK cycles between the end of one CS0 device access and start of another CS0 device access" "0,1,2,3" line.long 0x08 "LIDD_CS0_ADDR,LCD LIDD CS0 Address Read/Write Register" hexmask.long.word 0x08 0.--15. 1. " ADR_INDX ,Peripheral device address/index value" line.long 0x0c "LIDD_CS0_DATA,LCD LIDD CS0 Data Read/Write Register" hexmask.long.word 0x0c 0.--15. 1. " DATA ,Peripheral Device Data value" line.long 0x10 "LIDD_CS1_CONF,LCD LIDD CS1 Configuration Register" bitfld.long 0x10 27.--31. " W_SU ,Write strobe set-up cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 21.--26. " W_STROBE ,Write strobe duration cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 17.--20. " W_HOLD ,Write strobe hold cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 12.--16. " R_SU ,Read strobe set-up cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 6.--11. " R_STROBE ,Read strobe duration cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x10 2.--5. " R_HOLD ,Read strobe hold cycles" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 0.--1. " TA ,MCLK cycles between the end of one CS0 device access and start of another CS0 device access" "0,1,2,3" line.long 0x14 "LIDD_CS1_ADDR,LCD LIDD CS1 Address Read/Write Register" hexmask.long.word 0x14 0.--15. 1. " ADR_INDX ,Peripheral device address/index value" line.long 0x18 "LIDD_CS1_DATA,LCD LIDD CS1 Data Read/Write Register" hexmask.long.word 0x18 0.--15. 1. " DATA ,Peripheral Device Data value" line.long 0x1c "RASTER_CTRL,LCD Raster Control Register" bitfld.long 0x1c 26. " TFT24UNPACKED ,24 bit Mode Packing" "3 words,4 words" bitfld.long 0x1c 25. " TFT24 ,24 bit mode" "OFF,ON" bitfld.long 0x1c 24. " STN565 ,16-bit-per-pixel (5-6-5) mode" "Disabled,Enabled" textline " " bitfld.long 0x1c 23. " TFTALTMAP ,TFT alternative signal mapping" "Right alligned,Converted to 5-6-5" bitfld.long 0x1c 22. " NIBMODE ,Nibble mode" "Disabled,Enabled" bitfld.long 0x1c 20.--21. " PALMODE ,Palette Loading Mode" "Palette/data,Palette,Data,?..." textline " " hexmask.long.byte 0x1c 12.--19. 1. " REQDLY ,Palette Loading Delay" bitfld.long 0x1c 9. " MONO8B ,Mono 8-bit mode" "LCD_P[3:0],LCD_P[7:0]" bitfld.long 0x1c 8. " RDORDER ,Raster data order select" "LSB,MSB" textline " " bitfld.long 0x1c 7. " LCDTFT ,LCD" "Passive,Active" bitfld.long 0x1c 1. " LCDBW ,LCD monochrome or color" "Color,Monochrome" bitfld.long 0x1c 0. " LCDEN ,LCD controller enable" "Disabled,Enabled" line.long 0x20 "RASTER_TIMING_0,LCD Raster Timing Register 0" hexmask.long.byte 0x20 24.--31. 1. " HBP ,Horizontal back porch" hexmask.long.byte 0x20 16.--23. 1. " HFP ,Horizontal front porch" textline " " hexmask.long.byte 0x20 10.--15. 1. " HSW ,Horizontal sync pulse width" hexmask.long.byte 0x20 4.--9. 1. " PPLLSB ,Pixels per line LSB" bitfld.long 0x20 3. " PPLMSB ,Pixels per line MSB" "Low,High" line.long 0x24 "RASTER_TIMING_1,LCD Raster Timing Register 1" hexmask.long.byte 0x24 24.--31. 1. " VBP ,Vertical back porch" hexmask.long.byte 0x24 16.--23. 1. " VFP ,Vertical front porch" hexmask.long.byte 0x24 10.--15. 1. " VSW ,Vertical sync pulse width" textline " " hexmask.long.word 0x24 0.--9. 1. " LPP ,Lines per Panel" line.long 0x28 "RASTER_TIMING_2,LCD Raster Timing Register 2" bitfld.long 0x28 27.--30. " HSW_HIGHBITS ,Bits 9:6 of the horizontal sync width field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x28 26. " LPP_B10 ,Lines Per Panel Bit 10" "Low,High" bitfld.long 0x28 25. " PHSVS_ON_OFF ,Hsync/Vsync Pixel Clock Control On/Off" "Inactive,Active" textline " " bitfld.long 0x28 24. " PHSVS_RF ,Horizontal and vertical dync edge" "Rising,Falling" bitfld.long 0x28 23. " IEO ,Invert AC bias" "Active high,Active low" bitfld.long 0x28 22. " IPC ,Invert pixel clock" "Normal,Inverted" textline " " bitfld.long 0x28 21. " IHS ,Invert line clock" "Active high,Active low" bitfld.long 0x28 20. " IVS ,Invert frame clock" "Active high,Active low" bitfld.long 0x28 16.--19. " ACB_I ,AC Bias number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x28 8.--15. 1. " ACB ,AC bias pin frequency" bitfld.long 0x28 4.--5. " HBP_HIGHBITS ,Bits 9:8 of the horizontal back porch field" "0,1,2,3" bitfld.long 0x28 0.--1. " HFP_HIGHBITS ,Bits 9:8 of the horizontal front porch field" "0,1,2,3" line.long 0x2c "RASTER_SUBPANEL,LCD Raster Subpanel Display Register" bitfld.long 0x2c 31. " SPEN ,Subpanel enable" "Disabled,Enabled" bitfld.long 0x2c 29. " HOLS ,High or low signal" "Low/below,High/above" hexmask.long.word 0x2c 16.--25. 1. " LPPT ,Line per panel threshold" hexmask.long.word 0x2c 0.--15. 1. " DPDLSB ,Default Pixel Data LSB" line.long 0x30 "RASTER_SUBPANEL2,LCD Raster Subpanel Display Register" bitfld.long 0x30 8. " LPPT_B10 ,Lines Per Panel Threshold Bit 10" "Low,High" hexmask.long.byte 0x30 0.--7. 1. " DPDLSB ,Default Pixel Data MSB [23:16]" line.long 0x34 "LCDDMA_CTRL,LCD DMA Control Register" bitfld.long 0x34 16.--18. " DMA_MASTER_PRIO ,Priority for the L3 OCP Master Bus" "0,1,2,3,4,5,6,7" bitfld.long 0x34 8.--10. " TH_FIFO_READY ,DMA FIFO threshold" "8,16,32,64,128,256,512,?..." bitfld.long 0x34 4.--6. " BURST_SIZE ,Burst size" "1,2,4,8,16,?..." textline " " bitfld.long 0x34 3. " BYTE_SWAP ,This bit controls the bytelane ordering output/DMA module" "Disabled,Enabled" bitfld.long 0x34 1. " BIGENDIAN ,Big endian enable" "Disabled,Enabled" bitfld.long 0x34 0. " FRAME_MODE ,Frame mode" "One buffer,Two buffers" line.long 0x38 "LCDDMA_FB0_BASE,LCD DMA Frame Buffer 0 Base Address Register" hexmask.long 0x38 2.--31. 0x4 " FB0_BASE ,Frame buffer 0 base address Pointer" line.long 0x3c "LCDDMA_FB0_CEILING,LCD DMA Frame Buffer 0 Ceiling Address Register" hexmask.long 0x3c 2.--31. 0x4 " FB0_CEIL ,Frame buffer 0 ceiling address" line.long 0x40 "LCDDMA_FB1_BASE,LCD DMA Frame Buffer 1 Base Address Register" hexmask.long 0x40 2.--31. 0x4 " FB0_BASE ,Frame buffer 1 base address Pointer" line.long 0x44 "LCDDMA_FB1_CEILING,LCD DMA Frame Buffer 1 Ceiling Address Register" hexmask.long 0x44 2.--31. 0x4 " FB0_CEIL ,Frame buffer 1 ceiling address" width 19. line.long 0x48 "SYSCONFIG,SYSCONFIG Register" bitfld.long 0x48 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby,Smart-Standby/wakeup-capable" bitfld.long 0x48 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle/wakeup-capable" line.long 0x4c "IRQSTATUS_RAW,IRQSTATUS_RAW Register" bitfld.long 0x4c 9. " EOF1_RAW_SET ,DMA End-of-Frame 1 Raw Interrupt Status and Set Read indicates raw status" "Inactive,Active" bitfld.long 0x4c 8. " EOF0_RAW_SET ,DMA End-of-Frame 0 Raw Interrupt Status and Set" "Inactive,Active" bitfld.long 0x4c 6. " PL_RAW_SET ,DMA Palette Loaded Raw Interrupt Status and Set" "Inactive,Active" textline " " bitfld.long 0x4c 5. " FUF_RAW_SET ,DMA FIFO Underflow Raw Interrupt Status and Set LCD" "Inactive,Active" bitfld.long 0x4c 3. " ACB_EN_SET ,AC Bias Count Raw Interrupt Status and Set" "Inactive,Active" bitfld.long 0x4c 2. " SYNC_RAW_SET ,Frame Synchronization Read indicates raw status" "Inactive,Active" textline " " bitfld.long 0x4C 1. " RECURRENT_RASTER_DONE_RAW_SET ,Raster Mode Frame " "Inactive,Active" bitfld.long 0x4c 0. " DONE_RAW_SET ,Raster or LIDD Frame Done Raw Interrupt Status and Set Read indicates raw status" "Inactive,Active" line.long 0x50 "IRQSTATUS,IRQSTATUS Register" bitfld.long 0x50 9. " EOF1_EN_CLR ,DMA End-of-Frame 1 Raw Interrupt Enable Clear Read indicates raw status" "Inactive,Active" bitfld.long 0x50 8. " EOF0_EN_CLR ,DMA End-of-Frame 0 Raw Interrupt Enable Clear" "Inactive,Active" bitfld.long 0x50 6. " PL_EN_CLR ,DMA Palette Loaded Raw Interrupt Enable Clear" "Inactive,Active" textline " " bitfld.long 0x50 5. " FUF_EN_CLR ,DMA FIFO Underflow Raw Interrupt Enable Clear LCD" "Inactive,Active" bitfld.long 0x50 3. " ACB_EN_CLR ,AC Bias Count Interrupt Enable Clear" "Inactive,Active" bitfld.long 0x50 2. " SYNC_EN_CLR ,Frame Synchronization Read indicates enabled status" "Inactive,Active" textline " " bitfld.long 0x50 1. " RECURRENT_RASTER_DONE_EN_CLR ,Raster Frame Done Interrupt" "Inactive,Active" bitfld.long 0x50 0. " DONE_EN_CLR ,Raster or LIDD Frame Done Interrupt Enable Clear" "Inactive,Active" line.long 0x54 "IRQENABLE_SET,IRQ Enable Set Register" bitfld.long 0x54 9. " EOF1_EN_SET ,DMA End-of-Frame 1 Interrupt Enable Set" "Disabled,Enabled" bitfld.long 0x54 8. " EOF0_EN_SET ,DMA End-of-Frame 0 Raw Interrupt Enable Set" "Disabled,Enabled" bitfld.long 0x54 6. " PL_EN_SET ,DMA Palette Loaded Raw Interrupt Enable Set" "Disabled,Enabled" textline " " bitfld.long 0x54 5. " FUF_EN_SET ,DMA FIFO Underflow Raw Interrupt Enable Set LCD" "Disabled,Enabled" bitfld.long 0x54 3. " ACB_EN_SET ,AC Bias Count Raw Interrupt Enable Set" "Disabled,Enabled" bitfld.long 0x54 2. " SYNC_EN_SET ,Frame Synchronization Read Interrupt Enable Set" "Disabled,Enabled" textline " " bitfld.long 0x54 1. " RECURRENT_RASTER_DONE_EN_SET ,Raster Frame Done Interrupt" "Inactive,Active" bitfld.long 0x54 0. " DONE_EN_SET ,Raster or LIDD Frame Done Interrupt Enable Set" "Inactive,Active" line.long 0x58 "IRQENABLE_CLEAR,IRQSTATUS Register" bitfld.long 0x58 9. " EOF1_EN_CLR ,DMA End-of-Frame 1 Raw Interrupt Enable Clear Read indicates raw status" "Inactive,Active" bitfld.long 0x58 8. " EOF0_EN_CLR ,DMA End-of-Frame 0 Raw Interrupt Enable Clear" "Inactive,Active" bitfld.long 0x58 6. " PL_EN_CLR ,DMA Palette Loaded Raw Interrupt Enable Clear" "Inactive,Active" textline " " bitfld.long 0x58 5. " FUF_EN_CLR ,DMA FIFO Underflow Raw Interrupt Enable Clear LCD" "Inactive,Active" bitfld.long 0x58 3. " ACB_EN_CLR ,AC Bias Count Interrupt Enable Clear" "Inactive,Active" bitfld.long 0x58 2. " SYNC_EN_CLR ,Frame Synchronization Read indicates enabled status" "Inactive,Active" textline " " bitfld.long 0x58 1. " RECURRENT_RASTER_DONE_EN_CLR ,Raster Frame Done Interrupt" "Inactive,Active" bitfld.long 0x58 0. " DONE_EN_CLR ,Raster or LIDD Frame Done Interrupt Enable Clear" "Inactive,Active" sif (!cpuis("AM335*")) rgroup.long 0x68++0x03 line.long 0x00 "IRQEOI_VECTOR,IRQEOI_VECTOR Register" endif group.long 0x6c++0x07 line.long 0x00 "CLKC_ENABLE,CLKC_ENABLE Register" bitfld.long 0x00 2. " DMA_CLK_EN ,Software Reset for the entire LCD module" "Disabled,Enabled" bitfld.long 0x00 1. " LIDD_CLK_EN ,Software Clock Enable for the LIDD submodule" "Disabled,Enabled" bitfld.long 0x00 0. " CORE_CLK_EN ,Software Clock Enable for the Core, which encompasses the Raster Active Matrix and Passive Matrix logic" "Disabled,Enabled" line.long 0x04 "CLKC_ENABLE,CLKC_ENABLE Register" bitfld.long 0x04 3. " MAIN_RST ,Software Clock Reset the DMA submodule" "Disabled,Enabled" bitfld.long 0x04 2. " DMA_RST ,Software Clock Reset the DMA submodule" "Disabled,Enabled" bitfld.long 0x04 1. " LIDD_RST ,Software Clock Reset for the LIDD submodule" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " CORE_RST ,Software Clock Reset for the Core, which encompasses the Raster Active Matrix and Passive Matrix logic" "Disabled,Enabled" width 0xb tree.end tree "Ethernet Subsystem" tree "CPSW ALE" base ad:0x4A100D00 width 19. rgroup.long 0x00++0x03 line.long 0x00 "CPSW_ID_VER,ALE ID Version Register" hexmask.long.word 0x00 16.--31. 1. " IDENT ,ALE identification value" hexmask.long.byte 0x00 8.--15. 1. " MAJOR_VER ,ALE Major Version Value" textline " " hexmask.long.byte 0x00 0.--7. 1. " MINOR_VER ,ALE Minor Version Value" group.long 0x08++0x03 line.long 0x00 "CPSW_CONTROL,CONTROL Register" bitfld.long 0x00 31. " ENABLE_ALE ,Enable ALE" "Drop all packets,Enabled" bitfld.long 0x00 30. " CLEAR_TABLE ,Clear ALE address table" "No effect,Clear" bitfld.long 0x00 29. " AGE_OUT_NOW ,Age Out Address Table Now" "Has completed,Free up" textline " " bitfld.long 0x00 8. " EN_P0_UNI_FLOOD ,Enable Port 0 (Host Port) unicast floo" "Do not flood,Flood" bitfld.long 0x00 7. " LEARN_NO_VID ,Learn No VID" "Learned,Not learned" bitfld.long 0x00 6. " EN_VID0_MODE ,Enable VLAN ID = 0 Mode" "PORT_VLAN,0" textline " " bitfld.long 0x00 5. " ENABLE_OUI_DENY ,Enable OUI Deny Mode" "Disabled,Enabled" bitfld.long 0x00 4. " BYPASS ,ALE Bypass" "Disabled,Enabled" bitfld.long 0x00 3. " RATE_LIMIT_TX ,Rate Limit Transmit mode" "Received,Transmit" textline " " bitfld.long 0x00 2. " VLAN_AWARE ,Determines what is done if VLAN not found." "Flood,Drop packet" bitfld.long 0x00 1. " ENABLE_AUTH_MODE ,Enable MAC Authorization Mode" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE_RATE_LIMIT ,Enable Broadcast and Multicast Rate Limit" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "PRESCALE,ALE Prescale Register" hexmask.long.tbyte 0x00 0.--19. 1. " PRESCALE ,The input clock is divided by this value for use in the multicast/broadcast rate limiters" group.long 0x18++0x03 line.long 0x00 "UNKNOWN_VLAN,ADDRESS LOOKUP ENGINE UNKNOWN VLAN REGISTER" hexmask.long.byte 0x00 24.--29. 1. " UNKNOWN_FORCE_UNTAGGED_EGRESS ,Unknown VLAN Force Untagged Egress" hexmask.long.byte 0x00 16.--21. 1. " UNKNOWN_REG_MCAST_FLOOD_MASK ,Unknown VLAN Registered Multicast Flood Mask" hexmask.long.byte 0x00 8.--13. 1. " UNKNOWN_MCAST_FLOOD_MASK ,Unknown VLAN Multicast Flood Mask" textline " " hexmask.long.byte 0x00 0.--5. 1. " UNKNOWN_VLAN_MEMBER_LIST ,Unknown VLAN Member List" group.long 0x20++0x03 line.long 0x00 "TBLCTL,ADDRESS LOOKUP ENGINE TABLE CONTROL" bitfld.long 0x00 31. " WRITE_RDZ ,Write Bit" "Read,Write" hexmask.long.word 0x00 0.--9. 1. " ENTRY_POINTER ,Table Entry Pointer" group.long 0x34++0x23 line.long 0x00 "TBLW2,ADDRESS LOOKUP ENGINE TABLE WORD 2 REGISTER" hexmask.long.byte 0x00 0.--7. 1. " ENTRY71-64 ,Table entry bits 71:64" line.long 0x04 "TBLW1,ADDRESS LOOKUP ENGINE TABLE WORD 1 REGISTER" line.long 0x08 "TBLW0,ADDRESS LOOKUP ENGINE TABLE WORD 0 REGISTER" line.long 0x0c "PORTCTL0,ADDRESS LOOKUP ENGINE PORT 0 CONTROL REGISTER" hexmask.long.byte 0x0c 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit" hexmask.long.byte 0x0c 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit" bitfld.long 0x0C 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled" bitfld.long 0x0C 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled" bitfld.long 0x0C 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled" textline " " bitfld.long 0x0C 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x10 "PORTCTL1,ADDRESS LOOKUP ENGINE PORT 1 CONTROL REGISTER" hexmask.long.byte 0x10 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit" hexmask.long.byte 0x10 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit" bitfld.long 0x10 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled" bitfld.long 0x10 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled" bitfld.long 0x10 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled" textline " " bitfld.long 0x10 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x14 "PORTCTL2,ADDRESS LOOKUP ENGINE PORT 2 CONTROL REGISTER" hexmask.long.byte 0x14 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit" hexmask.long.byte 0x14 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit" bitfld.long 0x14 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled" textline " " bitfld.long 0x14 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled" bitfld.long 0x14 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled" bitfld.long 0x14 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled" textline " " bitfld.long 0x14 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x18 "PORTCTL3,ADDRESS LOOKUP ENGINE PORT 3 CONTROL REGISTER" hexmask.long.byte 0x18 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit" hexmask.long.byte 0x18 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit" bitfld.long 0x18 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled" textline " " bitfld.long 0x18 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled" bitfld.long 0x18 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled" bitfld.long 0x18 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled" textline " " bitfld.long 0x18 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x1c "PORTCTL4,ADDRESS LOOKUP ENGINE PORT 4 CONTROL REGISTER" hexmask.long.byte 0x1c 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit" hexmask.long.byte 0x1c 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit" bitfld.long 0x1c 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled" textline " " bitfld.long 0x1c 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled" bitfld.long 0x1c 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled" bitfld.long 0x1c 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled" textline " " bitfld.long 0x1c 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward" line.long 0x20 "PORTCTL5,ADDRESS LOOKUP ENGINE PORT 5 CONTROL REGISTER" hexmask.long.byte 0x20 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit" hexmask.long.byte 0x20 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit" bitfld.long 0x20 5. " NO_SA_UPDATE ,No Souce Address Update" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " NO_LEARN ,No Learn Mode" "Disabled,Enabled" bitfld.long 0x20 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check" "Disabled,Enabled" bitfld.long 0x20 2. " DROP_UNTAGGED ,Drop Untagged Packets" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x20 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,?..." else bitfld.long 0x20 0.--1. " PORT_STATE ,Port State" "Disabled,Blocked,Learn,Forward" endif width 0xB tree.end tree "CPSW CPDMA" base ad:0x4A100800 width 20. rgroup.long 0x00++0x03 line.long 0x00 "TX_IDVER,TX IDENTIFICATION AND VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " TX_IDENT ,TX Identification Value" hexmask.long.byte 0x00 8.--15. 1. " TX_MAJOR_VER ,TX Major Version Value - The value read is the major version number" hexmask.long.byte 0x00 0.--7. 1. " TX_MINOR_VER ,TX Minor Version Value - The value read is the minor version number" group.long 0x04++0x03 line.long 0x00 "TX_CONTROL,TX CONTROL REGISTER" bitfld.long 0x00 0. " TX_EN ,TX Enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "TX_TEARDOWN,TX TEARDOWN REGISTER" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x00 31. " TX_TDN_RDY ,Tx Teardown Ready" "Not ready,Ready" else bitfld.long 0x00 31. " TX_TDN_RDY ,Tx Teardown Ready" "Not ready,Ready" endif bitfld.long 0x00 0.--2. " TX_TDN_CH ,Tx Teardown Channel" "0,1,2,3,4,5,6,7" rgroup.long 0x10++0x03 line.long 0x00 "RX_IDVER,RX IDENTIFICATION AND VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " RX_IDENT ,RX Identification Value" hexmask.long.byte 0x00 8.--15. 1. " RX_MAJOR_VER ,RX Major Version Value" hexmask.long.byte 0x00 0.--7. 1. " RX_MINOR_VER ,RX Minor Version Value" group.long 0x14++0x03 line.long 0x00 "RX_CONTROL,RX CONTROL REGISTER" bitfld.long 0x00 0. " RX_EN ,RX DMA Enable" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "RX_TEARDOWN,RX TEARDOWN REGISTER" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x00 31. " RX_TDN_RDY ,RX Teardown Ready" "Not ready,Ready" else bitfld.long 0x00 31. " RX_TDN_RDY ,RX Teardown Ready" "Not ready,Ready" endif bitfld.long 0x00 0.--2. " RX_TDN_CH ,Rx Teardown Channel" "0,1,2,3,4,5,6,7" group.long 0x1C++0x03 line.long 0x00 "CPDMA_SOFT_RESET,SOFT RESET REGISTER" bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No reset,Reset" group.long 0x20++0x03 line.long 0x00 "DMACONTROL,CPDMA CONTROL REGISTER" hexmask.long.byte 0x00 8.--15. 1. " TX_RLIM ,Transmit Rate Limit Channel Bus" bitfld.long 0x00 4. " RX_CEF ,RX Copy Error Frames Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CMD_IDLE ,Command Idle" "Not idle,Idle" bitfld.long 0x00 2. " RX_OFFLEN_BLOCK ,Receive Offset/Length word write block" "CPPI 3.0,Block all CPDMA" textline " " bitfld.long 0x00 1. " RX_OWNERSHIP ,Receive Ownership Write Bit Value" "CPPI 3.0,Buffer descriptor is used" bitfld.long 0x00 0. " TX_PTYPE ,Transmit Queue Priority Type " "Robin scheme,Fixed priority" rgroup.long 0x24++0x03 line.long 0x00 "DMASTATUS,CPDMA STATUS REGISTER" bitfld.long 0x00 31. " IDLE ,Idle Status Bit" "Transferring,Not transferring" bitfld.long 0x00 20.--23. " TX_HOST_ERR_CODE ,TX Host Error Code" "No error,SOP error,Not set in SOP,Zero Without EOP,Zero Buffer Pointer,Zero Buffer Length,Length Error,?..." textline " " bitfld.long 0x00 16.--18. " TX_ERR_CH ,TX Host Error Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--15. " RX_HOST_ERR_CODE ,RX Host Error Code" "No error,Reserved,Ownership bit not set in input buffer,Reserved,Zero Buffer Pointer,Zero buffer length on non-SOP descriptor,SOP buffer length not greater than offset,?..." textline " " bitfld.long 0x00 8.--10. " RX_ERR_CH ,RX Host Error Channel" "0,1,2,3,4,5,6,7" group.long 0x28++0x03 line.long 0x00 "RX_BUFFER_OFFSET,RECEIVE BUFFER OFFSET" hexmask.long.word 0x00 0.--15. 1. " RX_BUFFER_OFFSET ,Receive Buffer Offset Value" group.long 0x2C++0x03 line.long 0x00 "EMCONTROL,EMULATION CONTROL" bitfld.long 0x00 1. " SOFT ,Emulation Soft Bit" "Disabled,Enabled" bitfld.long 0x00 0. " FREE ,Emulation Free Bit" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "TX_PRI0_RATE,TRANSMIT (INGRESS) PRIORITY 0 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count" group.long 0x34++0x03 line.long 0x00 "TX_PRI1_RATE,TRANSMIT (INGRESS) PRIORITY 1 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count" group.long 0x38++0x03 line.long 0x00 "TX_PRI2_RATE,TRANSMIT (INGRESS) PRIORITY 2 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count" group.long 0x3C++0x03 line.long 0x00 "TX_PRI3_RATE,TRANSMIT (INGRESS) PRIORITY 3 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count" group.long 0x40++0x03 line.long 0x00 "TX_PRI4_RATE,TRANSMIT (INGRESS) PRIORITY 4 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count" group.long 0x44++0x03 line.long 0x00 "TX_PRI5_RATE,TRANSMIT (INGRESS) PRIORITY 5 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count" group.long 0x48++0x03 line.long 0x00 "TX_PRI6_RATE,TRANSMIT (INGRESS) PRIORITY 6 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count" group.long 0x4C++0x03 line.long 0x00 "TX_PRI7_RATE,TRANSMIT (INGRESS) PRIORITY 7 RATE" hexmask.long.word 0x00 16.--29. 1. " PRIN_IDLE_CNT ,Priority (7:0) idle count" hexmask.long.word 0x00 0.--13. 1. " PRIN_SEND_CNT ,Priority (7:0) send count" rgroup.long 0x80++0x03 line.long 0x00 "TX_INTSTAT_RAW,CPDMA_INT TX INTERRUPT STATUS REGISTER" bitfld.long 0x00 7. " TX7_PEND ,TX7_PEND raw int read (before mask)" "Disabled,Enabled" bitfld.long 0x00 6. " TX6_PEND ,TX6_PEND raw int read (before mask)" "Disabled,Enabled" bitfld.long 0x00 5. " TX5_PEND ,TX5_PEND raw int read (before mask)." "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TX4_PEND ,TX4_PEND raw int read (before mask)" "Disabled,Enabled" bitfld.long 0x00 3. " TX3_PEND ,TX3_PEND raw int read (before mask)" "Disabled,Enabled" bitfld.long 0x00 2. " TX2_PEND ,TX2_PEND raw int read (before mask)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TX1_PEND ,TX1_PEND raw int read (before mask)" "Disabled,Enabled" bitfld.long 0x00 0. " TX0_PEND ,TX0_PEND raw int read (before mask)" "Disabled,Enabled" rgroup.long 0x84++0x03 line.long 0x00 "TX_INTSTAT_MASKED,CPDMA_INT TX INTERRUPT STATUS REGISTER" bitfld.long 0x00 7. " TX7_PEND ,TX7_PEND masked interrupt read" "Disabled,Enabled" bitfld.long 0x00 6. " TX6_PEND ,TX6_PEND masked interrupt read" "Disabled,Enabled" bitfld.long 0x00 5. " TX5_PEND ,TX5_PEND masked interrupt read" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TX4_PEND ,TX4_PEND masked interrupt read" "Disabled,Enabled" bitfld.long 0x00 3. " TX3_PEND ,TX3_PEND masked interrupt read" "Disabled,Enabled" bitfld.long 0x00 2. " TX2_PEND ,TX2_PEND masked interrupt read" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TX1_PEND ,TX1_PEND masked interrupt read" "Disabled,Enabled" bitfld.long 0x00 0. " TX0_PEND ,TX0_PEND masked interrupt read" "Disabled,Enabled" group.long 0x88++0x03 line.long 0x00 "TX_INTMASK_SET,CPDMA_INT TX INTERRUPT MASK SET REGISTER" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 7. " TX7_MASK ,TX Channel 7 Mask" "Disabled,Enabled" rbitfld.long 0x00 6. " TX6_MASK ,TX Channel 6 Mask" "Disabled,Enabled" bitfld.long 0x00 5. " TX5_MASK ,TX Channel 5 Mask" "Disabled,Enabled" textline " " rbitfld.long 0x00 4. " TX4_MASK ,TX Channel 4 Mask" "Disabled,Enabled" bitfld.long 0x00 3. " TX3_MASK ,TX Channel 3 Mask" "Disabled,Enabled" rbitfld.long 0x00 2. " TX2_MASK ,TX Channel 2 Mask" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TX1_MASK ,TX Channel 1 Mask" "Disabled,Enabled" rbitfld.long 0x00 0. " TX0_MASK ,TX Channel 0 Mask" "Disabled,Enabled" else bitfld.long 0x00 7. " TX7_MASK ,TX Channel 7 Mask" "Disabled,Enabled" bitfld.long 0x00 6. " TX6_MASK ,TX Channel 6 Mask" "Disabled,Enabled" bitfld.long 0x00 5. " TX5_MASK ,TX Channel 5 Mask" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " TX4_MASK ,TX Channel 4 Mask" "Disabled,Enabled" bitfld.long 0x00 3. " TX3_MASK ,TX Channel 3 Mask" "Disabled,Enabled" bitfld.long 0x00 2. " TX2_MASK ,TX Channel 2 Mask" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TX1_MASK ,TX Channel 1 Mask" "Disabled,Enabled" bitfld.long 0x00 0. " TX0_MASK ,TX Channel 0 Mask" "Disabled,Enabled" endif group.long 0x8C++0x03 line.long 0x00 "TX_INTMASK_CLEAR,CPDMA_INT TX INTERRUPT MASK CLEAR REGISTER" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 7. " TX7_MASK ,TX Channel 7 Mask" "Enabled,Disabled" rbitfld.long 0x00 6. " TX6_MASK ,TX Channel 6 Mask" "Enabled,Disabled" bitfld.long 0x00 5. " TX5_MASK ,TX Channel 5 Mask" "Enabled,Disabled" textline " " rbitfld.long 0x00 4. " TX4_MASK ,TX Channel 4 Mask" "Enabled,Disabled" bitfld.long 0x00 3. " TX3_MASK ,TX Channel 3 Mask" "Enabled,Disabled" rbitfld.long 0x00 2. " TX2_MASK ,TX Channel 2 Mask" "Enabled,Disabled" textline " " bitfld.long 0x00 1. " TX1_MASK ,TX Channel 1 Mask" "Enabled,Disabled" rbitfld.long 0x00 0. " TX0_MASK ,TX Channel 0 Mask" "Enabled,Disabled" else bitfld.long 0x00 7. " TX7_MASK ,TX Channel 7 Mask" "Enabled,Disabled" bitfld.long 0x00 6. " TX6_MASK ,TX Channel 6 Mask" "Enabled,Disabled" bitfld.long 0x00 5. " TX5_MASK ,TX Channel 5 Mask" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " TX4_MASK ,TX Channel 4 Mask" "Enabled,Disabled" bitfld.long 0x00 3. " TX3_MASK ,TX Channel 3 Mask" "Enabled,Disabled" bitfld.long 0x00 2. " TX2_MASK ,TX Channel 2 Mask" "Enabled,Disabled" textline " " bitfld.long 0x00 1. " TX1_MASK ,TX Channel 1 Mask" "Enabled,Disabled" bitfld.long 0x00 0. " TX0_MASK ,TX Channel 0 Mask" "Enabled,Disabled" endif rgroup.long 0x90++0x03 line.long 0x00 "CPDMA_IN_VECTOR,CPDMA_INT INPUT VECTOR" group.long 0x94++0x03 line.long 0x00 "CPDMA_EOI_VECTOR,CPDMA_INT END OF INTERRUPT VECTOR" bitfld.long 0x00 0.--4. " DMA_EOI_VECTOR ,DMA End of Interrupt Vector " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0xA0++0x03 line.long 0x00 "RX_INTSTAT_RAW,CPDMA_INT RX INTERRUPT STATUS REGISTER " bitfld.long 0x00 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND raw int read " "Disabled,Enabled" textline " " bitfld.long 0x00 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND raw int read " "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 7. " RX7_PEND ,RX7_PEND raw int read " "Disabled,Enabled" textline " " bitfld.long 0x00 6. " RX6_PEND ,RX6_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 5. " RX5_PEND ,RX5_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 4. " RX4_PEND ,RX4_PEND raw int read " "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RX3_PEND ,RX3_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 2. " RX2_PEND ,RX2_PEND raw int read " "Disabled,Enabled" bitfld.long 0x00 1. " RX1_PEND ,RX1_PEND raw int read " "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RX0_PEND ,RX0_PEND raw int read " "Disabled,Enabled" rgroup.long 0xA4++0x03 line.long 0x00 "RX_INTSTAT_MASKED,CPDMA_INT RX INTERRUPT STATUS REGISTER" bitfld.long 0x00 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND masked int read" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND masked int read" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 7. " RX7_PEND ,RX7_PEND masked int read" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " RX6_PEND ,RX6_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 5. " RX5_PEND ,RX5_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 4. " RX4_PEND ,RX4_PEND masked int read" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RX3_PEND ,RX3_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 2. " RX2_PEND ,RX2_PEND masked int read" "Disabled,Enabled" bitfld.long 0x00 1. " RX1_PEND ,RX1_PEND masked int read" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RX0_PEND ,RX0_PEND masked int read" "Disabled,Enabled" group.long 0xA8++0x03 line.long 0x00 "RX_INTMASK_SET,CPDMA_INT RX INTERRUPT MASK SET REGISTER" bitfld.long 0x00 15. " RX7_THRESH_PEND_MASK ,RX Channel 7 Threshold Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 14. " RX6_THRESH_PEND_MASK ,RX Channel 6 Threshold Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 13. " RX5_THRESH_PEND_MASK ,RX Channel 5 Threshold Pending Int. Mask " "Disabled,Enabled" textline " " bitfld.long 0x00 12. " RX4_THRESH_PEND_MASK ,RX Channel 4 Threshold Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 11. " RX3_THRESH_PEND_MASK ,RX Channel 3 Threshold Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 10. " RX2_THRESH_PEND_MASK ,RX Channel 2 Threshold Pending Int. Mask " "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RX1_THRESH_PEND_MASK ,RX Channel 1 Threshold Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 8. " RX0_THRESH_PEND_MASK ,RX Channel 0 Threshold Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 7. " RX7_PEND_MASK ,RX Channel 7 Pending Int. Mask " "Disabled,Enabled" textline " " bitfld.long 0x00 6. " RX6_PEND_MASK ,RX Channel 6 Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 5. " RX5_PEND_MASK ,RX Channel 5 Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 4. " RX4_PEND_MASK ,RX Channel 4 Pending Int. Mask " "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RX3_PEND_MASK ,RX Channel 3 Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 2. " RX2_PEND_MASK ,RX Channel 2 Pending Int. Mask " "Disabled,Enabled" bitfld.long 0x00 1. " RX1_PEND_MASK ,RX Channel 1 Pending Int. Mask " "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RX0_PEND_MASK ,RX Channel 0 Pending Int. Mask " "Disabled,Enabled" group.long 0xAC++0x03 line.long 0x00 "RX_INTMASK_CLEAR,CPDMA_INT RX INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x00 15. " RX7_THRESH_PEND_MASK ,RX Channel 7 Threshold Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 14. " RX6_THRESH_PEND_MASK ,RX Channel 6 Threshold Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 13. " RX5_THRESH_PEND_MASK ,RX Channel 5 Threshold Pending Int. Mask " "Enabled,Disabled" textline " " bitfld.long 0x00 12. " RX4_THRESH_PEND_MASK ,RX Channel 4 Threshold Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 11. " RX3_THRESH_PEND_MASK ,RX Channel 3 Threshold Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 10. " RX2_THRESH_PEND_MASK ,RX Channel 2 Threshold Pending Int. Mask " "Enabled,Disabled" textline " " bitfld.long 0x00 9. " RX1_THRESH_PEND_MASK ,RX Channel 1 Threshold Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 8. " RX0_THRESH_PEND_MASK ,RX Channel 0 Threshold Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 7. " RX7_PEND_MASK ,RX Channel 7 Pending Int. Mask " "Enabled,Disabled" textline " " bitfld.long 0x00 6. " RX6_PEND_MASK ,RX Channel 6 Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 5. " RX5_PEND_MASK ,RX Channel 5 Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 4. " RX4_PEND_MASK ,RX Channel 4 Pending Int. Mask " "Enabled,Disabled" textline " " bitfld.long 0x00 3. " RX3_PEND_MASK ,RX Channel 3 Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 2. " RX2_PEND_MASK ,RX Channel 2 Pending Int. Mask " "Enabled,Disabled" bitfld.long 0x00 1. " RX1_PEND_MASK ,RX Channel 1 Pending Int. Mask " "Enabled,Disabled" textline " " bitfld.long 0x00 0. " RX0_PEND_MASK ,RX Channel 0 Pending Int. Mask " "Enabled,Disabled" rgroup.long 0xB0++0x03 line.long 0x00 "DMA_INTSTAT_RAW,CPDMA_INT DMA INTERRUPT STATUS REGISTER " bitfld.long 0x00 1. " HOST_PEND ,Host Pending Interrupt " "Disabled,Enabled" bitfld.long 0x00 0. " STAT_PEND ,Statistics Pending Interrupt" "Disabled,Enabled" rgroup.long 0xB4++0x03 line.long 0x00 "DMA_INTSTAT_MASKED,CPDMA_INT DMA INTERRUPT STATUS REGISTER" bitfld.long 0x00 1. " HOST_PEND ,Host Pending Interrupt" "Disabled,Enabled" bitfld.long 0x00 0. " STAT_PEND ,Statistics Pending Interrupt" "Disabled,Enabled" group.long 0xB8++0x03 line.long 0x00 "DMA_INTMASK_SET,CPDMA_INT DMA INTERRUPT MASK SET REGISTER" bitfld.long 0x00 1. " HOST_ERR_INT_MASK ,Host Error Interrupt Mask" "Disabled,Enabled" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x00 0. " STAT_INT_MASK ,Statistics Interrupt Mask" "Disabled,Enabled" else bitfld.long 0x00 0. " STAT_INT_MASK ,Statistics Interrupt Mask" "Disabled,Enabled" endif group.long 0xBC++0x03 line.long 0x00 "DMA_INTMASK_CLEAR,CPDMA_INT DMA INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x00 1. " HOST_ERR_INT_MASK ,Host Error Interrupt Mask " "Enabled,Disabled" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x00 0. " STAT_INT_MASK ,Statistics Interrupt Mask " "Enabled,Disabled" else bitfld.long 0x00 0. " STAT_INT_MASK ,Statistics Interrupt Mask " "Enabled,Disabled" endif group.long 0xC0++0x03 line.long 0x00 "RX0_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 0" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold" group.long 0xC4++0x03 line.long 0x00 "RX1_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 1" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold" group.long 0xC8++0x03 line.long 0x00 "RX2_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 2" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold" group.long 0xCC++0x03 line.long 0x00 "RX3_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 3" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold" group.long 0xD0++0x03 line.long 0x00 "RX4_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 4" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold" group.long 0xD4++0x03 line.long 0x00 "RX5_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 5" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold" group.long 0xD8++0x03 line.long 0x00 "RX6_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 6" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold" group.long 0xDC++0x03 line.long 0x00 "RX7_PENDTHRESH,CPDMA_INT RECEIVE THRESHOLD PENDING REGISTER CHANNEL 7" hexmask.long.byte 0x00 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold" wgroup.long 0xE0++0x03 line.long 0x00 "RX0_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 0" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count" wgroup.long 0xE4++0x03 line.long 0x00 "RX1_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 1" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count" wgroup.long 0xE8++0x03 line.long 0x00 "RX2_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 2" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count" wgroup.long 0xEC++0x03 line.long 0x00 "RX3_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 3" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count" wgroup.long 0xF0++0x03 line.long 0x00 "RX4_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 4" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count" wgroup.long 0xF4++0x03 line.long 0x00 "RX5_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 5" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count" wgroup.long 0xF8++0x03 line.long 0x00 "RX6_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 6" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count" wgroup.long 0xFC++0x03 line.long 0x00 "RX7_FREEBUFFER,CPDMA_INT RECEIVE FREE BUFFER REGISTER CHANNEL 7" hexmask.long.word 0x00 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count" sif (!cpuis("AM335*")&&!cpuis("DRA62*")) group.long 0xA00++0x7F line.long 0x00 "TX0_HDP,CPDMA_STATERAM TX CHANNEL 0 HEAD DESC POINTER Register" line.long 0x04 "TX1_HDP,CPDMA_STATERAM TX CHANNEL 1 HEAD DESC POINTER Register" line.long 0x08 "TX2_HDP,CPDMA_STATERAM TX CHANNEL 2 HEAD DESC POINTER Register" line.long 0x0C "TX3_HDP,CPDMA_STATERAM TX CHANNEL 3 HEAD DESC POINTER Register" line.long 0x10 "TX4_HDP,CPDMA_STATERAM TX CHANNEL 4 HEAD DESC POINTER Register" line.long 0x14 "TX5_HDP,CPDMA_STATERAM TX CHANNEL 5 HEAD DESC POINTER Register" line.long 0x18 "TX6_HDP,CPDMA_STATERAM TX CHANNEL 6 HEAD DESC POINTER Register" line.long 0x1C "TX7_HDP,CPDMA_STATERAM TX CHANNEL 7 HEAD DESC POINTER Register" line.long 0x20 "RX0_HDP,CPDMA_STATERAM RX 0 CHANNEL 0 HEAD DESC POINTER Register" line.long 0x24 "RX1_HDP,CPDMA_STATERAM RX 1 CHANNEL 1 HEAD DESC POINTER Register" line.long 0x28 "RX2_HDP,CPDMA_STATERAM RX 2 CHANNEL 2 HEAD DESC POINTER Register" line.long 0x2C "RX3_HDP,CPDMA_STATERAM RX 3 CHANNEL 3 HEAD DESC POINTER Register" line.long 0x30 "RX4_HDP,CPDMA_STATERAM RX 4 CHANNEL 4 HEAD DESC POINTER Register" line.long 0x34 "RX5_HDP,CPDMA_STATERAM RX 5 CHANNEL 5 HEAD DESC POINTER Register" line.long 0x38 "RX6_HDP,CPDMA_STATERAM RX 6 CHANNEL 6 HEAD DESC POINTER Register" line.long 0x3C "RX7_HDP,CPDMA_STATERAM RX 7 CHANNEL 7 HEAD DESC POINTER Register" line.long 0x40 "TX0_CP,CPDMA_STATERAM TX CHANNEL 0 COMPLETION POINTER REGISTER" line.long 0x44 "TX1_CP,CPDMA_STATERAM TX CHANNEL 1 COMPLETION POINTER REGISTER Register" line.long 0x48 "TX2_CP,CPDMA_STATERAM TX CHANNEL 2 COMPLETION POINTER REGISTER Register" line.long 0x4C "TX3_CP,CPDMA_STATERAM TX CHANNEL 3 COMPLETION POINTER REGISTER Register" line.long 0x50 "TX4_CP,CPDMA_STATERAM TX CHANNEL 4 COMPLETION POINTER REGISTER Register" line.long 0x54 "TX5_CP,CPDMA_STATERAM TX CHANNEL 5 COMPLETION POINTER REGISTER Register" line.long 0x58 "TX6_CP,CPDMA_STATERAM TX CHANNEL 6 COMPLETION POINTER REGISTER Register" line.long 0x5C "TX7_CP,CPDMA_STATERAM TX CHANNEL 7 COMPLETION POINTER REGISTER Register" line.long 0x60 "RX0_CP,CPDMA_STATERAM RX CHANNEL 0 COMPLETION POINTER REGISTER Register" line.long 0x64 "RX1_CP,CPDMA_STATERAM RX CHANNEL 1 COMPLETION POINTER REGISTER Register" line.long 0x68 "RX2_CP,CPDMA_STATERAM RX CHANNEL 2 COMPLETION POINTER REGISTER Register" line.long 0x6C "RX3_CP,CPDMA_STATERAM RX CHANNEL 3 COMPLETION POINTER REGISTER Register" line.long 0x70 "RX4_CP,CPDMA_STATERAM RX CHANNEL 4 COMPLETION POINTER REGISTER Register" line.long 0x74 "RX5_CP,CPDMA_STATERAM RX CHANNEL 5 COMPLETION POINTER REGISTER Register" line.long 0x78 "RX6_CP,CPDMA_STATERAM RX CHANNEL 6 COMPLETION POINTER REGISTER Register" line.long 0x7C "RX7_CP,CPDMA_STATERAM RX CHANNEL 7 COMPLETION POINTER REGISTER Register" endif width 0xb tree.end tree "CPSW CPTS" base ad:0x4A101800 width 21. rgroup.long 0x00++0x03 line.long 0x00 "CPTS_IDVER,IDENTIFICATION AND VERSION REGISTER" hexmask.long.word 0x00 16.--31. 1. " TX_IDENT ,TX Identification Value" hexmask.long.byte 0x00 11.--15. 1. " REG_RTL_VERSION ,RTL Version" hexmask.long.byte 0x00 8.--10. 1. " REG_MAJOR_REVISION ,Major Revision" textline " " hexmask.long.byte 0x00 0.--7. 1. " MINOR_VER ,Minor Version Value" group.long 0x04++0x03 line.long 0x00 "CPTS_CONTROL,TIME SYNC CONTROL REGISTER" bitfld.long 0x00 11. " HW4_TS_PUSH_EN ,Hardware push 4 enable" "Disabled,Enabled" bitfld.long 0x00 10. " HW3_TS_PUSH_EN ,Hardware push 3 enable" "Disabled,Enabled" bitfld.long 0x00 9. " HW2_TS_PUSH_EN ,Hardware push 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HW1_TS_PUSH_EN ,Hardware push 1 enable" "Disabled,Enabled" bitfld.long 0x00 1. " INT_TEST ,Interrupt Test" "Disabled,Enabled" bitfld.long 0x00 0. " CPTS_EN ,Time Sync Enable" "Disabled,Enabled" sif (!cpuis("DRA62*")&&!cpuis("AM335*")) group.long 0x08++0x03 line.long 0x00 "CPTS_RFTCLK_SEL,REFERENCE CLOCK SELECT REGISTER" bitfld.long 0x00 0.--4. " RFTCLK_SEL ,Reference Clock Select" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" endif wgroup.long 0x0C++0x03 line.long 0x00 "CPTS_TS_PUSH,TIME STAMP EVENT PUSH REGISTER" bitfld.long 0x00 0. " TS_PUSH ,Time stamp event push" "No effect,Push" group.long 0x10++0x03 line.long 0x00 "CPTS_TS_LOAD_VAL,TIME STAMP LOAD VALUE REGISTER" wgroup.long 0x14++0x03 line.long 0x00 "CPTS_TS_LOAD_EN,TIME STAMP LOAD ENABLE REGISTER" bitfld.long 0x00 0. " TS_LOAD_EN ,Time Stamp Load" "Disable,Enable" group.long 0x20++0x03 line.long 0x00 "CPTS_INTSTAT_RAW,TIME SYNC INTERRUPT STATUS RAW REGISTER" bitfld.long 0x00 0. " TS_PEND_RAW ,TS_PEND_RAW int read " "Enabled,Disabled" rgroup.long 0x24++0x03 line.long 0x00 "CPTS_INTSTAT_MASKED,TIME SYNC INTERRUPT STATUS MASKED REGISTER" bitfld.long 0x00 0. " TS_PEND ,TS_PEND masked interrupt read" "Disabled,Enabled" group.long 0x28++0x03 line.long 0x00 "CPTS_INT_ENABLE,TIME SYNC INTERRUPT ENABLE REGISTER" bitfld.long 0x00 0. " TS_PEND_EN ,TS_PEND masked interrupt enable" "Disabled,Enabled" wgroup.long 0x30++0x03 line.long 0x00 "CPTS_EVENT_POP,EVENT INTERRUPT POP REGISTER" bitfld.long 0x00 0. " EVENT_POP ,Event Pop" "Disabled,Enabled" rgroup.long 0x34++0x03 line.long 0x00 "CPTS_EVENT_LOW,LOWER 32-BITS OF THE EVENT VALUE" rgroup.long 0x38++0x03 line.long 0x00 "CPTS_EVENT_HIGH,UPPER 32-BITS OF THE EVENT VALUE" bitfld.long 0x00 24.--28. " PORT_NUMBER ,Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--23. " EVENT_TYPE ,Time Sync Event Type," "Time Stamp Push Event,Time Stamp Rollover Event,Time Stamp Half Rollover Event,Hardware Time Stamp Push Event,Ethernet Receive Event,Ethernet Transmit Event,?..." bitfld.long 0x00 16.--19. " MESSAGE_TYPE ,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--15. 1. " SEQUENCE_ID ,The 16-bit sequence id is the value that was contained in an ethernet transmit or receivetime sync packet" width 0xb tree.end tree "CPSW STATS" base ad:0x4A100900 tree "Rx-only Statistics" width 9. group.long 0x00++0x2b line.long 0x00 "GRXFS,Good Rx Frames Section" line.long 0x04 "BRXFS,Broadcast Rx Frames Section" line.long 0x08 "MRXFS,Multicast Rx Frames Section" line.long 0x0c "PRXFS,Pause Rx Frames Section" line.long 0x10 "RXCRCES,Rx CRC Errors Section" line.long 0x14 "RXACES,Rx Align/Code Errors Section" line.long 0x18 "ORXFS,Oversize Rx Frames Section" line.long 0x1c "RXJS,Rx Jabbers Section" line.long 0x20 "URXFS,Undersize (Short) Rx Frames Section" line.long 0x24 "RXFS,Rx Fragments Section" line.long 0x28 "RXOS,Rx Octets Section" tree.end tree "Rx-only Statistics" width 9. group.long 0x34++0x33 line.long 0x00 "GTXFS,Good Tx Frames Section" line.long 0x04 "BTXFS,Broadcast Tx Frames Section" line.long 0x08 "MTXFS,Multicast Tx Frames Section" line.long 0x0c "PTXFS,Pause Tx Frames Section" line.long 0x10 "TXCRCES,Deferred Tx Frames Section" line.long 0x14 "TXACES,Collisions Section" line.long 0x18 "OTXFS,Single Collision Tx Frames Section" line.long 0x1c "TXJS,Multiple Collision Tx Frames Section" line.long 0x20 "UTXFS,Excessive Collisions Section" line.long 0x24 "TXFS,Late Collisions Section" line.long 0x28 "TXOS,Tx Underrun Section" line.long 0x2c "CSES,Carrier Sense Errors Section" line.long 0x30 "TXOS,Tx Octets Section" tree.end tree "Rx- and Tx-Shared Statistics" width 17. group.long 0x68++0x27 line.long 0x00 "RXTX64OFS,Rx + Tx 64 Octet Frames Section" line.long 0x04 "RXTX65_127OFS,Rx + Tx 65?27 Octet Frames Section" line.long 0x08 "RXTX128_255OFS,Rx + Tx 128?55 Octet Frames Section" line.long 0x0c "RXTX256_511OFS,Rx + Tx 256?11 Octet Frames Section" line.long 0x10 "RXTX512_1023OFS,Rx + Tx 512?023 Octet Frames Section" line.long 0x14 "RXTX1024_UPOFS,Rx + Tx 1024_Up Octet Frames Section" line.long 0x18 "NOS,Net Octets Section" line.long 0x1c "RXSFOS,Rx Start of Frame Overruns Section" line.long 0x20 "RXMFOS,Rx Middle of Frame Overruns Section" line.long 0x24 "RXDMAOS,Rx DMA Overruns Section" tree.end width 0xb tree.end tree "CPDMA STATERAM" base ad:0x4A100A00 width 9. tree "TX HEAD DESC POINTERS" group.long 0x0++0x03 line.long 0x00 "TX0_HDP,CPDMA_STATERAM TX CHANNEL 0 HEAD DESC POINTER" group.long 0x4++0x03 line.long 0x00 "TX1_HDP,CPDMA_STATERAM TX CHANNEL 1 HEAD DESC POINTER" group.long 0x8++0x03 line.long 0x00 "TX2_HDP,CPDMA_STATERAM TX CHANNEL 2 HEAD DESC POINTER" group.long 0xC++0x03 line.long 0x00 "TX3_HDP,CPDMA_STATERAM TX CHANNEL 3 HEAD DESC POINTER" group.long 0x10++0x03 line.long 0x00 "TX4_HDP,CPDMA_STATERAM TX CHANNEL 4 HEAD DESC POINTER" group.long 0x14++0x03 line.long 0x00 "TX5_HDP,CPDMA_STATERAM TX CHANNEL 5 HEAD DESC POINTER" group.long 0x18++0x03 line.long 0x00 "TX6_HDP,CPDMA_STATERAM TX CHANNEL 6 HEAD DESC POINTER" group.long 0x1C++0x03 line.long 0x00 "TX7_HDP,CPDMA_STATERAM TX CHANNEL 7 HEAD DESC POINTER" tree.end tree "RX HEAD DESC POINTERS" group.long 0x20++0x03 line.long 0x00 "RX0_HDP,CPDMA_STATERAM RX CHANNEL 0 HEAD DESC POINTER" group.long 0x24++0x03 line.long 0x00 "RX1_HDP,CPDMA_STATERAM RX CHANNEL 1 HEAD DESC POINTER" group.long 0x28++0x03 line.long 0x00 "RX2_HDP,CPDMA_STATERAM RX CHANNEL 2 HEAD DESC POINTER" group.long 0x2C++0x03 line.long 0x00 "RX3_HDP,CPDMA_STATERAM RX CHANNEL 3 HEAD DESC POINTER" group.long 0x30++0x03 line.long 0x00 "RX4_HDP,CPDMA_STATERAM RX CHANNEL 4 HEAD DESC POINTER" group.long 0x34++0x03 line.long 0x00 "RX5_HDP,CPDMA_STATERAM RX CHANNEL 5 HEAD DESC POINTER" group.long 0x38++0x03 line.long 0x00 "RX6_HDP,CPDMA_STATERAM RX CHANNEL 6 HEAD DESC POINTER" group.long 0x3C++0x03 line.long 0x00 "RX7_HDP,CPDMA_STATERAM RX CHANNEL 7 HEAD DESC POINTER" tree.end width 8. tree "TX COMPLETION POINTERS" group.long 0x40++0x03 line.long 0x00 "TX0_CP,CPDMA_STATERAM TX CHANNEL 0 COMPLETION POINTER REGISTER" group.long 0x44++0x03 line.long 0x00 "TX1_CP,CPDMA_STATERAM TX CHANNEL 1 COMPLETION POINTER REGISTER" group.long 0x48++0x03 line.long 0x00 "TX2_CP,CPDMA_STATERAM TX CHANNEL 2 COMPLETION POINTER REGISTER" group.long 0x4C++0x03 line.long 0x00 "TX3_CP,CPDMA_STATERAM TX CHANNEL 3 COMPLETION POINTER REGISTER" group.long 0x50++0x03 line.long 0x00 "TX4_CP,CPDMA_STATERAM TX CHANNEL 4 COMPLETION POINTER REGISTER" group.long 0x54++0x03 line.long 0x00 "TX5_CP,CPDMA_STATERAM TX CHANNEL 5 COMPLETION POINTER REGISTER" group.long 0x58++0x03 line.long 0x00 "TX6_CP,CPDMA_STATERAM TX CHANNEL 6 COMPLETION POINTER REGISTER" group.long 0x5C++0x03 line.long 0x00 "TX7_CP,CPDMA_STATERAM TX CHANNEL 7 COMPLETION POINTER REGISTER" tree.end tree "RX COMPLETION POINTERS" group.long 0x60++0x03 line.long 0x00 "RX0_CP,CPDMA_STATERAM RX CHANNEL 0 COMPLETION POINTER REGISTER" group.long 0x64++0x03 line.long 0x00 "RX1_CP,CPDMA_STATERAM RX CHANNEL 1 COMPLETION POINTER REGISTER" group.long 0x68++0x03 line.long 0x00 "RX2_CP,CPDMA_STATERAM RX CHANNEL 2 COMPLETION POINTER REGISTER" group.long 0x6C++0x03 line.long 0x00 "RX3_CP,CPDMA_STATERAM RX CHANNEL 3 COMPLETION POINTER REGISTER" group.long 0x70++0x03 line.long 0x00 "RX4_CP,CPDMA_STATERAM RX CHANNEL 4 COMPLETION POINTER REGISTER" group.long 0x74++0x03 line.long 0x00 "RX5_CP,CPDMA_STATERAM RX CHANNEL 5 COMPLETION POINTER REGISTER" group.long 0x78++0x03 line.long 0x00 "RX6_CP,CPDMA_STATERAM RX CHANNEL 6 COMPLETION POINTER REGISTER" group.long 0x7C++0x03 line.long 0x00 "RX7_CP,CPDMA_STATERAM RX CHANNEL 7 COMPLETION POINTER REGISTER" tree.end width 0xb tree.end tree "CPSW PORT" tree "PORT 0" base ad:0x4A100100 width 21. group.long 0x00++0x03 line.long 0x00 "P0_CONTROL,CPSW PORT 0 CONTROL REGISTER" bitfld.long 0x00 28.--30. " P0_DLR_CPDMA_CH ,Port 0 DLR CPDMA Channel This field indicates the CPDMA channel that DLR packets will be received on" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 24. " P0_PASS_PRI_TAGGED ,Port 0 Pass Priority Tagged" "P0_PORT_VLAN[11:0],Unchanged" bitfld.long 0x00 21. " P0_VLAN_LTYPE2_EN ,Port 0 VLAN LTYPE 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " P0_VLAN_LTYPE1_EN ,Port 0 VLAN LTYPE 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " P0_DSCP_PRI_EN ,Port 0 DSCP Priority Enable" "Disabled,Enabled" textline " " group.long 0x08++0x03 line.long 0x00 "P0_MAX_BLKS,CPSW PORT 0 MAXIMUM FIFO BLOCKS REGISTER" bitfld.long 0x00 4.--8. " P0_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P0_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "Reserved,Reserved,Reserved,3,4,5,6,?..." rgroup.long 0x0C++0x03 line.long 0x00 "P0_BLK_CNT,CPSW PORT 0 FIFO BLOCK USAGE COUNT (READ ONLY)" bitfld.long 0x00 4.--8. " P0_TX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P0_RX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "P0_TX_IN_CTL,CPSW PORT 0 TRANSMIT FIFO CONTROL" bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "Normal priority mode,Dual MAC mode,Rate Limit mode,?..." textline " " bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue" group.long 0x14++0x03 line.long 0x00 "P0_PORT_VLAN,CPSW PORT 0 VLAN REGISTER" bitfld.long 0x00 13.--15. " PORT_PRI ,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12. " PORT_CFI ,Port CFI bit" "Enabled,Disabled" hexmask.long.word 0x00 0.--11. 1. " PORT_VID ,Port VLAN ID" group.long 0x18++0x03 line.long 0x00 "P0_TX_PRI_MAP,CPSW PORT 0 TX HEADER PRI TO SWITCH PRI MAPPING REGISTER" bitfld.long 0x00 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue pri" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue pri" "0,1,2,3" group.long 0x1C++0x03 line.long 0x00 "P0_CPDMA_TX_PRI_MAP,CPSW CPDMA TX (PORT 0 RX) PKT PRIORITY TO HEADER PRIORITY" bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet pri of 0x7 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet pri of 0x6 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet pri of 0x5 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet pri of 0x4 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet pri of 0x3 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet pri of 0x2 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet pri of 0x1 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet pri of 0x0 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "P0_CPDMA_RX_CH_MAP,CPSW CPDMA RX (PORT 0 TX) SWITCH PRIORITY TO DMA CHANNEL" bitfld.long 0x00 28.--30. " P2_PRI3 ,Port 2 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " P2_PRI2 ,Port 2 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " P2_PRI1 ,Port 2 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " P2_PRI0 ,Port 2 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " P1_PRI3 ,Port 1 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " P1_PRI2 ,Port 1 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " P1_PRI1 ,Port 1 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " P1_PRI0 ,Port 1 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" group.long 0x30++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP0,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0 " bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x34++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP1,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1" bitfld.long 0x00 28.--30. " PRI15 ,Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI14 ,Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI13 ,Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI12 ,Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI11 ,Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI10 ,Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI9 ,Priority 9 - A packet TOS of 0d9 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI8 ,Priority 8 - A packet TOS of 0d8 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x38++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP2,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2" bitfld.long 0x00 28.--30. " PRI23 ,Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI22 ,Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI21 ,Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI20 ,Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI19 ,Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI18 ,Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI17 ,Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI16 ,Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x3C++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP3,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3" bitfld.long 0x00 28.--30. " PRI31 ,Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI30 ,Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI29 ,Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI28 ,Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI27 ,Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI26 ,Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI25 ,Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI24 ,Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x40++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP4,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4" bitfld.long 0x00 28.--30. " PRI39 ,Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI38 ,Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI37 ,Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI36 ,Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI35 ,Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI34 ,Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI33 ,Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI32 ,Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x44++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP5,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5" bitfld.long 0x00 28.--30. " PRI47 ,Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI46 ,Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI45 ,Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI44 ,Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI43 ,Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI42 ,Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI41 ,Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI40 ,Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP6,CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6" bitfld.long 0x00 28.--30. " PRI55 ,Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI54 ,Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI53 ,Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI52 ,Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI51 ,Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI50 ,Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI49 ,Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI48 ,Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x4C++0x03 line.long 0x00 "P0_RX_DSCP_PRI_MAP7,CPSW PORT 0 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE" bitfld.long 0x00 28.--30. " PRI63 ,Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI62 ,Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI61 ,Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI60 ,Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI59 ,Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI58 ,Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI57 ,Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI56 ,Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" width 0xb tree.end tree "PORT 1" base ad:0x4A100200 width 21. group.long 0x00++0x03 line.long 0x00 "P1_CONTROL,CPSW PORT 1 CONTROL REGISTER" bitfld.long 0x00 24. " P1_PASS_PRI_TAGGED ,Port 1 Pass Priority Tagged" "P1_PORT_VLAN[11:0],Unchanged" bitfld.long 0x00 21. " P1_VLAN_LTYPE2_EN ,Port 1 VLAN LTYPE 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " P1_VLAN_LTYPE1_EN ,Port 1 VLAN LTYPE 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " P1_DSCP_PRI_EN ,Port 1 DSCP Priority Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " P1_TS_320 ,Port 1 Time Sync Destination Port Number 320 enable" "Disabled,Annex D (UDP/IPv4)" bitfld.long 0x00 13. " P1_TS_319 ,Port 1 Time Sync Destination Port Number 319 enable" "Disabled,Annex D (UDP/IPv4)" bitfld.long 0x00 12. " P1_TS_132 ,Port 1 Time Sync Destination IP Address 132 enable" "Disabled,Annex D (UDP/IPv4)" textline " " bitfld.long 0x00 11. " P1_TS_131 ,Port 1 Time Sync Destination IP Address 131 enable" "Disabled,Annex D (UDP/IPv4)" bitfld.long 0x00 10. " P1_TS_130 ,Port 1 Time Sync Destination IP Address 130 enable" "Disabled,Annex D (UDP/IPv4)" textline " " bitfld.long 0x00 9. " P1_TS_129 ,Port 1 Time Sync Destination IP Address 129 enable" "Disabled,Annex D (UDP/IPv4)" bitfld.long 0x00 8. " P1_TS_TTL_NONZERO ,Port #1 Time Sync Time To Live Non-zero enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " P1_TS_ANNEX_D_EN ,Port 1 Time Sync Annex D enable" "Disabled,Annex D (UDP/IPv4)" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x00 3. " P1_TS_LTYPE2_EN ,Port 1 Time Sync LTYPE 2 enable" "Disabled,Enabled" else bitfld.long 0x00 3. " P1_TS_LTYPE2_EN ,Port 1 Time Sync LTYPE 2 enable" "Disabled,Enabled" endif bitfld.long 0x00 2. " P1_TS_LTYPE1_EN ,Port 1 Time Sync LTYPE 1" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " P1_TS_TX_EN ,Port 1 Time Sync Transmit Enable 0 " "Disabled,Enabled" bitfld.long 0x00 0. " P1_TS_RX_EN ,Port 1 Time Sync Receive Enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "P1_MAX_BLKS,CPSW PORT 1 MAXIMUM FIFO BLOCKS REGISTER" bitfld.long 0x00 4.--8. " P1_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P1_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "Reserved,Reserved,Reserved,3,4,5,6,?..." rgroup.long 0x0C++0x03 line.long 0x00 "P1_BLK_CNT,CPSW PORT 1 FIFO BLOCK USAGE COUNT (READ ONLY)" bitfld.long 0x00 4.--8. " P1_TX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P1_RX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "P1_TX_IN_CTL,CPSW PORT 1 TRANSMIT FIFO CONTROL" bitfld.long 0x00 24.--27. " HOST_BLKS_REM ,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "Normal priority mode,Reserved,Rate Limit mode,?..." textline " " bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue" group.long 0x14++0x03 line.long 0x00 "P1_PORT_VLAN,CPSW PORT 1 VLAN REGISTER" bitfld.long 0x00 13.--15. " PORT_PRI ,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12. " PORT_CFI ,Port CFI bit" "Enabled,Disabled" hexmask.long.word 0x00 0.--11. 1. " PORT_VID ,Port VLAN ID" group.long 0x18++0x03 line.long 0x00 "P1_TX_PRI_MAP,CPSW PORT 1 TX HEADER PRI TO SWITCH PRI MAPPING REGISTER" bitfld.long 0x00 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue pri" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue pri" "0,1,2,3" group.long 0x1C++0x03 line.long 0x00 "P1_TS_SEQ_MTYPE,TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE REGISTER" hexmask.long.byte 0x00 16.--21. 1. " P1_TS_SEQ_ID_OFFSET ,Port 1 Time Sync Sequence ID Offset" hexmask.long.word 0x00 0.--15. 1. " P1_TS_MSG_TYPE_EN ,Port 1 Time Sync Message Type Enable" group.long 0x20++0x03 line.long 0x00 "P1_SA_LO,SOURCE ADDRESS LOW REGISTER" hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_7_0 ,Source Address bits 0:7" hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_15_8 ,Source Address bits 8:15" group.long 0x24++0x03 line.long 0x00 "P1_SA_HI,CPSW CPGMAC_SL1 SOURCE ADDRESS HIGH REGISTER" hexmask.long.byte 0x00 24.--31. 1. " MACSRCADDR_23_16 ,Source Address bits 23:16" hexmask.long.byte 0x00 16.--23. 1. " MACSRCADDR_31_24 ,Source Address bits 31:24" hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_39_32 ,Source Address bits 39:32" hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_47_40 ,Source Address bits 47:40 " group.long 0x28++0x03 line.long 0x00 "P1_SEND_PERCENT,CPSW PORT 1 TRANSMIT QUEUE SEND PERCENTAGES" hexmask.long.byte 0x00 16.--22. 1. " PRI3_SEND_PERCENT ,SPriority 3 Transmit Percentage" hexmask.long.byte 0x00 8.--14. 1. " PRI2_SEND_PERCENT ,SPriority 2 Transmit Percentage" hexmask.long.byte 0x00 0.--6. 1. " PRI1_SEND_PERCENT ,SPriority 1 Transmit Percentage" group.long 0x30++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP0,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0 " bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x34++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP1,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1" bitfld.long 0x00 28.--30. " PRI15 ,Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI14 ,Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI13 ,Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI12 ,Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI11 ,Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI10 ,Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI9 ,Priority 9 - A packet TOS of 0d9 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI8 ,Priority 8 - A packet TOS of 0d8 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x38++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP2,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2" bitfld.long 0x00 28.--30. " PRI23 ,Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI22 ,Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI21 ,Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI20 ,Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI19 ,Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI18 ,Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI17 ,Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI16 ,Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x3C++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP3,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3" bitfld.long 0x00 28.--30. " PRI31 ,Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI30 ,Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI29 ,Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI28 ,Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI27 ,Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI26 ,Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI25 ,Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI24 ,Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x40++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP4,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4" bitfld.long 0x00 28.--30. " PRI39 ,Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI38 ,Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI37 ,Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI36 ,Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI35 ,Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI34 ,Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI33 ,Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI32 ,Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x44++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP5,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5" bitfld.long 0x00 28.--30. " PRI47 ,Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI46 ,Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI45 ,Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI44 ,Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI43 ,Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI42 ,Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI41 ,Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI40 ,Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP6,CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6" bitfld.long 0x00 28.--30. " PRI55 ,Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI54 ,Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI53 ,Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI52 ,Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI51 ,Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI50 ,Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI49 ,Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI48 ,Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x4C++0x03 line.long 0x00 "P1_RX_DSCP_PRI_MAP7,CPSW PORT 1 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE" bitfld.long 0x00 28.--30. " PRI63 ,Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI62 ,Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI61 ,Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI60 ,Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI59 ,Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI58 ,Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI57 ,Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI56 ,Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" width 0xb tree.end tree "PORT 2" base ad:0x4A100300 width 21. group.long 0x00++0x03 line.long 0x00 "P2_CONTROL,CPSW PORT 2 CONTROL REGISTER" bitfld.long 0x00 24. " P2_PASS_PRI_TAGGED ,Port 2 Pass Priority Tagged" "P2_PORT_VLAN[11:0],Unchanged" bitfld.long 0x00 21. " P2_VLAN_LTYPE2_EN ,Port 2 VLAN LTYPE 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " P2_VLAN_LTYPE1_EN ,Port 2 VLAN LTYPE 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " P2_DSCP_PRI_EN ,Port 2 DSCP Priority Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " P1_TS_320 ,Port 2 Time Sync Destination Port Number 320 enable" "Disabled,Annex D (UDP/IPv4)" bitfld.long 0x00 13. " P1_TS_319 ,Port 2 Time Sync Destination Port Number 319 enable" "Disabled,Annex D (UDP/IPv4)" bitfld.long 0x00 12. " P1_TS_132 ,Port 2 Time Sync Destination IP Address 132 enable" "Disabled,Annex D (UDP/IPv4)" textline " " bitfld.long 0x00 11. " P1_TS_131 ,Port 2 Time Sync Destination IP Address 131 enable" "Disabled,Annex D (UDP/IPv4)" bitfld.long 0x00 10. " P1_TS_130 ,Port 2 Time Sync Destination IP Address 130 enable" "Disabled,Annex D (UDP/IPv4)" textline " " bitfld.long 0x00 9. " P2_TS_129 ,Port 2 Time Sync Destination IP Address 129 enable" "Disabled,Annex D (UDP/IPv4)" bitfld.long 0x00 8. " P2_TS_TTL_NONZERO ,Port #1 Time Sync Time To Live Non-zero enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " P1_TS_ANNEX_D_EN ,Port 2 Time Sync Annex D enable" "Disabled,Annex D (UDP/IPv4)" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x00 3. " P1_TS_LTYPE2_EN ,Port 2 Time Sync LTYPE 2 enable" "Disabled,Enabled" else bitfld.long 0x00 3. " P1_TS_LTYPE2_EN ,Port 2 Time Sync LTYPE 2 enable" "Disabled,Enabled" endif bitfld.long 0x00 2. " P1_TS_LTYPE1_EN ,Port 2 Time Sync LTYPE 1" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " P1_TS_TX_EN ,Port 2 Time Sync Transmit Enable 0 " "Disabled,Enabled" bitfld.long 0x00 0. " P1_TS_RX_EN ,Port 2 Time Sync Receive Enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "P2_MAX_BLKS,CPSW PORT 2 MAXIMUM FIFO BLOCKS REGISTER" bitfld.long 0x00 4.--8. " P2_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P2_RX_MAX_BLKS ,Receive FIFO Maximum Blocks" "Reserved,Reserved,Reserved,3,4,5,6,?..." rgroup.long 0x0C++0x03 line.long 0x00 "P2_BLK_CNT,CPSW PORT 2 FIFO BLOCK USAGE COUNT (READ ONLY)" bitfld.long 0x00 4.--8. " P2_TX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical transmit queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--3. " P2_RX_BLK_CNT ,This value is the number of blocks allocated to the FIFO logical receive queues" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "P2_TX_IN_CTL,CPSW PORT 2 TRANSMIT FIFO CONTROL" bitfld.long 0x00 24.--27. " HOST_BLKS_REM ,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select" "Normal priority mode,Reserved,Rate Limit mode,?..." textline " " bitfld.long 0x00 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual mac mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue" group.long 0x14++0x03 line.long 0x00 "P2_PORT_VLAN,CPSW PORT 2 VLAN REGISTER" bitfld.long 0x00 13.--15. " PORT_PRI ,Port VLAN Priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12. " PORT_CFI ,Port CFI bit" "Enabled,Disabled" hexmask.long.word 0x00 0.--11. 1. " PORT_VID ,Port VLAN ID" group.long 0x18++0x03 line.long 0x00 "P2_TX_PRI_MAP,CPSW PORT 2 TX HEADER PRI TO SWITCH PRI MAPPING REGISTER" bitfld.long 0x00 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue pri" "0,1,2,3" textline " " bitfld.long 0x00 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue pri" "0,1,2,3" bitfld.long 0x00 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue pri" "0,1,2,3" group.long 0x1C++0x03 line.long 0x00 "P2_TS_SEQ_MTYPE,TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE REGISTER" hexmask.long.byte 0x00 16.--21. 1. " P2_TS_SEQ_ID_OFFSET ,Port 2 Time Sync Sequence ID Offset" hexmask.long.word 0x00 0.--15. 1. " P2_TS_MSG_TYPE_EN ,Port 2 Time Sync Message Type Enable" group.long 0x20++0x03 line.long 0x00 "P2_SA_LO,SOURCE ADDRESS LOW REGISTER" hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_7_0 ,Source Address bits 0:7" hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_15_8 ,Source Address bits 8:15" group.long 0x24++0x03 line.long 0x00 "P2_SA_HI,CPSW CPGMAC_SL1 SOURCE ADDRESS HIGH REGISTER" hexmask.long.byte 0x00 24.--31. 1. " MACSRCADDR_23_16 ,Source Address bits 23:16" hexmask.long.byte 0x00 16.--23. 1. " MACSRCADDR_31_24 ,Source Address bits 31:24" hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR_39_32 ,Source Address bits 39:32" hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR_47_40 ,Source Address bits 47:40 " group.long 0x28++0x03 line.long 0x00 "P2_SEND_PERCENT,CPSW PORT 2 TRANSMIT QUEUE SEND PERCENTAGES" hexmask.long.byte 0x00 16.--22. 1. " PRI3_SEND_PERCENT ,SPriority 3 Transmit Percentage" hexmask.long.byte 0x00 8.--14. 1. " PRI2_SEND_PERCENT ,SPriority 2 Transmit Percentage" hexmask.long.byte 0x00 0.--6. 1. " PRI1_SEND_PERCENT ,SPriority 1 Transmit Percentage" group.long 0x30++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP0,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0 " bitfld.long 0x00 28.--30. " PRI7 ,Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI6 ,Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI5 ,Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI4 ,Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI3 ,Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI2 ,Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI1 ,Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI0 ,Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x34++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP1,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1" bitfld.long 0x00 28.--30. " PRI15 ,Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI14 ,Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI13 ,Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI12 ,Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI11 ,Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI10 ,Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI9 ,Priority 9 - A packet TOS of 0d9 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI8 ,Priority 8 - A packet TOS of 0d8 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x38++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP2,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2" bitfld.long 0x00 28.--30. " PRI23 ,Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI22 ,Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI21 ,Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI20 ,Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI19 ,Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI18 ,Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI17 ,Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI16 ,Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x3C++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP3,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3" bitfld.long 0x00 28.--30. " PRI31 ,Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI30 ,Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI29 ,Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI28 ,Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI27 ,Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI26 ,Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI25 ,Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI24 ,Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x40++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP4,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4" bitfld.long 0x00 28.--30. " PRI39 ,Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI38 ,Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI37 ,Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI36 ,Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI35 ,Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI34 ,Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI33 ,Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI32 ,Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x44++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP5,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5" bitfld.long 0x00 28.--30. " PRI47 ,Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI46 ,Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI45 ,Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI44 ,Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI43 ,Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI42 ,Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI41 ,Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI40 ,Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP6,CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6" bitfld.long 0x00 28.--30. " PRI55 ,Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI54 ,Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI53 ,Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI52 ,Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI51 ,Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI50 ,Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI49 ,Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI48 ,Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" group.long 0x4C++0x03 line.long 0x00 "P2_RX_DSCP_PRI_MAP7,CPSW PORT 2 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE" bitfld.long 0x00 28.--30. " PRI63 ,Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " PRI62 ,Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " PRI61 ,Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " PRI60 ,Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--14. " PRI59 ,Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. " PRI58 ,Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PRI57 ,Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PRI56 ,Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority" "0,1,2,3,4,5,6,7" width 0xb tree.end tree.end tree "CPSW SL" tree "CPSW SL 1" base ad:0x4A100D80 width 19. rgroup.long 0x00++0x03 line.long 0x00 "IDVER,ID/VERSION REGISTER" sif (cpuis("DRA62*")||cpuis("AM335*")) hexmask.long.word 0x00 16.--31. 1. " IDENT ,Rx Identification Value" bitfld.long 0x00 11.--15. " Z ,Rx Z value (X.Y.Z)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X ,Rx X value (major)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " Y ,Rx Y value (minor)" else hexmask.long.word 0x00 20.--31. 1. " SCHEME ,Scheme value" bitfld.long 0x00 11.--15. " RTL ,Rx Z value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Rx X value" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR_VER ,Minor version" endif group.long 0x04++0x03 line.long 0x00 "MACCONTROL,CPGMAC_SL MAC CONTROL REGISTER" bitfld.long 0x00 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable" "Disabled,Enabled" bitfld.long 0x00 23. " RX_CSF_EN ,RX Copy Short Frames Enable" "Disabled,Enabled" bitfld.long 0x00 22. " RX_CEF_EN ,RX Copy Error Frames Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " TX_SHORT_GAP_LIM_EN ,Transmit Short Gap Limit Enable" "Disabled,Enabled" bitfld.long 0x00 18. " EXT_EN ,Control Enable" "Disabled,Enabled" bitfld.long 0x00 17. " GIG_FORCE ,Gigabit Mode Force" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " IFCTL_B ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps" bitfld.long 0x00 15. " IFCTL_A ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps" bitfld.long 0x00 11. " CMD_IDLE ,Command Idle" "Not idle,Idle" textline " " bitfld.long 0x00 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable" "Disabled IPG,Enabled IPG" bitfld.long 0x00 7. " GIG ,Gigabit Mode" "Disabled,Enabled" bitfld.long 0x00 6. " TX_PACE ,Transmit Pacing Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " GMII_EN ,GMII Enable" "Disabled,Enabled" bitfld.long 0x00 4. " TX_FLOW_EN ,Transmit Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 3. " RX_FLOW_EN ,Receive Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " MTEST ,Manufacturing Test mode" "Disabled,Enabled" bitfld.long 0x00 1. " LOOPBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 0. " FULLDUPLEX ,Full Duplex mode" "Half duplex,Full duplex" rgroup.long 0x08++0x03 line.long 0x00 "MACSTATUS,CPGMAC_SL MAC STATUS REGISTER" bitfld.long 0x00 31. " IDLE ,CPGMAC_SL IDLE" "Not idle,Idle" bitfld.long 0x00 4. " EXT_GIG ,External GIG" "Low,High" bitfld.long 0x00 3. " EXT_FULLDUPLEX ,External Fullduplex" "Low,High" textline " " bitfld.long 0x00 1. " RX_FLOW_ACT ,Receive Flow Control Active" "Disabled,Enabled" bitfld.long 0x00 0. " TX_FLOW_ACT ,Transmit Flow Control Active" "Disabled,Enabled" group.long 0x0c++0x0b line.long 0x00 "SOFT_RESET,Software reset" bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No effect,Reset" line.long 0x04 "RX_MAXLEN,RX_MAXLEN Register" hexmask.long.word 0x04 0.--13. 1. " RX_MAXLEN ,RX Maximum Frame Length" line.long 0x08 "BOFFTEST,CPGMAC_SL BACKOFF TEST REGISTER" bitfld.long 0x08 26.--30. " PACEVAL ,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x08 16.--25. 1. " RNDNUM ,Backoff Random Number Generator" bitfld.long 0x08 12.--15. " COLL_COUNT ,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")) hexmask.long.word 0x08 0.--9. 1. " TX_BACKOFF ,Backoff Count" else hexmask.long.word 0x08 0.--10. 1. " TX_BACKOFF ,Backoff Count" endif rgroup.long 0x18++0x07 line.long 0x00 "RX_PAUSE,CPGMAC_SL RECEIVE PAUSE TIMER REGISTER" hexmask.long.word 0x00 16.--31. 1. " RX_PAUSETIMER ,RX Pause Timer Value" line.long 0x04 "TX_PAUSE,CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER" hexmask.long.word 0x04 16.--31. 1. " TX_PAUSETIMER ,TX Pause Timer Value" group.long 0x20++0x0b line.long 0x00 "EMCONTROL,CPGMAC_SL EMULATION CONTROL REGISTER" bitfld.long 0x00 1. " SOFT ,Emulation Soft Bit" "Disabled,Enabled" bitfld.long 0x00 0. " FREE ,Emulation Free Bit" "Disabled,Enabled" line.long 0x04 "RX_PRI_MAP,CPGMAC_SL RX PKT PRIORITY TO HEADER PRIORITY MAPPING REGISTER" bitfld.long 0x04 28.--30. " PRI7 ,Priority 7 - A packet pri of 0x7 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. " PRI6 ,Priority 6 - A packet pri of 0x6 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. " PRI5 ,Priority 5 - A packet pri of 0x5 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 16.--18. " PRI4 ,Priority 4 - A packet pri of 0x4 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12.--14. " PRI3 ,Priority 3 - A packet pri of 0x3 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " PRI2 ,Priority 2 - A packet pri of 0x2 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 4.--6. " PRI1 ,Priority 1 - A packet pri of 0x1 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " PRI0 ,Priority 0 - A packet pri of 0x0 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" line.long 0x08 "TX_GAP,TRANSMIT INTER-PACKET GAP REGISTER" hexmask.long.word 0x08 0.--8. 1. " TX_GAP ,Transmit Inter-Packet Gap" width 0xb tree.end tree "CPSW SL 2" base ad:0x4A100DC0 width 19. rgroup.long 0x00++0x03 line.long 0x00 "IDVER,ID/VERSION REGISTER" sif (cpuis("DRA62*")||cpuis("AM335*")) hexmask.long.word 0x00 16.--31. 1. " IDENT ,Rx Identification Value" bitfld.long 0x00 11.--15. " Z ,Rx Z value (X.Y.Z)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X ,Rx X value (major)" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " Y ,Rx Y value (minor)" else hexmask.long.word 0x00 20.--31. 1. " SCHEME ,Scheme value" bitfld.long 0x00 11.--15. " RTL ,Rx Z value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Rx X value" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR_VER ,Minor version" endif group.long 0x04++0x03 line.long 0x00 "MACCONTROL,CPGMAC_SL MAC CONTROL REGISTER" bitfld.long 0x00 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable" "Disabled,Enabled" bitfld.long 0x00 23. " RX_CSF_EN ,RX Copy Short Frames Enable" "Disabled,Enabled" bitfld.long 0x00 22. " RX_CEF_EN ,RX Copy Error Frames Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " TX_SHORT_GAP_LIM_EN ,Transmit Short Gap Limit Enable" "Disabled,Enabled" bitfld.long 0x00 18. " EXT_EN ,Control Enable" "Disabled,Enabled" bitfld.long 0x00 17. " GIG_FORCE ,Gigabit Mode Force" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " IFCTL_B ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps" bitfld.long 0x00 15. " IFCTL_A ,Connects to the speed_in input of the respective RMII gasket" "10Mbps,100Mbps" bitfld.long 0x00 11. " CMD_IDLE ,Command Idle" "Not idle,Idle" textline " " bitfld.long 0x00 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable" "Disabled IPG,Enabled IPG" bitfld.long 0x00 7. " GIG ,Gigabit Mode" "Disabled,Enabled" bitfld.long 0x00 6. " TX_PACE ,Transmit Pacing Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " GMII_EN ,GMII Enable" "Disabled,Enabled" bitfld.long 0x00 4. " TX_FLOW_EN ,Transmit Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 3. " RX_FLOW_EN ,Receive Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " MTEST ,Manufacturing Test mode" "Disabled,Enabled" bitfld.long 0x00 1. " LOOPBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 0. " FULLDUPLEX ,Full Duplex mode" "Half duplex,Full duplex" rgroup.long 0x08++0x03 line.long 0x00 "MACSTATUS,CPGMAC_SL MAC STATUS REGISTER" bitfld.long 0x00 31. " IDLE ,CPGMAC_SL IDLE" "Not idle,Idle" bitfld.long 0x00 4. " EXT_GIG ,External GIG" "Low,High" bitfld.long 0x00 3. " EXT_FULLDUPLEX ,External Fullduplex" "Low,High" textline " " bitfld.long 0x00 1. " RX_FLOW_ACT ,Receive Flow Control Active" "Disabled,Enabled" bitfld.long 0x00 0. " TX_FLOW_ACT ,Transmit Flow Control Active" "Disabled,Enabled" group.long 0x0c++0x0b line.long 0x00 "SOFT_RESET,Software reset" bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No effect,Reset" line.long 0x04 "RX_MAXLEN,RX_MAXLEN Register" hexmask.long.word 0x04 0.--13. 1. " RX_MAXLEN ,RX Maximum Frame Length" line.long 0x08 "BOFFTEST,CPGMAC_SL BACKOFF TEST REGISTER" bitfld.long 0x08 26.--30. " PACEVAL ,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x08 16.--25. 1. " RNDNUM ,Backoff Random Number Generator" bitfld.long 0x08 12.--15. " COLL_COUNT ,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")) hexmask.long.word 0x08 0.--9. 1. " TX_BACKOFF ,Backoff Count" else hexmask.long.word 0x08 0.--10. 1. " TX_BACKOFF ,Backoff Count" endif rgroup.long 0x18++0x07 line.long 0x00 "RX_PAUSE,CPGMAC_SL RECEIVE PAUSE TIMER REGISTER" hexmask.long.word 0x00 16.--31. 1. " RX_PAUSETIMER ,RX Pause Timer Value" line.long 0x04 "TX_PAUSE,CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER" hexmask.long.word 0x04 16.--31. 1. " TX_PAUSETIMER ,TX Pause Timer Value" group.long 0x20++0x0b line.long 0x00 "EMCONTROL,CPGMAC_SL EMULATION CONTROL REGISTER" bitfld.long 0x00 1. " SOFT ,Emulation Soft Bit" "Disabled,Enabled" bitfld.long 0x00 0. " FREE ,Emulation Free Bit" "Disabled,Enabled" line.long 0x04 "RX_PRI_MAP,CPGMAC_SL RX PKT PRIORITY TO HEADER PRIORITY MAPPING REGISTER" bitfld.long 0x04 28.--30. " PRI7 ,Priority 7 - A packet pri of 0x7 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 24.--26. " PRI6 ,Priority 6 - A packet pri of 0x6 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 20.--22. " PRI5 ,Priority 5 - A packet pri of 0x5 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 16.--18. " PRI4 ,Priority 4 - A packet pri of 0x4 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 12.--14. " PRI3 ,Priority 3 - A packet pri of 0x3 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 8.--10. " PRI2 ,Priority 2 - A packet pri of 0x2 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 4.--6. " PRI1 ,Priority 1 - A packet pri of 0x1 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0.--2. " PRI0 ,Priority 0 - A packet pri of 0x0 is mapped to this header packet pri" "0,1,2,3,4,5,6,7" line.long 0x08 "TX_GAP,TRANSMIT INTER-PACKET GAP REGISTER" hexmask.long.word 0x08 0.--8. 1. " TX_GAP ,Transmit Inter-Packet Gap" width 0xb tree.end tree.end tree "CPSW SS" base ad:0x4A100000 width 19. rgroup.long 0x00++0x03 line.long 0x00 "ID_VER,ID Version Register" hexmask.long.word 0x00 16.--31. 1. " CPSW_3G_IDENT ,Rx Identification Value" bitfld.long 0x00 11.--15. " CPSW_3G_RTL_VER ,3G RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " CPSW_3G_MAJ_VER ,3G Major Version Value" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x00 0.--7. 1. " CPSW_3G_MINOR_VER ,3G Minor Version Value" group.long 0x04++0x2f line.long 0x00 "CONTROL,SWITCH CONTROL REGISTER" bitfld.long 0x00 3. " DLR_EN ,DLR enable" "Disabled,Enabled" bitfld.long 0x00 2. " RX_VLAN_ENCAP ,Port 0 VLAN Encapsulation" "Disabled,Enabled" bitfld.long 0x00 1. " VLAN_AWARE ,VLAN Aware Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FIFO_LOOPBACK ,FIFO Loopback Mode" "Disabled,Enabled" line.long 0x04 "SOFT_RESET, Soft Reset Register" bitfld.long 0x04 0. " SOFT_RESET ,Software reset" "No reset,Reset" line.long 0x08 "STAT_PORT_EN,Statistics port enable register" bitfld.long 0x08 2. " P2_STAT_EN ,Port 2 (GMII2 and Port 2 FIFO) Statistics Enable" "Disabled,Enabled" bitfld.long 0x08 1. " P1_STAT_EN ,Port 1 (GMII1 and Port 1 FIFO) Statistics Enable" "Disabled,Enabled" bitfld.long 0x08 0. " P0_STAT_EN ,Port 0 Statistics Enable" "Disabled,Enabled" line.long 0x0c "PTYPE,Transmit priority type register" bitfld.long 0x0C 21. " P2_PRI3_SHAPE_EN ,Port 2 Queue Priority 3 Transmit Shape Enable" "Disabled,Enabled" bitfld.long 0x0C 20. " P2_PRI2_SHAPE_EN ,Port 2 Queue Priority 2 Transmit Shape Enable" "Disabled,Enabled" bitfld.long 0x0C 19. " P2_PRI1_SHAPE_EN ,Port 2 Queue Priority 1 Transmit Shape Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 18. " P1_PRI3_SHAPE_EN ,Port 1 Queue Priority 3 Transmit Shape Enable" "Disabled,Enabled" bitfld.long 0x0C 17. " P1_PRI2_SHAPE_EN ,Port 1 Queue Priority 2 Transmit Shape Enable" "Disabled,Enabled" bitfld.long 0x0C 16. " P1_PRI1_SHAPE_EN ,Port 1 Queue Priority 1 Transmit Shape Enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 10. " P2_PTYPE_ESC ,Port 2 Priority Type Escalate" "Fixed,Escalate" bitfld.long 0x0C 9. " P1_PTYPE_ESC ,Port 1 Priority Type Escalate" "Fixed,Escalate" bitfld.long 0x0C 8. " P0_PTYPE_ESC ,Port 0 Priority Type Escalate" "Fixed,Escalate" textline " " bitfld.long 0x0C 0.--4. " ESC_PRI_LD_VAL ,Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "SOFT_IDLE,Software idle" bitfld.long 0x10 0. " SOFT_IDLE ,Software Idle" "Not idle,Idle" line.long 0x14 "THRU_RATE,Throughput rate" bitfld.long 0x14 12.--15. " SL_RX_THRU_RATE ,CPGMAC_SL Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--3. " CPDMA_THRU_RATE ,CPDMA Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "GAP_THRESH,Short Gap Threshold" bitfld.long 0x18 0.--4. " GAP_THRESH ,CPGMAC_SL Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x1c "TX_START_WDS,Transmit start words" hexmask.long.word 0x1c 0.--10. 1. " TX_START_WDS ,FIFO Packet Transmit (egress) Start Words" line.long 0x20 "FLOW_CONTROL,Flow control Register" bitfld.long 0x20 2. " P2_FLOW_EN ,Port 2 Receive flow control enable" "Disabled,Enabled" bitfld.long 0x20 1. " P1_FLOW_EN ,Port 1 Receive flow control enable" "Disabled,Enabled" bitfld.long 0x20 0. " P0_FLOW_EN ,Port 0 Receive flow control enable" "Disabled,Enabled" line.long 0x24 "VLAN_LTYPE,LTYPE1 and LTYPE 2 register" hexmask.long.word 0x24 16.--31. 1. " VLAN_LTYPE2 ,Time Sync VLAN LTYPE2" hexmask.long.word 0x24 0.--15. 1. " VLAN_LTYPE1 ,Time Sync VLAN LTYPE1" line.long 0x28 "TS_LTYPE,VLAN_LTYPE1 and VLAN_LTYPE2 register" hexmask.long.byte 0x28 16.--21. 1. " TS_LTYPE2 ,Time Sync LTYPE2 This is an Ethertype value" hexmask.long.word 0x28 0.--15. 1. " TS_LTYPE1 ,Time Sync LTYPE1 This is an Ethertype value" line.long 0x2C "DLR_LTYPE,DLR LTYPE register" hexmask.long.word 0x2C 0.--15. 1. " DLR_LTYPE2 ,Time Sync LTYPE1 This is an ethertype value" width 0xb tree.end tree "CPSW WR" base ad:0x4A101200 width 19. tree "Others" rgroup.long 0x00++0x03 line.long 0x00 "IDVER,SUBSYSTEM ID VERSION REGISTER" hexmask.long.word 0x00 30.--31. 1. " SCHEME ,Scheme value" hexmask.long.word 0x00 16.--27. 1. " FUNCTION ,Function value" bitfld.long 0x00 11.--15. " RTL ,Rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " MAJOR ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor version" group.long 0x04++0x03 line.long 0x00 "SOFT_RESET,SUBSYSTEM SOFT RESET REGISTER" bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "Not occured,Occurred" group.long 0x08++0x03 line.long 0x00 "CONTROL,SUBSYSTEM CONTROL REGISTER" bitfld.long 0x00 2.--3. " MMR_STDBYMODE ,Standbymode MMR bits" "0,1,2,3" bitfld.long 0x00 0.--1. " MMR_IDLEMODE ,Idlemode MMR bits" "0,1,2,3" group.long 0x0C++0x03 line.long 0x00 "INT_CONTROL,SUBSYSTEM INTERRUPT CONTROL" bitfld.long 0x00 31. " INT_TEST ,Interrupt Test" "Disabled,Enabled" bitfld.long 0x00 21. " INT_PACE_EN[5] ,Enables C0_Rx_Pulse" "Disabled,Enabled" bitfld.long 0x00 20. " INT_PACE_EN[4] ,Enables C0_Tx_Pulse" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " INT_PACE_EN[3] ,Enables C1_Rx_Pulse" "Disabled,Enabled" bitfld.long 0x00 18. " INT_PACE_EN[2] ,Enables C1_Tx_Pulse" "Disabled,Enabled" bitfld.long 0x00 17. " INT_PACE_EN[1] ,Enables C2_Rx_Pulse" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " INT_PACE_EN[0] ,Enables C2_Tx_Pulse" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " INT_PRESCALE ,Interrupt Counter Prescaler" rgroup.long 0x88++0x03 line.long 0x00 "RGMII_CTL,RGMII CONTROL SIGNAL REGISTER" bitfld.long 0x00 7. " RGMII2_FULLDUPLEX ,RGMII 2 Fullduplex" "Half-duplex,Full-duplex" bitfld.long 0x00 5.--6. " RGMII2_SPEED ,CPRGMI speed output signal" "10Mbps,100Mbps,1000Mbps,?..." bitfld.long 0x00 4. " RGMII2_LINK ,CPRGMII link" "Down,Up" textline " " bitfld.long 0x00 3. " RGMII1_FULLDUPLEX ,CPRGMII fullduplex output signal" "Half-duplex,Fullduplex" bitfld.long 0x00 1.--2. " RGMII1_SPEED ,CRGMII1 Speed" "10Mbps,100Mbps,1000Mbps,?..." bitfld.long 0x00 0. " RGMII1_LINK ,RGMII1 Link Indicator - This is the CPRGMII link output signal 0 - RGMII1 link is down " "Down,Up" tree.end base ad:0x4A101210 width 20. tree "Channel 0" group.long 0x00++0x03 line.long 0x00 "C0_RX_THRESH_EN,SUBSYSTEM CORE 0RECEIVE THRESHOLD INT ENABLE REGISTER" bitfld.long 0x00 7. " C0_RX_THRESH_EN[7] ,Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C0_RX_THRESH_EN[6] ,Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C0_RX_THRESH_EN[5] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " C0_RX_THRESH_EN[4] ,Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C0_RX_THRESH_EN[3] ,Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C0_RX_THRESH_EN[2] ,Core 0 Receive Threshold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C0_RX_THRESH_EN[1] ,Core 0 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C0_RX_THRESH_EN[0] ,Core 0 Receive Threshold Enable" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "C0_RX_EN,SUBSYSTEM CORE 0RECEIVE INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C0_RX_EN[7] ,Core 0Receive Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C0_RX_EN[6] ,Core 0Receive Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C0_RX_EN[5] ,Core 0Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " C0_RX_EN[4] ,Core 0Receive Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C0_RX_EN[3] ,Core 0Receive Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C0_RX_EN[2] ,Core 0Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C0_RX_EN[1] ,Core 0Receive Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C0_RX_EN[0] ,Core 0Receive Enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "C0_TX_EN,SUBSYSTEM CORE 0TRANSMIT INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C0_TX_EN[7] ,Core 0Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C0_TX_EN[6] ,Core 0Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C0_TX_EN[5] ,Core 0Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " C0_TX_EN[4] ,Core 0Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C0_TX_EN[3] ,Core 0Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C0_TX_EN[2] ,Core 0Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C0_TX_EN[1] ,Core 0Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C0_TX_EN[0] ,Core 0Transmit Enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "C0_MISC_EN,SUBSYSTEM Core 0MISC INTERRUPT ENABLE REGISTER" bitfld.long 0x00 4. " C0_MISC_EN[4] ,Core 0Misc Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C0_MISC_EN[3] ,Core 0Misc Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C0_MISC_EN[2] ,Core 0Misc Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C0_MISC_EN[1] ,Core 0Misc Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C0_MISC_EN[0] ,Core 0Misc Enable" "Disabled,Enaabled" rgroup.long 0x30++0x03 line.long 0x00 "C0_RX_THRESH_STAT,SUBSYSTEM CORE 0RX THRESHOLD MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C0_RX_THRESH_STAT[7] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C0_RX_THRESH_STAT[6] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C0_RX_THRESH_STAT[5] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C0_RX_THRESH_STAT[4] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C0_RX_THRESH_STAT[3] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C0_RX_THRESH_STAT[2] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C0_RX_THRESH_STAT[1] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C0_RX_THRESH_STAT[0] ,Core 0Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x34++0x03 line.long 0x00 "C0_RX_STAT,SUBSYSTEM CORE 0RX INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C0_RX_STAT[7] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C0_RX_STAT[6] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C0_RX_STAT[5] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C0_RX_STAT[4] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C0_RX_STAT[3] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C0_RX_STAT[2] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C0_RX_STAT[1] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C0_RX_STAT[0] ,Core 0Receive Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x38++0x03 line.long 0x00 "C0_TX_STAT,SUBSYSTEM CORE 0TX INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C0_TX_STAT[7] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C0_TX_STAT[6] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C0_TX_STAT[5] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C0_TX_STAT[4] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C0_TX_STAT[3] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C0_TX_STAT[2] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C0_TX_STAT[1] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C0_TX_STAT[0] ,Core 0Transmit Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x3C++0x03 line.long 0x00 "C0_MISC_STAT,SUBSYSTEM CORE 0MISC INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 4. " C0_MISC_STAT[4] ,Core 0Misc Masked Interrupt Status" "Disabled,Enabled" bitfld.long 0x00 3. " C0_MISC_STAT[3] ,Core 0Misc Masked Interrupt Status" "Disabled,Enabled" bitfld.long 0x00 2. " C0_MISC_STAT[2] ,Core 0Misc Masked Interrupt Status" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C0_MISC_STAT[1] ,Core 0Misc Masked Interrupt Status" "Disabled,Enabled" bitfld.long 0x00 0. " C0_MISC_STAT[0] ,Core 0Misc Masked Interrupt Status" "Disabled,Enaabled" group.long 0x60++0x03 line.long 0x00 "C0_RX_IMAX,SUBSYSTEM CORE 0RECEIVE INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C0_RX_IMAX ,Core 0Receive Interrupts per Millisecond" group.long 0x64++0x03 line.long 0x00 "C0_TX_IMAX,SUBSYSTEM CORE 0TRANSMIT INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C0_TX_IMAX ,Core 0Transmit Interrupts per Millisecond" tree.end base ad:0x4A101220 width 20. tree "Channel 1" group.long 0x00++0x03 line.long 0x00 "C1_RX_THRESH_EN,SUBSYSTEM CORE 1RECEIVE THRESHOLD INT ENABLE REGISTER" bitfld.long 0x00 7. " C1_RX_THRESH_EN[7] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C1_RX_THRESH_EN[6] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C1_RX_THRESH_EN[5] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " C1_RX_THRESH_EN[4] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C1_RX_THRESH_EN[3] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C1_RX_THRESH_EN[2] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C1_RX_THRESH_EN[1] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C1_RX_THRESH_EN[0] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "C1_RX_EN,SUBSYSTEM CORE 1RECEIVE INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C1_RX_EN[7] ,Core 1Receive Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C1_RX_EN[6] ,Core 1Receive Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C1_RX_EN[5] ,Core 1Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " C1_RX_EN[4] ,Core 1Receive Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C1_RX_EN[3] ,Core 1Receive Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C1_RX_EN[2] ,Core 1Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C1_RX_EN[1] ,Core 1Receive Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C1_RX_EN[0] ,Core 1Receive Enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "C1_TX_EN,SUBSYSTEM CORE 1TRANSMIT INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C1_TX_EN[7] ,Core 1Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C1_TX_EN[6] ,Core 1Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C1_TX_EN[5] ,Core 1Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " C1_TX_EN[4] ,Core 1Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C1_TX_EN[3] ,Core 1Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C1_TX_EN[2] ,Core 1Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C1_TX_EN[1] ,Core 1Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C1_TX_EN[0] ,Core 1Transmit Enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "C1_MISC_EN,SUBSYSTEM Core 1MISC INTERRUPT ENABLE REGISTER" bitfld.long 0x00 4. " C1_MISC_EN[4] ,Core 1Misc Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C1_MISC_EN[3] ,Core 1Misc Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C1_MISC_EN[2] ,Core 1Misc Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C1_MISC_EN[1] ,Core 1Misc Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C1_MISC_EN[0] ,Core 1Misc Enable" "Disabled,Enaabled" rgroup.long 0x30++0x03 line.long 0x00 "C1_RX_THRESH_STAT,SUBSYSTEM CORE 1RX THRESHOLD MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C1_RX_THRESH_STAT[7] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C1_RX_THRESH_STAT[6] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C1_RX_THRESH_STAT[5] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C1_RX_THRESH_STAT[4] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C1_RX_THRESH_STAT[3] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C1_RX_THRESH_STAT[2] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C1_RX_THRESH_STAT[1] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C1_RX_THRESH_STAT[0] ,Core 1Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x34++0x03 line.long 0x00 "C1_RX_STAT,SUBSYSTEM CORE 1RX INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C1_RX_STAT[7] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C1_RX_STAT[6] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C1_RX_STAT[5] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C1_RX_STAT[4] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C1_RX_STAT[3] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C1_RX_STAT[2] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C1_RX_STAT[1] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C1_RX_STAT[0] ,Core 1Receive Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x38++0x03 line.long 0x00 "C1_TX_STAT,SUBSYSTEM CORE 1TX INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C1_TX_STAT[7] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C1_TX_STAT[6] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C1_TX_STAT[5] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C1_TX_STAT[4] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C1_TX_STAT[3] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C1_TX_STAT[2] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C1_TX_STAT[1] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C1_TX_STAT[0] ,Core 1Transmit Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x3C++0x03 line.long 0x00 "C1_MISC_STAT,SUBSYSTEM CORE 1MISC INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 4. " C1_MISC_STAT[4] ,Core 1Misc Masked Interrupt Status" "Disabled,Enabled" bitfld.long 0x00 3. " C1_MISC_STAT[3] ,Core 1Misc Masked Interrupt Status" "Disabled,Enabled" bitfld.long 0x00 2. " C1_MISC_STAT[2] ,Core 1Misc Masked Interrupt Status" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C1_MISC_STAT[1] ,Core 1Misc Masked Interrupt Status" "Disabled,Enabled" bitfld.long 0x00 0. " C1_MISC_STAT[0] ,Core 1Misc Masked Interrupt Status" "Disabled,Enaabled" group.long 0x60++0x03 line.long 0x00 "C1_RX_IMAX,SUBSYSTEM CORE 1RECEIVE INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C1_RX_IMAX ,Core 1Receive Interrupts per Millisecond" group.long 0x64++0x03 line.long 0x00 "C1_TX_IMAX,SUBSYSTEM CORE 1TRANSMIT INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C1_TX_IMAX ,Core 1Transmit Interrupts per Millisecond" tree.end base ad:0x4A101230 width 20. tree "Channel 2" group.long 0x00++0x03 line.long 0x00 "C2_RX_THRESH_EN,SUBSYSTEM CORE 2RECEIVE THRESHOLD INT ENABLE REGISTER" bitfld.long 0x00 7. " C2_RX_THRESH_EN[7] ,Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C2_RX_THRESH_EN[6] ,Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C2_RX_THRESH_EN[5] ,Core 1 Receive Threshold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " C2_RX_THRESH_EN[4] ,Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C2_RX_THRESH_EN[3] ,Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C2_RX_THRESH_EN[2] ,Core 2 Receive Threshold Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C2_RX_THRESH_EN[1] ,Core 2 Receive Threshold Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C2_RX_THRESH_EN[0] ,Core 2 Receive Threshold Enable" "Disabled,Enabled" group.long 0x04++0x03 line.long 0x00 "C2_RX_EN,SUBSYSTEM CORE 2RECEIVE INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C2_RX_EN[7] ,Core 2Receive Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C2_RX_EN[6] ,Core 2Receive Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C2_RX_EN[5] ,Core 2Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " C2_RX_EN[4] ,Core 2Receive Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C2_RX_EN[3] ,Core 2Receive Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C2_RX_EN[2] ,Core 2Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C2_RX_EN[1] ,Core 2Receive Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C2_RX_EN[0] ,Core 2Receive Enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "C2_TX_EN,SUBSYSTEM CORE 2TRANSMIT INTERRUPT ENABLE REGISTER" bitfld.long 0x00 7. " C2_TX_EN[7] ,Core 2Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 6. " C2_TX_EN[6] ,Core 2Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 5. " C2_TX_EN[5] ,Core 2Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " C2_TX_EN[4] ,Core 2Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C2_TX_EN[3] ,Core 2Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C2_TX_EN[2] ,Core 2Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C2_TX_EN[1] ,Core 2Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C2_TX_EN[0] ,Core 2Transmit Enable" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "C2_MISC_EN,SUBSYSTEM Core 2MISC INTERRUPT ENABLE REGISTER" bitfld.long 0x00 4. " C2_MISC_EN[4] ,Core 2Misc Enable" "Disabled,Enabled" bitfld.long 0x00 3. " C2_MISC_EN[3] ,Core 2Misc Enable" "Disabled,Enabled" bitfld.long 0x00 2. " C2_MISC_EN[2] ,Core 2Misc Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C2_MISC_EN[1] ,Core 2Misc Enable" "Disabled,Enabled" bitfld.long 0x00 0. " C2_MISC_EN[0] ,Core 2Misc Enable" "Disabled,Enaabled" rgroup.long 0x30++0x03 line.long 0x00 "C2_RX_THRESH_STAT,SUBSYSTEM CORE 2RX THRESHOLD MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C2_RX_THRESH_STAT[7] ,Core 2Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C2_RX_THRESH_STAT[6] ,Core 2Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C2_RX_THRESH_STAT[5] ,Core 2Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C2_RX_THRESH_STAT[4] ,Core 2Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C2_RX_THRESH_STAT[3] ,Core 2Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C2_RX_THRESH_STAT[2] ,Core 2Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C2_RX_THRESH_STAT[1] ,Core 2Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C2_RX_THRESH_STAT[0] ,Core 2Receive Threshold Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x34++0x03 line.long 0x00 "C2_RX_STAT,SUBSYSTEM CORE 2RX INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C2_RX_STAT[7] ,Core 2Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C2_RX_STAT[6] ,Core 2Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C2_RX_STAT[5] ,Core 2Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C2_RX_STAT[4] ,Core 2Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C2_RX_STAT[3] ,Core 2Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C2_RX_STAT[2] ,Core 2Receive Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C2_RX_STAT[1] ,Core 2Receive Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C2_RX_STAT[0] ,Core 2Receive Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x38++0x03 line.long 0x00 "C2_TX_STAT,SUBSYSTEM CORE 2TX INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 7. " C2_TX_STAT[7] ,Core 2Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " C2_TX_STAT[6] ,Core 2Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 5. " C2_TX_STAT[5] ,Core 2Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " C2_TX_STAT[4] ,Core 2Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " C2_TX_STAT[3] ,Core 2Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 2. " C2_TX_STAT[2] ,Core 2Transmit Masked Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " C2_TX_STAT[1] ,Core 2Transmit Masked Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 0. " C2_TX_STAT[0] ,Core 2Transmit Masked Interrupt Status" "No interrupt,Interrupt" rgroup.long 0x3C++0x03 line.long 0x00 "C2_MISC_STAT,SUBSYSTEM CORE 2MISC INTERRUPT MASKED INT STATUS REGISTER" bitfld.long 0x00 4. " C2_MISC_STAT[4] ,Core 2Misc Masked Interrupt Status" "Disabled,Enabled" bitfld.long 0x00 3. " C2_MISC_STAT[3] ,Core 2Misc Masked Interrupt Status" "Disabled,Enabled" bitfld.long 0x00 2. " C2_MISC_STAT[2] ,Core 2Misc Masked Interrupt Status" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " C2_MISC_STAT[1] ,Core 2Misc Masked Interrupt Status" "Disabled,Enabled" bitfld.long 0x00 0. " C2_MISC_STAT[0] ,Core 2Misc Masked Interrupt Status" "Disabled,Enaabled" group.long 0x60++0x03 line.long 0x00 "C2_RX_IMAX,SUBSYSTEM CORE 2RECEIVE INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C2_RX_IMAX ,Core 2Receive Interrupts per Millisecond" group.long 0x64++0x03 line.long 0x00 "C2_TX_IMAX,SUBSYSTEM CORE 2TRANSMIT INTERRUPTS PER MILLISECOND" hexmask.long.byte 0x00 0.--5. 1. " C2_TX_IMAX ,Core 2Transmit Interrupts per Millisecond" tree.end tree.end tree "MDIO" base ad:0x4A101000 width 13. rgroup.long 0x00++0x03 line.long 0x00 "MDIOVER,MDIO Version Register" hexmask.long.word 0x00 16.--31. 1. " MODID ,Identifies type of peripheral" hexmask.long.byte 0x00 8.--15. 1. " REVMAJ ,Management interface module major revision value" hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Management interface module minor revision value" group.long 0x04++0x07 line.long 0x00 "MDIOCONTROL,MDIO Control Register" rbitfld.long 0x00 31. " IDLE ,MDIO state machine IDLE" "Not idle,Idle" bitfld.long 0x00 30. " ENABLE ,Enable control" "Disabled,Enabled" textline " " rbitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL ,Enable control" "0,1,?..." textline " " bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "No,Yes" eventfld.long 0x00 19. " FAULT ,Fault indicator" "No fault,Fault" bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " INTTESTENB ,Interupt test enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider" line.long 0x04 "MDIOALIVE,PHY Acknowledge Status Register" eventfld.long 0x04 31. " ALIVE[31] ,MDIO alive bit 31" "Not ACK,ACK" eventfld.long 0x04 30. " ALIVE[30] ,MDIO alive bit 30" "Not ACK,ACK" eventfld.long 0x04 29. " ALIVE[29] ,MDIO alive bit 29" "Not ACK,ACK" textline " " eventfld.long 0x04 28. " ALIVE[28] ,MDIO alive bit 28" "Not ACK,ACK" eventfld.long 0x04 27. " ALIVE[27] ,MDIO alive bit 27" "Not ACK,ACK" eventfld.long 0x04 26. " ALIVE[26] ,MDIO alive bit 26" "Not ACK,ACK" textline " " eventfld.long 0x04 25. " ALIVE[25] ,MDIO alive bit 25" "Not ACK,ACK" eventfld.long 0x04 24. " ALIVE[24] ,MDIO alive bit 24" "Not ACK,ACK" eventfld.long 0x04 23. " ALIVE[23] ,MDIO alive bit 23" "Not ACK,ACK" textline " " eventfld.long 0x04 22. " ALIVE[22] ,MDIO alive bit 22" "Not ACK,ACK" eventfld.long 0x04 21. " ALIVE[21] ,MDIO alive bit 21" "Not ACK,ACK" eventfld.long 0x04 20. " ALIVE[20] ,MDIO alive bit 20" "Not ACK,ACK" textline " " eventfld.long 0x04 19. " ALIVE[19] ,MDIO alive bit 19" "Not ACK,ACK" eventfld.long 0x04 18. " ALIVE[18] ,MDIO alive bit 18" "Not ACK,ACK" eventfld.long 0x04 17. " ALIVE[17] ,MDIO alive bit 17" "Not ACK,ACK" textline " " eventfld.long 0x04 16. " ALIVE[16] ,MDIO alive bit 16" "Not ACK,ACK" eventfld.long 0x04 15. " ALIVE[15] ,MDIO alive bit 15" "Not ACK,ACK" eventfld.long 0x04 14. " ALIVE[14] ,MDIO alive bit 14" "Not ACK,ACK" textline " " eventfld.long 0x04 13. " ALIVE[13] ,MDIO alive bit 13" "Not ACK,ACK" eventfld.long 0x04 12. " ALIVE[12] ,MDIO alive bit 12" "Not ACK,ACK" eventfld.long 0x04 11. " ALIVE[11] ,MDIO alive bit 11" "Not ACK,ACK" textline " " eventfld.long 0x04 10. " ALIVE[10] ,MDIO alive bit 10" "Not ACK,ACK" eventfld.long 0x04 9. " ALIVE[9] ,MDIO alive bit 9" "Not ACK,ACK" eventfld.long 0x04 8. " ALIVE[8] ,MDIO alive bit 8" "Not ACK,ACK" textline " " eventfld.long 0x04 7. " ALIVE[7] ,MDIO alive bit 7" "Not ACK,ACK" eventfld.long 0x04 6. " ALIVE[6] ,MDIO alive bit 6" "Not ACK,ACK" eventfld.long 0x04 5. " ALIVE[5] ,MDIO alive bit 5" "Not ACK,ACK" textline " " eventfld.long 0x04 4. " ALIVE[4] ,MDIO alive bit 4" "Not ACK,ACK" eventfld.long 0x04 3. " ALIVE[3] ,MDIO alive bit 3" "Not ACK,ACK" eventfld.long 0x04 2. " ALIVE[2] ,MDIO alive bit 2" "Not ACK,ACK" textline " " eventfld.long 0x04 1. " ALIVE[1] ,MDIO alive bit 1" "Not ACK,ACK" eventfld.long 0x04 0. " ALIVE[0] ,MDIO alive bit 0" "Not ACK,ACK" rgroup.long 0x0c++0x03 line.long 0x00 "MDIOLINK,PHY Link Status Register" bitfld.long 0x00 31. " LINK[31] ,MDIO link state bit 31" "Not linked,Linked" bitfld.long 0x00 30. " LINK[30] ,MDIO link state bit 30" "Not linked,Linked" bitfld.long 0x00 29. " LINK[29] ,MDIO link state bit 29" "Not linked,Linked" textline " " bitfld.long 0x00 28. " LINK[28] ,MDIO link state bit 28" "Not linked,Linked" bitfld.long 0x00 27. " LINK[27] ,MDIO link state bit 27" "Not linked,Linked" bitfld.long 0x00 26. " LINK[26] ,MDIO link state bit 26" "Not linked,Linked" textline " " bitfld.long 0x00 25. " LINK[25] ,MDIO link state bit 25" "Not linked,Linked" bitfld.long 0x00 24. " LINK[24] ,MDIO link state bit 24" "Not linked,Linked" bitfld.long 0x00 23. " LINK[23] ,MDIO link state bit 23" "Not linked,Linked" textline " " bitfld.long 0x00 22. " LINK[22] ,MDIO link state bit 22" "Not linked,Linked" bitfld.long 0x00 21. " LINK[21] ,MDIO link state bit 21" "Not linked,Linked" bitfld.long 0x00 20. " LINK[20] ,MDIO link state bit 20" "Not linked,Linked" textline " " bitfld.long 0x00 19. " LINK[19] ,MDIO link state bit 19" "Not linked,Linked" bitfld.long 0x00 18. " LINK[18] ,MDIO link state bit 18" "Not linked,Linked" bitfld.long 0x00 17. " LINK[17] ,MDIO link state bit 17" "Not linked,Linked" textline " " bitfld.long 0x00 16. " LINK[16] ,MDIO link state bit 16" "Not linked,Linked" bitfld.long 0x00 15. " LINK[15] ,MDIO link state bit 15" "Not linked,Linked" bitfld.long 0x00 14. " LINK[14] ,MDIO link state bit 14" "Not linked,Linked" textline " " bitfld.long 0x00 13. " LINK[13] ,MDIO link state bit 13" "Not linked,Linked" bitfld.long 0x00 12. " LINK[12] ,MDIO link state bit 12" "Not linked,Linked" bitfld.long 0x00 11. " LINK[11] ,MDIO link state bit 11" "Not linked,Linked" textline " " bitfld.long 0x00 10. " LINK[10] ,MDIO link state bit 10" "Not linked,Linked" bitfld.long 0x00 9. " LINK[9] ,MDIO link state bit 9" "Not linked,Linked" bitfld.long 0x00 8. " LINK[8] ,MDIO link state bit 8" "Not linked,Linked" textline " " bitfld.long 0x00 7. " LINK[7] ,MDIO link state bit 7" "Not linked,Linked" bitfld.long 0x00 6. " LINK[6] ,MDIO link state bit 6" "Not linked,Linked" bitfld.long 0x00 5. " LINK[5] ,MDIO link state bit 5" "Not linked,Linked" textline " " bitfld.long 0x00 4. " LINK[4] ,MDIO link state bit 4" "Not linked,Linked" bitfld.long 0x00 3. " LINK[3] ,MDIO link state bit 3" "Not linked,Linked" bitfld.long 0x00 2. " LINK[2] ,MDIO link state bit 2" "Not linked,Linked" textline " " bitfld.long 0x00 1. " LINK[1] ,MDIO link state bit 1" "Not linked,Linked" bitfld.long 0x00 0. " LINK[0] ,MDIO link state bit 0" "Not linked,Linked" width 20. group.long 0x10++0x17 line.long 0x00 "MDIOLINKINTRAW,MDIO Link Status Change Interrupt Register (Raw Value)" eventfld.long 0x00 1. " LINKINTRAW[1] ,MDIO link change event raw value - MDIOUSERPHYSEL1" "Not changed,Changed" eventfld.long 0x00 0. " LINKINTRAW[0] ,MDIO link change event raw value - MDIOUSERPHYSEL0" "Not changed,Changed" line.long 0x04 "MDIOLINKINTMASKED,MDIO Link Status Change Interrupt Register (Masked Value)" eventfld.long 0x04 1. " LINKINTMASKED[1] ,MDIO link change event raw value - MDIOUSERPHYSEL1 [read/write]" "Not changed/No effect,Changed/Clear" eventfld.long 0x04 0. " LINKINTMASKED[0] ,MDIO link change event raw value - MDIOUSERPHYSEL0 [read/write]" "Not changed/No effect,Changed/Clear" line.long 0x08 "MDIOUSERINTRAW,MDIO User Command Complete Interrupt Register (Raw Value)" eventfld.long 0x08 1. " USERINTRAW[1] ,Raw value of MDIO user command complete event for the MDIOUSERACCESS1" "Not changed,Changed" eventfld.long 0x08 0. " USERINTRAW[0] ,Raw value of MDIO user command complete event for the MDIOUSERACCESS0" "Not changed,Changed" line.long 0x0c "MDIOUSERINTMASKED,MDIO User Command Complete Interrupt Register (Masked Value)" eventfld.long 0x0c 1. " USERINTMASKED[1] ,Masked value of MDIO user command complete event for the MDIOUSERACCESS1 [read/write]" "Not changed/No effect,Changed/Clear" eventfld.long 0x0c 0. " USERINTMASKED[0] ,Masked value of MDIO user command complete event for the MDIOUSERACCESS0 [read/write]" "Not changed/No effect,Changed/Clear" line.long 0x10 "MDIOUSERINTMASKSET,MDIO User Command Complete Interrupt Mask Set Register" eventfld.long 0x10 1. " USERINTMASKSET[1] ,MDIO user interrupt mask set for USERINTMASKED[1]" "Masked,Not masked" eventfld.long 0x10 0. " USERINTMASKSET[0] ,MDIO user interrupt mask set for USERINTMASKED[0]" "Masked,Not masked" line.long 0x14 "MDIOUSERINTMASKSET,MDIO User Command Complete Interrupt Mask Set Register" eventfld.long 0x14 1. " USERINTMASKCLEAR[1] ,MDIO user interrupt mask clear for USERINTMASKED[1]" "No effect,Cleared" eventfld.long 0x14 0. " USERINTMASKCLEAR[0] ,MDIO user interrupt mask clear for USERINTMASKED[0]" "No effect,Cleared" if (((d.l(ad:0x4A101000+0x80))&0x80000000)==0x00000000) group.long 0x80++0x03 line.long 0x00 "MDIOUSERACCESS0,MDIO User Access Register 0" bitfld.long 0x00 31. " GO ,Go - perform an MDIO access" "No effect,Perform access" bitfld.long 0x00 30. " WRITE ,Write enable" "Read access,Write access" bitfld.long 0x00 29. " ACK ,PHY acknowledged the read transaction" "Not ACK,ACK" textline " " bitfld.long 0x00 21.--25. " REGADR ,PHY register address for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PHYADR ,PHY address to be accesses for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " DATA ,User data" else rgroup.long 0x80++0x03 line.long 0x00 "MDIOUSERACCESS0,MDIO User Access Register 0" bitfld.long 0x00 31. " GO ,Go - perform an MDIO access" "No effect,Perform access" bitfld.long 0x00 30. " WRITE ,Write enable" "Read access,Write access" bitfld.long 0x00 29. " ACK ,PHY acknowledged the read transaction" "Not ACK,ACK" textline " " bitfld.long 0x00 21.--25. " REGADR ,PHY register address for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PHYADR ,PHY address to be accesses for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " DATA ,User data" endif group.long (0x80+0x04)++0x03 line.long 0x00 "MDIOUSERPHYSEL0,MDIO User PHY Select Register 0" bitfld.long 0x00 7. " LINKSEL ,Link status determination select" "MDIO state machine,MLINK pin" bitfld.long 0x00 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " PHYADDRMON ,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((d.l(ad:0x4A101000+0x88))&0x80000000)==0x00000000) group.long 0x88++0x03 line.long 0x00 "MDIOUSERACCESS1,MDIO User Access Register 1" bitfld.long 0x00 31. " GO ,Go - perform an MDIO access" "No effect,Perform access" bitfld.long 0x00 30. " WRITE ,Write enable" "Read access,Write access" bitfld.long 0x00 29. " ACK ,PHY acknowledged the read transaction" "Not ACK,ACK" textline " " bitfld.long 0x00 21.--25. " REGADR ,PHY register address for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PHYADR ,PHY address to be accesses for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " DATA ,User data" else rgroup.long 0x88++0x03 line.long 0x00 "MDIOUSERACCESS1,MDIO User Access Register 1" bitfld.long 0x00 31. " GO ,Go - perform an MDIO access" "No effect,Perform access" bitfld.long 0x00 30. " WRITE ,Write enable" "Read access,Write access" bitfld.long 0x00 29. " ACK ,PHY acknowledged the read transaction" "Not ACK,ACK" textline " " bitfld.long 0x00 21.--25. " REGADR ,PHY register address for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PHYADR ,PHY address to be accesses for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " DATA ,User data" endif group.long (0x88+0x04)++0x03 line.long 0x00 "MDIOUSERPHYSEL1,MDIO User PHY Select Register 1" bitfld.long 0x00 7. " LINKSEL ,Link status determination select" "MDIO state machine,MLINK pin" bitfld.long 0x00 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " PHYADDRMON ,PHY address whose link status is to be monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0xb tree.end tree.end tree "PWMS (Pulse-Width Modulation Subsystem)" tree "PWM Subsystem 0" tree "PWMSS Configuration Registers" base ad:0x48300000 width 10. rgroup.long 0x00++0x3 line.long 0x00 "IDVER,IP Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme value" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function" hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL revision" textline " " hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major number" hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Number" group.long 0x04++0x7 line.long 0x00 "SYSCONFIG,System Configuration Register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby,Smart-Standby" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation" "is sensitive,is not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Disabled,Enabled" line.long 0x04 "CLKCONFG,Clock Configuration Register" bitfld.long 0x04 9. " EPWMCLKSTOP_REQ ,This bit controls the clkstop_req input to the ePWM module" "Disabled,Enabled" bitfld.long 0x04 8. " EPWMCLK_EN ,This bit controls the clk_en input to the ePWM module" "Disabled,Enabled" bitfld.long 0x04 5. " EQEPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eQEP module" "Disabled,Enabled" bitfld.long 0x04 4. " EQEPCLK_EN ,This bit controls the clk_en input to the eQEP module" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " ECAPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eCAP module" "Disabled,Enabled" bitfld.long 0x04 0. " ECAPCLK_EN ,This bit controls the clk_en input to the eCAP module" "Disabled,Enabled" rgroup.long 0x0C++0x3 line.long 0x00 "CLKSTATUS,Clock Status Register" bitfld.long 0x00 9. " EPWMCLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM module" "Disabled,Enabled" bitfld.long 0x00 8. " EPWMCLK_EN_ACK ,This bit is the clk_en status output of the ePWM module" "Disabled,Enabled" bitfld.long 0x00 5. " EQEPCLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module" "Disabled,Enabled" bitfld.long 0x00 4. " EQEPCLK_EN_ACK ,This bit is the clk_en status output of the eQEP module" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ECAPCLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eCAP module" "Disabled,Enabled" bitfld.long 0x00 0. " ECAPCLK_EN_ACK ,This bit is the clk_en status output of the eCAP module" "Disabled,Enabled" width 0xB tree.end tree "Enhanced PWM (ePWM)" base ad:0x48300200 width 7. group.word 0x00++0x03 "Time-Base Submodule Registers" line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode" "Stop after next count,Stop when complete,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale" "1,2,4,8,16,32,64,128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale" "/1,/2,/4,/6,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disable EPWMxSYNCO" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "TBCNT=0,Immediately" textline " " bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze" line.word 0x02 "TBSTS,Time-Base Status Register" eventfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status" "Not reached,Reached" eventfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status" "Count down,Count up" group.word 0x06++0x05 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCNT,Time-Base Counter Register" line.word 0x04 "TBPRD,Time-Base Period Register" width 8. group.word 0x0e++0x01 "Counter-Compare Submodule Registers" line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" width 9. group.word 0x16++0x07 "Action-Qualifier Submodule Registers" line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled" textline " " bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "0,Period,0/Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggled" textline " " bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Disabled,Low,High,Disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Disabled,Low,High,Disabled" width 7. group.word 0x1e++0x05 "Dead-Band Generator Submodule Registers" line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control (Falling-edge/rising-edge)" "EPWMxA/EPWMxA,EPWMxA/EPWMxB,EPWMxB/EPWMxA,EPWMxB/EPWMxB" bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control (Falling-edge/rising-edge)" "Disabled/Disabled,Enabled/Disabled,Disabled/Enabled,Enabled/Enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" width 8. group.word 0x24++0x01 "Trip-Zone Submodule Registers" line.word 0x00 "TZSEL,Trip-Zone Select Register" bitfld.word 0x00 8. " OSHT1 ,One-Shot (OSHT) trip-zone 1 enable/disable" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone 1 enable/disable" "Disabled,Enabled" group.word 0x28++0x03 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 2.--3. " TZB ,Action taken on output EPWMxB" "High-impedance,High,Low,No action" bitfld.word 0x00 0.--1. " TZA ,Action taken on output EPWMxA" "Tri-state,High,Low,No action" line.word 0x02 "TZEINT,Trip-Zone Enable Interrupt Register" bitfld.word 0x02 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled" bitfld.word 0x02 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled" rgroup.word 0x2c++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register" bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred" bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred" bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x2e++0x03 line.word 0x00 "TZCLR,Trip-Zone Clear Register" bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Cleared" bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Cleared" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Cleared" line.word 0x02 "TZFRC,Trip-Zone Force Register" bitfld.word 0x02 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x02 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" width 9. group.word 0x32++0x03 "Event-Trigger Submodule Registers" line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt (EPWMx_INT) Selection Options" "Reserved,TBCNT=0,TBCNT=TBPRD,Reserved,TBCNT=CMPA when incr.,TBCNT=CMPA when decr.,TBCNT=CMPB when incr.,TBCNT=CMPB when decr." line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event" rgroup.word 0x36++0x05 line.word 0x00 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "No interrupt,Interrupt" line.word 0x02 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x02 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear" "No effect,Cleared" line.word 0x04 "ETFRC,Event-Trigger Force Register" bitfld.word 0x04 0. " INT ,INT Force" "No effect,Interrupt" group.word 0x3c++0x01 "PWM-Chopper Submodule Register" line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..." bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "1,2,3,4,5,6,7,8" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" group.word 0x40++0x01 line.word 0x00 "HRPWM,HRPWM Control Register (HRCTL" bitfld.word 0x00 3. " PULSESEL ,Pulse select bits" "CNT_zero,PRD_eq" bitfld.word 0x00 2. " DELBUSSEL ,Delay Bus Select Bit" "CMPAHR,TBPHSHR" bitfld.word 0x00 0.--1. " DELMODE ,Delay Mode Bits" "No delay,rising edge,falling edge,both edges" group.word 0x04++0x01 "High-Resolution PWM Submodule Registers" line.word 0x00 "TBPHSHR,Time-Base Phase High-Resolution Register" hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution" group.word 0x10++0x01 line.word 0x00 "CMPAHR,Counter-Compare A High-Resolution Register" hexmask.word.byte 0x00 8.--15. 1. " CMPAHR ,Compare A High-Resolution register bits for MEP step control" sif (!cpuis("AM335*")) group.word 0x1040++0x01 line.word 0x00 "HRCNFG,HRPWM Configuration Register" bitfld.word 0x00 3. " HRLOAD ,Shadow mode" "CTR=0,CTR=PRD" bitfld.word 0x00 2. " CTLMODE ,Control Mode" "CMPAHR(8),TBPHSHR(8)" bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode" "Disabled,Rising,Falling,Both" endif width 0x0b tree.end tree "Enhanced Capture (eCAP)" base ad:0x48300100 width 8. group.long 0x0++0x17 line.long 0x0 "TSCTR,Time-Stamp Counter Register" line.long 0x4 "CTRPHS,Counter Phase Control Register" line.long 0x8 "CAP1,Capture 1 Register" line.long 0xc "CAP2,Capture 2 Register" line.long 0x10 "CAP3,Capture 3 Register" line.long 0x14 "CAP4,Capture 4 Register" group.word 0x28++0x5 line.word 0x0 "ECCTL1,ECAP Control Register" bitfld.word 0x0 14.--15. " FREE/SOFT ,Emulation Control" "Stopped,Run Until = 0,Run Free,Run Free" bitfld.word 0x0 9.--13. " PRESCALE ,Event Filter prescale select" "Divide by 1,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,Divide by 12,Divide by 14,Divide by 16,Divide by 18,Divide by 20,Divide by 22,Divide by 24,Divide by 26,Divide by 28,Divide by 30,Divide by 32,Divide by 34,Divide by 36,Divide by 38,Divide by 40,Divide by 42,Divide by 44,Divide by 46,Divide by 48,Divide by 50,Divide by 52,Divide by 54,Divide by 56,Divide by 58,Divide by 60,Divide by 62" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled" textline " " bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4" "No reset,Reset" bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3" "No reset,Reset" bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2" "No reset,Reset" bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1" "No reset,Reset" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select" "Rising edge,Falling edge" line.word 0x2 "ECCTL2,ECAP Control Register" bitfld.word 0x2 10. " APWMPOL ,APWM output polarity select" "High,Low" bitfld.word 0x2 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture,APWM" textline " " bitfld.word 0x2 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "Not forced,Forced" bitfld.word 0x2 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-In,CTR=PRD,Disabled,Disabled" textline " " bitfld.word 0x2 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled" bitfld.word 0x2 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running" textline " " bitfld.word 0x2 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,Re-armed" bitfld.word 0x2 1.--2. " STOP_WRAP ,Stop value for One-Shot mode" "Event 1,Event 2,Event 3,Event 4" textline " " bitfld.word 0x2 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot" line.word 0x4 "ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x4 7. " CTR=CMP ,Counter Equal Compare Interrupt Enable" "Disabled,Enabled" bitfld.word 0x4 6. " CTR=PRD ,Counter Equal Period Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x4 5. " CTROVF ,Counter Overflow Interrupt Enable" "Disabled,Enabled" bitfld.word 0x4 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x4 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "Disabled,Enabled" bitfld.word 0x4 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x4 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "Disabled,Enabled" group.word 0x2e++0x1 line.word 0x0 "ECFLG,ECAP Interrupt Flag Register" setclrfld.word 0x0 7. 0x4 7. 0x2 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not equal,Equal" setclrfld.word 0x0 6. 0x4 6. 0x2 6. " CTR=PRD_set/clr ,Counter Equal Period Status Flag" "Not equal,Equal" textline " " setclrfld.word 0x0 5. 0x4 5. 0x2 5. " CTROVF_set/clr ,Counter Overflow Status Flag" "No overflow,Overflow" setclrfld.word 0x0 4. 0x4 4. 0x2 4. " CEVT4_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x0 3. 0x4 3. 0x2 3. " CETV3_set/clr ,Capture Event 3 Status Flag" "Not occurred,Occurred" setclrfld.word 0x0 2. 0x4 2. 0x2 2. " CETV2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x0 1. 0x4 1. 0x2 1. " CETV1_set/clr ,Capture Event 1 Status Flag" "Not occurred,Occurred" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x30++0x3 line.word 0x0 "ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT_clr ,Global Interrupt Clear Flag" "No effect,Cleared" rgroup.long 0x5c++0x03 line.long 0x00 "REVID,Revision ID Register" width 0xb tree.end tree "Enhanced Quadrature Encoder Pulse (eQEP)" base ad:0x48300180 width 0xb group.long 0x00++0x0f line.long 0x00 "QPOSCNT,eQEP Position Counter Register" line.long 0x04 "QPOSINIT,eQEP Position Counter Initialization Register" line.long 0x08 "QPOSMAX,eQEP Maximum Position Count Register" line.long 0x0c "QPOSCMP,eQEP Position-Compare Register" rgroup.long 0x10++0x0b line.long 0x00 "QPOSILAT,eQEP Index Position Latch Register" line.long 0x04 "QPOSSLAT,eQEP Strobe Position Latch Register" line.long 0x08 "QPOSLAT,eQEP Position Counter Latch Register" group.long 0x1c++0x07 line.long 0x00 "QUTMR,eQEP Unit Timer Register" line.long 0x04 "QUPRD,eQEP Unit Period Register" group.word 0x24++0x0d line.word 0x00 "QWDTMR,eQEP Watchdog Timer Register" line.word 0x02 "QWDPRD,eQEP Watchdog Period Register" line.word 0x04 "QDECCTL,QEP Decoder Control Register" bitfld.word 0x04 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count" bitfld.word 0x04 13. " SOEN ,Sync output-enable" "Disabled,Enabled" bitfld.word 0x04 12. " SPSEL ,Sync output pin selection" "Index,Strobe" textline " " bitfld.word 0x04 11. " XCR ,External clock rate" "2 resolution: rising/falling,1 resolution: rising" textline " " bitfld.word 0x04 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x04 9. " IGATE ,Index pulse gating option" "Disabled,Enabled" bitfld.word 0x04 8. " QAP ,QEPA input polarity" "No effect,Negated" textline " " bitfld.word 0x04 7. " QBP ,QEPB input polarity" "No effect,Negated" bitfld.word 0x04 6. " QIP ,QEPI input polarity" "No effect,Negated" bitfld.word 0x04 5. " QSP ,QEPS input polarity" "No effect,Negated" line.word 0x06 "QEPCTL,eQEP Control Register" bitfld.word 0x06 14.--15. " FREE/SOFT ,Emulation Control (QPOSCNT/QWDTMR/QUTMR/QCTMR)" "Stopped immediately,Until period,Unaffected,Unaffected" textline " " bitfld.word 0x06 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" textline " " bitfld.word 0x06 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising,Clockwise:rising/Count. Clockwise:falling" textline " " bitfld.word 0x06 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising,Falling" textline " " bitfld.word 0x06 7. " SWI ,Software initialization of position counter" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " SEL ,Strobe event latch of position counter" "Rising,Clockwise:Rising/Count. Clockwise:falling" textline " " bitfld.word 0x06 4.--5. " IEL ,Index event latch of position counter" "Reserved,Rising,Falling,Software index marker" textline " " bitfld.word 0x06 3. " PHEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x06 2. " QCLM ,eQEP capture latch mode" "Position counter read by CPU,Unit time out" textline " " bitfld.word 0x06 1. " UTE ,eQEP unit timer enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " WDE ,eQEP watchdog enable" "Disabled,Enabled" line.word 0x08 "QCAPCTL,eQEP Capture Control Register" bitfld.word 0x08 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x08 4.--6. " CCPS ,eQEP capture timer clock prescaler" "SYSCLKOUT/1,SYSCLKOUT/2,SYSCLKOUT/4,SYSCLKOUT/8,SYSCLKOUT/16,SYSCLKOUT/32,SYSCLKOUT/64,SYSCLKOUT/128" bitfld.word 0x08 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..." line.word 0x0a "QPOSCTL,eQEP Position-Compare Control Register" bitfld.word 0x0a 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x0a 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT=0,QPOSCNT=QPOSCMP" bitfld.word 0x0a 13. " PCPOL ,Polarity of sync output" "Active high,Active low" textline " " bitfld.word 0x0a 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" hexmask.word 0x0a 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" line.word 0x0c "QEINT,eQEP Interrupt Enable Register" bitfld.word 0x0c 11. " UTO ,Unit time out interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 10. " IEL ,Index event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x0c 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x0c 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 2. " PHE ,Quadrature phase error interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 1. " PCE ,Position counter error interrupt enable" "Disabled,Enabled" rgroup.word 0x32++0x01 line.word 0x00 "QFLG,eQEP Interrupt Flag Register" bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 8. " PCM ,Position-compare match interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x34++0x09 line.word 0x00 "QCLR,eQEP Interrupt Clear Register" bitfld.word 0x00 11. " UTO ,Clear Unit time out interrupt flag" "No effect,Cleared" bitfld.word 0x00 10. " IEL ,Clear Index event latch interrupt flag" "No effect,Cleared" bitfld.word 0x00 9. " SEL ,Clear Strobe event latch interrupt flag" "No effect,Cleared" bitfld.word 0x00 8. " PCM ,Clear Position-compare match interrupt flag" "No effect,Cleared" textline " " bitfld.word 0x00 7. " PCR ,Clear Position-compare ready interrupt flag" "No effect,Cleared" bitfld.word 0x00 6. " PCO ,Clear Position counter overflow interrupt flag" "No effect,Cleared" bitfld.word 0x00 5. " PCU ,Clear Position counter underflow interrupt flag" "No effect,Cleared" bitfld.word 0x00 4. " WTO ,Clear Watchdog time out interrupt flag" "No effect,Cleared" textline " " bitfld.word 0x00 3. " QDC ,Clear Quadrature direction change interrupt flag" "No effect,Cleared" bitfld.word 0x00 2. " PHE ,Clear Quadrature phase error interrupt flag" "No effect,Cleared" bitfld.word 0x00 1. " PCE ,Clear Position counter error interrupt flag" "No effect,Cleared" bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Cleared" line.word 0x02 "QFRC,eQEP Interrupt Force Register" bitfld.word 0x02 11. " UTO ,Force unit time out interrupt" "No effect,Forced" bitfld.word 0x02 10. " IEL ,Force index event latch interrupt" "No effect,Forced" bitfld.word 0x02 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced" bitfld.word 0x02 8. " PCM ,Force position-compare match interrupt" "No effect,Forced" textline " " bitfld.word 0x02 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced" bitfld.word 0x02 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced" bitfld.word 0x02 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced" bitfld.word 0x02 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced" textline " " bitfld.word 0x02 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced" bitfld.word 0x02 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced" bitfld.word 0x02 1. " PCE ,Force position counter error interrupt" "No effect,Forced" line.word 0x04 "QEPSTS,eQEP Status Register" eventfld.word 0x04 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" bitfld.word 0x04 6. " FDF ,Direction on the first index marker" "Counter-clockwise rot.,Clockwise rot." textline " " bitfld.word 0x04 5. " QDF ,Quadrature direction flag" "Counter-clockwise rot.,Clockwise rot." bitfld.word 0x04 4. " QDLF ,eQEP direction latch flag" "Counter-clockwise rot.,Clockwise rot." textline " " eventfld.word 0x04 3. " COEF ,Capture overflow error flag" "No error,Error" eventfld.word 0x04 2. " CDEF ,Capture direction error flag" "No error,Error" textline " " eventfld.word 0x04 1. " FIMF ,First index marker flag" "No error,Error" bitfld.word 0x04 0. " PCEF ,Position counter error flag" "No error,Error" line.word 0x06 "QCTMR,eQEP Capture Timer Register" line.word 0x08 "QCPRD,eQEP Capture Period Register" rgroup.word 0x3e++0x01 line.word 0x00 "QCTMRLAT,eQEP Capture Timer Latch Register" group.word 0x40++0x01 line.word 0x00 "QCPRDLAT,eQEP Capture Period Latch Register" rgroup.long 0x5c++0x03 line.long 0x00 "REVID,eQEP Revision ID Register" width 0xb tree.end tree.end tree "PWM Subsystem 1" tree "PWMSS Configuration Registers" base ad:0x48302000 width 10. rgroup.long 0x00++0x3 line.long 0x00 "IDVER,IP Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme value" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function" hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL revision" textline " " hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major number" hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Number" group.long 0x04++0x7 line.long 0x00 "SYSCONFIG,System Configuration Register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby,Smart-Standby" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation" "is sensitive,is not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Disabled,Enabled" line.long 0x04 "CLKCONFG,Clock Configuration Register" bitfld.long 0x04 9. " EPWMCLKSTOP_REQ ,This bit controls the clkstop_req input to the ePWM module" "Disabled,Enabled" bitfld.long 0x04 8. " EPWMCLK_EN ,This bit controls the clk_en input to the ePWM module" "Disabled,Enabled" bitfld.long 0x04 5. " EQEPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eQEP module" "Disabled,Enabled" bitfld.long 0x04 4. " EQEPCLK_EN ,This bit controls the clk_en input to the eQEP module" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " ECAPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eCAP module" "Disabled,Enabled" bitfld.long 0x04 0. " ECAPCLK_EN ,This bit controls the clk_en input to the eCAP module" "Disabled,Enabled" rgroup.long 0x0C++0x3 line.long 0x00 "CLKSTATUS,Clock Status Register" bitfld.long 0x00 9. " EPWMCLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM module" "Disabled,Enabled" bitfld.long 0x00 8. " EPWMCLK_EN_ACK ,This bit is the clk_en status output of the ePWM module" "Disabled,Enabled" bitfld.long 0x00 5. " EQEPCLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module" "Disabled,Enabled" bitfld.long 0x00 4. " EQEPCLK_EN_ACK ,This bit is the clk_en status output of the eQEP module" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ECAPCLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eCAP module" "Disabled,Enabled" bitfld.long 0x00 0. " ECAPCLK_EN_ACK ,This bit is the clk_en status output of the eCAP module" "Disabled,Enabled" width 0xB tree.end tree "Enhanced PWM (ePWM)" base ad:0x48302200 width 7. group.word 0x00++0x03 "Time-Base Submodule Registers" line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode" "Stop after next count,Stop when complete,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale" "1,2,4,8,16,32,64,128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale" "/1,/2,/4,/6,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disable EPWMxSYNCO" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "TBCNT=0,Immediately" textline " " bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze" line.word 0x02 "TBSTS,Time-Base Status Register" eventfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status" "Not reached,Reached" eventfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status" "Count down,Count up" group.word 0x06++0x05 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCNT,Time-Base Counter Register" line.word 0x04 "TBPRD,Time-Base Period Register" width 8. group.word 0x0e++0x01 "Counter-Compare Submodule Registers" line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" width 9. group.word 0x16++0x07 "Action-Qualifier Submodule Registers" line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled" textline " " bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "0,Period,0/Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggled" textline " " bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Disabled,Low,High,Disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Disabled,Low,High,Disabled" width 7. group.word 0x1e++0x05 "Dead-Band Generator Submodule Registers" line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control (Falling-edge/rising-edge)" "EPWMxA/EPWMxA,EPWMxA/EPWMxB,EPWMxB/EPWMxA,EPWMxB/EPWMxB" bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control (Falling-edge/rising-edge)" "Disabled/Disabled,Enabled/Disabled,Disabled/Enabled,Enabled/Enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" width 8. group.word 0x24++0x01 "Trip-Zone Submodule Registers" line.word 0x00 "TZSEL,Trip-Zone Select Register" bitfld.word 0x00 8. " OSHT1 ,One-Shot (OSHT) trip-zone 1 enable/disable" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone 1 enable/disable" "Disabled,Enabled" group.word 0x28++0x03 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 2.--3. " TZB ,Action taken on output EPWMxB" "High-impedance,High,Low,No action" bitfld.word 0x00 0.--1. " TZA ,Action taken on output EPWMxA" "Tri-state,High,Low,No action" line.word 0x02 "TZEINT,Trip-Zone Enable Interrupt Register" bitfld.word 0x02 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled" bitfld.word 0x02 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled" rgroup.word 0x2c++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register" bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred" bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred" bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x2e++0x03 line.word 0x00 "TZCLR,Trip-Zone Clear Register" bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Cleared" bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Cleared" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Cleared" line.word 0x02 "TZFRC,Trip-Zone Force Register" bitfld.word 0x02 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x02 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" width 9. group.word 0x32++0x03 "Event-Trigger Submodule Registers" line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt (EPWMx_INT) Selection Options" "Reserved,TBCNT=0,TBCNT=TBPRD,Reserved,TBCNT=CMPA when incr.,TBCNT=CMPA when decr.,TBCNT=CMPB when incr.,TBCNT=CMPB when decr." line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event" rgroup.word 0x36++0x05 line.word 0x00 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "No interrupt,Interrupt" line.word 0x02 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x02 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear" "No effect,Cleared" line.word 0x04 "ETFRC,Event-Trigger Force Register" bitfld.word 0x04 0. " INT ,INT Force" "No effect,Interrupt" group.word 0x3c++0x01 "PWM-Chopper Submodule Register" line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..." bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "1,2,3,4,5,6,7,8" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" group.word 0x40++0x01 line.word 0x00 "HRPWM,HRPWM Control Register (HRCTL" bitfld.word 0x00 3. " PULSESEL ,Pulse select bits" "CNT_zero,PRD_eq" bitfld.word 0x00 2. " DELBUSSEL ,Delay Bus Select Bit" "CMPAHR,TBPHSHR" bitfld.word 0x00 0.--1. " DELMODE ,Delay Mode Bits" "No delay,rising edge,falling edge,both edges" group.word 0x04++0x01 "High-Resolution PWM Submodule Registers" line.word 0x00 "TBPHSHR,Time-Base Phase High-Resolution Register" hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution" group.word 0x10++0x01 line.word 0x00 "CMPAHR,Counter-Compare A High-Resolution Register" hexmask.word.byte 0x00 8.--15. 1. " CMPAHR ,Compare A High-Resolution register bits for MEP step control" sif (!cpuis("AM335*")) group.word 0x1040++0x01 line.word 0x00 "HRCNFG,HRPWM Configuration Register" bitfld.word 0x00 3. " HRLOAD ,Shadow mode" "CTR=0,CTR=PRD" bitfld.word 0x00 2. " CTLMODE ,Control Mode" "CMPAHR(8),TBPHSHR(8)" bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode" "Disabled,Rising,Falling,Both" endif width 0x0b tree.end tree "Enhanced Capture (eCAP)" base ad:0x48302100 width 8. group.long 0x0++0x17 line.long 0x0 "TSCTR,Time-Stamp Counter Register" line.long 0x4 "CTRPHS,Counter Phase Control Register" line.long 0x8 "CAP1,Capture 1 Register" line.long 0xc "CAP2,Capture 2 Register" line.long 0x10 "CAP3,Capture 3 Register" line.long 0x14 "CAP4,Capture 4 Register" group.word 0x28++0x5 line.word 0x0 "ECCTL1,ECAP Control Register" bitfld.word 0x0 14.--15. " FREE/SOFT ,Emulation Control" "Stopped,Run Until = 0,Run Free,Run Free" bitfld.word 0x0 9.--13. " PRESCALE ,Event Filter prescale select" "Divide by 1,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,Divide by 12,Divide by 14,Divide by 16,Divide by 18,Divide by 20,Divide by 22,Divide by 24,Divide by 26,Divide by 28,Divide by 30,Divide by 32,Divide by 34,Divide by 36,Divide by 38,Divide by 40,Divide by 42,Divide by 44,Divide by 46,Divide by 48,Divide by 50,Divide by 52,Divide by 54,Divide by 56,Divide by 58,Divide by 60,Divide by 62" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled" textline " " bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4" "No reset,Reset" bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3" "No reset,Reset" bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2" "No reset,Reset" bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1" "No reset,Reset" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select" "Rising edge,Falling edge" line.word 0x2 "ECCTL2,ECAP Control Register" bitfld.word 0x2 10. " APWMPOL ,APWM output polarity select" "High,Low" bitfld.word 0x2 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture,APWM" textline " " bitfld.word 0x2 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "Not forced,Forced" bitfld.word 0x2 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-In,CTR=PRD,Disabled,Disabled" textline " " bitfld.word 0x2 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled" bitfld.word 0x2 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running" textline " " bitfld.word 0x2 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,Re-armed" bitfld.word 0x2 1.--2. " STOP_WRAP ,Stop value for One-Shot mode" "Event 1,Event 2,Event 3,Event 4" textline " " bitfld.word 0x2 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot" line.word 0x4 "ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x4 7. " CTR=CMP ,Counter Equal Compare Interrupt Enable" "Disabled,Enabled" bitfld.word 0x4 6. " CTR=PRD ,Counter Equal Period Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x4 5. " CTROVF ,Counter Overflow Interrupt Enable" "Disabled,Enabled" bitfld.word 0x4 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x4 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "Disabled,Enabled" bitfld.word 0x4 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x4 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "Disabled,Enabled" group.word 0x2e++0x1 line.word 0x0 "ECFLG,ECAP Interrupt Flag Register" setclrfld.word 0x0 7. 0x4 7. 0x2 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not equal,Equal" setclrfld.word 0x0 6. 0x4 6. 0x2 6. " CTR=PRD_set/clr ,Counter Equal Period Status Flag" "Not equal,Equal" textline " " setclrfld.word 0x0 5. 0x4 5. 0x2 5. " CTROVF_set/clr ,Counter Overflow Status Flag" "No overflow,Overflow" setclrfld.word 0x0 4. 0x4 4. 0x2 4. " CEVT4_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x0 3. 0x4 3. 0x2 3. " CETV3_set/clr ,Capture Event 3 Status Flag" "Not occurred,Occurred" setclrfld.word 0x0 2. 0x4 2. 0x2 2. " CETV2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x0 1. 0x4 1. 0x2 1. " CETV1_set/clr ,Capture Event 1 Status Flag" "Not occurred,Occurred" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x30++0x3 line.word 0x0 "ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT_clr ,Global Interrupt Clear Flag" "No effect,Cleared" rgroup.long 0x5c++0x03 line.long 0x00 "REVID,Revision ID Register" width 0xb tree.end tree "Enhanced Quadrature Encoder Pulse (eQEP)" base ad:0x48302180 width 0xb group.long 0x00++0x0f line.long 0x00 "QPOSCNT,eQEP Position Counter Register" line.long 0x04 "QPOSINIT,eQEP Position Counter Initialization Register" line.long 0x08 "QPOSMAX,eQEP Maximum Position Count Register" line.long 0x0c "QPOSCMP,eQEP Position-Compare Register" rgroup.long 0x10++0x0b line.long 0x00 "QPOSILAT,eQEP Index Position Latch Register" line.long 0x04 "QPOSSLAT,eQEP Strobe Position Latch Register" line.long 0x08 "QPOSLAT,eQEP Position Counter Latch Register" group.long 0x1c++0x07 line.long 0x00 "QUTMR,eQEP Unit Timer Register" line.long 0x04 "QUPRD,eQEP Unit Period Register" group.word 0x24++0x0d line.word 0x00 "QWDTMR,eQEP Watchdog Timer Register" line.word 0x02 "QWDPRD,eQEP Watchdog Period Register" line.word 0x04 "QDECCTL,QEP Decoder Control Register" bitfld.word 0x04 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count" bitfld.word 0x04 13. " SOEN ,Sync output-enable" "Disabled,Enabled" bitfld.word 0x04 12. " SPSEL ,Sync output pin selection" "Index,Strobe" textline " " bitfld.word 0x04 11. " XCR ,External clock rate" "2 resolution: rising/falling,1 resolution: rising" textline " " bitfld.word 0x04 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x04 9. " IGATE ,Index pulse gating option" "Disabled,Enabled" bitfld.word 0x04 8. " QAP ,QEPA input polarity" "No effect,Negated" textline " " bitfld.word 0x04 7. " QBP ,QEPB input polarity" "No effect,Negated" bitfld.word 0x04 6. " QIP ,QEPI input polarity" "No effect,Negated" bitfld.word 0x04 5. " QSP ,QEPS input polarity" "No effect,Negated" line.word 0x06 "QEPCTL,eQEP Control Register" bitfld.word 0x06 14.--15. " FREE/SOFT ,Emulation Control (QPOSCNT/QWDTMR/QUTMR/QCTMR)" "Stopped immediately,Until period,Unaffected,Unaffected" textline " " bitfld.word 0x06 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" textline " " bitfld.word 0x06 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising,Clockwise:rising/Count. Clockwise:falling" textline " " bitfld.word 0x06 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising,Falling" textline " " bitfld.word 0x06 7. " SWI ,Software initialization of position counter" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " SEL ,Strobe event latch of position counter" "Rising,Clockwise:Rising/Count. Clockwise:falling" textline " " bitfld.word 0x06 4.--5. " IEL ,Index event latch of position counter" "Reserved,Rising,Falling,Software index marker" textline " " bitfld.word 0x06 3. " PHEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x06 2. " QCLM ,eQEP capture latch mode" "Position counter read by CPU,Unit time out" textline " " bitfld.word 0x06 1. " UTE ,eQEP unit timer enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " WDE ,eQEP watchdog enable" "Disabled,Enabled" line.word 0x08 "QCAPCTL,eQEP Capture Control Register" bitfld.word 0x08 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x08 4.--6. " CCPS ,eQEP capture timer clock prescaler" "SYSCLKOUT/1,SYSCLKOUT/2,SYSCLKOUT/4,SYSCLKOUT/8,SYSCLKOUT/16,SYSCLKOUT/32,SYSCLKOUT/64,SYSCLKOUT/128" bitfld.word 0x08 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..." line.word 0x0a "QPOSCTL,eQEP Position-Compare Control Register" bitfld.word 0x0a 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x0a 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT=0,QPOSCNT=QPOSCMP" bitfld.word 0x0a 13. " PCPOL ,Polarity of sync output" "Active high,Active low" textline " " bitfld.word 0x0a 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" hexmask.word 0x0a 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" line.word 0x0c "QEINT,eQEP Interrupt Enable Register" bitfld.word 0x0c 11. " UTO ,Unit time out interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 10. " IEL ,Index event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x0c 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x0c 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 2. " PHE ,Quadrature phase error interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 1. " PCE ,Position counter error interrupt enable" "Disabled,Enabled" rgroup.word 0x32++0x01 line.word 0x00 "QFLG,eQEP Interrupt Flag Register" bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 8. " PCM ,Position-compare match interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x34++0x09 line.word 0x00 "QCLR,eQEP Interrupt Clear Register" bitfld.word 0x00 11. " UTO ,Clear Unit time out interrupt flag" "No effect,Cleared" bitfld.word 0x00 10. " IEL ,Clear Index event latch interrupt flag" "No effect,Cleared" bitfld.word 0x00 9. " SEL ,Clear Strobe event latch interrupt flag" "No effect,Cleared" bitfld.word 0x00 8. " PCM ,Clear Position-compare match interrupt flag" "No effect,Cleared" textline " " bitfld.word 0x00 7. " PCR ,Clear Position-compare ready interrupt flag" "No effect,Cleared" bitfld.word 0x00 6. " PCO ,Clear Position counter overflow interrupt flag" "No effect,Cleared" bitfld.word 0x00 5. " PCU ,Clear Position counter underflow interrupt flag" "No effect,Cleared" bitfld.word 0x00 4. " WTO ,Clear Watchdog time out interrupt flag" "No effect,Cleared" textline " " bitfld.word 0x00 3. " QDC ,Clear Quadrature direction change interrupt flag" "No effect,Cleared" bitfld.word 0x00 2. " PHE ,Clear Quadrature phase error interrupt flag" "No effect,Cleared" bitfld.word 0x00 1. " PCE ,Clear Position counter error interrupt flag" "No effect,Cleared" bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Cleared" line.word 0x02 "QFRC,eQEP Interrupt Force Register" bitfld.word 0x02 11. " UTO ,Force unit time out interrupt" "No effect,Forced" bitfld.word 0x02 10. " IEL ,Force index event latch interrupt" "No effect,Forced" bitfld.word 0x02 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced" bitfld.word 0x02 8. " PCM ,Force position-compare match interrupt" "No effect,Forced" textline " " bitfld.word 0x02 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced" bitfld.word 0x02 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced" bitfld.word 0x02 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced" bitfld.word 0x02 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced" textline " " bitfld.word 0x02 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced" bitfld.word 0x02 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced" bitfld.word 0x02 1. " PCE ,Force position counter error interrupt" "No effect,Forced" line.word 0x04 "QEPSTS,eQEP Status Register" eventfld.word 0x04 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" bitfld.word 0x04 6. " FDF ,Direction on the first index marker" "Counter-clockwise rot.,Clockwise rot." textline " " bitfld.word 0x04 5. " QDF ,Quadrature direction flag" "Counter-clockwise rot.,Clockwise rot." bitfld.word 0x04 4. " QDLF ,eQEP direction latch flag" "Counter-clockwise rot.,Clockwise rot." textline " " eventfld.word 0x04 3. " COEF ,Capture overflow error flag" "No error,Error" eventfld.word 0x04 2. " CDEF ,Capture direction error flag" "No error,Error" textline " " eventfld.word 0x04 1. " FIMF ,First index marker flag" "No error,Error" bitfld.word 0x04 0. " PCEF ,Position counter error flag" "No error,Error" line.word 0x06 "QCTMR,eQEP Capture Timer Register" line.word 0x08 "QCPRD,eQEP Capture Period Register" rgroup.word 0x3e++0x01 line.word 0x00 "QCTMRLAT,eQEP Capture Timer Latch Register" group.word 0x40++0x01 line.word 0x00 "QCPRDLAT,eQEP Capture Period Latch Register" rgroup.long 0x5c++0x03 line.long 0x00 "REVID,eQEP Revision ID Register" width 0xb tree.end tree.end tree "PWM Subsystem 2" tree "PWMSS Configuration Registers" base ad:0x48304000 width 10. rgroup.long 0x00++0x3 line.long 0x00 "IDVER,IP Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme value" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function" hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL revision" textline " " hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major number" hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Number" group.long 0x04++0x7 line.long 0x00 "SYSCONFIG,System Configuration Register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode" "Force-standby,No-standby,Smart-standby,Smart-Standby" bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation" "is sensitive,is not sensitive" bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Disabled,Enabled" line.long 0x04 "CLKCONFG,Clock Configuration Register" bitfld.long 0x04 9. " EPWMCLKSTOP_REQ ,This bit controls the clkstop_req input to the ePWM module" "Disabled,Enabled" bitfld.long 0x04 8. " EPWMCLK_EN ,This bit controls the clk_en input to the ePWM module" "Disabled,Enabled" bitfld.long 0x04 5. " EQEPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eQEP module" "Disabled,Enabled" bitfld.long 0x04 4. " EQEPCLK_EN ,This bit controls the clk_en input to the eQEP module" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " ECAPCLKSTOP_REQ ,This bit controls the clkstop_req input to the eCAP module" "Disabled,Enabled" bitfld.long 0x04 0. " ECAPCLK_EN ,This bit controls the clk_en input to the eCAP module" "Disabled,Enabled" rgroup.long 0x0C++0x3 line.long 0x00 "CLKSTATUS,Clock Status Register" bitfld.long 0x00 9. " EPWMCLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM module" "Disabled,Enabled" bitfld.long 0x00 8. " EPWMCLK_EN_ACK ,This bit is the clk_en status output of the ePWM module" "Disabled,Enabled" bitfld.long 0x00 5. " EQEPCLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module" "Disabled,Enabled" bitfld.long 0x00 4. " EQEPCLK_EN_ACK ,This bit is the clk_en status output of the eQEP module" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ECAPCLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eCAP module" "Disabled,Enabled" bitfld.long 0x00 0. " ECAPCLK_EN_ACK ,This bit is the clk_en status output of the eCAP module" "Disabled,Enabled" width 0xB tree.end tree "Enhanced PWM (ePWM)" base ad:0x48304200 width 7. group.word 0x00++0x03 "Time-Base Submodule Registers" line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode" "Stop after next count,Stop when complete,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale" "1,2,4,8,16,32,64,128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale" "/1,/2,/4,/6,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Forced" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR=zero,CTR=CMPB,Disable EPWMxSYNCO" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "TBCNT=0,Immediately" textline " " bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze" line.word 0x02 "TBSTS,Time-Base Status Register" eventfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status" "Not reached,Reached" eventfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status" "Count down,Count up" group.word 0x06++0x05 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCNT,Time-Base Counter Register" line.word 0x04 "TBPRD,Time-Base Period Register" width 8. group.word 0x0e++0x01 "Counter-Compare Submodule Registers" line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B (CMPB) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A (CMPA) Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B (CMPB) Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A (CMPA) Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "CTR=0,CTR= PRD,either CTR=0/CTR=PRD,Freeze" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" width 9. group.word 0x16++0x07 "Action-Qualifier Submodule Registers" line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled" textline " " bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggled" textline " " bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Clear,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "0,Period,0/Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Clear,Set,Toggled" textline " " bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Clear,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Disabled,Low,High,Disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Disabled,Low,High,Disabled" width 7. group.word 0x1e++0x05 "Dead-Band Generator Submodule Registers" line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control (Falling-edge/rising-edge)" "EPWMxA/EPWMxA,EPWMxA/EPWMxB,EPWMxB/EPWMxA,EPWMxB/EPWMxB" bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control (Falling-edge/rising-edge)" "Disabled/Disabled,Enabled/Disabled,Disabled/Enabled,Enabled/Enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" width 8. group.word 0x24++0x01 "Trip-Zone Submodule Registers" line.word 0x00 "TZSEL,Trip-Zone Select Register" bitfld.word 0x00 8. " OSHT1 ,One-Shot (OSHT) trip-zone 1 enable/disable" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Cycle-by-Cycle (CBC) trip-zone 1 enable/disable" "Disabled,Enabled" group.word 0x28++0x03 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 2.--3. " TZB ,Action taken on output EPWMxB" "High-impedance,High,Low,No action" bitfld.word 0x00 0.--1. " TZA ,Action taken on output EPWMxA" "Tri-state,High,Low,No action" line.word 0x02 "TZEINT,Trip-Zone Enable Interrupt Register" bitfld.word 0x02 2. " OST ,Trip-zone One-Shot Interrupt Enable" "Disabled,Enabled" bitfld.word 0x02 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable" "Disabled,Enabled" rgroup.word 0x2c++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register" bitfld.word 0x00 2. " OST ,Latched Status Flag for A One-Shot Trip Event" "Not occurred,Occurred" bitfld.word 0x00 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event" "Not occurred,Occurred" bitfld.word 0x00 0. " INT ,Latched Trip Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x2e++0x03 line.word 0x00 "TZCLR,Trip-Zone Clear Register" bitfld.word 0x00 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch" "No effect,Cleared" bitfld.word 0x00 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch" "No effect,Cleared" bitfld.word 0x00 0. " INT ,Global Interrupt Clear Flag" "No effect,Cleared" line.word 0x02 "TZFRC,Trip-Zone Force Register" bitfld.word 0x02 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x02 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" width 9. group.word 0x32++0x03 "Event-Trigger Submodule Registers" line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt (EPWMx_INT) Selection Options" "Reserved,TBCNT=0,TBCNT=TBPRD,Reserved,TBCNT=CMPA when incr.,TBCNT=CMPA when decr.,TBCNT=CMPB when incr.,TBCNT=CMPB when decr." line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event (EPWMx_INT) Counter Register" "0,1,2,3" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt (EPWMx_INT) Period Select" "Disabled,First event,Second event,Third event" rgroup.word 0x36++0x05 line.word 0x00 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x00 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag" "No interrupt,Interrupt" line.word 0x02 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x02 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear" "No effect,Cleared" line.word 0x04 "ETFRC,Event-Trigger Force Register" bitfld.word 0x04 0. " INT ,INT Force" "No effect,Interrupt" group.word 0x3c++0x01 "PWM-Chopper Submodule Register" line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..." bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "1,2,3,4,5,6,7,8" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" group.word 0x40++0x01 line.word 0x00 "HRPWM,HRPWM Control Register (HRCTL" bitfld.word 0x00 3. " PULSESEL ,Pulse select bits" "CNT_zero,PRD_eq" bitfld.word 0x00 2. " DELBUSSEL ,Delay Bus Select Bit" "CMPAHR,TBPHSHR" bitfld.word 0x00 0.--1. " DELMODE ,Delay Mode Bits" "No delay,rising edge,falling edge,both edges" group.word 0x04++0x01 "High-Resolution PWM Submodule Registers" line.word 0x00 "TBPHSHR,Time-Base Phase High-Resolution Register" hexmask.word.byte 0x00 8.--15. 1. " TBPHSH ,Time-base phase high-resolution" group.word 0x10++0x01 line.word 0x00 "CMPAHR,Counter-Compare A High-Resolution Register" hexmask.word.byte 0x00 8.--15. 1. " CMPAHR ,Compare A High-Resolution register bits for MEP step control" sif (!cpuis("AM335*")) group.word 0x1040++0x01 line.word 0x00 "HRCNFG,HRPWM Configuration Register" bitfld.word 0x00 3. " HRLOAD ,Shadow mode" "CTR=0,CTR=PRD" bitfld.word 0x00 2. " CTLMODE ,Control Mode" "CMPAHR(8),TBPHSHR(8)" bitfld.word 0x00 0.--1. " EDGMODE ,Edge Mode" "Disabled,Rising,Falling,Both" endif width 0x0b tree.end tree "Enhanced Capture (eCAP)" base ad:0x48304100 width 8. group.long 0x0++0x17 line.long 0x0 "TSCTR,Time-Stamp Counter Register" line.long 0x4 "CTRPHS,Counter Phase Control Register" line.long 0x8 "CAP1,Capture 1 Register" line.long 0xc "CAP2,Capture 2 Register" line.long 0x10 "CAP3,Capture 3 Register" line.long 0x14 "CAP4,Capture 4 Register" group.word 0x28++0x5 line.word 0x0 "ECCTL1,ECAP Control Register" bitfld.word 0x0 14.--15. " FREE/SOFT ,Emulation Control" "Stopped,Run Until = 0,Run Free,Run Free" bitfld.word 0x0 9.--13. " PRESCALE ,Event Filter prescale select" "Divide by 1,Divide by 2,Divide by 4,Divide by 6,Divide by 8,Divide by 10,Divide by 12,Divide by 14,Divide by 16,Divide by 18,Divide by 20,Divide by 22,Divide by 24,Divide by 26,Divide by 28,Divide by 30,Divide by 32,Divide by 34,Divide by 36,Divide by 38,Divide by 40,Divide by 42,Divide by 44,Divide by 46,Divide by 48,Divide by 50,Divide by 52,Divide by 54,Divide by 56,Divide by 58,Divide by 60,Divide by 62" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled" textline " " bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4" "No reset,Reset" bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3" "No reset,Reset" bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2" "No reset,Reset" bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select" "Rising edge,Falling edge" textline " " bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1" "No reset,Reset" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select" "Rising edge,Falling edge" line.word 0x2 "ECCTL2,ECAP Control Register" bitfld.word 0x2 10. " APWMPOL ,APWM output polarity select" "High,Low" bitfld.word 0x2 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture,APWM" textline " " bitfld.word 0x2 8. " SWSYNC ,Software-forced Counter (TSCTR) Synchronizing" "Not forced,Forced" bitfld.word 0x2 6.--7. " SYNCO_SEL ,Sync-Out Select" "Sync-In,CTR=PRD,Disabled,Disabled" textline " " bitfld.word 0x2 5. " SYNCI_EN ,Counter (TSCTR) Sync-In select mode" "Disabled,Enabled" bitfld.word 0x2 4. " TSCTRSTOP ,Time Stamp (TSCTR) Counter Stop (freeze) Control" "Stopped,Free-running" textline " " bitfld.word 0x2 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,Re-armed" bitfld.word 0x2 1.--2. " STOP_WRAP ,Stop value for One-Shot mode" "Event 1,Event 2,Event 3,Event 4" textline " " bitfld.word 0x2 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot" line.word 0x4 "ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x4 7. " CTR=CMP ,Counter Equal Compare Interrupt Enable" "Disabled,Enabled" bitfld.word 0x4 6. " CTR=PRD ,Counter Equal Period Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x4 5. " CTROVF ,Counter Overflow Interrupt Enable" "Disabled,Enabled" bitfld.word 0x4 4. " CEVT4 ,Capture Event 4 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x4 3. " CEVT3 ,Capture Event 3 Interrupt Enable" "Disabled,Enabled" bitfld.word 0x4 2. " CEVT2 ,Capture Event 2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x4 1. " CEVT1 ,Capture Event 1 Interrupt Enable" "Disabled,Enabled" group.word 0x2e++0x1 line.word 0x0 "ECFLG,ECAP Interrupt Flag Register" setclrfld.word 0x0 7. 0x4 7. 0x2 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not equal,Equal" setclrfld.word 0x0 6. 0x4 6. 0x2 6. " CTR=PRD_set/clr ,Counter Equal Period Status Flag" "Not equal,Equal" textline " " setclrfld.word 0x0 5. 0x4 5. 0x2 5. " CTROVF_set/clr ,Counter Overflow Status Flag" "No overflow,Overflow" setclrfld.word 0x0 4. 0x4 4. 0x2 4. " CEVT4_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x0 3. 0x4 3. 0x2 3. " CETV3_set/clr ,Capture Event 3 Status Flag" "Not occurred,Occurred" setclrfld.word 0x0 2. 0x4 2. 0x2 2. " CETV2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x0 1. 0x4 1. 0x2 1. " CETV1_set/clr ,Capture Event 1 Status Flag" "Not occurred,Occurred" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag" "No interrupt,Interrupt" group.word 0x30++0x3 line.word 0x0 "ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT_clr ,Global Interrupt Clear Flag" "No effect,Cleared" rgroup.long 0x5c++0x03 line.long 0x00 "REVID,Revision ID Register" width 0xb tree.end tree "Enhanced Quadrature Encoder Pulse (eQEP)" base ad:0x48304180 width 0xb group.long 0x00++0x0f line.long 0x00 "QPOSCNT,eQEP Position Counter Register" line.long 0x04 "QPOSINIT,eQEP Position Counter Initialization Register" line.long 0x08 "QPOSMAX,eQEP Maximum Position Count Register" line.long 0x0c "QPOSCMP,eQEP Position-Compare Register" rgroup.long 0x10++0x0b line.long 0x00 "QPOSILAT,eQEP Index Position Latch Register" line.long 0x04 "QPOSSLAT,eQEP Strobe Position Latch Register" line.long 0x08 "QPOSLAT,eQEP Position Counter Latch Register" group.long 0x1c++0x07 line.long 0x00 "QUTMR,eQEP Unit Timer Register" line.long 0x04 "QUPRD,eQEP Unit Period Register" group.word 0x24++0x0d line.word 0x00 "QWDTMR,eQEP Watchdog Timer Register" line.word 0x02 "QWDPRD,eQEP Watchdog Period Register" line.word 0x04 "QDECCTL,QEP Decoder Control Register" bitfld.word 0x04 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count" bitfld.word 0x04 13. " SOEN ,Sync output-enable" "Disabled,Enabled" bitfld.word 0x04 12. " SPSEL ,Sync output pin selection" "Index,Strobe" textline " " bitfld.word 0x04 11. " XCR ,External clock rate" "2 resolution: rising/falling,1 resolution: rising" textline " " bitfld.word 0x04 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x04 9. " IGATE ,Index pulse gating option" "Disabled,Enabled" bitfld.word 0x04 8. " QAP ,QEPA input polarity" "No effect,Negated" textline " " bitfld.word 0x04 7. " QBP ,QEPB input polarity" "No effect,Negated" bitfld.word 0x04 6. " QIP ,QEPI input polarity" "No effect,Negated" bitfld.word 0x04 5. " QSP ,QEPS input polarity" "No effect,Negated" line.word 0x06 "QEPCTL,eQEP Control Register" bitfld.word 0x06 14.--15. " FREE/SOFT ,Emulation Control (QPOSCNT/QWDTMR/QUTMR/QCTMR)" "Stopped immediately,Until period,Unaffected,Unaffected" textline " " bitfld.word 0x06 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" textline " " bitfld.word 0x06 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Rising,Clockwise:rising/Count. Clockwise:falling" textline " " bitfld.word 0x06 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Rising,Falling" textline " " bitfld.word 0x06 7. " SWI ,Software initialization of position counter" "Disabled,Enabled" textline " " bitfld.word 0x06 6. " SEL ,Strobe event latch of position counter" "Rising,Clockwise:Rising/Count. Clockwise:falling" textline " " bitfld.word 0x06 4.--5. " IEL ,Index event latch of position counter" "Reserved,Rising,Falling,Software index marker" textline " " bitfld.word 0x06 3. " PHEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x06 2. " QCLM ,eQEP capture latch mode" "Position counter read by CPU,Unit time out" textline " " bitfld.word 0x06 1. " UTE ,eQEP unit timer enable" "Disabled,Enabled" textline " " bitfld.word 0x06 0. " WDE ,eQEP watchdog enable" "Disabled,Enabled" line.word 0x08 "QCAPCTL,eQEP Capture Control Register" bitfld.word 0x08 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x08 4.--6. " CCPS ,eQEP capture timer clock prescaler" "SYSCLKOUT/1,SYSCLKOUT/2,SYSCLKOUT/4,SYSCLKOUT/8,SYSCLKOUT/16,SYSCLKOUT/32,SYSCLKOUT/64,SYSCLKOUT/128" bitfld.word 0x08 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..." line.word 0x0a "QPOSCTL,eQEP Position-Compare Control Register" bitfld.word 0x0a 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x0a 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT=0,QPOSCNT=QPOSCMP" bitfld.word 0x0a 13. " PCPOL ,Polarity of sync output" "Active high,Active low" textline " " bitfld.word 0x0a 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" hexmask.word 0x0a 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" line.word 0x0c "QEINT,eQEP Interrupt Enable Register" bitfld.word 0x0c 11. " UTO ,Unit time out interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 10. " IEL ,Index event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 9. " SEL ,Strobe event latch interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 8. " PCM ,Position-compare match interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x0c 7. " PCR ,Position-compare ready interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 6. " PCO ,Position counter overflow interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 5. " PCU ,Position counter underflow interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 4. " WTO ,Watchdog time out interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x0c 3. " QDC ,Quadrature direction change interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 2. " PHE ,Quadrature phase error interrupt enable" "Disabled,Enabled" bitfld.word 0x0c 1. " PCE ,Position counter error interrupt enable" "Disabled,Enabled" rgroup.word 0x32++0x01 line.word 0x00 "QFLG,eQEP Interrupt Flag Register" bitfld.word 0x00 11. " UTO ,Unit time out interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 10. " IEL ,Index event latch interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 9. " SEL ,Strobe event latch interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 8. " PCM ,Position-compare match interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 7. " PCR ,Position-compare ready interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 6. " PCO ,Position counter overflow interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 5. " PCU ,Position counter underflow interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 4. " WTO ,Watchdog time out interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 3. " QDC ,Quadrature direction change interrupt flag" "No interrupt,Interrupt" textline " " bitfld.word 0x00 2. " PHE ,Quadrature phase error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 1. " PCE ,Position counter error interrupt flag" "No interrupt,Interrupt" bitfld.word 0x00 0. " INT ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x34++0x09 line.word 0x00 "QCLR,eQEP Interrupt Clear Register" bitfld.word 0x00 11. " UTO ,Clear Unit time out interrupt flag" "No effect,Cleared" bitfld.word 0x00 10. " IEL ,Clear Index event latch interrupt flag" "No effect,Cleared" bitfld.word 0x00 9. " SEL ,Clear Strobe event latch interrupt flag" "No effect,Cleared" bitfld.word 0x00 8. " PCM ,Clear Position-compare match interrupt flag" "No effect,Cleared" textline " " bitfld.word 0x00 7. " PCR ,Clear Position-compare ready interrupt flag" "No effect,Cleared" bitfld.word 0x00 6. " PCO ,Clear Position counter overflow interrupt flag" "No effect,Cleared" bitfld.word 0x00 5. " PCU ,Clear Position counter underflow interrupt flag" "No effect,Cleared" bitfld.word 0x00 4. " WTO ,Clear Watchdog time out interrupt flag" "No effect,Cleared" textline " " bitfld.word 0x00 3. " QDC ,Clear Quadrature direction change interrupt flag" "No effect,Cleared" bitfld.word 0x00 2. " PHE ,Clear Quadrature phase error interrupt flag" "No effect,Cleared" bitfld.word 0x00 1. " PCE ,Clear Position counter error interrupt flag" "No effect,Cleared" bitfld.word 0x00 0. " INT ,Global interrupt clear flag" "No effect,Cleared" line.word 0x02 "QFRC,eQEP Interrupt Force Register" bitfld.word 0x02 11. " UTO ,Force unit time out interrupt" "No effect,Forced" bitfld.word 0x02 10. " IEL ,Force index event latch interrupt" "No effect,Forced" bitfld.word 0x02 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced" bitfld.word 0x02 8. " PCM ,Force position-compare match interrupt" "No effect,Forced" textline " " bitfld.word 0x02 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced" bitfld.word 0x02 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced" bitfld.word 0x02 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced" bitfld.word 0x02 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced" textline " " bitfld.word 0x02 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced" bitfld.word 0x02 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced" bitfld.word 0x02 1. " PCE ,Force position counter error interrupt" "No effect,Forced" line.word 0x04 "QEPSTS,eQEP Status Register" eventfld.word 0x04 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" bitfld.word 0x04 6. " FDF ,Direction on the first index marker" "Counter-clockwise rot.,Clockwise rot." textline " " bitfld.word 0x04 5. " QDF ,Quadrature direction flag" "Counter-clockwise rot.,Clockwise rot." bitfld.word 0x04 4. " QDLF ,eQEP direction latch flag" "Counter-clockwise rot.,Clockwise rot." textline " " eventfld.word 0x04 3. " COEF ,Capture overflow error flag" "No error,Error" eventfld.word 0x04 2. " CDEF ,Capture direction error flag" "No error,Error" textline " " eventfld.word 0x04 1. " FIMF ,First index marker flag" "No error,Error" bitfld.word 0x04 0. " PCEF ,Position counter error flag" "No error,Error" line.word 0x06 "QCTMR,eQEP Capture Timer Register" line.word 0x08 "QCPRD,eQEP Capture Period Register" rgroup.word 0x3e++0x01 line.word 0x00 "QCTMRLAT,eQEP Capture Timer Latch Register" group.word 0x40++0x01 line.word 0x00 "QCPRDLAT,eQEP Capture Period Latch Register" rgroup.long 0x5c++0x03 line.long 0x00 "REVID,eQEP Revision ID Register" width 0xb tree.end tree.end tree.end tree.open "USB (Universal Serial Bus)" tree "USBSS" base ad:0x47400000 width 12. rgroup.long 0x00++0x03 line.long 0x00 "REVREG,Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "Legacy ASP or WTBU,Highlander 0.8,?..." hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "SYSCONFIG,SYSCONFIG Register" sif cpuis("DM814?DSP") bitfld.long 0x00 17. " USB1_D2_OCP_EN_N ,Active low clock enable for USB1_D2_OCP_CLK" "Enabled,Disabled" bitfld.long 0x00 16. " USB0_D2_OCP_EN_N ,Active low clock enable for USB1_D2_OCP_CLK" "Enabled,Disabled" textline " " endif bitfld.long 0x00 11. " USB0_OCP_CLK_EN ,Active low clock enable for usb0_ocp_clk" "Enabled,Disabled" bitfld.long 0x00 10. " PHY0_UTMI_CLK_EN ,Active low clock enable for phy0_utmi_clk" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " USB1_OCP_CLK_EN ,Active low clock enable for usb1_ocp_clk" "Enabled,Disabled" bitfld.long 0x00 8. " PHY1_UTMI_CLK_EN ,Active low clock enable for phy1_utmi_clk" "Enabled,Disabled" textline " " sif (cpuis("DM814?DSP")||cpuis("AM335*")||cpuis("AM387*")||cpuis("DRA62*")) bitfld.long 0x00 4.--5. " STANDBY_MODE ,Standby mode select" "Force-standby,No-standby,Smart-standby,Smart-standby wakeup capable" bitfld.long 0x00 2.--3. " IDLEMODE ,Idlemode select" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup capable" else bitfld.long 0x00 4.--5. " STANDBY_MODE ,Standby mode select" "Force-standby,Reserved,Smart-standby,Smart-standby wakeup capable" bitfld.long 0x00 2.--3. " IDLEMODE ,Idlemode select" "Reserved,Reserved,Smart-standby,Smart-standby wakeup capable" endif textline " " bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive" bitfld.long 0x00 0. " SOFT_RESET ,Software reset of USBSS USB0 and USB1 modules" "No reset,Reset" sif (!cpuis("AM335*")) group.long 0x20++0x3 line.long 0x00 "EOI,End of Interrupt Register" bitfld.long 0x00 0. " EOI_VECTOR ,End of interrupt for USBSS Interrupt" "Completed,Not completed" endif group.long 0x24++0xf line.long 0x00 "IRQSTATRAW,IRQ Status Raw Register" bitfld.long 0x00 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt" bitfld.long 0x00 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt" bitfld.long 0x00 8. " TX_PKT_CMP_0 ,USB0 Tx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " PD_CMP_FLAG ,Packet completed interrupt raw status" "No interrupt,Interrupt" bitfld.long 0x00 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt raw status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt raw status" "No interrupt,Interrupt" line.long 0x04 "IRQSTAT,IRQ Status Register" eventfld.long 0x04 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 8. " TX_PKT_CMP_0 ,IUSB0 Tx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 2. " PD_CMP_FLAG ,Packet completed interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt status" "No interrupt,Interrupt" line.long 0x08 "IRQENABLER,IRQ Enable Set Register" bitfld.long 0x08 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled" bitfld.long 0x08 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled" bitfld.long 0x08 8. " TX_PKT_CMP_0 ,IUSB0 Tx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled" textline " " bitfld.long 0x08 2. " PD_CMP_FLAG ,Packet completed interrupt enable status" "Disabled,Enabled" bitfld.long 0x08 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt enable status" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt enable status" "Disabled,Enabled" line.long 0x0c "IRQCLEARR,IRQ Enable Clear Register" eventfld.long 0x0c 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled" eventfld.long 0x0c 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled" textline " " eventfld.long 0x0c 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled" eventfld.long 0x0c 8. " TX_PKT_CMP_0 ,IUSB0 Tx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled" textline " " eventfld.long 0x0c 2. " PD_CMP_FLAG ,Packet completed interrupt disable status" "Disabled,Enabled" eventfld.long 0x0c 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt disable status" "Disabled,Enabled" textline " " eventfld.long 0x0c 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt disable status" "Disabled,Enabled" width 17. tree "DMA Thresholds" group.long 0x100++0x47 line.long (0x0+0x00) "IRQDMATHOLDTX00,IRQ DMA Threshold TX0 0 Register" hexmask.long.byte (0x0+0x00) 24.--31. 1. " DMA_THRES_TX0_3 ,Threshold value for USB0 endpoint 3" hexmask.long.byte (0x0+0x00) 16.--23. 1. " DMA_THRES_TX0_2 ,Threshold value for USB0 endpoint 2" textline " " hexmask.long.byte (0x0+0x00) 8.--15. 1. " DMA_THRES_TX0_1 ,Threshold value for USB0 endpoint 1" line.long (0x0+0x04) "IRQDMATHOLDTX01,IRQ DMA Threshold TX0 1 Register" hexmask.long.byte (0x0+0x04) 24.--31. 1. " DMA_THRES_TX0_7 ,Threshold value for USB0 endpoint 7" hexmask.long.byte (0x0+0x04) 16.--23. 1. " DMA_THRES_TX0_6 ,Threshold value for USB0 endpoint 6" textline " " hexmask.long.byte (0x0+0x04) 8.--15. 1. " DMA_THRES_TX0_5 ,Threshold value for USB0 endpoint 5" hexmask.long.byte (0x0+0x04) 0.--7. 1. " DMA_THRES_TX0_4 ,Threshold value for USB0 endpoint 4" line.long (0x0+0x08) "IRQDMATHOLDTX02,IRQ DMA Threshold TX0 2 Register" hexmask.long.byte (0x0+0x08) 24.--31. 1. " DMA_THRES_TX0_11 ,Threshold value for USB0 endpoint 11" hexmask.long.byte (0x0+0x08) 16.--23. 1. " DMA_THRES_TX0_10 ,Threshold value for USB0 endpoint 10" textline " " hexmask.long.byte (0x0+0x08) 8.--15. 1. " DMA_THRES_TX0_9 ,Threshold value for USB0 endpoint 9" hexmask.long.byte (0x0+0x08) 0.--7. 1. " DMA_THRES_TX0_8 ,Threshold value for USB0 endpoint 8" line.long (0x0+0x0C) "IRQDMATHOLDTX03,IRQ DMA Threshold TX0 3 Register" hexmask.long.byte (0x0+0x0C) 24.--31. 1. " DMA_THRES_TX0_15 ,Threshold value for USB0 endpoint 15" hexmask.long.byte (0x0+0x0C) 16.--23. 1. " DMA_THRES_TX0_14 ,Threshold value for USB0 endpoint 14" textline " " hexmask.long.byte (0x0+0x0C) 8.--15. 1. " DMA_THRES_TX0_13 ,Threshold value for USB0 endpoint 13" hexmask.long.byte (0x0+0x0C) 0.--7. 1. " DMA_THRES_TX0_12 ,Threshold value for USB0 endpoint 12" line.long (0x10+0x00) "IRQDMATHOLDRX00,IRQ DMA Threshold RX0 0 Register" hexmask.long.byte (0x10+0x00) 24.--31. 1. " DMA_THRES_RX0_3 ,Threshold value for USB0 endpoint 3" hexmask.long.byte (0x10+0x00) 16.--23. 1. " DMA_THRES_RX0_2 ,Threshold value for USB0 endpoint 2" textline " " hexmask.long.byte (0x10+0x00) 8.--15. 1. " DMA_THRES_RX0_1 ,Threshold value for USB0 endpoint 1" line.long (0x10+0x04) "IRQDMATHOLDRX01,IRQ DMA Threshold RX0 1 Register" hexmask.long.byte (0x10+0x04) 24.--31. 1. " DMA_THRES_RX0_7 ,Threshold value for USB0 endpoint 7" hexmask.long.byte (0x10+0x04) 16.--23. 1. " DMA_THRES_RX0_6 ,Threshold value for USB0 endpoint 6" textline " " hexmask.long.byte (0x10+0x04) 8.--15. 1. " DMA_THRES_RX0_5 ,Threshold value for USB0 endpoint 5" hexmask.long.byte (0x10+0x04) 0.--7. 1. " DMA_THRES_RX0_4 ,Threshold value for USB0 endpoint 4" line.long (0x10+0x08) "IRQDMATHOLDRX02,IRQ DMA Threshold RX0 2 Register" hexmask.long.byte (0x10+0x08) 24.--31. 1. " DMA_THRES_RX0_11 ,Threshold value for USB0 endpoint 11" hexmask.long.byte (0x10+0x08) 16.--23. 1. " DMA_THRES_RX0_10 ,Threshold value for USB0 endpoint 10" textline " " hexmask.long.byte (0x10+0x08) 8.--15. 1. " DMA_THRES_RX0_9 ,Threshold value for USB0 endpoint 9" hexmask.long.byte (0x10+0x08) 0.--7. 1. " DMA_THRES_RX0_8 ,Threshold value for USB0 endpoint 8" line.long (0x10+0x0C) "IRQDMATHOLDRX03,IRQ DMA Threshold RX0 3 Register" hexmask.long.byte (0x10+0x0C) 24.--31. 1. " DMA_THRES_RX0_15 ,Threshold value for USB0 endpoint 15" hexmask.long.byte (0x10+0x0C) 16.--23. 1. " DMA_THRES_RX0_14 ,Threshold value for USB0 endpoint 14" textline " " hexmask.long.byte (0x10+0x0C) 8.--15. 1. " DMA_THRES_RX0_13 ,Threshold value for USB0 endpoint 13" hexmask.long.byte (0x10+0x0C) 0.--7. 1. " DMA_THRES_RX0_12 ,Threshold value for USB0 endpoint 12" line.long (0x20+0x00) "IRQDMATHOLDTX10,IRQ DMA Threshold TX1 0 Register" hexmask.long.byte (0x20+0x00) 24.--31. 1. " DMA_THRES_TX1_3 ,Threshold value for USB1 endpoint 3" hexmask.long.byte (0x20+0x00) 16.--23. 1. " DMA_THRES_TX1_2 ,Threshold value for USB1 endpoint 2" textline " " hexmask.long.byte (0x20+0x00) 8.--15. 1. " DMA_THRES_TX1_1 ,Threshold value for USB1 endpoint 1" line.long (0x20+0x04) "IRQDMATHOLDTX11,IRQ DMA Threshold TX1 1 Register" hexmask.long.byte (0x20+0x04) 24.--31. 1. " DMA_THRES_TX1_7 ,Threshold value for USB1 endpoint 7" hexmask.long.byte (0x20+0x04) 16.--23. 1. " DMA_THRES_TX1_6 ,Threshold value for USB1 endpoint 6" textline " " hexmask.long.byte (0x20+0x04) 8.--15. 1. " DMA_THRES_TX1_5 ,Threshold value for USB1 endpoint 5" hexmask.long.byte (0x20+0x04) 0.--7. 1. " DMA_THRES_TX1_4 ,Threshold value for USB1 endpoint 4" line.long (0x20+0x08) "IRQDMATHOLDTX12,IRQ DMA Threshold TX1 2 Register" hexmask.long.byte (0x20+0x08) 24.--31. 1. " DMA_THRES_TX1_11 ,Threshold value for USB1 endpoint 11" hexmask.long.byte (0x20+0x08) 16.--23. 1. " DMA_THRES_TX1_10 ,Threshold value for USB1 endpoint 10" textline " " hexmask.long.byte (0x20+0x08) 8.--15. 1. " DMA_THRES_TX1_9 ,Threshold value for USB1 endpoint 9" hexmask.long.byte (0x20+0x08) 0.--7. 1. " DMA_THRES_TX1_8 ,Threshold value for USB1 endpoint 8" line.long (0x20+0x0C) "IRQDMATHOLDTX13,IRQ DMA Threshold TX1 3 Register" hexmask.long.byte (0x20+0x0C) 24.--31. 1. " DMA_THRES_TX1_15 ,Threshold value for USB1 endpoint 15" hexmask.long.byte (0x20+0x0C) 16.--23. 1. " DMA_THRES_TX1_14 ,Threshold value for USB1 endpoint 14" textline " " hexmask.long.byte (0x20+0x0C) 8.--15. 1. " DMA_THRES_TX1_13 ,Threshold value for USB1 endpoint 13" hexmask.long.byte (0x20+0x0C) 0.--7. 1. " DMA_THRES_TX1_12 ,Threshold value for USB1 endpoint 12" line.long (0x30+0x00) "IRQDMATHOLDRX10,IRQ DMA Threshold RX1 0 Register" hexmask.long.byte (0x30+0x00) 24.--31. 1. " DMA_THRES_RX1_3 ,Threshold value for USB1 endpoint 3" hexmask.long.byte (0x30+0x00) 16.--23. 1. " DMA_THRES_RX1_2 ,Threshold value for USB1 endpoint 2" textline " " hexmask.long.byte (0x30+0x00) 8.--15. 1. " DMA_THRES_RX1_1 ,Threshold value for USB1 endpoint 1" line.long (0x30+0x04) "IRQDMATHOLDRX11,IRQ DMA Threshold RX1 1 Register" hexmask.long.byte (0x30+0x04) 24.--31. 1. " DMA_THRES_RX1_7 ,Threshold value for USB1 endpoint 7" hexmask.long.byte (0x30+0x04) 16.--23. 1. " DMA_THRES_RX1_6 ,Threshold value for USB1 endpoint 6" textline " " hexmask.long.byte (0x30+0x04) 8.--15. 1. " DMA_THRES_RX1_5 ,Threshold value for USB1 endpoint 5" hexmask.long.byte (0x30+0x04) 0.--7. 1. " DMA_THRES_RX1_4 ,Threshold value for USB1 endpoint 4" line.long (0x30+0x08) "IRQDMATHOLDRX12,IRQ DMA Threshold RX1 2 Register" hexmask.long.byte (0x30+0x08) 24.--31. 1. " DMA_THRES_RX1_11 ,Threshold value for USB1 endpoint 11" hexmask.long.byte (0x30+0x08) 16.--23. 1. " DMA_THRES_RX1_10 ,Threshold value for USB1 endpoint 10" textline " " hexmask.long.byte (0x30+0x08) 8.--15. 1. " DMA_THRES_RX1_9 ,Threshold value for USB1 endpoint 9" hexmask.long.byte (0x30+0x08) 0.--7. 1. " DMA_THRES_RX1_8 ,Threshold value for USB1 endpoint 8" line.long (0x30+0x0C) "IRQDMATHOLDRX13,IRQ DMA Threshold RX1 3 Register" hexmask.long.byte (0x30+0x0C) 24.--31. 1. " DMA_THRES_RX1_15 ,Threshold value for USB1 endpoint 15" hexmask.long.byte (0x30+0x0C) 16.--23. 1. " DMA_THRES_RX1_14 ,Threshold value for USB1 endpoint 14" textline " " hexmask.long.byte (0x30+0x0C) 8.--15. 1. " DMA_THRES_RX1_13 ,Threshold value for USB1 endpoint 13" hexmask.long.byte (0x30+0x0C) 0.--7. 1. " DMA_THRES_RX1_12 ,Threshold value for USB1 endpoint 12" line.long 0x40 "IRQDMAENABLE0,IRQ DMA Enable 0 Register" bitfld.long 0x40 31. " DMA_EN_RX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled" sif (!cpuis("AM335*")) bitfld.long 0x40 30. " DMA_EN_RX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled" bitfld.long 0x40 29. " DMA_EN_RX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled" textline " " bitfld.long 0x40 28. " DMA_EN_RX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled" bitfld.long 0x40 27. " DMA_EN_RX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled" bitfld.long 0x40 26. " DMA_EN_RX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled" textline " " bitfld.long 0x40 25. " DMA_EN_RX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled" bitfld.long 0x40 24. " DMA_EN_RX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled" bitfld.long 0x40 23. " DMA_EN_RX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled" textline " " bitfld.long 0x40 22. " DMA_EN_RX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled" bitfld.long 0x40 21. " DMA_EN_RX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled" bitfld.long 0x40 20. " DMA_EN_RX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled" textline " " bitfld.long 0x40 19. " DMA_EN_RX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled" bitfld.long 0x40 18. " DMA_EN_RX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled" endif bitfld.long 0x40 17. " DMA_EN_RX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled" textline " " bitfld.long 0x40 15. " DMA_EN_TX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled" sif (!cpuis("AM335*")) bitfld.long 0x40 14. " DMA_EN_TX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled" bitfld.long 0x40 13. " DMA_EN_TX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled" textline " " bitfld.long 0x40 12. " DMA_EN_TX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled" bitfld.long 0x40 11. " DMA_EN_TX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled" bitfld.long 0x40 10. " DMA_EN_TX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled" textline " " bitfld.long 0x40 9. " DMA_EN_TX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled" bitfld.long 0x40 8. " DMA_EN_TX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled" bitfld.long 0x40 7. " DMA_EN_TX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled" textline " " bitfld.long 0x40 6. " DMA_EN_TX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled" bitfld.long 0x40 5. " DMA_EN_TX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled" bitfld.long 0x40 4. " DMA_EN_TX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled" textline " " bitfld.long 0x40 3. " DMA_EN_TX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled" endif bitfld.long 0x40 2. " DMA_EN_TX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled" sif (cpuis("AM335*")) bitfld.long 0x40 0. " DMA_EN_TX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled" else bitfld.long 0x40 1. " DMA_EN_TX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled" endif line.long 0x44 "IRQDMAENABLE1,IRQ DMA Enable 1 Register" bitfld.long 0x44 31. " DMA_EN_RX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled" sif (!cpuis("AM335*")) bitfld.long 0x44 30. " DMA_EN_RX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled" bitfld.long 0x44 29. " DMA_EN_RX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled" textline " " bitfld.long 0x44 28. " DMA_EN_RX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled" bitfld.long 0x44 27. " DMA_EN_RX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled" bitfld.long 0x44 26. " DMA_EN_RX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled" textline " " bitfld.long 0x44 25. " DMA_EN_RX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled" bitfld.long 0x44 24. " DMA_EN_RX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled" bitfld.long 0x44 23. " DMA_EN_RX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled" textline " " bitfld.long 0x44 22. " DMA_EN_RX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled" bitfld.long 0x44 21. " DMA_EN_RX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled" bitfld.long 0x44 20. " DMA_EN_RX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled" textline " " bitfld.long 0x44 19. " DMA_EN_RX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled" bitfld.long 0x44 18. " DMA_EN_RX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled" endif bitfld.long 0x44 17. " DMA_EN_RX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled" textline " " bitfld.long 0x44 15. " DMA_EN_TX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled" sif (!cpuis("AM335*")) bitfld.long 0x44 14. " DMA_EN_TX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled" bitfld.long 0x44 13. " DMA_EN_TX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled" textline " " bitfld.long 0x44 12. " DMA_EN_TX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled" bitfld.long 0x44 11. " DMA_EN_TX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled" bitfld.long 0x44 10. " DMA_EN_TX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled" textline " " bitfld.long 0x44 9. " DMA_EN_TX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled" bitfld.long 0x44 8. " DMA_EN_TX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled" bitfld.long 0x44 7. " DMA_EN_TX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled" textline " " bitfld.long 0x44 6. " DMA_EN_TX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled" bitfld.long 0x44 5. " DMA_EN_TX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled" bitfld.long 0x44 4. " DMA_EN_TX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled" textline " " bitfld.long 0x44 3. " DMA_EN_TX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled" bitfld.long 0x44 2. " DMA_EN_TX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled" endif bitfld.long 0x44 1. " DMA_EN_TX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled" tree.end tree "FRAME Thresholds" group.long 0x200++0x47 line.long (0x0+0x00) "IRQFRAMETHOLDTX00,IRQ FRAME Threshold TX0 0 Register" hexmask.long.byte (0x0+0x00) 24.--31. 1. " FRAME_THRES_TX0_3 ,Threshold value for USB0 endpoint 3" hexmask.long.byte (0x0+0x00) 16.--23. 1. " FRAME_THRES_TX0_2 ,Threshold value for USB0 endpoint 2" textline " " hexmask.long.byte (0x0+0x00) 8.--15. 1. " FRAME_THRES_TX0_1 ,Threshold value for USB0 endpoint 1" line.long (0x0+0x04) "IRQFRAMETHOLDTX01,IRQ FRAME Threshold TX0 1 Register" hexmask.long.byte (0x0+0x04) 24.--31. 1. " FRAME_THRES_TX0_7 ,Threshold value for USB0 endpoint 7" hexmask.long.byte (0x0+0x04) 16.--23. 1. " FRAME_THRES_TX0_6 ,Threshold value for USB0 endpoint 6" textline " " hexmask.long.byte (0x0+0x04) 8.--15. 1. " FRAME_THRES_TX0_5 ,Threshold value for USB0 endpoint 5" hexmask.long.byte (0x0+0x04) 0.--7. 1. " FRAME_THRES_TX0_4 ,Threshold value for USB0 endpoint 4" line.long (0x0+0x08) "IRQFRAMETHOLDTX02,IRQ FRAME Threshold TX0 2 Register" hexmask.long.byte (0x0+0x08) 24.--31. 1. " FRAME_THRES_TX0_11 ,Threshold value for USB0 endpoint 11" hexmask.long.byte (0x0+0x08) 16.--23. 1. " FRAME_THRES_TX0_10 ,Threshold value for USB0 endpoint 10" textline " " hexmask.long.byte (0x0+0x08) 8.--15. 1. " FRAME_THRES_TX0_9 ,Threshold value for USB0 endpoint 9" hexmask.long.byte (0x0+0x08) 0.--7. 1. " FRAME_THRES_TX0_8 ,Threshold value for USB0 endpoint 8" line.long (0x0+0x0C) "IRQFRAMETHOLDTX03,IRQ FRAME Threshold TX0 3 Register" hexmask.long.byte (0x0+0x0C) 24.--31. 1. " FRAME_THRES_TX0_15 ,Threshold value for USB0 endpoint 15" hexmask.long.byte (0x0+0x0C) 16.--23. 1. " FRAME_THRES_TX0_14 ,Threshold value for USB0 endpoint 14" textline " " hexmask.long.byte (0x0+0x0C) 8.--15. 1. " FRAME_THRES_TX0_13 ,Threshold value for USB0 endpoint 13" hexmask.long.byte (0x0+0x0C) 0.--7. 1. " FRAME_THRES_TX0_12 ,Threshold value for USB0 endpoint 12" line.long (0x10+0x00) "IRQFRAMETHOLDRX00,IRQ FRAME Threshold RX0 0 Register" hexmask.long.byte (0x10+0x00) 24.--31. 1. " FRAME_THRES_RX0_3 ,Threshold value for USB0 endpoint 3" hexmask.long.byte (0x10+0x00) 16.--23. 1. " FRAME_THRES_RX0_2 ,Threshold value for USB0 endpoint 2" textline " " hexmask.long.byte (0x10+0x00) 8.--15. 1. " FRAME_THRES_RX0_1 ,Threshold value for USB0 endpoint 1" line.long (0x10+0x04) "IRQFRAMETHOLDRX01,IRQ FRAME Threshold RX0 1 Register" hexmask.long.byte (0x10+0x04) 24.--31. 1. " FRAME_THRES_RX0_7 ,Threshold value for USB0 endpoint 7" hexmask.long.byte (0x10+0x04) 16.--23. 1. " FRAME_THRES_RX0_6 ,Threshold value for USB0 endpoint 6" textline " " hexmask.long.byte (0x10+0x04) 8.--15. 1. " FRAME_THRES_RX0_5 ,Threshold value for USB0 endpoint 5" hexmask.long.byte (0x10+0x04) 0.--7. 1. " FRAME_THRES_RX0_4 ,Threshold value for USB0 endpoint 4" line.long (0x10+0x08) "IRQFRAMETHOLDRX02,IRQ FRAME Threshold RX0 2 Register" hexmask.long.byte (0x10+0x08) 24.--31. 1. " FRAME_THRES_RX0_11 ,Threshold value for USB0 endpoint 11" hexmask.long.byte (0x10+0x08) 16.--23. 1. " FRAME_THRES_RX0_10 ,Threshold value for USB0 endpoint 10" textline " " hexmask.long.byte (0x10+0x08) 8.--15. 1. " FRAME_THRES_RX0_9 ,Threshold value for USB0 endpoint 9" hexmask.long.byte (0x10+0x08) 0.--7. 1. " FRAME_THRES_RX0_8 ,Threshold value for USB0 endpoint 8" line.long (0x10+0x0C) "IRQFRAMETHOLDRX03,IRQ FRAME Threshold RX0 3 Register" hexmask.long.byte (0x10+0x0C) 24.--31. 1. " FRAME_THRES_RX0_15 ,Threshold value for USB0 endpoint 15" hexmask.long.byte (0x10+0x0C) 16.--23. 1. " FRAME_THRES_RX0_14 ,Threshold value for USB0 endpoint 14" textline " " hexmask.long.byte (0x10+0x0C) 8.--15. 1. " FRAME_THRES_RX0_13 ,Threshold value for USB0 endpoint 13" hexmask.long.byte (0x10+0x0C) 0.--7. 1. " FRAME_THRES_RX0_12 ,Threshold value for USB0 endpoint 12" line.long (0x20+0x00) "IRQFRAMETHOLDTX10,IRQ FRAME Threshold TX1 0 Register" hexmask.long.byte (0x20+0x00) 24.--31. 1. " FRAME_THRES_TX1_3 ,Threshold value for USB1 endpoint 3" hexmask.long.byte (0x20+0x00) 16.--23. 1. " FRAME_THRES_TX1_2 ,Threshold value for USB1 endpoint 2" textline " " hexmask.long.byte (0x20+0x00) 8.--15. 1. " FRAME_THRES_TX1_1 ,Threshold value for USB1 endpoint 1" line.long (0x20+0x04) "IRQFRAMETHOLDTX11,IRQ FRAME Threshold TX1 1 Register" hexmask.long.byte (0x20+0x04) 24.--31. 1. " FRAME_THRES_TX1_7 ,Threshold value for USB1 endpoint 7" hexmask.long.byte (0x20+0x04) 16.--23. 1. " FRAME_THRES_TX1_6 ,Threshold value for USB1 endpoint 6" textline " " hexmask.long.byte (0x20+0x04) 8.--15. 1. " FRAME_THRES_TX1_5 ,Threshold value for USB1 endpoint 5" hexmask.long.byte (0x20+0x04) 0.--7. 1. " FRAME_THRES_TX1_4 ,Threshold value for USB1 endpoint 4" line.long (0x20+0x08) "IRQFRAMETHOLDTX12,IRQ FRAME Threshold TX1 2 Register" hexmask.long.byte (0x20+0x08) 24.--31. 1. " FRAME_THRES_TX1_11 ,Threshold value for USB1 endpoint 11" hexmask.long.byte (0x20+0x08) 16.--23. 1. " FRAME_THRES_TX1_10 ,Threshold value for USB1 endpoint 10" textline " " hexmask.long.byte (0x20+0x08) 8.--15. 1. " FRAME_THRES_TX1_9 ,Threshold value for USB1 endpoint 9" hexmask.long.byte (0x20+0x08) 0.--7. 1. " FRAME_THRES_TX1_8 ,Threshold value for USB1 endpoint 8" line.long (0x20+0x0C) "IRQFRAMETHOLDTX13,IRQ FRAME Threshold TX1 3 Register" hexmask.long.byte (0x20+0x0C) 24.--31. 1. " FRAME_THRES_TX1_15 ,Threshold value for USB1 endpoint 15" hexmask.long.byte (0x20+0x0C) 16.--23. 1. " FRAME_THRES_TX1_14 ,Threshold value for USB1 endpoint 14" textline " " hexmask.long.byte (0x20+0x0C) 8.--15. 1. " FRAME_THRES_TX1_13 ,Threshold value for USB1 endpoint 13" hexmask.long.byte (0x20+0x0C) 0.--7. 1. " FRAME_THRES_TX1_12 ,Threshold value for USB1 endpoint 12" line.long (0x30+0x00) "IRQFRAMETHOLDRX10,IRQ FRAME Threshold RX1 0 Register" hexmask.long.byte (0x30+0x00) 24.--31. 1. " FRAME_THRES_RX1_3 ,Threshold value for USB1 endpoint 3" hexmask.long.byte (0x30+0x00) 16.--23. 1. " FRAME_THRES_RX1_2 ,Threshold value for USB1 endpoint 2" textline " " hexmask.long.byte (0x30+0x00) 8.--15. 1. " FRAME_THRES_RX1_1 ,Threshold value for USB1 endpoint 1" line.long (0x30+0x04) "IRQFRAMETHOLDRX11,IRQ FRAME Threshold RX1 1 Register" hexmask.long.byte (0x30+0x04) 24.--31. 1. " FRAME_THRES_RX1_7 ,Threshold value for USB1 endpoint 7" hexmask.long.byte (0x30+0x04) 16.--23. 1. " FRAME_THRES_RX1_6 ,Threshold value for USB1 endpoint 6" textline " " hexmask.long.byte (0x30+0x04) 8.--15. 1. " FRAME_THRES_RX1_5 ,Threshold value for USB1 endpoint 5" hexmask.long.byte (0x30+0x04) 0.--7. 1. " FRAME_THRES_RX1_4 ,Threshold value for USB1 endpoint 4" line.long (0x30+0x08) "IRQFRAMETHOLDRX12,IRQ FRAME Threshold RX1 2 Register" hexmask.long.byte (0x30+0x08) 24.--31. 1. " FRAME_THRES_RX1_11 ,Threshold value for USB1 endpoint 11" hexmask.long.byte (0x30+0x08) 16.--23. 1. " FRAME_THRES_RX1_10 ,Threshold value for USB1 endpoint 10" textline " " hexmask.long.byte (0x30+0x08) 8.--15. 1. " FRAME_THRES_RX1_9 ,Threshold value for USB1 endpoint 9" hexmask.long.byte (0x30+0x08) 0.--7. 1. " FRAME_THRES_RX1_8 ,Threshold value for USB1 endpoint 8" line.long (0x30+0x0C) "IRQFRAMETHOLDRX13,IRQ FRAME Threshold RX1 3 Register" hexmask.long.byte (0x30+0x0C) 24.--31. 1. " FRAME_THRES_RX1_15 ,Threshold value for USB1 endpoint 15" hexmask.long.byte (0x30+0x0C) 16.--23. 1. " FRAME_THRES_RX1_14 ,Threshold value for USB1 endpoint 14" textline " " hexmask.long.byte (0x30+0x0C) 8.--15. 1. " FRAME_THRES_RX1_13 ,Threshold value for USB1 endpoint 13" hexmask.long.byte (0x30+0x0C) 0.--7. 1. " FRAME_THRES_RX1_12 ,Threshold value for USB1 endpoint 12" line.long 0x40 "IRQFRAMEENABLE0,IRQ FRAME Enable 0 Register" bitfld.long 0x40 31. " FRAME_EN_RX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled" sif (!cpuis("AM335*")) bitfld.long 0x40 30. " FRAME_EN_RX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled" bitfld.long 0x40 29. " FRAME_EN_RX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled" textline " " bitfld.long 0x40 28. " FRAME_EN_RX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled" bitfld.long 0x40 27. " FRAME_EN_RX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled" bitfld.long 0x40 26. " FRAME_EN_RX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled" textline " " bitfld.long 0x40 25. " FRAME_EN_RX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled" bitfld.long 0x40 24. " FRAME_EN_RX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled" bitfld.long 0x40 23. " FRAME_EN_RX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled" textline " " bitfld.long 0x40 22. " FRAME_EN_RX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled" bitfld.long 0x40 21. " FRAME_EN_RX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled" bitfld.long 0x40 20. " FRAME_EN_RX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled" textline " " bitfld.long 0x40 19. " FRAME_EN_RX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled" bitfld.long 0x40 18. " FRAME_EN_RX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled" endif bitfld.long 0x40 17. " FRAME_EN_RX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled" textline " " bitfld.long 0x40 15. " FRAME_EN_TX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled" sif (!cpuis("AM335*")) bitfld.long 0x40 14. " FRAME_EN_TX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled" bitfld.long 0x40 13. " FRAME_EN_TX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled" textline " " bitfld.long 0x40 12. " FRAME_EN_TX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled" bitfld.long 0x40 11. " FRAME_EN_TX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled" bitfld.long 0x40 10. " FRAME_EN_TX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled" textline " " bitfld.long 0x40 9. " FRAME_EN_TX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled" bitfld.long 0x40 8. " FRAME_EN_TX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled" bitfld.long 0x40 7. " FRAME_EN_TX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled" textline " " bitfld.long 0x40 6. " FRAME_EN_TX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled" bitfld.long 0x40 5. " FRAME_EN_TX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled" bitfld.long 0x40 4. " FRAME_EN_TX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled" textline " " bitfld.long 0x40 3. " FRAME_EN_TX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled" bitfld.long 0x40 2. " FRAME_EN_TX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled" endif bitfld.long 0x40 1. " FRAME_EN_TX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled" line.long 0x44 "IRQFRAMEENABLE1,IRQ FRAME Enable 1 Register" bitfld.long 0x44 31. " FRAME_EN_RX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled" sif (!cpuis("AM335*")) bitfld.long 0x44 30. " FRAME_EN_RX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled" bitfld.long 0x44 29. " FRAME_EN_RX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled" textline " " bitfld.long 0x44 28. " FRAME_EN_RX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled" bitfld.long 0x44 27. " FRAME_EN_RX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled" bitfld.long 0x44 26. " FRAME_EN_RX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled" textline " " bitfld.long 0x44 25. " FRAME_EN_RX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled" bitfld.long 0x44 24. " FRAME_EN_RX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled" bitfld.long 0x44 23. " FRAME_EN_RX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled" textline " " bitfld.long 0x44 22. " FRAME_EN_RX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled" bitfld.long 0x44 21. " FRAME_EN_RX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled" bitfld.long 0x44 20. " FRAME_EN_RX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled" textline " " bitfld.long 0x44 19. " FRAME_EN_RX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled" bitfld.long 0x44 18. " FRAME_EN_RX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled" endif bitfld.long 0x44 17. " FRAME_EN_RX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled" textline " " bitfld.long 0x44 15. " FRAME_EN_TX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled" sif (!cpuis("AM335*")) bitfld.long 0x44 14. " FRAME_EN_TX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled" bitfld.long 0x44 13. " FRAME_EN_TX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled" textline " " bitfld.long 0x44 12. " FRAME_EN_TX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled" bitfld.long 0x44 11. " FRAME_EN_TX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled" bitfld.long 0x44 10. " FRAME_EN_TX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled" textline " " bitfld.long 0x44 9. " FRAME_EN_TX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled" bitfld.long 0x44 8. " FRAME_EN_TX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled" bitfld.long 0x44 7. " FRAME_EN_TX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled" textline " " bitfld.long 0x44 6. " FRAME_EN_TX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled" bitfld.long 0x44 5. " FRAME_EN_TX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled" bitfld.long 0x44 4. " FRAME_EN_TX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled" textline " " bitfld.long 0x44 3. " FRAME_EN_TX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled" bitfld.long 0x44 2. " FRAME_EN_TX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled" endif bitfld.long 0x44 1. " FRAME_EN_TX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled" tree.end width 11. tree.end tree "USB_PHY" tree "USB0PHY" base ad:0x47401300 width 30. group.long 0x0++0x3 line.long 0x00 "TERMINATION_CONTROL,Contains bits related to control of terminations in USBPHY" bitfld.long 0x00 29. " ALWAYS_UPDATE ,When set to 1, the calibration code is updated immediately after a code computation without waiting for idle periods." "0,1" bitfld.long 0x00 28. " RTERM_CAL_DONE ,Rterm calibration is done. First time cal is done this bit gets set and gets reset at a restart cal" "0,1" bitfld.long 0x00 24.--27. " FS_CODE_SEL ,FS Code selection control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " USE_RTERM_RMX_REG ,Override termination resistor trim code with RTERM_RMX from this register" "0,1" hexmask.long.byte 0x00 14.--20. 1. " RTERM_RMX ,When read, this field returns the current Termination resistor trim code The value written to this field is used as Termination resistor trim code if bit 21 is set to 1" bitfld.long 0x00 11.--13. " HS_CODE_SEL ,HS Code selection control. A higher positive value" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 10. " RTERM_COMP_OUT ,Master loop comparator output" "0,1" bitfld.long 0x00 9. " RESTART_RTERM_CAL ,Restart the rterm calibration. the calibration restarts on any toggle 0-1 or 1-0 on this bit." "0,1" bitfld.long 0x00 8. " DISABLE_TEMP_TRACK ,Disables the temperature tracking function of the termination calibration" "0,1" textline " " bitfld.long 0x00 7. " USE_RTERM_CAL_REG ,When 1, the rterm cal code is overridden by values in RTERM_CAL" "0,1" hexmask.long.byte 0x00 0.--6. 1. " RTERM_CAL ,When read this field returns the current rterm calibration code The value written to this filed is used as rterm calibration code if the bit USE_RTERM_CAL_REG is 1." group.long 0x4++0x3 line.long 0x00 "RX_CALIB,Contains bits related to RX calibration" bitfld.long 0x00 31. " RESTART_HSRX_CAL ,Restart the HSRX calibration state machine when this bit goes from 0 to 1." "0,1" bitfld.long 0x00 30. " USE_HS_OFF_REG ,Override HS offset correction with HS_OFF_CODE" "No override,Override" bitfld.long 0x00 24.--29. " HS_OFF_CODE ,HS offset code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 23. " HSRX_COMP_OUT ,HSRX comparator output" "0,1" bitfld.long 0x00 22. " HSRX_CAL_DONE ,HSRX calibration done" "Not done,Done" bitfld.long 0x00 21. " USE_SQ_OFF_DAC1 ,Override Squelch offset DAC1" "No override,Override" textline " " bitfld.long 0x00 15.--20. " SQ_OFF_CODE_DAC1 ,When read returns current Sq offset code for DAC1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14. " USE_SQ_OFF_DAC2 ,Override Squelch offset DAC2 code when '1'" "0,1" bitfld.long 0x00 9.--13. " SQ_OFF_CODE_DAC2 ,When read returns current Sq offset code for DAC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8. " USE_SQ_OFF_DAC3 ,Override Squelch offset DAC3 code when 1" "0,1" bitfld.long 0x00 3.--7. " SQ_OFF_CODE_DAC3 ,When read returns current Sq offset code for DAC3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " SQ_COMP_OUT ,Sq comp output" "0,1" textline " " bitfld.long 0x00 1. " SQ_CAL_DONE ,Sq calibration " "0,1" bitfld.long 0x00 0. " RESTART_SQ_CAL ,Restart cycles" "No restart,Restart" group.long 0x8++0x3 line.long 0x00 "DLLHS_2,Second DLLHS control register" hexmask.long.byte 0x00 24.--31. 1. " DLLHS_CNTRL_LDO ,DLLHS controll LDO" hexmask.long.byte 0x00 16.--23. 1. " DLLHS_STATUS_LDO ,DLLHS status LDO" bitfld.long 0x00 4. " LINESTATE_DEBOUNCE_EN ,Enables the linestate debounce filter" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " LINESTATE_DEBOUNCE_CNTL ,Used for control of the linestate debounce filter when going from syncronous to async linestate." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC++0x3 line.long 0x00 "RX_TEST_2,Second receiver test register" bitfld.long 0x00 31. " HSOSREVERSAL ,Swaps the dataout from HSOS" "0,1" bitfld.long 0x00 30. " HSOSBITINVERSION ,Inverts the HSOS bits" "0,1" bitfld.long 0x00 29. " PHYCLKOUTINVERSION ,This inverts the phase for the PHYCLKOUT" "0,1" textline " " bitfld.long 0x00 28. " RXPIDERR ,Flags if the RX data packet has PID error. NOT IMPLEMENTED." "0,1" bitfld.long 0x00 27. " USEINTDATAOUT ,This will bypass the analog and will send data packet to controller incase of receiver (Faking the receive data). data used will be INTDATAOUTREG" "0,1" hexmask.long.word 0x00 11.--26. 1. " INTDATAOUTREG ,This register will be loaded through OCP and this data will be given to the controller if USEINTDATAOUT is set to 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " CDR_TESTOUT ,CDR debug bits" sif (!cpuis("AM335*")) group.long 0x10++0x3 line.long 0x00 "TX_TEST_CHRG_DET,TX test register" bitfld.long 0x00 31. " TXSYNCERR ,Sync error on TX data. NOT IMPLEMENTED." "0,1" hexmask.long.word 0x00 15.--30. 1. " UTMIDATATX ,Stores Last 2 byte of transmit data coming from the controller" bitfld.long 0x00 13. " TXPIDERR ,Flags if the TX packet has PID error. NOT IMPLEMENTED." "0,1" textline " " bitfld.long 0x00 12. " USE_CHGDET_DPDMSW ,Use bits 11:8 as override bits" "0,1" bitfld.long 0x00 11. " CHGDET_DPSW0EN ,Overrides the same named A/D interface signal for the charger detect block" "0,1" bitfld.long 0x00 10. " CHGDET_DPSW1EN ,Overrides the same named A/D interface signal for the charger detect block. Read value is valid only if VCHGLDO is on." "0,1" textline " " bitfld.long 0x00 9. " CHGDET_DMSW0EN ,Overrides the same named A/D interface signal for the charger detect block. Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 8. " CHGDET_DMSW1EN ,Overrides the same named A/D interface signal for the charger detect block..Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 6. " RDPPDCHGDETEN ,When set to 1 connects a 15K (+/- 30%) pulldown resistor on DP. Read value is valid only if VCHGLDO is on." "0,1" textline " " bitfld.long 0x00 5. " RDMPDCHGDETEN ,When set to 1 connects a 15K (+/- 30%) pulldown resistor on DM. Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 4. " RDPPUCHGDETEN ,When set to 1 connects a 150K (+/- 30%) pullup resistor on DP. Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 3. " RDMPUCHGDETEN ,When set to 1 connects a 150K (+/- 30%) pullup resistor on DM. Read value is valid only if VCHGLDO is on." "0,1" textline " " bitfld.long 0x00 2. " USE_CHG_DET_PU_REG ,Use bits 4:3 from this register" "0,1" bitfld.long 0x00 1. " USE_CHG_DET_PD_REG ,Use bits 6:5 from this register." "0,1" endif group.long 0x14++0x3 line.long 0x00 "CHRG_DET,This is the charger detect register" bitfld.long 0x00 29. " USE_CHG_DET_REG ,Use bits 28:24 and 18:17 from this register" "0,1" bitfld.long 0x00 28. " DIS_CHG_DET ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 27. " SRC_ON_DM ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" textline " " bitfld.long 0x00 26. " SINK_ON_DP ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 25. " CHG_DET_EXT_CTL ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 24. " RESTART_CHG_DET ,Restart the charger detection protocol when this goes from 0 to 1" "0,1" textline " " bitfld.long 0x00 23. " CHG_DET_DONE ,Charger detect protocol has completed" "0,1" bitfld.long 0x00 22. " CHG_DETECTED ,Same signal as CE pin" "0,1" bitfld.long 0x00 21. " DATA_DET ,Output of the data det comparator" "0,1" textline " " bitfld.long 0x00 18. " CHG_ISINK_EN ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 17. " CHG_VSRC_EN ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 16. " COMP_DP ,Comparator on the DP line value" "0,1" textline " " bitfld.long 0x00 15. " COMP_DM ,Comparator on the DM line value" "0,1" bitfld.long 0x00 13.--14. " CHG_DET_OSC_CNTRL ,Charger detect osc control" "0,1,2,3" bitfld.long 0x00 7.--12. " CHG_DET_TIMER ,Charger detect timer control." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 3.--4. " CHG_DET_ICTRL ,Charger detect current control" "0,1,2,3" bitfld.long 0x00 1.--2. " CHG_DET_VCTRL ,Charger detect voltage buffer control" "0,1,2,3" bitfld.long 0x00 0. " FOR_CE ,Force CE = 1 when this bit is set" "0,1" group.long 0x18++0x3 line.long 0x00 "PWR_CNTL,Includes all the power control bits" bitfld.long 0x00 31. " RESETDONETCLK ,Goes high when the RESET is synchronized to TCLK" "0,1" bitfld.long 0x00 30. " RESET_DONE_VMAIN ,Goes high when LDO domain is up, PLL LOCK is available, and utmi_reset is deasserted." "0,1" bitfld.long 0x00 29. " VMAIN_GLOBAL_RESET_DONE ,Goes high when LDO domain is up and PLL LOCK is available." "0,1" textline " " bitfld.long 0x00 28. " RESETDONEMCLK ,Goes high when the RESET is synchronized to MCLK" "0,1" bitfld.long 0x00 27. " RESETDONE_CHGDET ,Goes high when the RESET is synchronized to charger detect oscillator clock domain" "0,1" hexmask.long.word 0x00 12.--26. 1. " LDOPWRCOUNTER ,This is the value of the counter used for LDO power up. RESET to default." textline " " bitfld.long 0x00 11. " FORCEPLLSLOWCLK ,Forces the PLL to the slow clk mode" "0,1" bitfld.long 0x00 10. " FORCELDOON ,Forces the LDO to be ON." "0,1" bitfld.long 0x00 9. " FORCEPLLON ,Forces the PLL to be ON." "0,1" textline " " bitfld.long 0x00 6. " PLLLOCK ,Lock signal from the PLL" "0,1" bitfld.long 0x00 5. " USEPLLLOCK ,Indicate to the Phy" "0,1" bitfld.long 0x00 4. " USE_DATAPOLARITYN_REG ,1 - use bit 3 as override for the DATAPOLARITYN signal." "0,1" textline " " bitfld.long 0x00 3. " DATAPOLARITYN ,Override value of datapolarityn" "0,1" bitfld.long 0x00 2. " USE_PD_REG ,Use bit 1 from this register as PD override when set to 1" "0,1" bitfld.long 0x00 1. " PD ,Override value for PD" "0,1" group.long 0x1C++0x3 line.long 0x00 "UTMI_INTERFACE_CNTL_1,Register to override UTMI interface control pins." bitfld.long 0x00 31. " USEUTMIDATAREG ,Use datain from UTMI interface register" "0,1" hexmask.long.word 0x00 15.--30. 1. " UTMIDATAIN ,Override value for the UTMIDATAIN" bitfld.long 0x00 13. " USEDATABUSREG ,When set to 1 use bit 12 from register instead of interface" "0,1" textline " " bitfld.long 0x00 12. " DATABUS16OR8 ,Override value for UTMI signal DATABUS16OR8" "0,1" bitfld.long 0x00 11. " USEOPMODEREG ,When set to 1 use bits 10:9 from register instead of interface" "0,1" bitfld.long 0x00 9.--10. " OPMODE ,Override value for UTMI signal OPMODE[1:0]" "0,1,2,3" textline " " bitfld.long 0x00 8. " OVERRIDESUSRESET ,Override the suspend and reset values. Use bits 6 and 7" "0,1" bitfld.long 0x00 7. " SUSPENDM ,Override value for UTMI signal SUSPENDM" "0,1" bitfld.long 0x00 6. " UTMIRESET ,Override value for UTMI signal UTMIRESET" "0,1" textline " " bitfld.long 0x00 5. " OVERRIDEXCVRSEL ,When set to 1 use bits 4:3 from register instead of interface" "0,1" bitfld.long 0x00 3.--4. " XCVRSEL ,Override value for UTMI signal XCVRSEL[1:0]" "0,1,2,3" bitfld.long 0x00 2. " USETXVALIDREG ,When set to 1 use bits 1:0 from register instead of interface" "0,1" textline " " bitfld.long 0x00 1. " TXVALID ,Override value for UTMI signal TXVALID" "0,1" bitfld.long 0x00 0. " TXVALIDH ,Override value for UTMI signal TXVALIDH" "0,1" group.long 0x20++0x3 line.long 0x00 "UTMI_INTERFACE_CNTL_2,UTMI interface override and observe register 2" bitfld.long 0x00 31. " RXRCV ,Read for UTMI signal value" "0,1" bitfld.long 0x00 30. " RXDP ,Read for UTMI signal" "0,1" bitfld.long 0x00 29. " RXDM ,Read for UTMI signal" "0,1" textline " " bitfld.long 0x00 28. " HOSTDISCONNECT ,Read for UTMI signal" "0,1" bitfld.long 0x00 26.--27. " LINESTATE ,Read for UTMI signal" "0,1,2,3" bitfld.long 0x00 25. " RXVALID ,Read for UTMI signal" "0,1" textline " " bitfld.long 0x00 24. " RXVALIDH ,Read for UTMI signal" "0,1" bitfld.long 0x00 23. " RXACTIVE ,Read for UTMI signal" "0,1" bitfld.long 0x00 22. " RXERROR ,Read for UTMI signal" "0,1" textline " " bitfld.long 0x00 21. " TXREADY ,Read for UTMI signal" "0,1" bitfld.long 0x00 20. " UTMIRESETDONE ,Read for UTMIRESETDONE signal" "0,1" bitfld.long 0x00 19. " USEBITSTUFFREG ,When set to 1 use bits 18-17 from register instead of interface" "0,1" textline " " bitfld.long 0x00 18. " TXBITSTUFFENABLE ,Override value for signal TXBITSTUFFENABLE" "0,1" bitfld.long 0x00 17. " TXBITSTUFFENABLEH ,Override value for pin TXBITSTUFFENABLE" "0,1" bitfld.long 0x00 16. " USETERMCONTROLREG ,When set to 1, bits 15:13 from register are used instead of interface" "0,1" textline " " bitfld.long 0x00 15. " TERMSEL ,Override value for signal TERMSEL" "0,1" bitfld.long 0x00 14. " DPPULLDOWN ,Override value for signal DPPULLDOWN" "0,1" bitfld.long 0x00 13. " DMPULLDOWN ,Override value for signal DMPULLDOWN" "0,1" textline " " bitfld.long 0x00 9. " USEREGSERIALMODE ,When set to 1 use bits 8:5 from register instead of interface" "0,1" bitfld.long 0x00 8. " TXSE0 ,Override value for signal TXSE0" "0,1" bitfld.long 0x00 7. " TXDAT ,Override value for signal TXDAT" "0,1" textline " " bitfld.long 0x00 6. " FSLSSERIALMODE ,Override value for signal FSLSSERIALMODE" "0,1" bitfld.long 0x00 5. " TXENABLEN ,Override value for signal TXENABLEN" "0,1" bitfld.long 0x00 0. " SIG_BYPASS_SUSPENDMPULSE_INCR ,Pulse-extended so that the sampling" "Pulse_extension_active,Bypass_pulse_extension" group.long 0x24++0x3 line.long 0x00 "BIST,COntains bits related to the built in self test of the phy" bitfld.long 0x00 31. " BIST_START ,When set to 1 the BIST mode is started." "0,1" bitfld.long 0x00 30. " REDUCED_SWING ,When 1 the TX swing is reduced in BIST mode" "0,1" bitfld.long 0x00 29. " BIST_CRC_CALC_EN ,Enables CRC calculation during BIST when set to 1" "0,1" textline " " hexmask.long.word 0x00 20.--28. 1. " BIST_PKT_LENGTH ,Address for which BIST to select" bitfld.long 0x00 19. " LOOPBACK_EN ,Enables the loopback mode" "0,1" bitfld.long 0x00 16.--18. " BIST_OP_PHASE_SEL ,Selects which phase to use for data transmission during BIST" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " SWEEP_EN ,Enables freq sweep on CDR" "0,1" bitfld.long 0x00 12.--14. " SWEEP_MODE ,Selects the freq sweep mode." "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " BIST_PASS ,Indicates that the BIST has passed" "0,1" textline " " bitfld.long 0x00 10. " BIST_BUSY ,Indicates that BIST is running" "0,1" bitfld.long 0x00 5.--6. " OP_CODE ,Op code" "0,1,2,3" bitfld.long 0x00 4. " RX_TEST_MODE ,Rx Test Mode" "0,1" textline " " bitfld.long 0x00 2. " INTER_PKT_DELAY_TEST ,INTER_PKT_DELAY_TEST" "0,1" bitfld.long 0x00 1. " HS_ALL_ONES_TEST ,HS_ALL_ONES_TEST" "0,1" bitfld.long 0x00 0. " USE_BIST_TX_PHASES ,Transmitting phase" "0,1" group.long 0x28++0x3 line.long 0x00 "BIST_CRC,CRC code for BIST test" hexmask.long 0x00 0.--31. 1. " BIST_CRC ,The CRC value from the BIST." group.long 0x2C++0x3 line.long 0x00 "CDR_BIST2,Clock data recovery register and BIST register 2" bitfld.long 0x00 31. " CDR_EXE_EN ,CDR debug bits" "0,1" bitfld.long 0x00 28.--30. " CDR_EXE_MODE ,CDR debug bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--27. " NUM_DECISIONS ,CDR debug bits" "0,1,2,3,4,5,6,7" textline " " sif (cpuis("AM335*")) rbitfld.long 0x00 22.--24. " CDR_CHOSEN_PHASE ,CDR_CHOSEN_PHASE" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19.--21. " FORCE_CDR_PHASE ,FORCE_CDR_PHASE" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 18. " DISABLE_CDR_FREQ_TRACK ,DISABLE_CDR_FREQ_TRACK" "0,1" textline " " rbitfld.long 0x00 12. " FORCE_CDR_PHASE_EN ,Use bits 21-19 as the phase to be forced on the CDR" "0,1" rbitfld.long 0x00 13.--17. " CDR_CONFIGURE ,CDR_CONFIGURE " "0,1,?..." textline " " endif bitfld.long 0x00 6.--11. " BIST_START_ADDR ,Bist start adres" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " BIST_END_ADDR ,Bist end adres" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30++0x3 line.long 0x00 "GPIO,GPIO mode configurations and reads" bitfld.long 0x00 31. " USEGPIOMODEREG ,When set to 1 use bits 31:24 from this register instead of primary inputs" "0,1" bitfld.long 0x00 30. " GPIOMODE ,Overrides the corresponding primary input" "0,1" bitfld.long 0x00 29. " DPGPIOGZ ,Overrides the corresponding primary input" "0,1" textline " " bitfld.long 0x00 28. " DMGPIOGZ ,Overrides the corresponding primary input" "0,1" bitfld.long 0x00 27. " DPGPIOA ,Overrides the corresponding primary input" "0,1" bitfld.long 0x00 26. " DMGPIOA ,Overrides the corresponding primary input" "0,1" textline " " bitfld.long 0x00 25. " DPGPIOY ,The GPIO Y output is stored here" "0,1" bitfld.long 0x00 24. " DMGPIOY ,The GPIO Y output is stored here" "0,1" bitfld.long 0x00 23. " GPIO1P8VCONFIG ,Overrides the corresponding primary input" "0,1" textline " " bitfld.long 0x00 20.--22. " GPIOCONFIG ,Used for configuring the GPIOs." "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " DMGPIOPIPD ,GPIO mode DM pull-down enabled. Overrides the corresponding primary input" "0,1" bitfld.long 0x00 18. " DPGPIOPIPD ,GPIO mode DP pull-down enabled. Overrides the corresponding primary input." "0,1" group.long 0x34++0x3 line.long 0x00 "DLLHS,Bits for control and debug of the DLL inside the USBPHY" bitfld.long 0x00 28. " DLLHS_LOCK ,Read the AFE output by this name" "0,1" bitfld.long 0x00 22.--27. " DLLHS_GENERATED_CODE ,Read the AFE output by this name" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21. " DLL_SEL_CODE_PHS ,Connect to DLLHS_TEST_LDO[0] on AFE interface." "0,1" textline " " bitfld.long 0x00 19.--20. " DLL_LOCKCHK ,Connect to DLLHS_TEST_LDO[2:1] on AFE interface." "0,1,2,3" bitfld.long 0x00 16.--18. " DLL_SEL_COD ,Connect to DLLHS_TEST_LDO[5:3] on AFE interface." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " DLL_PHS0_8 ,Connect to DLLHS_TEST_LDO[6] on AFE interface." "0,1" textline " " sif (cpuis("AM335*")) bitfld.long 0x00 8. " FORCE_DLL_CODE ,Connect to DLLHS_TEST_LDO[11] on AFE interface." "0,1" bitfld.long 0x00 6.--7. " DLL_RATE ,Connect to DLLHS_TEST_LDO[8:7] on AFE interface." "0,1,2,3" else bitfld.long 0x00 9.--14. " DLL_FORCED_CODE ,Connect to the pin of this name on AFE interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8. " FORCE_DLL_CODE ,Connect to DLLHS_TEST_LDO[11] on AFE interface." "0,1" bitfld.long 0x00 6.--7. " DLL_RATE ,Connect to DLLHS_TEST_LDO[8:7] on AFE interface." "0,1,2,3" endif textline " " bitfld.long 0x00 4.--5. " DLL_FILT ,Connect to DLLHS_TEST_LDO[10:9] on AFE interface." "0,1,2,3" bitfld.long 0x00 3. " DLL_CDR_MODE ,Connect to the pin of this name on AFE interface." "0,1" bitfld.long 0x00 2. " DLL_IDLE ,Connect to DLLHS_TEST_LDO[12] on AFE interface." "0,1" textline " " bitfld.long 0x00 1. " DLL_FREEZE ,Connect to DLLHS_TEST_LDO[13] on AFE interface." "0,1" sif (!cpuis("AM335*")) group.long 0x38++0x3 line.long 0x00 "USB2PHYCM_TRIM,Contains trim bit overrides for the USBPHYCM" bitfld.long 0x00 31. " USEBGTRIM ,When set to 1 bits 30:16 are used as the trim value for the USBPHYCM bandgap" "0,1" hexmask.long.word 0x00 16.--30. 1. " BGTRIM ,Override value for the BGTRIM value" bitfld.long 0x00 15. " USE_SW_TRIM ,Use bits 14:8 to override the switch cap trim value." "0,1" textline " " hexmask.long.byte 0x00 8.--14. 1. " SWTRIM ,Override value for the switch cap trim value." bitfld.long 0x00 7. " USE_NWELLTRIM_REG ,Override NWELL resistor trim using NWELLTRIM_CODE" "0,1" bitfld.long 0x00 4.--6. " NWELLTRIM_CODE ,NWELL resistor trim code." "0,1,2,3,4,5,6,7" endif group.long 0x3C++0x3 line.long 0x00 "USB2PHYCM_CONFIG,Configuration and status register for the USBPHYCM and LDO" hexmask.long.byte 0x00 24.--31. 1. " CONFIGURECM ,Connects to the CONFIGURECM pins." bitfld.long 0x00 18.--23. " CMSTATUS ,Reads the CMSTATUS bits." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 2.--17. 1. " LDOCONFIG ,The LDOCONFIG bit settings." textline " " bitfld.long 0x00 0.--1. " LDOSTATUS ,Reads the LDOSTATUS bits." "0,1,2,3" sif (!cpuis("AM335*")) group.long 0x40++0x3 line.long 0x00 "USBOTG,USBOTG" hexmask.long.word 0x00 16.--31. 1. " TESTOTGCONFIG ,Used to control the OTG module" hexmask.long.word 0x00 6.--15. 1. " TESTOTGSTATUS ,The OTG status bits" endif group.long 0x44++0x3 line.long 0x00 "AD_INTERFACE_REG1,Bypass bits for internal analog to digital interface pins with the same name" bitfld.long 0x00 31. " USE_AD_DATA_REG ,Override for bits 30:29" "0,1" bitfld.long 0x00 30. " HS_TX_DATA ,HS_TX_DATA" "0,1" bitfld.long 0x00 29. " FS_TX_DATA ,FS_TX_DATA" "0,1" textline " " bitfld.long 0x00 28. " TEST_PRE_EN_CNTRL ,Override for bits 27:25" "0,1" bitfld.long 0x00 27. " SQ_PRE_EN ,SQ_PRE_EN" "0,1" bitfld.long 0x00 26. " HS_TX_PRE_EN ,HS_TX_PRE_EN" "0,1" textline " " bitfld.long 0x00 25. " HS_RX_PRE_EN ,HS_RX_PRE_EN" "0,1" bitfld.long 0x00 24. " TEST_EN_CNTRL ,Override for bits 23:19" "0,1" bitfld.long 0x00 23. " HS_TX_EN ,HS_TX_EN" "0,1" textline " " bitfld.long 0x00 22. " FS_RX_EN ,FS_RX_EN" "0,1" bitfld.long 0x00 20. " SQ_EN ,SQ_EN" "0,1" bitfld.long 0x00 19. " HS_RX_EN ,HS_RX_EN" "0,1" textline " " bitfld.long 0x00 18. " TEST_HS_MODE ,Override for bits 17:16" "0,1" bitfld.long 0x00 17. " HS_HV_SW ,HS_HV_SW" "0,1" bitfld.long 0x00 16. " HS_CHIRP ,HS_CHIRP" "0,1" textline " " bitfld.long 0x00 15. " TEST_FS_MODE ,Override for bits 14:12" "0,1" bitfld.long 0x00 14. " FSTX_GZ ,FSTX_GZ" "0,1" bitfld.long 0x00 13. " FSTX_PRE_EN ,FSTX_PRE_EN" "0,1" textline " " bitfld.long 0x00 11. " TEST_SQ_CAL_CONTROL ,Override for bits 10:8" "0,1" bitfld.long 0x00 10. " SQ_CAL_EN3 ,SQ_CAL_EN3" "0,1" bitfld.long 0x00 9. " SQ_CAL_EN1 ,SQ_CAL_EN1" "0,1" textline " " bitfld.long 0x00 8. " SQ_CAL_EN2 ,SQ_CAL_EN2" "0,1" bitfld.long 0x00 7. " TEST_RTERM_CAL_CONTROL ,Override for bits 6" "0,1" bitfld.long 0x00 6. " RTERM_CAL_EN ,RTERM_CAL_EN" "0,1" textline " " bitfld.long 0x00 5. " DLL_RX_DATA ,DLL_RX_DATA" "0,1" bitfld.long 0x00 4. " DISCON_DETECT ,DISCON_DETECT" "0,1" bitfld.long 0x00 3. " USE_LSHOST_REG ,Use bit 2 for this reg" "0,1" textline " " bitfld.long 0x00 2. " LSHOSTMODE ,LSHOSTMODE" "0,1" bitfld.long 0x00 1. " LSFS_RX_DATA ,LSFS_RX_DATA" "0,1" bitfld.long 0x00 0. " SQUELCH ,SQUELCH" "0,1" group.long 0x48++0x3 line.long 0x00 "AD_INTERFACE_REG2,Bypass bits for internal analog to digital interface pins with the same name" bitfld.long 0x00 31. " USE_SUSP_DRV_REG ,Use bits 30:27 from this register as overrides" "0,1" bitfld.long 0x00 30. " SUS_DRV_DP_DATA ,SUS_DRV_DP_DATA" "0,1" bitfld.long 0x00 29. " SUS_DRV_DP_EN ,SUS_DRV_DP_EN" "0,1" textline " " bitfld.long 0x00 28. " SUS_DRV_DM_DATA ,SUS_DRV_DM_DATA" "0,1" bitfld.long 0x00 27. " SUS_DRV_DM_EN ,SUS_DRV_DM_EN" "0,1" bitfld.long 0x00 26. " USE_DISCON_REG ,Use bits 25:24 from this register as override" "0,1" textline " " bitfld.long 0x00 25. " DISCON_EN ,DISCON_EN" "0,1" bitfld.long 0x00 24. " DISCON_PRE_EN ,DISCON_PRE_EN" "0,1" bitfld.long 0x00 18.--22. " SPARE_OUT_CORE ,SPARE_OUT_CORE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 17. " SERX_DP_CORE ,SERX_DP_CORE" "0,1" bitfld.long 0x00 16. " SERX_DM_CORE ,SERX_DM_CORE" "0,1" bitfld.long 0x00 15. " USE_HSRX_CAL_EN_REG ,Use bit 14 from this register as override" "0,1" textline " " bitfld.long 0x00 14. " HSRX_CAL_EN ,HSRX_CAL_EN" "0,1" bitfld.long 0x00 13. " USE_RPU_RPD_REG ,Use override from bits 12:7" "0,1" bitfld.long 0x00 12. " RPU_DP_SW1_EN_CORE ,RPU_DP_SW1_EN_CORE" "0,1" textline " " bitfld.long 0x00 11. " RPU_DP_SW2_EN_CORE ,RPU_DP_SW2_EN_CORE" "0,1" bitfld.long 0x00 10. " RPU_DM_SW1_EN_CORE ,RPU_DM_SW1_EN_CORE" "0,1" bitfld.long 0x00 9. " RPU_DM_SW2_EN_CORE ,RPU_DM_SW2_EN_CORE" "0,1" textline " " bitfld.long 0x00 8. " DP_PULLDOWN_EN_CORE ,DP_PULLDOWN_EN_CORE" "0,1" bitfld.long 0x00 7. " DM_PULLDOWN_EN_CORE ,DM_PULLDOWN_EN_CORE" "0,1" bitfld.long 0x00 6. " DP_DM_5V_SHORT ,DP_DM_5V_SHORT" "0,1" textline " " bitfld.long 0x00 1.--5. " SPARE_IN_CORE ,SPARE_IN_CORE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " PORZ ,Read only bit - the PORZ generated from the digital registered on the A-D interface." "0,1" group.long 0x4C++0x3 line.long 0x00 "AD_INTERFACE_REG3,Bypass bits for internal analog to digital interface pins with the same name" bitfld.long 0x00 31. " USE_HSOS_DATA_REG ,Use bits 30:23 in this register as bypass bits" "0,1" hexmask.long.byte 0x00 23.--30. 1. " HSOS_DATA ,HSOS_DATA" bitfld.long 0x00 22. " USE_FS_REG3 ,Use bits 21:20 as bypass bits" "0,1" textline " " bitfld.long 0x00 21. " FSTX_MODE ,FSTX_MODE" "0,1" bitfld.long 0x00 20. " FSTX_SE0 ,FSTX_SE0" "0,1" bitfld.long 0x00 19. " USE_HS_TERM_RES_REG ,Use bit 18 as override bit" "0,1" textline " " bitfld.long 0x00 18. " HS_TERM_RES ,HS_TERM_RES" "0,1" hexmask.long.byte 0x00 10.--17. 1. " SPARE_IN_LDO ,SPARE_IN_LDO" hexmask.long.byte 0x00 2.--9. 1. " SPARE_OUT_LDO ,SPARE_OUT_LDO" textline " " bitfld.long 0x00 1. " USE_FARCORE_REG ,Use bit 0 from this register as bypass" "0,1" bitfld.long 0x00 0. " FARCORE ,FARCORE" "0,1" sif (!cpuis("AM335*")) group.long 0x50++0x3 line.long 0x00 "ANA_CONFIG1,Used to configure and debug the analog blocks." hexmask.long.word 0x00 17.--31. 1. " SQ_CTRL_REG ,SQ_CTRL_REG" bitfld.long 0x00 14.--16. " FS_SLEW ,FS_SLEW" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " HS_PRE_EMP_CNTRL ,HS_PRE_EMP_CNTRL" "0,1,2,3" textline " " hexmask.long.byte 0x00 5.--11. 1. " HSFSTX_TEST ,HSFSTX_TEST" bitfld.long 0x00 0.--4. " PROTECT_TEST ,PROTECT_TEST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x54++0x3 line.long 0x00 "ANA_CONFIG2,Configure and debug the analog blocks" sif (!cpuis("AM335*")) bitfld.long 0x00 27.--31. " RTERM_CAL_TEST ,RTERM_CAL_TEST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " endif hexmask.long.byte 0x00 20.--26. 1. " REF_GEN_TEST ,NOT IMPLEMENTED" sif (!cpuis("AM335*")) bitfld.long 0x00 18.--19. " FSRX_TEST ,FSRX_TEST" "0,1,2,3" endif textline " " sif (cpuis("AM335*")) bitfld.long 0x00 15.--17. " RTERM_TEST ,RTERM_TEST0x0 is default 0x3 decreases the termination impedance by 2 to 3% (can be used to get 1 to 1.5% better eye vertical opening)" "0,1,2,3,4,5,6,7" else bitfld.long 0x00 15.--19. " RTERM_TEST ,RTERM_TEST0x0 is default 0x3 decreases the termination impedance by 2 to 3% (can be used to get 1 to 1.5% better eye vertical opening)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif textline " " sif (!cpuis("AM335*")) bitfld.long 0x00 11.--14. " DISCON_TEST ,DISCON_TEST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--10. " HSRX_TEST ,HSRX_TEST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 3.--5. " SERX_TEST ,SERX_TEST" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--2. " SERX_HYST_CNTRL ,SERX_HYST_CNTRL" "0,1,2,3" bitfld.long 0x00 0. " SQ_LPMODEZ ,SQ_LPMODEZ" "0,1" endif width 0xb tree.end tree "USB1PHY" base ad:0x47401B00 width 30. group.long 0x0++0x3 line.long 0x00 "TERMINATION_CONTROL,Contains bits related to control of terminations in USBPHY" bitfld.long 0x00 29. " ALWAYS_UPDATE ,When set to 1, the calibration code is updated immediately after a code computation without waiting for idle periods." "0,1" bitfld.long 0x00 28. " RTERM_CAL_DONE ,Rterm calibration is done. First time cal is done this bit gets set and gets reset at a restart cal" "0,1" bitfld.long 0x00 24.--27. " FS_CODE_SEL ,FS Code selection control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21. " USE_RTERM_RMX_REG ,Override termination resistor trim code with RTERM_RMX from this register" "0,1" hexmask.long.byte 0x00 14.--20. 1. " RTERM_RMX ,When read, this field returns the current Termination resistor trim code The value written to this field is used as Termination resistor trim code if bit 21 is set to 1" bitfld.long 0x00 11.--13. " HS_CODE_SEL ,HS Code selection control. A higher positive value" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 10. " RTERM_COMP_OUT ,Master loop comparator output" "0,1" bitfld.long 0x00 9. " RESTART_RTERM_CAL ,Restart the rterm calibration. the calibration restarts on any toggle 0-1 or 1-0 on this bit." "0,1" bitfld.long 0x00 8. " DISABLE_TEMP_TRACK ,Disables the temperature tracking function of the termination calibration" "0,1" textline " " bitfld.long 0x00 7. " USE_RTERM_CAL_REG ,When 1, the rterm cal code is overridden by values in RTERM_CAL" "0,1" hexmask.long.byte 0x00 0.--6. 1. " RTERM_CAL ,When read this field returns the current rterm calibration code The value written to this filed is used as rterm calibration code if the bit USE_RTERM_CAL_REG is 1." group.long 0x4++0x3 line.long 0x00 "RX_CALIB,Contains bits related to RX calibration" bitfld.long 0x00 31. " RESTART_HSRX_CAL ,Restart the HSRX calibration state machine when this bit goes from 0 to 1." "0,1" bitfld.long 0x00 30. " USE_HS_OFF_REG ,Override HS offset correction with HS_OFF_CODE" "No override,Override" bitfld.long 0x00 24.--29. " HS_OFF_CODE ,HS offset code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 23. " HSRX_COMP_OUT ,HSRX comparator output" "0,1" bitfld.long 0x00 22. " HSRX_CAL_DONE ,HSRX calibration done" "Not done,Done" bitfld.long 0x00 21. " USE_SQ_OFF_DAC1 ,Override Squelch offset DAC1" "No override,Override" textline " " bitfld.long 0x00 15.--20. " SQ_OFF_CODE_DAC1 ,When read returns current Sq offset code for DAC1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 14. " USE_SQ_OFF_DAC2 ,Override Squelch offset DAC2 code when '1'" "0,1" bitfld.long 0x00 9.--13. " SQ_OFF_CODE_DAC2 ,When read returns current Sq offset code for DAC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8. " USE_SQ_OFF_DAC3 ,Override Squelch offset DAC3 code when 1" "0,1" bitfld.long 0x00 3.--7. " SQ_OFF_CODE_DAC3 ,When read returns current Sq offset code for DAC3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2. " SQ_COMP_OUT ,Sq comp output" "0,1" textline " " bitfld.long 0x00 1. " SQ_CAL_DONE ,Sq calibration " "0,1" bitfld.long 0x00 0. " RESTART_SQ_CAL ,Restart cycles" "No restart,Restart" group.long 0x8++0x3 line.long 0x00 "DLLHS_2,Second DLLHS control register" hexmask.long.byte 0x00 24.--31. 1. " DLLHS_CNTRL_LDO ,DLLHS controll LDO" hexmask.long.byte 0x00 16.--23. 1. " DLLHS_STATUS_LDO ,DLLHS status LDO" bitfld.long 0x00 4. " LINESTATE_DEBOUNCE_EN ,Enables the linestate debounce filter" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " LINESTATE_DEBOUNCE_CNTL ,Used for control of the linestate debounce filter when going from syncronous to async linestate." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC++0x3 line.long 0x00 "RX_TEST_2,Second receiver test register" bitfld.long 0x00 31. " HSOSREVERSAL ,Swaps the dataout from HSOS" "0,1" bitfld.long 0x00 30. " HSOSBITINVERSION ,Inverts the HSOS bits" "0,1" bitfld.long 0x00 29. " PHYCLKOUTINVERSION ,This inverts the phase for the PHYCLKOUT" "0,1" textline " " bitfld.long 0x00 28. " RXPIDERR ,Flags if the RX data packet has PID error. NOT IMPLEMENTED." "0,1" bitfld.long 0x00 27. " USEINTDATAOUT ,This will bypass the analog and will send data packet to controller incase of receiver (Faking the receive data). data used will be INTDATAOUTREG" "0,1" hexmask.long.word 0x00 11.--26. 1. " INTDATAOUTREG ,This register will be loaded through OCP and this data will be given to the controller if USEINTDATAOUT is set to 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " CDR_TESTOUT ,CDR debug bits" sif (!cpuis("AM335*")) group.long 0x10++0x3 line.long 0x00 "TX_TEST_CHRG_DET,TX test register" bitfld.long 0x00 31. " TXSYNCERR ,Sync error on TX data. NOT IMPLEMENTED." "0,1" hexmask.long.word 0x00 15.--30. 1. " UTMIDATATX ,Stores Last 2 byte of transmit data coming from the controller" bitfld.long 0x00 13. " TXPIDERR ,Flags if the TX packet has PID error. NOT IMPLEMENTED." "0,1" textline " " bitfld.long 0x00 12. " USE_CHGDET_DPDMSW ,Use bits 11:8 as override bits" "0,1" bitfld.long 0x00 11. " CHGDET_DPSW0EN ,Overrides the same named A/D interface signal for the charger detect block" "0,1" bitfld.long 0x00 10. " CHGDET_DPSW1EN ,Overrides the same named A/D interface signal for the charger detect block. Read value is valid only if VCHGLDO is on." "0,1" textline " " bitfld.long 0x00 9. " CHGDET_DMSW0EN ,Overrides the same named A/D interface signal for the charger detect block. Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 8. " CHGDET_DMSW1EN ,Overrides the same named A/D interface signal for the charger detect block..Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 6. " RDPPDCHGDETEN ,When set to 1 connects a 15K (+/- 30%) pulldown resistor on DP. Read value is valid only if VCHGLDO is on." "0,1" textline " " bitfld.long 0x00 5. " RDMPDCHGDETEN ,When set to 1 connects a 15K (+/- 30%) pulldown resistor on DM. Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 4. " RDPPUCHGDETEN ,When set to 1 connects a 150K (+/- 30%) pullup resistor on DP. Read value is valid only if VCHGLDO is on." "0,1" bitfld.long 0x00 3. " RDMPUCHGDETEN ,When set to 1 connects a 150K (+/- 30%) pullup resistor on DM. Read value is valid only if VCHGLDO is on." "0,1" textline " " bitfld.long 0x00 2. " USE_CHG_DET_PU_REG ,Use bits 4:3 from this register" "0,1" bitfld.long 0x00 1. " USE_CHG_DET_PD_REG ,Use bits 6:5 from this register." "0,1" endif group.long 0x14++0x3 line.long 0x00 "CHRG_DET,This is the charger detect register" bitfld.long 0x00 29. " USE_CHG_DET_REG ,Use bits 28:24 and 18:17 from this register" "0,1" bitfld.long 0x00 28. " DIS_CHG_DET ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 27. " SRC_ON_DM ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" textline " " bitfld.long 0x00 26. " SINK_ON_DP ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 25. " CHG_DET_EXT_CTL ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 24. " RESTART_CHG_DET ,Restart the charger detection protocol when this goes from 0 to 1" "0,1" textline " " bitfld.long 0x00 23. " CHG_DET_DONE ,Charger detect protocol has completed" "0,1" bitfld.long 0x00 22. " CHG_DETECTED ,Same signal as CE pin" "0,1" bitfld.long 0x00 21. " DATA_DET ,Output of the data det comparator" "0,1" textline " " bitfld.long 0x00 18. " CHG_ISINK_EN ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 17. " CHG_VSRC_EN ,When read, returns current value of charger detect input. When USE_CHG_DET_REG = 1, the value written to this filed overrides the corresponding charger detect input." "0,1" bitfld.long 0x00 16. " COMP_DP ,Comparator on the DP line value" "0,1" textline " " bitfld.long 0x00 15. " COMP_DM ,Comparator on the DM line value" "0,1" bitfld.long 0x00 13.--14. " CHG_DET_OSC_CNTRL ,Charger detect osc control" "0,1,2,3" bitfld.long 0x00 7.--12. " CHG_DET_TIMER ,Charger detect timer control." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 3.--4. " CHG_DET_ICTRL ,Charger detect current control" "0,1,2,3" bitfld.long 0x00 1.--2. " CHG_DET_VCTRL ,Charger detect voltage buffer control" "0,1,2,3" bitfld.long 0x00 0. " FOR_CE ,Force CE = 1 when this bit is set" "0,1" group.long 0x18++0x3 line.long 0x00 "PWR_CNTL,Includes all the power control bits" bitfld.long 0x00 31. " RESETDONETCLK ,Goes high when the RESET is synchronized to TCLK" "0,1" bitfld.long 0x00 30. " RESET_DONE_VMAIN ,Goes high when LDO domain is up, PLL LOCK is available, and utmi_reset is deasserted." "0,1" bitfld.long 0x00 29. " VMAIN_GLOBAL_RESET_DONE ,Goes high when LDO domain is up and PLL LOCK is available." "0,1" textline " " bitfld.long 0x00 28. " RESETDONEMCLK ,Goes high when the RESET is synchronized to MCLK" "0,1" bitfld.long 0x00 27. " RESETDONE_CHGDET ,Goes high when the RESET is synchronized to charger detect oscillator clock domain" "0,1" hexmask.long.word 0x00 12.--26. 1. " LDOPWRCOUNTER ,This is the value of the counter used for LDO power up. RESET to default." textline " " bitfld.long 0x00 11. " FORCEPLLSLOWCLK ,Forces the PLL to the slow clk mode" "0,1" bitfld.long 0x00 10. " FORCELDOON ,Forces the LDO to be ON." "0,1" bitfld.long 0x00 9. " FORCEPLLON ,Forces the PLL to be ON." "0,1" textline " " bitfld.long 0x00 6. " PLLLOCK ,Lock signal from the PLL" "0,1" bitfld.long 0x00 5. " USEPLLLOCK ,Indicate to the Phy" "0,1" bitfld.long 0x00 4. " USE_DATAPOLARITYN_REG ,1 - use bit 3 as override for the DATAPOLARITYN signal." "0,1" textline " " bitfld.long 0x00 3. " DATAPOLARITYN ,Override value of datapolarityn" "0,1" bitfld.long 0x00 2. " USE_PD_REG ,Use bit 1 from this register as PD override when set to 1" "0,1" bitfld.long 0x00 1. " PD ,Override value for PD" "0,1" group.long 0x1C++0x3 line.long 0x00 "UTMI_INTERFACE_CNTL_1,Register to override UTMI interface control pins." bitfld.long 0x00 31. " USEUTMIDATAREG ,Use datain from UTMI interface register" "0,1" hexmask.long.word 0x00 15.--30. 1. " UTMIDATAIN ,Override value for the UTMIDATAIN" bitfld.long 0x00 13. " USEDATABUSREG ,When set to 1 use bit 12 from register instead of interface" "0,1" textline " " bitfld.long 0x00 12. " DATABUS16OR8 ,Override value for UTMI signal DATABUS16OR8" "0,1" bitfld.long 0x00 11. " USEOPMODEREG ,When set to 1 use bits 10:9 from register instead of interface" "0,1" bitfld.long 0x00 9.--10. " OPMODE ,Override value for UTMI signal OPMODE[1:0]" "0,1,2,3" textline " " bitfld.long 0x00 8. " OVERRIDESUSRESET ,Override the suspend and reset values. Use bits 6 and 7" "0,1" bitfld.long 0x00 7. " SUSPENDM ,Override value for UTMI signal SUSPENDM" "0,1" bitfld.long 0x00 6. " UTMIRESET ,Override value for UTMI signal UTMIRESET" "0,1" textline " " bitfld.long 0x00 5. " OVERRIDEXCVRSEL ,When set to 1 use bits 4:3 from register instead of interface" "0,1" bitfld.long 0x00 3.--4. " XCVRSEL ,Override value for UTMI signal XCVRSEL[1:0]" "0,1,2,3" bitfld.long 0x00 2. " USETXVALIDREG ,When set to 1 use bits 1:0 from register instead of interface" "0,1" textline " " bitfld.long 0x00 1. " TXVALID ,Override value for UTMI signal TXVALID" "0,1" bitfld.long 0x00 0. " TXVALIDH ,Override value for UTMI signal TXVALIDH" "0,1" group.long 0x20++0x3 line.long 0x00 "UTMI_INTERFACE_CNTL_2,UTMI interface override and observe register 2" bitfld.long 0x00 31. " RXRCV ,Read for UTMI signal value" "0,1" bitfld.long 0x00 30. " RXDP ,Read for UTMI signal" "0,1" bitfld.long 0x00 29. " RXDM ,Read for UTMI signal" "0,1" textline " " bitfld.long 0x00 28. " HOSTDISCONNECT ,Read for UTMI signal" "0,1" bitfld.long 0x00 26.--27. " LINESTATE ,Read for UTMI signal" "0,1,2,3" bitfld.long 0x00 25. " RXVALID ,Read for UTMI signal" "0,1" textline " " bitfld.long 0x00 24. " RXVALIDH ,Read for UTMI signal" "0,1" bitfld.long 0x00 23. " RXACTIVE ,Read for UTMI signal" "0,1" bitfld.long 0x00 22. " RXERROR ,Read for UTMI signal" "0,1" textline " " bitfld.long 0x00 21. " TXREADY ,Read for UTMI signal" "0,1" bitfld.long 0x00 20. " UTMIRESETDONE ,Read for UTMIRESETDONE signal" "0,1" bitfld.long 0x00 19. " USEBITSTUFFREG ,When set to 1 use bits 18-17 from register instead of interface" "0,1" textline " " bitfld.long 0x00 18. " TXBITSTUFFENABLE ,Override value for signal TXBITSTUFFENABLE" "0,1" bitfld.long 0x00 17. " TXBITSTUFFENABLEH ,Override value for pin TXBITSTUFFENABLE" "0,1" bitfld.long 0x00 16. " USETERMCONTROLREG ,When set to 1, bits 15:13 from register are used instead of interface" "0,1" textline " " bitfld.long 0x00 15. " TERMSEL ,Override value for signal TERMSEL" "0,1" bitfld.long 0x00 14. " DPPULLDOWN ,Override value for signal DPPULLDOWN" "0,1" bitfld.long 0x00 13. " DMPULLDOWN ,Override value for signal DMPULLDOWN" "0,1" textline " " bitfld.long 0x00 9. " USEREGSERIALMODE ,When set to 1 use bits 8:5 from register instead of interface" "0,1" bitfld.long 0x00 8. " TXSE0 ,Override value for signal TXSE0" "0,1" bitfld.long 0x00 7. " TXDAT ,Override value for signal TXDAT" "0,1" textline " " bitfld.long 0x00 6. " FSLSSERIALMODE ,Override value for signal FSLSSERIALMODE" "0,1" bitfld.long 0x00 5. " TXENABLEN ,Override value for signal TXENABLEN" "0,1" bitfld.long 0x00 0. " SIG_BYPASS_SUSPENDMPULSE_INCR ,Pulse-extended so that the sampling" "Pulse_extension_active,Bypass_pulse_extension" group.long 0x24++0x3 line.long 0x00 "BIST,COntains bits related to the built in self test of the phy" bitfld.long 0x00 31. " BIST_START ,When set to 1 the BIST mode is started." "0,1" bitfld.long 0x00 30. " REDUCED_SWING ,When 1 the TX swing is reduced in BIST mode" "0,1" bitfld.long 0x00 29. " BIST_CRC_CALC_EN ,Enables CRC calculation during BIST when set to 1" "0,1" textline " " hexmask.long.word 0x00 20.--28. 1. " BIST_PKT_LENGTH ,Address for which BIST to select" bitfld.long 0x00 19. " LOOPBACK_EN ,Enables the loopback mode" "0,1" bitfld.long 0x00 16.--18. " BIST_OP_PHASE_SEL ,Selects which phase to use for data transmission during BIST" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15. " SWEEP_EN ,Enables freq sweep on CDR" "0,1" bitfld.long 0x00 12.--14. " SWEEP_MODE ,Selects the freq sweep mode." "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " BIST_PASS ,Indicates that the BIST has passed" "0,1" textline " " bitfld.long 0x00 10. " BIST_BUSY ,Indicates that BIST is running" "0,1" bitfld.long 0x00 5.--6. " OP_CODE ,Op code" "0,1,2,3" bitfld.long 0x00 4. " RX_TEST_MODE ,Rx Test Mode" "0,1" textline " " bitfld.long 0x00 2. " INTER_PKT_DELAY_TEST ,INTER_PKT_DELAY_TEST" "0,1" bitfld.long 0x00 1. " HS_ALL_ONES_TEST ,HS_ALL_ONES_TEST" "0,1" bitfld.long 0x00 0. " USE_BIST_TX_PHASES ,Transmitting phase" "0,1" group.long 0x28++0x3 line.long 0x00 "BIST_CRC,CRC code for BIST test" hexmask.long 0x00 0.--31. 1. " BIST_CRC ,The CRC value from the BIST." group.long 0x2C++0x3 line.long 0x00 "CDR_BIST2,Clock data recovery register and BIST register 2" bitfld.long 0x00 31. " CDR_EXE_EN ,CDR debug bits" "0,1" bitfld.long 0x00 28.--30. " CDR_EXE_MODE ,CDR debug bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--27. " NUM_DECISIONS ,CDR debug bits" "0,1,2,3,4,5,6,7" textline " " sif (cpuis("AM335*")) rbitfld.long 0x00 22.--24. " CDR_CHOSEN_PHASE ,CDR_CHOSEN_PHASE" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 19.--21. " FORCE_CDR_PHASE ,FORCE_CDR_PHASE" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 18. " DISABLE_CDR_FREQ_TRACK ,DISABLE_CDR_FREQ_TRACK" "0,1" textline " " rbitfld.long 0x00 12. " FORCE_CDR_PHASE_EN ,Use bits 21-19 as the phase to be forced on the CDR" "0,1" rbitfld.long 0x00 13.--17. " CDR_CONFIGURE ,CDR_CONFIGURE " "0,1,?..." textline " " endif bitfld.long 0x00 6.--11. " BIST_START_ADDR ,Bist start adres" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " BIST_END_ADDR ,Bist end adres" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x30++0x3 line.long 0x00 "GPIO,GPIO mode configurations and reads" bitfld.long 0x00 31. " USEGPIOMODEREG ,When set to 1 use bits 31:24 from this register instead of primary inputs" "0,1" bitfld.long 0x00 30. " GPIOMODE ,Overrides the corresponding primary input" "0,1" bitfld.long 0x00 29. " DPGPIOGZ ,Overrides the corresponding primary input" "0,1" textline " " bitfld.long 0x00 28. " DMGPIOGZ ,Overrides the corresponding primary input" "0,1" bitfld.long 0x00 27. " DPGPIOA ,Overrides the corresponding primary input" "0,1" bitfld.long 0x00 26. " DMGPIOA ,Overrides the corresponding primary input" "0,1" textline " " bitfld.long 0x00 25. " DPGPIOY ,The GPIO Y output is stored here" "0,1" bitfld.long 0x00 24. " DMGPIOY ,The GPIO Y output is stored here" "0,1" bitfld.long 0x00 23. " GPIO1P8VCONFIG ,Overrides the corresponding primary input" "0,1" textline " " bitfld.long 0x00 20.--22. " GPIOCONFIG ,Used for configuring the GPIOs." "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " DMGPIOPIPD ,GPIO mode DM pull-down enabled. Overrides the corresponding primary input" "0,1" bitfld.long 0x00 18. " DPGPIOPIPD ,GPIO mode DP pull-down enabled. Overrides the corresponding primary input." "0,1" group.long 0x34++0x3 line.long 0x00 "DLLHS,Bits for control and debug of the DLL inside the USBPHY" bitfld.long 0x00 28. " DLLHS_LOCK ,Read the AFE output by this name" "0,1" bitfld.long 0x00 22.--27. " DLLHS_GENERATED_CODE ,Read the AFE output by this name" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 21. " DLL_SEL_CODE_PHS ,Connect to DLLHS_TEST_LDO[0] on AFE interface." "0,1" textline " " bitfld.long 0x00 19.--20. " DLL_LOCKCHK ,Connect to DLLHS_TEST_LDO[2:1] on AFE interface." "0,1,2,3" bitfld.long 0x00 16.--18. " DLL_SEL_COD ,Connect to DLLHS_TEST_LDO[5:3] on AFE interface." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " DLL_PHS0_8 ,Connect to DLLHS_TEST_LDO[6] on AFE interface." "0,1" textline " " sif (cpuis("AM335*")) bitfld.long 0x00 8. " FORCE_DLL_CODE ,Connect to DLLHS_TEST_LDO[11] on AFE interface." "0,1" bitfld.long 0x00 6.--7. " DLL_RATE ,Connect to DLLHS_TEST_LDO[8:7] on AFE interface." "0,1,2,3" else bitfld.long 0x00 9.--14. " DLL_FORCED_CODE ,Connect to the pin of this name on AFE interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 8. " FORCE_DLL_CODE ,Connect to DLLHS_TEST_LDO[11] on AFE interface." "0,1" bitfld.long 0x00 6.--7. " DLL_RATE ,Connect to DLLHS_TEST_LDO[8:7] on AFE interface." "0,1,2,3" endif textline " " bitfld.long 0x00 4.--5. " DLL_FILT ,Connect to DLLHS_TEST_LDO[10:9] on AFE interface." "0,1,2,3" bitfld.long 0x00 3. " DLL_CDR_MODE ,Connect to the pin of this name on AFE interface." "0,1" bitfld.long 0x00 2. " DLL_IDLE ,Connect to DLLHS_TEST_LDO[12] on AFE interface." "0,1" textline " " bitfld.long 0x00 1. " DLL_FREEZE ,Connect to DLLHS_TEST_LDO[13] on AFE interface." "0,1" sif (!cpuis("AM335*")) group.long 0x38++0x3 line.long 0x00 "USB2PHYCM_TRIM,Contains trim bit overrides for the USBPHYCM" bitfld.long 0x00 31. " USEBGTRIM ,When set to 1 bits 30:16 are used as the trim value for the USBPHYCM bandgap" "0,1" hexmask.long.word 0x00 16.--30. 1. " BGTRIM ,Override value for the BGTRIM value" bitfld.long 0x00 15. " USE_SW_TRIM ,Use bits 14:8 to override the switch cap trim value." "0,1" textline " " hexmask.long.byte 0x00 8.--14. 1. " SWTRIM ,Override value for the switch cap trim value." bitfld.long 0x00 7. " USE_NWELLTRIM_REG ,Override NWELL resistor trim using NWELLTRIM_CODE" "0,1" bitfld.long 0x00 4.--6. " NWELLTRIM_CODE ,NWELL resistor trim code." "0,1,2,3,4,5,6,7" endif group.long 0x3C++0x3 line.long 0x00 "USB2PHYCM_CONFIG,Configuration and status register for the USBPHYCM and LDO" hexmask.long.byte 0x00 24.--31. 1. " CONFIGURECM ,Connects to the CONFIGURECM pins." bitfld.long 0x00 18.--23. " CMSTATUS ,Reads the CMSTATUS bits." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 2.--17. 1. " LDOCONFIG ,The LDOCONFIG bit settings." textline " " bitfld.long 0x00 0.--1. " LDOSTATUS ,Reads the LDOSTATUS bits." "0,1,2,3" sif (!cpuis("AM335*")) group.long 0x40++0x3 line.long 0x00 "USBOTG,USBOTG" hexmask.long.word 0x00 16.--31. 1. " TESTOTGCONFIG ,Used to control the OTG module" hexmask.long.word 0x00 6.--15. 1. " TESTOTGSTATUS ,The OTG status bits" endif group.long 0x44++0x3 line.long 0x00 "AD_INTERFACE_REG1,Bypass bits for internal analog to digital interface pins with the same name" bitfld.long 0x00 31. " USE_AD_DATA_REG ,Override for bits 30:29" "0,1" bitfld.long 0x00 30. " HS_TX_DATA ,HS_TX_DATA" "0,1" bitfld.long 0x00 29. " FS_TX_DATA ,FS_TX_DATA" "0,1" textline " " bitfld.long 0x00 28. " TEST_PRE_EN_CNTRL ,Override for bits 27:25" "0,1" bitfld.long 0x00 27. " SQ_PRE_EN ,SQ_PRE_EN" "0,1" bitfld.long 0x00 26. " HS_TX_PRE_EN ,HS_TX_PRE_EN" "0,1" textline " " bitfld.long 0x00 25. " HS_RX_PRE_EN ,HS_RX_PRE_EN" "0,1" bitfld.long 0x00 24. " TEST_EN_CNTRL ,Override for bits 23:19" "0,1" bitfld.long 0x00 23. " HS_TX_EN ,HS_TX_EN" "0,1" textline " " bitfld.long 0x00 22. " FS_RX_EN ,FS_RX_EN" "0,1" bitfld.long 0x00 20. " SQ_EN ,SQ_EN" "0,1" bitfld.long 0x00 19. " HS_RX_EN ,HS_RX_EN" "0,1" textline " " bitfld.long 0x00 18. " TEST_HS_MODE ,Override for bits 17:16" "0,1" bitfld.long 0x00 17. " HS_HV_SW ,HS_HV_SW" "0,1" bitfld.long 0x00 16. " HS_CHIRP ,HS_CHIRP" "0,1" textline " " bitfld.long 0x00 15. " TEST_FS_MODE ,Override for bits 14:12" "0,1" bitfld.long 0x00 14. " FSTX_GZ ,FSTX_GZ" "0,1" bitfld.long 0x00 13. " FSTX_PRE_EN ,FSTX_PRE_EN" "0,1" textline " " bitfld.long 0x00 11. " TEST_SQ_CAL_CONTROL ,Override for bits 10:8" "0,1" bitfld.long 0x00 10. " SQ_CAL_EN3 ,SQ_CAL_EN3" "0,1" bitfld.long 0x00 9. " SQ_CAL_EN1 ,SQ_CAL_EN1" "0,1" textline " " bitfld.long 0x00 8. " SQ_CAL_EN2 ,SQ_CAL_EN2" "0,1" bitfld.long 0x00 7. " TEST_RTERM_CAL_CONTROL ,Override for bits 6" "0,1" bitfld.long 0x00 6. " RTERM_CAL_EN ,RTERM_CAL_EN" "0,1" textline " " bitfld.long 0x00 5. " DLL_RX_DATA ,DLL_RX_DATA" "0,1" bitfld.long 0x00 4. " DISCON_DETECT ,DISCON_DETECT" "0,1" bitfld.long 0x00 3. " USE_LSHOST_REG ,Use bit 2 for this reg" "0,1" textline " " bitfld.long 0x00 2. " LSHOSTMODE ,LSHOSTMODE" "0,1" bitfld.long 0x00 1. " LSFS_RX_DATA ,LSFS_RX_DATA" "0,1" bitfld.long 0x00 0. " SQUELCH ,SQUELCH" "0,1" group.long 0x48++0x3 line.long 0x00 "AD_INTERFACE_REG2,Bypass bits for internal analog to digital interface pins with the same name" bitfld.long 0x00 31. " USE_SUSP_DRV_REG ,Use bits 30:27 from this register as overrides" "0,1" bitfld.long 0x00 30. " SUS_DRV_DP_DATA ,SUS_DRV_DP_DATA" "0,1" bitfld.long 0x00 29. " SUS_DRV_DP_EN ,SUS_DRV_DP_EN" "0,1" textline " " bitfld.long 0x00 28. " SUS_DRV_DM_DATA ,SUS_DRV_DM_DATA" "0,1" bitfld.long 0x00 27. " SUS_DRV_DM_EN ,SUS_DRV_DM_EN" "0,1" bitfld.long 0x00 26. " USE_DISCON_REG ,Use bits 25:24 from this register as override" "0,1" textline " " bitfld.long 0x00 25. " DISCON_EN ,DISCON_EN" "0,1" bitfld.long 0x00 24. " DISCON_PRE_EN ,DISCON_PRE_EN" "0,1" bitfld.long 0x00 18.--22. " SPARE_OUT_CORE ,SPARE_OUT_CORE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 17. " SERX_DP_CORE ,SERX_DP_CORE" "0,1" bitfld.long 0x00 16. " SERX_DM_CORE ,SERX_DM_CORE" "0,1" bitfld.long 0x00 15. " USE_HSRX_CAL_EN_REG ,Use bit 14 from this register as override" "0,1" textline " " bitfld.long 0x00 14. " HSRX_CAL_EN ,HSRX_CAL_EN" "0,1" bitfld.long 0x00 13. " USE_RPU_RPD_REG ,Use override from bits 12:7" "0,1" bitfld.long 0x00 12. " RPU_DP_SW1_EN_CORE ,RPU_DP_SW1_EN_CORE" "0,1" textline " " bitfld.long 0x00 11. " RPU_DP_SW2_EN_CORE ,RPU_DP_SW2_EN_CORE" "0,1" bitfld.long 0x00 10. " RPU_DM_SW1_EN_CORE ,RPU_DM_SW1_EN_CORE" "0,1" bitfld.long 0x00 9. " RPU_DM_SW2_EN_CORE ,RPU_DM_SW2_EN_CORE" "0,1" textline " " bitfld.long 0x00 8. " DP_PULLDOWN_EN_CORE ,DP_PULLDOWN_EN_CORE" "0,1" bitfld.long 0x00 7. " DM_PULLDOWN_EN_CORE ,DM_PULLDOWN_EN_CORE" "0,1" bitfld.long 0x00 6. " DP_DM_5V_SHORT ,DP_DM_5V_SHORT" "0,1" textline " " bitfld.long 0x00 1.--5. " SPARE_IN_CORE ,SPARE_IN_CORE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " PORZ ,Read only bit - the PORZ generated from the digital registered on the A-D interface." "0,1" group.long 0x4C++0x3 line.long 0x00 "AD_INTERFACE_REG3,Bypass bits for internal analog to digital interface pins with the same name" bitfld.long 0x00 31. " USE_HSOS_DATA_REG ,Use bits 30:23 in this register as bypass bits" "0,1" hexmask.long.byte 0x00 23.--30. 1. " HSOS_DATA ,HSOS_DATA" bitfld.long 0x00 22. " USE_FS_REG3 ,Use bits 21:20 as bypass bits" "0,1" textline " " bitfld.long 0x00 21. " FSTX_MODE ,FSTX_MODE" "0,1" bitfld.long 0x00 20. " FSTX_SE0 ,FSTX_SE0" "0,1" bitfld.long 0x00 19. " USE_HS_TERM_RES_REG ,Use bit 18 as override bit" "0,1" textline " " bitfld.long 0x00 18. " HS_TERM_RES ,HS_TERM_RES" "0,1" hexmask.long.byte 0x00 10.--17. 1. " SPARE_IN_LDO ,SPARE_IN_LDO" hexmask.long.byte 0x00 2.--9. 1. " SPARE_OUT_LDO ,SPARE_OUT_LDO" textline " " bitfld.long 0x00 1. " USE_FARCORE_REG ,Use bit 0 from this register as bypass" "0,1" bitfld.long 0x00 0. " FARCORE ,FARCORE" "0,1" sif (!cpuis("AM335*")) group.long 0x50++0x3 line.long 0x00 "ANA_CONFIG1,Used to configure and debug the analog blocks." hexmask.long.word 0x00 17.--31. 1. " SQ_CTRL_REG ,SQ_CTRL_REG" bitfld.long 0x00 14.--16. " FS_SLEW ,FS_SLEW" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " HS_PRE_EMP_CNTRL ,HS_PRE_EMP_CNTRL" "0,1,2,3" textline " " hexmask.long.byte 0x00 5.--11. 1. " HSFSTX_TEST ,HSFSTX_TEST" bitfld.long 0x00 0.--4. " PROTECT_TEST ,PROTECT_TEST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x54++0x3 line.long 0x00 "ANA_CONFIG2,Configure and debug the analog blocks" sif (!cpuis("AM335*")) bitfld.long 0x00 27.--31. " RTERM_CAL_TEST ,RTERM_CAL_TEST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " endif hexmask.long.byte 0x00 20.--26. 1. " REF_GEN_TEST ,NOT IMPLEMENTED" sif (!cpuis("AM335*")) bitfld.long 0x00 18.--19. " FSRX_TEST ,FSRX_TEST" "0,1,2,3" endif textline " " sif (cpuis("AM335*")) bitfld.long 0x00 15.--17. " RTERM_TEST ,RTERM_TEST0x0 is default 0x3 decreases the termination impedance by 2 to 3% (can be used to get 1 to 1.5% better eye vertical opening)" "0,1,2,3,4,5,6,7" else bitfld.long 0x00 15.--19. " RTERM_TEST ,RTERM_TEST0x0 is default 0x3 decreases the termination impedance by 2 to 3% (can be used to get 1 to 1.5% better eye vertical opening)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif textline " " sif (!cpuis("AM335*")) bitfld.long 0x00 11.--14. " DISCON_TEST ,DISCON_TEST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--10. " HSRX_TEST ,HSRX_TEST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 3.--5. " SERX_TEST ,SERX_TEST" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--2. " SERX_HYST_CNTRL ,SERX_HYST_CNTRL" "0,1,2,3" bitfld.long 0x00 0. " SQ_LPMODEZ ,SQ_LPMODEZ" "0,1" endif width 0xb tree.end tree.end tree "USB Controller" tree "USB0 Controller Registers" base ad:0x47401000 width 18. rgroup.long 0x00++0x03 line.long 0x00 "USB0REV,USB0 Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "Legacy ASP or WTBU,Highlander 0.8,?..." hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x14++0x03 line.long 0x00 "USB0CONTROL,USB0 Control Register" bitfld.long 0x00 31. " DIS_DEB ,Disable the VBUS debouncer circuit fix" "No,Yes" bitfld.long 0x00 30. " DIS_SRP ,Disable the SRP a_valid circuit fix" "No,Yes" textline " " sif ((cpuis("DM814?DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")) bitfld.long 0x00 5. " SRI ,Soft reset isolation" "Disabled,Enabled" bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled" else bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled" endif textline " " bitfld.long 0x00 3. " UINT ,USB non-Highlander interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " CLKFACK ,Clock stop fast ack enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SOFT_RESET ,Software reset of USB0" "No reset,Reset" rgroup.long 0x18++0x03 line.long 0x00 "USB0STATUS,USB0 Status Register" bitfld.long 0x00 0. " DRVVBUS ,Current DRVVBUS value" "Low,High" rgroup.long 0x20++0x03 line.long 0x00 "USB0IRQMSTAT,USB0 IRQ Merged Status Register" bitfld.long 0x00 1. " BANK1 ,Events from IRQ_STATUS_1" "Not pending,Pending" textline " " bitfld.long 0x00 0. " BANK0 ,Events from IRQ_STATUS_0" "Not pending,Pending" sif (!cpuis("AM335*")) group.long 0x24++03 line.long 0x00 "USB0IRQEOI,USB0 IRQ End of Interrupt Register" bitfld.long 0x00 0. " EOI ,End of interrupt" "Low,High" endif group.long 0x28++0x1F line.long 0x00 "USB0IRQSTATRAW0,USB0 IRQ Status Raw 0 Register" bitfld.long 0x00 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending" bitfld.long 0x00 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending" bitfld.long 0x00 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending" bitfld.long 0x00 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending" bitfld.long 0x00 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending" bitfld.long 0x00 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending" bitfld.long 0x00 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending" bitfld.long 0x00 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending" bitfld.long 0x00 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending" bitfld.long 0x00 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending" bitfld.long 0x00 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending" bitfld.long 0x00 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending" bitfld.long 0x00 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending" bitfld.long 0x00 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending" bitfld.long 0x00 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending" bitfld.long 0x00 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending" line.long 0x04 "USB0IRQSTATRAW1,USB0 IRQ Status Raw 1 Register" bitfld.long 0x04 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 9. " USB[9] , Mentor controller USB_INT generic interrupt raw status" "Not pending,Pending" bitfld.long 0x04 8. " USB[8] ,DRVVBUS level change interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 7. " USB[7] ,VBUS < VBUS valid threshold interrupt raw status" "Not pending,Pending" bitfld.long 0x04 6. " USB[6] ,SRP detected interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 5. " USB[5] ,Device disconnected interrupt raw status (host mode)" "Not pending,Pending" bitfld.long 0x04 4. " USB[4] ,Device connected interrupt raw status (host mode)" "Not pending,Pending" textline " " bitfld.long 0x04 3. " USB[3] ,SOF started interrupt raw status" "Not pending,Pending" bitfld.long 0x04 2. " USB[2] ,Reset signaling/Babble detected interrupt raw status (peripheral/host mode)" "Not pending,Pending" textline " " bitfld.long 0x04 1. " USB[1] ,Resume signaling interrupt raw status" "Not pending,Pending" bitfld.long 0x04 0. " USB[0] ,Suspend signaling interrupt raw status" "Not pending,Pending" line.long 0x08 "USB0IRQSTAT0,USB0 IRQ Status 0 Register" eventfld.long 0x08 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending" eventfld.long 0x08 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending" eventfld.long 0x08 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending" eventfld.long 0x08 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending" eventfld.long 0x08 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending" eventfld.long 0x08 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending" eventfld.long 0x08 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending" eventfld.long 0x08 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending" eventfld.long 0x08 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending" eventfld.long 0x08 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending" eventfld.long 0x08 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending" eventfld.long 0x08 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending" eventfld.long 0x08 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending" eventfld.long 0x08 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending" eventfld.long 0x08 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending" eventfld.long 0x08 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending" line.long 0x0C "USB0IRQSTAT1,USB0 IRQ Status 1 Register" eventfld.long 0x0C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt status" "Not pending,Pending" eventfld.long 0x0C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt status" "Not pending,Pending" eventfld.long 0x0C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt status" "Not pending,Pending" eventfld.long 0x0C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt status" "Not pending,Pending" eventfld.long 0x0C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt status" "Not pending,Pending" eventfld.long 0x0C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt status" "Not pending,Pending" eventfld.long 0x0C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt status" "Not pending,Pending" eventfld.long 0x0C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt status" "Not pending,Pending" eventfld.long 0x0C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 9. " USB[9] , Mentor controller USB_INT generic interrupt status" "Not pending,Pending" eventfld.long 0x0C 8. " USB[8] ,DRVVBUS level change interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt status" "Not pending,Pending" eventfld.long 0x0C 6. " USB[6] ,SRP detected interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 5. " USB[5] ,Device disconnected interrupt status (host mode)" "Not pending,Pending" eventfld.long 0x0C 4. " USB[4] ,Device connected interrupt status (host mode)" "Not pending,Pending" textline " " eventfld.long 0x0C 3. " USB[3] ,SOF started interrupt status" "Not pending,Pending" eventfld.long 0x0C 2. " USB[2] ,Reset signaling/Babble detected interrupt status (peripheral/host mode)" "Not pending,Pending" textline " " eventfld.long 0x0C 1. " USB[1] ,Resume signaling interrupt status" "Not pending,Pending" eventfld.long 0x0C 0. " USB[0] ,Suspend signaling interrupt status" "Not pending,Pending" line.long 0x10 "USB0IRQENABLESET0,USB0 IRQ Enable Set 0 Register" bitfld.long 0x10 31. " RX_EP15 ,RX EP15 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 30. " RX_EP14 ,RX EP14 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 29. " RX_EP13 ,RX EP13 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 28. " RX_EP12 ,RX EP12 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " RX_EP11 ,RX EP11 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 26. " RX_EP10 ,RX EP10 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " RX_EP9 ,RX EP9 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 24. " RX_EP8 ,RX EP8 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " RX_EP7 ,RX EP7 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 22. " RX_EP6 ,RX EP6 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 21. " RX_EP5 ,RX EP5 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 20. " RX_EP4 ,RX EP4 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " RX_EP3 ,RX EP3 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 18. " RX_EP2 ,RX EP2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 17. " RX_EP1 ,RX EP1 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 15. " TX_EP15 ,TX EP15 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 14. " TX_EP14 ,TX EP14 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 13. " TX_EP13 ,TX EP13 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 12. " TX_EP12 ,TX EP12 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 11. " TX_EP11 ,TX EP11 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " TX_EP10 ,TX EP10 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 9. " TX_EP9 ,TX EP9 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 8. " TX_EP8 ,TX EP8 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 7. " TX_EP7 ,TX EP7 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " TX_EP6 ,TX EP6 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 5. " TX_EP5 ,TX EP5 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " TX_EP4 ,TX EP4 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 3. " TX_EP3 ,TX EP3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 2. " TX_EP2 ,TX EP2 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 1. " TX_EP1 ,TX EP1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " TX_EP0 ,TX EP0 interrupt enable" "Disabled,Enabled" line.long 0x14 "USB0IRQENABLESET1,USB0 IRQ Enable Set 1 Register" bitfld.long 0x14 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 9. " USB[9] , Mentor controller USB_INT generic interrupt enable" "Disabled,Enabled" bitfld.long 0x14 8. " USB[8] ,DRVVBUS level change interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " USB[7] ,VBUS < VBUS valid threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x14 6. " USB[6] ,SRP detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " USB[5] ,Device disconnected interrupt enable status (host mode)" "Disabled,Enabled" bitfld.long 0x14 4. " USB[4] ,Device connected interrupt enable status (host mode)" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " USB[3] ,SOF started interrupt enable" "Disabled,Enabled" bitfld.long 0x14 2. " USB[2] ,Reset signaling/Babble detected interrupt enable status (peripheral/host mode)" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " USB[1] ,Resume signaling interrupt enable" "Disabled,Enabled" bitfld.long 0x14 0. " USB[0] ,Suspend signaling interrupt enable" "Disabled,Enabled" line.long 0x18 "USB0IRQENABLECLR0,USB0 IRQ Enable Clear 0 Register" eventfld.long 0x18 31. " RX_EP15 ,RX EP15 iinterrupt disable" "Disabled,Enabled" eventfld.long 0x18 30. " RX_EP14 ,RX EP14 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 29. " RX_EP13 ,RX EP13 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 28. " RX_EP12 ,RX EP12 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 27. " RX_EP11 ,RX EP11 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 26. " RX_EP10 ,RX EP10 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 25. " RX_EP9 ,RX EP9 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 24. " RX_EP8 ,RX EP8 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 23. " RX_EP7 ,RX EP7 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 22. " RX_EP6 ,RX EP6 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 21. " RX_EP5 ,RX EP5 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 20. " RX_EP4 ,RX EP4 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 19. " RX_EP3 ,RX EP3 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 18. " RX_EP2 ,RX EP2 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 17. " RX_EP1 ,RX EP1 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 15. " TX_EP15 ,TX EP15 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 14. " TX_EP14 ,TX EP14 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 13. " TX_EP13 ,TX EP13 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 12. " TX_EP12 ,TX EP12 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 11. " TX_EP11 ,TX EP11 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 10. " TX_EP10 ,TX EP10 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 9. " TX_EP9 ,TX EP9 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 8. " TX_EP8 ,TX EP8 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 7. " TX_EP7 ,TX EP7 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 6. " TX_EP6 ,TX EP6 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 5. " TX_EP5 ,TX EP5 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 4. " TX_EP4 ,TX EP4 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 3. " TX_EP3 ,TX EP3 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 2. " TX_EP2 ,TX EP2 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 1. " TX_EP1 ,TX EP1 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 0. " TX_EP0 ,TX EP0 interrupt disable" "Disabled,Enabled" line.long 0x1C "USB0IRQENABLECLR1,USB0 IRQ Enable Clear 1 Register" eventfld.long 0x1C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 9. " USB[9] , Mentor controller USB_INT generic interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 8. " USB[8] ,DRVVBUS level change interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 6. " USB[6] ,SRP detected interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 5. " USB[5] ,Device disconnected interrupt disable (host mode)" "Disabled,Enabled" eventfld.long 0x1C 4. " USB[4] ,Device connected interrupt disable (host mode)" "Disabled,Enabled" textline " " eventfld.long 0x1C 3. " USB[3] ,SOF started interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 2. " USB[2] ,Reset signaling/Babble detected interrupt disable (peripheral/host mode)" "Disabled,Enabled" textline " " eventfld.long 0x1C 1. " USB[1] ,Resume signaling interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 0. " USB[0] ,Suspend signaling interrupt disable" "Disabled,Enabled" group.long 0x70++0x07 line.long 0x00 "USB0TXMODE,USB0 Tx Mode Register" bitfld.long 0x00 28.--29. " TX15_MODE ,Endpoint 15 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 26.--27. " TX14_MODE ,Endpoint 14 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 24.--25. " TX13_MODE ,Endpoint 13 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 22.--23. " TX12_MODE ,Endpoint 12 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 20.--21. " TX11_MODE ,Endpoint 11 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 18.--19. " TX10_MODE ,Endpoint 10 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 16.--17. " TX9_MODE ,Endpoint 9 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 14.--15. " TX8_MODE ,Endpoint 8 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 12.--13. " TX7_MODE ,Endpoint 7 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 10.--11. " TX6_MODE ,Endpoint 6 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 8.--9. " TX5_MODE ,Endpoint 5 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 6.--7. " TX4_MODE ,Endpoint 4 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 4.--5. " TX3_MODE ,Endpoint 3 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 2.--3. " TX2_MODE ,Endpoint 2 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 0.--1. " TX1_MODE ,Endpoint 1 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" line.long 0x04 "USB0RXMODE,USB0 Rx Mode Register" bitfld.long 0x04 28.--29. " RX15_MODE ,Endpoint 15 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 26.--27. " RX14_MODE ,Endpoint 14 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 24.--25. " RX13_MODE ,Endpoint 13 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 22.--23. " RX12_MODE ,Endpoint 12 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 20.--21. " RX11_MODE ,Endpoint 11 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 18.--19. " RX10_MODE ,Endpoint 10 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 16.--17. " RX9_MODE ,Endpoint 9 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 14.--15. " RX8_MODE ,Endpoint 8 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 12.--13. " RX7_MODE ,Endpoint 7 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 10.--11. " RX6_MODE ,Endpoint 6 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 8.--9. " RX5_MODE ,Endpoint 5 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 6.--7. " RX4_MODE ,Endpoint 4 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 4.--5. " RX3_MODE ,Endpoint 3 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 2.--3. " RX2_MODE ,Endpoint 2 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 0.--1. " RX1_MODE ,Endpoint 1 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" group.long 0x80++0x3B line.long 0x0 "USB0GENRNDISEP1,USB0 Generic RNDIS EP1 Size Register" hexmask.long.tbyte 0x0 0.--16. 1. " EP1_SIZE ,Generic RNDIS packeet size 1" line.long 0x4 "USB0GENRNDISEP2,USB0 Generic RNDIS EP2 Size Register" hexmask.long.tbyte 0x4 0.--16. 1. " EP2_SIZE ,Generic RNDIS packeet size 2" line.long 0x8 "USB0GENRNDISEP3,USB0 Generic RNDIS EP3 Size Register" hexmask.long.tbyte 0x8 0.--16. 1. " EP3_SIZE ,Generic RNDIS packeet size 3" line.long 0xC "USB0GENRNDISEP4,USB0 Generic RNDIS EP4 Size Register" hexmask.long.tbyte 0xC 0.--16. 1. " EP4_SIZE ,Generic RNDIS packeet size 4" line.long 0x10 "USB0GENRNDISEP5,USB0 Generic RNDIS EP5 Size Register" hexmask.long.tbyte 0x10 0.--16. 1. " EP5_SIZE ,Generic RNDIS packeet size 5" line.long 0x14 "USB0GENRNDISEP6,USB0 Generic RNDIS EP6 Size Register" hexmask.long.tbyte 0x14 0.--16. 1. " EP6_SIZE ,Generic RNDIS packeet size 6" line.long 0x18 "USB0GENRNDISEP7,USB0 Generic RNDIS EP7 Size Register" hexmask.long.tbyte 0x18 0.--16. 1. " EP7_SIZE ,Generic RNDIS packeet size 7" line.long 0x1C "USB0GENRNDISEP8,USB0 Generic RNDIS EP8 Size Register" hexmask.long.tbyte 0x1C 0.--16. 1. " EP8_SIZE ,Generic RNDIS packeet size 8" line.long 0x20 "USB0GENRNDISEP9,USB0 Generic RNDIS EP9 Size Register" hexmask.long.tbyte 0x20 0.--16. 1. " EP9_SIZE ,Generic RNDIS packeet size 9" line.long 0x24 "USB0GENRNDISEP10,USB0 Generic RNDIS EP10 Size Register" hexmask.long.tbyte 0x24 0.--16. 1. " EP10_SIZE ,Generic RNDIS packeet size 10" line.long 0x28 "USB0GENRNDISEP11,USB0 Generic RNDIS EP11 Size Register" hexmask.long.tbyte 0x28 0.--16. 1. " EP11_SIZE ,Generic RNDIS packeet size 11" line.long 0x2C "USB0GENRNDISEP12,USB0 Generic RNDIS EP12 Size Register" hexmask.long.tbyte 0x2C 0.--16. 1. " EP12_SIZE ,Generic RNDIS packeet size 12" line.long 0x30 "USB0GENRNDISEP13,USB0 Generic RNDIS EP13 Size Register" hexmask.long.tbyte 0x30 0.--16. 1. " EP13_SIZE ,Generic RNDIS packeet size 13" line.long 0x34 "USB0GENRNDISEP14,USB0 Generic RNDIS EP14 Size Register" hexmask.long.tbyte 0x34 0.--16. 1. " EP14_SIZE ,Generic RNDIS packeet size 14" line.long 0x38 "USB0GENRNDISEP15,USB0 Generic RNDIS EP15 Size Register" hexmask.long.tbyte 0x38 0.--16. 1. " EP15_SIZE ,Generic RNDIS packeet size 15" group.long 0xD0++0xB line.long 0x00 "USB0AUTOREQ,USB0 Auto Req Register" bitfld.long 0x00 28.--29. " RX15_AUTOREQ ,RX endpoint 15 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 26.--27. " RX14_AUTOREQ ,RX endpoint 14 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 24.--25. " RX13_AUTOREQ ,RX endpoint 13 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 22.--23. " RX12_AUTOREQ ,RX endpoint 12 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 20.--21. " RX11_AUTOREQ ,RX endpoint 11 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 18.--19. " RX10_AUTOREQ ,RX endpoint 10 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 16.--17. " RX9_AUTOREQ ,RX endpoint 9 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 14.--15. " RX8_AUTOREQ ,RX endpoint 8 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 12.--13. " RX7_AUTOREQ ,RX endpoint 7 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 10.--11. " RX6_AUTOREQ ,RX endpoint 6 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 8.--9. " RX5_AUTOREQ ,RX endpoint 5 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 6.--7. " RX4_AUTOREQ ,RX endpoint 4 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 4.--5. " RX3_AUTOREQ ,RX endpoint 3 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 2.--3. " RX2_AUTOREQ ,RX endpoint 2 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 0.--1. " RX1_AUTOREQ ,RX endpoint 1 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" line.long 0x04 "USB0SRPFIXTIME,USB0 SRP Fix Time Register" line.long 0x08 "USB0TDOWN,USB0 Teardown Register" bitfld.long 0x08 31. " TX_TDOWN15 ,Transmit endpoint 15 teardown" "Disabled,Enabled" bitfld.long 0x08 30. " TX_TDOWN14 ,Transmit endpoint 14 teardown" "Disabled,Enabled" bitfld.long 0x08 29. " TX_TDOWN13 ,Transmit endpoint 13 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " TX_TDOWN12 ,Transmit endpoint 12 teardown" "Disabled,Enabled" bitfld.long 0x08 27. " TX_TDOWN11 ,Transmit endpoint 11 teardown" "Disabled,Enabled" bitfld.long 0x08 26. " TX_TDOWN10 ,Transmit endpoint 10 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 25. " TX_TDOWN9 ,Transmit endpoint 9 teardown" "Disabled,Enabled" bitfld.long 0x08 24. " TX_TDOWN8 ,Transmit endpoint 8 teardown" "Disabled,Enabled" bitfld.long 0x08 23. " TX_TDOWN7 ,Transmit endpoint 7 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 22. " TX_TDOWN6 ,Transmit endpoint 6 teardown" "Disabled,Enabled" bitfld.long 0x08 21. " TX_TDOWN5 ,Transmit endpoint 5 teardown" "Disabled,Enabled" bitfld.long 0x08 20. " TX_TDOWN4 ,Transmit endpoint 4 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " TX_TDOWN3 ,Transmit endpoint 3 teardown" "Disabled,Enabled" bitfld.long 0x08 18. " TX_TDOWN2 ,Transmit endpoint 2 teardown" "Disabled,Enabled" bitfld.long 0x08 17. " TX_TDOWN1 ,Transmit endpoint 1 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 15. " RX_TDOWN15 ,Receive endpoint 15 teardown" "Disabled,Enabled" bitfld.long 0x08 14. " RX_TDOWN14 ,Receive endpoint 14 teardown" "Disabled,Enabled" bitfld.long 0x08 13. " RX_TDOWN13 ,Receive endpoint 13 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 12. " RX_TDOWN12 ,Receive endpoint 12 teardown" "Disabled,Enabled" bitfld.long 0x08 11. " RX_TDOWN11 ,Receive endpoint 11 teardown" "Disabled,Enabled" bitfld.long 0x08 10. " RX_TDOWN10 ,Receive endpoint 10 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " RX_TDOWN9 ,Receive endpoint 9 teardown" "Disabled,Enabled" bitfld.long 0x08 8. " RX_TDOWN8 ,Receive endpoint 8 teardown" "Disabled,Enabled" bitfld.long 0x08 7. " RX_TDOWN7 ,Receive endpoint 7 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 6. " RX_TDOWN6 ,Receive endpoint 6 teardown" "Disabled,Enabled" bitfld.long 0x08 5. " RX_TDOWN5 ,Receive endpoint 5 teardown" "Disabled,Enabled" bitfld.long 0x08 4. " RX_TDOWN4 ,Receive endpoint 4 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " RX_TDOWN3 ,Receive endpoint 3 teardown" "Disabled,Enabled" bitfld.long 0x08 2. " RX_TDOWN2 ,Receive endpoint 2 teardown" "Disabled,Enabled" bitfld.long 0x08 1. " RX_TDOWN1 ,Receive endpoint 1 teardown" "Disabled,Enabled" sif cpuis("DM814?DSP") group.long 0xDC++0x03 line.long 0x00 "USB0THRESXDMA,USB0 Threshold XDMA Idle Register" hexmask.long.byte 0x00 0.--7. 0x1 " THRES_XDMA_IDLE ,Threshold XDMA Idle cycle parameter" endif group.long 0xE0++0x0B line.long 0x00 "USB0UTMI,USB0 PHY UTMI Register" bitfld.long 0x00 23. " TXBITSTUFFEN ,Input for signal txbitstuffen" "Low,High" sif !cpuis("DM814?DSP") bitfld.long 0x00 22. " TXBITSTUFFENH ,Input for signal txbitstuffenh" "Low,High" textline " " bitfld.long 0x00 21. " OTGDISABLE ,Input for signal otgdisable" "Low,High" bitfld.long 0x00 20. " VBUSVLDEXTSEL ,Input for signal vbusvldextsel" "Low,High" textline " " bitfld.long 0x00 19. " VBUSVLDEXT ,Input for signal vbusvldext" "Low,High" endif bitfld.long 0x00 18. " TXENABLEN ,Input for signal txenablen" "Low,High" sif !cpuis("DM814?DSP") textline " " bitfld.long 0x00 17. " FSXCVROWNER ,Input for signal fsxcvrowner" "Low,High" bitfld.long 0x00 16. " TXVALIDH ,Input for signal txvalidh" "Low,High" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAINH ,Input for signal datainh" bitfld.long 0x00 2. " WORDINTERFACE ,Input for signal wordinterface" "Low,High" textline " " bitfld.long 0x00 1. " FSDATAEXT ,Input for signal fsdataext" "Low,High" bitfld.long 0x00 0. " FSSE0EXT ,Input for signal fsse0ext" "Low,High" endif line.long 0x04 "USB0UTMILB,USB0 MGC UTMI Loopback Register" sif (cpuis("DM814?DSP")||cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High" rbitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3" textline " " rbitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High" rbitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3" textline " " rbitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High" rbitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High" textline " " rbitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High" rbitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High" textline " " rbitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High" rbitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High" textline " " rbitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High" else bitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High" bitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3" textline " " bitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High" bitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3" textline " " bitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High" bitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High" textline " " bitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High" bitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High" textline " " bitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High" bitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High" textline " " bitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High" endif bitfld.long 0x04 11. " IDDIG ,LB test value for iddig" "Low,High" textline " " bitfld.long 0x04 10. " HOSTDISCON ,LB test value for hostdiscon" "Low,High" bitfld.long 0x04 9. " SESSEND ,LB test value for sessend" "Low,High" textline " " bitfld.long 0x04 8. " AVALID ,LB test value for avalid" "Low,High" bitfld.long 0x04 7. " VBUSVALID ,LB test value for vbusvalid" "Low,High" textline " " bitfld.long 0x04 6. " RXERROR ,LB test value for rxerror" "Low,High" bitfld.long 0x04 2.--3. " LINESTATE ,LB test value for linestate" "0,1,2,3" line.long 0x08 "USB0MODE,USB0 Mode Register" bitfld.long 0x08 8. " IDDIG ,MGC input value for IDDIG" "A-type,B-type" textline " " sif (cpuis("AM335*")) bitfld.long 0x08 7. " IDDIG_MUX ,Multiplexer control for IDDIG signal going to the controller" "From PHY,From bit 8 (IDDIG)" textline " " endif bitfld.long 0x08 1. " PHY_TEST ,PHY test" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " LOOPBACK ,Loopback test mode" "Disabled,Enabled" width 0xb tree.end tree "USB1 Controller Registers" base ad:0x47401800 width 18. rgroup.long 0x00++0x03 line.long 0x00 "USB1REV,USB1 Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "Legacy ASP or WTBU,Highlander 0.8,?..." hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x14++0x03 line.long 0x00 "USB1CONTROL,USB1 Control Register" bitfld.long 0x00 31. " DIS_DEB ,Disable the VBUS debouncer circuit fix" "No,Yes" bitfld.long 0x00 30. " DIS_SRP ,Disable the SRP a_valid circuit fix" "No,Yes" textline " " sif ((cpuis("DM814?DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")) bitfld.long 0x00 5. " SRI ,Soft reset isolation" "Disabled,Enabled" bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled" else bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled" endif textline " " bitfld.long 0x00 3. " UINT ,USB non-Highlander interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " CLKFACK ,Clock stop fast ack enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SOFT_RESET ,Software reset of USB1" "No reset,Reset" rgroup.long 0x18++0x03 line.long 0x00 "USB1STATUS,USB1 Status Register" bitfld.long 0x00 0. " DRVVBUS ,Current DRVVBUS value" "Low,High" rgroup.long 0x20++0x03 line.long 0x00 "USB1IRQMSTAT,USB1 IRQ Merged Status Register" bitfld.long 0x00 1. " BANK1 ,Events from IRQ_STATUS_1" "Not pending,Pending" textline " " bitfld.long 0x00 0. " BANK0 ,Events from IRQ_STATUS_0" "Not pending,Pending" sif (!cpuis("AM335*")) group.long 0x24++03 line.long 0x00 "USB1IRQEOI,USB1 IRQ End of Interrupt Register" bitfld.long 0x00 0. " EOI ,End of interrupt" "Low,High" endif group.long 0x28++0x1F line.long 0x00 "USB1IRQSTATRAW0,USB1 IRQ Status Raw 0 Register" bitfld.long 0x00 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending" bitfld.long 0x00 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending" bitfld.long 0x00 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending" bitfld.long 0x00 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending" bitfld.long 0x00 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending" bitfld.long 0x00 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending" bitfld.long 0x00 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending" bitfld.long 0x00 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending" bitfld.long 0x00 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending" bitfld.long 0x00 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending" bitfld.long 0x00 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending" bitfld.long 0x00 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending" bitfld.long 0x00 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending" bitfld.long 0x00 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending" bitfld.long 0x00 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending" bitfld.long 0x00 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending" textline " " bitfld.long 0x00 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending" line.long 0x04 "USB1IRQSTATRAW1,USB1 IRQ Status Raw 1 Register" bitfld.long 0x04 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt raw status" "Not pending,Pending" bitfld.long 0x04 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 9. " USB[9] , Mentor controller USB_INT generic interrupt raw status" "Not pending,Pending" bitfld.long 0x04 8. " USB[8] ,DRVVBUS level change interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 7. " USB[7] ,VBUS < VBUS valid threshold interrupt raw status" "Not pending,Pending" bitfld.long 0x04 6. " USB[6] ,SRP detected interrupt raw status" "Not pending,Pending" textline " " bitfld.long 0x04 5. " USB[5] ,Device disconnected interrupt raw status (host mode)" "Not pending,Pending" bitfld.long 0x04 4. " USB[4] ,Device connected interrupt raw status (host mode)" "Not pending,Pending" textline " " bitfld.long 0x04 3. " USB[3] ,SOF started interrupt raw status" "Not pending,Pending" bitfld.long 0x04 2. " USB[2] ,Reset signaling/Babble detected interrupt raw status (peripheral/host mode)" "Not pending,Pending" textline " " bitfld.long 0x04 1. " USB[1] ,Resume signaling interrupt raw status" "Not pending,Pending" bitfld.long 0x04 0. " USB[0] ,Suspend signaling interrupt raw status" "Not pending,Pending" line.long 0x08 "USB1IRQSTAT0,USB1 IRQ Status 0 Register" eventfld.long 0x08 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending" eventfld.long 0x08 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending" eventfld.long 0x08 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending" eventfld.long 0x08 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending" eventfld.long 0x08 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending" eventfld.long 0x08 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending" eventfld.long 0x08 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending" eventfld.long 0x08 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending" eventfld.long 0x08 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending" eventfld.long 0x08 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending" eventfld.long 0x08 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending" eventfld.long 0x08 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending" eventfld.long 0x08 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending" eventfld.long 0x08 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending" eventfld.long 0x08 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending" eventfld.long 0x08 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x08 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending" line.long 0x0C "USB1IRQSTAT1,USB1 IRQ Status 1 Register" eventfld.long 0x0C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt status" "Not pending,Pending" eventfld.long 0x0C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt status" "Not pending,Pending" eventfld.long 0x0C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt status" "Not pending,Pending" eventfld.long 0x0C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt status" "Not pending,Pending" eventfld.long 0x0C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt status" "Not pending,Pending" eventfld.long 0x0C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt status" "Not pending,Pending" eventfld.long 0x0C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt status" "Not pending,Pending" eventfld.long 0x0C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt status" "Not pending,Pending" eventfld.long 0x0C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 9. " USB[9] , Mentor controller USB_INT generic interrupt status" "Not pending,Pending" eventfld.long 0x0C 8. " USB[8] ,DRVVBUS level change interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt status" "Not pending,Pending" eventfld.long 0x0C 6. " USB[6] ,SRP detected interrupt status" "Not pending,Pending" textline " " eventfld.long 0x0C 5. " USB[5] ,Device disconnected interrupt status (host mode)" "Not pending,Pending" eventfld.long 0x0C 4. " USB[4] ,Device connected interrupt status (host mode)" "Not pending,Pending" textline " " eventfld.long 0x0C 3. " USB[3] ,SOF started interrupt status" "Not pending,Pending" eventfld.long 0x0C 2. " USB[2] ,Reset signaling/Babble detected interrupt status (peripheral/host mode)" "Not pending,Pending" textline " " eventfld.long 0x0C 1. " USB[1] ,Resume signaling interrupt status" "Not pending,Pending" eventfld.long 0x0C 0. " USB[0] ,Suspend signaling interrupt status" "Not pending,Pending" line.long 0x10 "USB1IRQENABLESET0,USB1 IRQ Enable Set 0 Register" bitfld.long 0x10 31. " RX_EP15 ,RX EP15 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 30. " RX_EP14 ,RX EP14 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 29. " RX_EP13 ,RX EP13 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 28. " RX_EP12 ,RX EP12 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " RX_EP11 ,RX EP11 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 26. " RX_EP10 ,RX EP10 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " RX_EP9 ,RX EP9 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 24. " RX_EP8 ,RX EP8 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " RX_EP7 ,RX EP7 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 22. " RX_EP6 ,RX EP6 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 21. " RX_EP5 ,RX EP5 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 20. " RX_EP4 ,RX EP4 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " RX_EP3 ,RX EP3 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 18. " RX_EP2 ,RX EP2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 17. " RX_EP1 ,RX EP1 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 15. " TX_EP15 ,TX EP15 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 14. " TX_EP14 ,TX EP14 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 13. " TX_EP13 ,TX EP13 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 12. " TX_EP12 ,TX EP12 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 11. " TX_EP11 ,TX EP11 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " TX_EP10 ,TX EP10 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 9. " TX_EP9 ,TX EP9 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 8. " TX_EP8 ,TX EP8 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 7. " TX_EP7 ,TX EP7 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " TX_EP6 ,TX EP6 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 5. " TX_EP5 ,TX EP5 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " TX_EP4 ,TX EP4 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 3. " TX_EP3 ,TX EP3 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 2. " TX_EP2 ,TX EP2 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 1. " TX_EP1 ,TX EP1 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " TX_EP0 ,TX EP0 interrupt enable" "Disabled,Enabled" line.long 0x14 "USB1IRQENABLESET1,USB1 IRQ Enable Set 1 Register" bitfld.long 0x14 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x14 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 9. " USB[9] , Mentor controller USB_INT generic interrupt enable" "Disabled,Enabled" bitfld.long 0x14 8. " USB[8] ,DRVVBUS level change interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " USB[7] ,VBUS < VBUS valid threshold interrupt enable" "Disabled,Enabled" bitfld.long 0x14 6. " USB[6] ,SRP detected interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 5. " USB[5] ,Device disconnected interrupt enable status (host mode)" "Disabled,Enabled" bitfld.long 0x14 4. " USB[4] ,Device connected interrupt enable status (host mode)" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " USB[3] ,SOF started interrupt enable" "Disabled,Enabled" bitfld.long 0x14 2. " USB[2] ,Reset signaling/Babble detected interrupt enable status (peripheral/host mode)" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " USB[1] ,Resume signaling interrupt enable" "Disabled,Enabled" bitfld.long 0x14 0. " USB[0] ,Suspend signaling interrupt enable" "Disabled,Enabled" line.long 0x18 "USB1IRQENABLECLR0,USB1 IRQ Enable Clear 0 Register" eventfld.long 0x18 31. " RX_EP15 ,RX EP15 iinterrupt disable" "Disabled,Enabled" eventfld.long 0x18 30. " RX_EP14 ,RX EP14 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 29. " RX_EP13 ,RX EP13 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 28. " RX_EP12 ,RX EP12 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 27. " RX_EP11 ,RX EP11 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 26. " RX_EP10 ,RX EP10 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 25. " RX_EP9 ,RX EP9 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 24. " RX_EP8 ,RX EP8 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 23. " RX_EP7 ,RX EP7 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 22. " RX_EP6 ,RX EP6 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 21. " RX_EP5 ,RX EP5 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 20. " RX_EP4 ,RX EP4 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 19. " RX_EP3 ,RX EP3 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 18. " RX_EP2 ,RX EP2 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 17. " RX_EP1 ,RX EP1 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 15. " TX_EP15 ,TX EP15 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 14. " TX_EP14 ,TX EP14 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 13. " TX_EP13 ,TX EP13 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 12. " TX_EP12 ,TX EP12 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 11. " TX_EP11 ,TX EP11 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 10. " TX_EP10 ,TX EP10 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 9. " TX_EP9 ,TX EP9 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 8. " TX_EP8 ,TX EP8 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 7. " TX_EP7 ,TX EP7 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 6. " TX_EP6 ,TX EP6 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 5. " TX_EP5 ,TX EP5 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 4. " TX_EP4 ,TX EP4 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 3. " TX_EP3 ,TX EP3 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 2. " TX_EP2 ,TX EP2 interrupt disable" "Disabled,Enabled" eventfld.long 0x18 1. " TX_EP1 ,TX EP1 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x18 0. " TX_EP0 ,TX EP0 interrupt disable" "Disabled,Enabled" line.long 0x1C "USB1IRQENABLECLR1,USB1 IRQ Enable Clear 1 Register" eventfld.long 0x1C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 9. " USB[9] , Mentor controller USB_INT generic interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 8. " USB[8] ,DRVVBUS level change interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 6. " USB[6] ,SRP detected interrupt disable" "Disabled,Enabled" textline " " eventfld.long 0x1C 5. " USB[5] ,Device disconnected interrupt disable (host mode)" "Disabled,Enabled" eventfld.long 0x1C 4. " USB[4] ,Device connected interrupt disable (host mode)" "Disabled,Enabled" textline " " eventfld.long 0x1C 3. " USB[3] ,SOF started interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 2. " USB[2] ,Reset signaling/Babble detected interrupt disable (peripheral/host mode)" "Disabled,Enabled" textline " " eventfld.long 0x1C 1. " USB[1] ,Resume signaling interrupt disable" "Disabled,Enabled" eventfld.long 0x1C 0. " USB[0] ,Suspend signaling interrupt disable" "Disabled,Enabled" group.long 0x70++0x07 line.long 0x00 "USB1TXMODE,USB1 Tx Mode Register" bitfld.long 0x00 28.--29. " TX15_MODE ,Endpoint 15 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 26.--27. " TX14_MODE ,Endpoint 14 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 24.--25. " TX13_MODE ,Endpoint 13 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 22.--23. " TX12_MODE ,Endpoint 12 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 20.--21. " TX11_MODE ,Endpoint 11 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 18.--19. " TX10_MODE ,Endpoint 10 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 16.--17. " TX9_MODE ,Endpoint 9 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 14.--15. " TX8_MODE ,Endpoint 8 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 12.--13. " TX7_MODE ,Endpoint 7 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 10.--11. " TX6_MODE ,Endpoint 6 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 8.--9. " TX5_MODE ,Endpoint 5 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 6.--7. " TX4_MODE ,Endpoint 4 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 4.--5. " TX3_MODE ,Endpoint 3 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x00 2.--3. " TX2_MODE ,Endpoint 2 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x00 0.--1. " TX1_MODE ,Endpoint 1 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS" line.long 0x04 "USB1RXMODE,USB1 Rx Mode Register" bitfld.long 0x04 28.--29. " RX15_MODE ,Endpoint 15 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 26.--27. " RX14_MODE ,Endpoint 14 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 24.--25. " RX13_MODE ,Endpoint 13 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 22.--23. " RX12_MODE ,Endpoint 12 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 20.--21. " RX11_MODE ,Endpoint 11 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 18.--19. " RX10_MODE ,Endpoint 10 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 16.--17. " RX9_MODE ,Endpoint 9 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 14.--15. " RX8_MODE ,Endpoint 8 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 12.--13. " RX7_MODE ,Endpoint 7 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 10.--11. " RX6_MODE ,Endpoint 6 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 8.--9. " RX5_MODE ,Endpoint 5 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 6.--7. " RX4_MODE ,Endpoint 4 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 4.--5. " RX3_MODE ,Endpoint 3 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" bitfld.long 0x04 2.--3. " RX2_MODE ,Endpoint 2 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" textline " " bitfld.long 0x04 0.--1. " RX1_MODE ,Endpoint 1 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS" group.long 0x80++0x3B line.long 0x0 "USB1GENRNDISEP1,USB1 Generic RNDIS EP1 Size Register" hexmask.long.tbyte 0x0 0.--16. 1. " EP1_SIZE ,Generic RNDIS packeet size 1" line.long 0x4 "USB1GENRNDISEP2,USB1 Generic RNDIS EP2 Size Register" hexmask.long.tbyte 0x4 0.--16. 1. " EP2_SIZE ,Generic RNDIS packeet size 2" line.long 0x8 "USB1GENRNDISEP3,USB1 Generic RNDIS EP3 Size Register" hexmask.long.tbyte 0x8 0.--16. 1. " EP3_SIZE ,Generic RNDIS packeet size 3" line.long 0xC "USB1GENRNDISEP4,USB1 Generic RNDIS EP4 Size Register" hexmask.long.tbyte 0xC 0.--16. 1. " EP4_SIZE ,Generic RNDIS packeet size 4" line.long 0x10 "USB1GENRNDISEP5,USB1 Generic RNDIS EP5 Size Register" hexmask.long.tbyte 0x10 0.--16. 1. " EP5_SIZE ,Generic RNDIS packeet size 5" line.long 0x14 "USB1GENRNDISEP6,USB1 Generic RNDIS EP6 Size Register" hexmask.long.tbyte 0x14 0.--16. 1. " EP6_SIZE ,Generic RNDIS packeet size 6" line.long 0x18 "USB1GENRNDISEP7,USB1 Generic RNDIS EP7 Size Register" hexmask.long.tbyte 0x18 0.--16. 1. " EP7_SIZE ,Generic RNDIS packeet size 7" line.long 0x1C "USB1GENRNDISEP8,USB1 Generic RNDIS EP8 Size Register" hexmask.long.tbyte 0x1C 0.--16. 1. " EP8_SIZE ,Generic RNDIS packeet size 8" line.long 0x20 "USB1GENRNDISEP9,USB1 Generic RNDIS EP9 Size Register" hexmask.long.tbyte 0x20 0.--16. 1. " EP9_SIZE ,Generic RNDIS packeet size 9" line.long 0x24 "USB1GENRNDISEP10,USB1 Generic RNDIS EP10 Size Register" hexmask.long.tbyte 0x24 0.--16. 1. " EP10_SIZE ,Generic RNDIS packeet size 10" line.long 0x28 "USB1GENRNDISEP11,USB1 Generic RNDIS EP11 Size Register" hexmask.long.tbyte 0x28 0.--16. 1. " EP11_SIZE ,Generic RNDIS packeet size 11" line.long 0x2C "USB1GENRNDISEP12,USB1 Generic RNDIS EP12 Size Register" hexmask.long.tbyte 0x2C 0.--16. 1. " EP12_SIZE ,Generic RNDIS packeet size 12" line.long 0x30 "USB1GENRNDISEP13,USB1 Generic RNDIS EP13 Size Register" hexmask.long.tbyte 0x30 0.--16. 1. " EP13_SIZE ,Generic RNDIS packeet size 13" line.long 0x34 "USB1GENRNDISEP14,USB1 Generic RNDIS EP14 Size Register" hexmask.long.tbyte 0x34 0.--16. 1. " EP14_SIZE ,Generic RNDIS packeet size 14" line.long 0x38 "USB1GENRNDISEP15,USB1 Generic RNDIS EP15 Size Register" hexmask.long.tbyte 0x38 0.--16. 1. " EP15_SIZE ,Generic RNDIS packeet size 15" group.long 0xD0++0xB line.long 0x00 "USB1AUTOREQ,USB1 Auto Req Register" bitfld.long 0x00 28.--29. " RX15_AUTOREQ ,RX endpoint 15 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 26.--27. " RX14_AUTOREQ ,RX endpoint 14 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 24.--25. " RX13_AUTOREQ ,RX endpoint 13 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 22.--23. " RX12_AUTOREQ ,RX endpoint 12 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 20.--21. " RX11_AUTOREQ ,RX endpoint 11 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 18.--19. " RX10_AUTOREQ ,RX endpoint 10 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 16.--17. " RX9_AUTOREQ ,RX endpoint 9 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 14.--15. " RX8_AUTOREQ ,RX endpoint 8 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 12.--13. " RX7_AUTOREQ ,RX endpoint 7 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 10.--11. " RX6_AUTOREQ ,RX endpoint 6 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 8.--9. " RX5_AUTOREQ ,RX endpoint 5 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 6.--7. " RX4_AUTOREQ ,RX endpoint 4 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 4.--5. " RX3_AUTOREQ ,RX endpoint 3 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" bitfld.long 0x00 2.--3. " RX2_AUTOREQ ,RX endpoint 2 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" textline " " bitfld.long 0x00 0.--1. " RX1_AUTOREQ ,RX endpoint 1 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled" line.long 0x04 "USB1SRPFIXTIME,USB1 SRP Fix Time Register" line.long 0x08 "USB1TDOWN,USB1 Teardown Register" bitfld.long 0x08 31. " TX_TDOWN15 ,Transmit endpoint 15 teardown" "Disabled,Enabled" bitfld.long 0x08 30. " TX_TDOWN14 ,Transmit endpoint 14 teardown" "Disabled,Enabled" bitfld.long 0x08 29. " TX_TDOWN13 ,Transmit endpoint 13 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " TX_TDOWN12 ,Transmit endpoint 12 teardown" "Disabled,Enabled" bitfld.long 0x08 27. " TX_TDOWN11 ,Transmit endpoint 11 teardown" "Disabled,Enabled" bitfld.long 0x08 26. " TX_TDOWN10 ,Transmit endpoint 10 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 25. " TX_TDOWN9 ,Transmit endpoint 9 teardown" "Disabled,Enabled" bitfld.long 0x08 24. " TX_TDOWN8 ,Transmit endpoint 8 teardown" "Disabled,Enabled" bitfld.long 0x08 23. " TX_TDOWN7 ,Transmit endpoint 7 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 22. " TX_TDOWN6 ,Transmit endpoint 6 teardown" "Disabled,Enabled" bitfld.long 0x08 21. " TX_TDOWN5 ,Transmit endpoint 5 teardown" "Disabled,Enabled" bitfld.long 0x08 20. " TX_TDOWN4 ,Transmit endpoint 4 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " TX_TDOWN3 ,Transmit endpoint 3 teardown" "Disabled,Enabled" bitfld.long 0x08 18. " TX_TDOWN2 ,Transmit endpoint 2 teardown" "Disabled,Enabled" bitfld.long 0x08 17. " TX_TDOWN1 ,Transmit endpoint 1 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 15. " RX_TDOWN15 ,Receive endpoint 15 teardown" "Disabled,Enabled" bitfld.long 0x08 14. " RX_TDOWN14 ,Receive endpoint 14 teardown" "Disabled,Enabled" bitfld.long 0x08 13. " RX_TDOWN13 ,Receive endpoint 13 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 12. " RX_TDOWN12 ,Receive endpoint 12 teardown" "Disabled,Enabled" bitfld.long 0x08 11. " RX_TDOWN11 ,Receive endpoint 11 teardown" "Disabled,Enabled" bitfld.long 0x08 10. " RX_TDOWN10 ,Receive endpoint 10 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " RX_TDOWN9 ,Receive endpoint 9 teardown" "Disabled,Enabled" bitfld.long 0x08 8. " RX_TDOWN8 ,Receive endpoint 8 teardown" "Disabled,Enabled" bitfld.long 0x08 7. " RX_TDOWN7 ,Receive endpoint 7 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 6. " RX_TDOWN6 ,Receive endpoint 6 teardown" "Disabled,Enabled" bitfld.long 0x08 5. " RX_TDOWN5 ,Receive endpoint 5 teardown" "Disabled,Enabled" bitfld.long 0x08 4. " RX_TDOWN4 ,Receive endpoint 4 teardown" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " RX_TDOWN3 ,Receive endpoint 3 teardown" "Disabled,Enabled" bitfld.long 0x08 2. " RX_TDOWN2 ,Receive endpoint 2 teardown" "Disabled,Enabled" bitfld.long 0x08 1. " RX_TDOWN1 ,Receive endpoint 1 teardown" "Disabled,Enabled" sif cpuis("DM814?DSP") group.long 0xDC++0x03 line.long 0x00 "USB1THRESXDMA,USB1 Threshold XDMA Idle Register" hexmask.long.byte 0x00 0.--7. 0x1 " THRES_XDMA_IDLE ,Threshold XDMA Idle cycle parameter" endif group.long 0xE0++0x0B line.long 0x00 "USB1UTMI,USB1 PHY UTMI Register" bitfld.long 0x00 23. " TXBITSTUFFEN ,Input for signal txbitstuffen" "Low,High" sif !cpuis("DM814?DSP") bitfld.long 0x00 22. " TXBITSTUFFENH ,Input for signal txbitstuffenh" "Low,High" textline " " bitfld.long 0x00 21. " OTGDISABLE ,Input for signal otgdisable" "Low,High" bitfld.long 0x00 20. " VBUSVLDEXTSEL ,Input for signal vbusvldextsel" "Low,High" textline " " bitfld.long 0x00 19. " VBUSVLDEXT ,Input for signal vbusvldext" "Low,High" endif bitfld.long 0x00 18. " TXENABLEN ,Input for signal txenablen" "Low,High" sif !cpuis("DM814?DSP") textline " " bitfld.long 0x00 17. " FSXCVROWNER ,Input for signal fsxcvrowner" "Low,High" bitfld.long 0x00 16. " TXVALIDH ,Input for signal txvalidh" "Low,High" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATAINH ,Input for signal datainh" bitfld.long 0x00 2. " WORDINTERFACE ,Input for signal wordinterface" "Low,High" textline " " bitfld.long 0x00 1. " FSDATAEXT ,Input for signal fsdataext" "Low,High" bitfld.long 0x00 0. " FSSE0EXT ,Input for signal fsse0ext" "Low,High" endif line.long 0x04 "USB1UTMILB,USB1 MGC UTMI Loopback Register" sif (cpuis("DM814?DSP")||cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High" rbitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3" textline " " rbitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High" rbitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3" textline " " rbitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High" rbitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High" textline " " rbitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High" rbitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High" textline " " rbitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High" rbitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High" textline " " rbitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High" else bitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High" bitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3" textline " " bitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High" bitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3" textline " " bitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High" bitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High" textline " " bitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High" bitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High" textline " " bitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High" bitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High" textline " " bitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High" endif bitfld.long 0x04 11. " IDDIG ,LB test value for iddig" "Low,High" textline " " bitfld.long 0x04 10. " HOSTDISCON ,LB test value for hostdiscon" "Low,High" bitfld.long 0x04 9. " SESSEND ,LB test value for sessend" "Low,High" textline " " bitfld.long 0x04 8. " AVALID ,LB test value for avalid" "Low,High" bitfld.long 0x04 7. " VBUSVALID ,LB test value for vbusvalid" "Low,High" textline " " bitfld.long 0x04 6. " RXERROR ,LB test value for rxerror" "Low,High" bitfld.long 0x04 2.--3. " LINESTATE ,LB test value for linestate" "0,1,2,3" line.long 0x08 "USB1MODE,USB1 Mode Register" bitfld.long 0x08 8. " IDDIG ,MGC input value for IDDIG" "A-type,B-type" textline " " sif (cpuis("AM335*")) bitfld.long 0x08 7. " IDDIG_MUX ,Multiplexer control for IDDIG signal going to the controller" "From PHY,From bit 8 (IDDIG)" textline " " endif bitfld.long 0x08 1. " PHY_TEST ,PHY test" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " LOOPBACK ,Loopback test mode" "Disabled,Enabled" width 0xb tree.end tree.end tree "CPPI_DMA" base ad:0x47404000 width 18. rgroup.long 0x00++0x3 line.long 0x0 "DMAREVID,CPPI DMA Revision Register" hexmask.long.word 0x00 16.--29. 1. " MODID ,Module ID field" bitfld.long 0x00 11.--15. " REVRTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Minor revision" group.long 0x04++0x7 line.long 0x00 "TDFDQ,CPPI DMA Teardown Free Descriptor Queue Control Register" bitfld.long 0x00 12.--13. " TD_DESC_QMGR ,Teardown descriptor queue menager select" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TD_DESC_QNUM ,Teardown descriptor queue number select" line.long 0x04 "DMAEMU,CPPI DMA Emulation Control Register" bitfld.long 0x04 1. " SOFT ,Force emulation pause request low" "Forced,Not forced" bitfld.long 0x04 0. " FREE ,Emulation suspend enable" "Disabled,Enabled" width 13. group.long 0x800++0x3 line.long 0x00 "TXGCR[0],CPPI DMA Transmit Channel 0 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x800+0x08)++0x3 line.long 0x00 "RXGCR[0],CPPI DMA Receive Channel 0 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x800+0x0C)++0x3 line.long 0x00 "RXHPCRA[0],CPPI DMA Receive Channel 0 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x800+0x10)++0x3 line.long 0x00 "RXHPCRB[0],CPPI DMA Receive Channel 0 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x820++0x3 line.long 0x00 "TXGCR[1],CPPI DMA Transmit Channel 1 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x820+0x08)++0x3 line.long 0x00 "RXGCR[1],CPPI DMA Receive Channel 1 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x820+0x0C)++0x3 line.long 0x00 "RXHPCRA[1],CPPI DMA Receive Channel 1 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x820+0x10)++0x3 line.long 0x00 "RXHPCRB[1],CPPI DMA Receive Channel 1 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x840++0x3 line.long 0x00 "TXGCR[2],CPPI DMA Transmit Channel 2 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x840+0x08)++0x3 line.long 0x00 "RXGCR[2],CPPI DMA Receive Channel 2 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x840+0x0C)++0x3 line.long 0x00 "RXHPCRA[2],CPPI DMA Receive Channel 2 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x840+0x10)++0x3 line.long 0x00 "RXHPCRB[2],CPPI DMA Receive Channel 2 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x860++0x3 line.long 0x00 "TXGCR[3],CPPI DMA Transmit Channel 3 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x860+0x08)++0x3 line.long 0x00 "RXGCR[3],CPPI DMA Receive Channel 3 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x860+0x0C)++0x3 line.long 0x00 "RXHPCRA[3],CPPI DMA Receive Channel 3 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x860+0x10)++0x3 line.long 0x00 "RXHPCRB[3],CPPI DMA Receive Channel 3 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x880++0x3 line.long 0x00 "TXGCR[4],CPPI DMA Transmit Channel 4 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x880+0x08)++0x3 line.long 0x00 "RXGCR[4],CPPI DMA Receive Channel 4 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x880+0x0C)++0x3 line.long 0x00 "RXHPCRA[4],CPPI DMA Receive Channel 4 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x880+0x10)++0x3 line.long 0x00 "RXHPCRB[4],CPPI DMA Receive Channel 4 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x8A0++0x3 line.long 0x00 "TXGCR[5],CPPI DMA Transmit Channel 5 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x8A0+0x08)++0x3 line.long 0x00 "RXGCR[5],CPPI DMA Receive Channel 5 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x8A0+0x0C)++0x3 line.long 0x00 "RXHPCRA[5],CPPI DMA Receive Channel 5 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x8A0+0x10)++0x3 line.long 0x00 "RXHPCRB[5],CPPI DMA Receive Channel 5 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x8C0++0x3 line.long 0x00 "TXGCR[6],CPPI DMA Transmit Channel 6 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x8C0+0x08)++0x3 line.long 0x00 "RXGCR[6],CPPI DMA Receive Channel 6 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x8C0+0x0C)++0x3 line.long 0x00 "RXHPCRA[6],CPPI DMA Receive Channel 6 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x8C0+0x10)++0x3 line.long 0x00 "RXHPCRB[6],CPPI DMA Receive Channel 6 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x8E0++0x3 line.long 0x00 "TXGCR[7],CPPI DMA Transmit Channel 7 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x8E0+0x08)++0x3 line.long 0x00 "RXGCR[7],CPPI DMA Receive Channel 7 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x8E0+0x0C)++0x3 line.long 0x00 "RXHPCRA[7],CPPI DMA Receive Channel 7 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x8E0+0x10)++0x3 line.long 0x00 "RXHPCRB[7],CPPI DMA Receive Channel 7 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x900++0x3 line.long 0x00 "TXGCR[8],CPPI DMA Transmit Channel 8 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x900+0x08)++0x3 line.long 0x00 "RXGCR[8],CPPI DMA Receive Channel 8 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x900+0x0C)++0x3 line.long 0x00 "RXHPCRA[8],CPPI DMA Receive Channel 8 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x900+0x10)++0x3 line.long 0x00 "RXHPCRB[8],CPPI DMA Receive Channel 8 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x920++0x3 line.long 0x00 "TXGCR[9],CPPI DMA Transmit Channel 9 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x920+0x08)++0x3 line.long 0x00 "RXGCR[9],CPPI DMA Receive Channel 9 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x920+0x0C)++0x3 line.long 0x00 "RXHPCRA[9],CPPI DMA Receive Channel 9 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x920+0x10)++0x3 line.long 0x00 "RXHPCRB[9],CPPI DMA Receive Channel 9 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x940++0x3 line.long 0x00 "TXGCR[10],CPPI DMA Transmit Channel 10 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x940+0x08)++0x3 line.long 0x00 "RXGCR[10],CPPI DMA Receive Channel 10 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x940+0x0C)++0x3 line.long 0x00 "RXHPCRA[10],CPPI DMA Receive Channel 10 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x940+0x10)++0x3 line.long 0x00 "RXHPCRB[10],CPPI DMA Receive Channel 10 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x960++0x3 line.long 0x00 "TXGCR[11],CPPI DMA Transmit Channel 11 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x960+0x08)++0x3 line.long 0x00 "RXGCR[11],CPPI DMA Receive Channel 11 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x960+0x0C)++0x3 line.long 0x00 "RXHPCRA[11],CPPI DMA Receive Channel 11 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x960+0x10)++0x3 line.long 0x00 "RXHPCRB[11],CPPI DMA Receive Channel 11 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x980++0x3 line.long 0x00 "TXGCR[12],CPPI DMA Transmit Channel 12 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x980+0x08)++0x3 line.long 0x00 "RXGCR[12],CPPI DMA Receive Channel 12 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x980+0x0C)++0x3 line.long 0x00 "RXHPCRA[12],CPPI DMA Receive Channel 12 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x980+0x10)++0x3 line.long 0x00 "RXHPCRB[12],CPPI DMA Receive Channel 12 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x9A0++0x3 line.long 0x00 "TXGCR[13],CPPI DMA Transmit Channel 13 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x9A0+0x08)++0x3 line.long 0x00 "RXGCR[13],CPPI DMA Receive Channel 13 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x9A0+0x0C)++0x3 line.long 0x00 "RXHPCRA[13],CPPI DMA Receive Channel 13 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x9A0+0x10)++0x3 line.long 0x00 "RXHPCRB[13],CPPI DMA Receive Channel 13 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x9C0++0x3 line.long 0x00 "TXGCR[14],CPPI DMA Transmit Channel 14 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x9C0+0x08)++0x3 line.long 0x00 "RXGCR[14],CPPI DMA Receive Channel 14 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x9C0+0x0C)++0x3 line.long 0x00 "RXHPCRA[14],CPPI DMA Receive Channel 14 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x9C0+0x10)++0x3 line.long 0x00 "RXHPCRB[14],CPPI DMA Receive Channel 14 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0x9E0++0x3 line.long 0x00 "TXGCR[15],CPPI DMA Transmit Channel 15 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0x9E0+0x08)++0x3 line.long 0x00 "RXGCR[15],CPPI DMA Receive Channel 15 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0x9E0+0x0C)++0x3 line.long 0x00 "RXHPCRA[15],CPPI DMA Receive Channel 15 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0x9E0+0x10)++0x3 line.long 0x00 "RXHPCRB[15],CPPI DMA Receive Channel 15 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xA00++0x3 line.long 0x00 "TXGCR[16],CPPI DMA Transmit Channel 16 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xA00+0x08)++0x3 line.long 0x00 "RXGCR[16],CPPI DMA Receive Channel 16 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xA00+0x0C)++0x3 line.long 0x00 "RXHPCRA[16],CPPI DMA Receive Channel 16 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xA00+0x10)++0x3 line.long 0x00 "RXHPCRB[16],CPPI DMA Receive Channel 16 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xA20++0x3 line.long 0x00 "TXGCR[17],CPPI DMA Transmit Channel 17 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xA20+0x08)++0x3 line.long 0x00 "RXGCR[17],CPPI DMA Receive Channel 17 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xA20+0x0C)++0x3 line.long 0x00 "RXHPCRA[17],CPPI DMA Receive Channel 17 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xA20+0x10)++0x3 line.long 0x00 "RXHPCRB[17],CPPI DMA Receive Channel 17 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xA40++0x3 line.long 0x00 "TXGCR[18],CPPI DMA Transmit Channel 18 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xA40+0x08)++0x3 line.long 0x00 "RXGCR[18],CPPI DMA Receive Channel 18 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xA40+0x0C)++0x3 line.long 0x00 "RXHPCRA[18],CPPI DMA Receive Channel 18 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xA40+0x10)++0x3 line.long 0x00 "RXHPCRB[18],CPPI DMA Receive Channel 18 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xA60++0x3 line.long 0x00 "TXGCR[19],CPPI DMA Transmit Channel 19 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xA60+0x08)++0x3 line.long 0x00 "RXGCR[19],CPPI DMA Receive Channel 19 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xA60+0x0C)++0x3 line.long 0x00 "RXHPCRA[19],CPPI DMA Receive Channel 19 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xA60+0x10)++0x3 line.long 0x00 "RXHPCRB[19],CPPI DMA Receive Channel 19 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xA80++0x3 line.long 0x00 "TXGCR[20],CPPI DMA Transmit Channel 20 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xA80+0x08)++0x3 line.long 0x00 "RXGCR[20],CPPI DMA Receive Channel 20 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xA80+0x0C)++0x3 line.long 0x00 "RXHPCRA[20],CPPI DMA Receive Channel 20 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xA80+0x10)++0x3 line.long 0x00 "RXHPCRB[20],CPPI DMA Receive Channel 20 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xAA0++0x3 line.long 0x00 "TXGCR[21],CPPI DMA Transmit Channel 21 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xAA0+0x08)++0x3 line.long 0x00 "RXGCR[21],CPPI DMA Receive Channel 21 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xAA0+0x0C)++0x3 line.long 0x00 "RXHPCRA[21],CPPI DMA Receive Channel 21 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xAA0+0x10)++0x3 line.long 0x00 "RXHPCRB[21],CPPI DMA Receive Channel 21 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xAC0++0x3 line.long 0x00 "TXGCR[22],CPPI DMA Transmit Channel 22 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xAC0+0x08)++0x3 line.long 0x00 "RXGCR[22],CPPI DMA Receive Channel 22 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xAC0+0x0C)++0x3 line.long 0x00 "RXHPCRA[22],CPPI DMA Receive Channel 22 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xAC0+0x10)++0x3 line.long 0x00 "RXHPCRB[22],CPPI DMA Receive Channel 22 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xAE0++0x3 line.long 0x00 "TXGCR[23],CPPI DMA Transmit Channel 23 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xAE0+0x08)++0x3 line.long 0x00 "RXGCR[23],CPPI DMA Receive Channel 23 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xAE0+0x0C)++0x3 line.long 0x00 "RXHPCRA[23],CPPI DMA Receive Channel 23 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xAE0+0x10)++0x3 line.long 0x00 "RXHPCRB[23],CPPI DMA Receive Channel 23 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xB00++0x3 line.long 0x00 "TXGCR[24],CPPI DMA Transmit Channel 24 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xB00+0x08)++0x3 line.long 0x00 "RXGCR[24],CPPI DMA Receive Channel 24 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xB00+0x0C)++0x3 line.long 0x00 "RXHPCRA[24],CPPI DMA Receive Channel 24 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xB00+0x10)++0x3 line.long 0x00 "RXHPCRB[24],CPPI DMA Receive Channel 24 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xB20++0x3 line.long 0x00 "TXGCR[25],CPPI DMA Transmit Channel 25 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xB20+0x08)++0x3 line.long 0x00 "RXGCR[25],CPPI DMA Receive Channel 25 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xB20+0x0C)++0x3 line.long 0x00 "RXHPCRA[25],CPPI DMA Receive Channel 25 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xB20+0x10)++0x3 line.long 0x00 "RXHPCRB[25],CPPI DMA Receive Channel 25 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xB40++0x3 line.long 0x00 "TXGCR[26],CPPI DMA Transmit Channel 26 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xB40+0x08)++0x3 line.long 0x00 "RXGCR[26],CPPI DMA Receive Channel 26 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xB40+0x0C)++0x3 line.long 0x00 "RXHPCRA[26],CPPI DMA Receive Channel 26 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xB40+0x10)++0x3 line.long 0x00 "RXHPCRB[26],CPPI DMA Receive Channel 26 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xB60++0x3 line.long 0x00 "TXGCR[27],CPPI DMA Transmit Channel 27 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xB60+0x08)++0x3 line.long 0x00 "RXGCR[27],CPPI DMA Receive Channel 27 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xB60+0x0C)++0x3 line.long 0x00 "RXHPCRA[27],CPPI DMA Receive Channel 27 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xB60+0x10)++0x3 line.long 0x00 "RXHPCRB[27],CPPI DMA Receive Channel 27 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xB80++0x3 line.long 0x00 "TXGCR[28],CPPI DMA Transmit Channel 28 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xB80+0x08)++0x3 line.long 0x00 "RXGCR[28],CPPI DMA Receive Channel 28 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xB80+0x0C)++0x3 line.long 0x00 "RXHPCRA[28],CPPI DMA Receive Channel 28 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xB80+0x10)++0x3 line.long 0x00 "RXHPCRB[28],CPPI DMA Receive Channel 28 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 13. group.long 0xBA0++0x3 line.long 0x00 "TXGCR[29],CPPI DMA Transmit Channel 29 Global Configuration Register" bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested" textline " " bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager" group.long (0xBA0+0x08)++0x3 line.long 0x00 "RXGCR[29],CPPI DMA Receive Channel 29 Global Configuration Register" bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled" bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed" bitfld.long 0x00 29. " RX_PAUSE ,RX Paule" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry" hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer" textline " " bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..." bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3" textline " " hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use" wgroup.long (0xBA0+0x0C)++0x3 line.long 0x00 "RXHPCRA[29],CPPI DMA Receive Channel 29 Host Packet Configuration Register A" bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer" wgroup.long (0xBA0+0x10)++0x3 line.long 0x00 "RXHPCRB[29],CPPI DMA Receive Channel 29 Host Packet Configuration Register B" bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer" textline " " bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer" width 0xb tree.end tree "CPPI_DMA_SCHEDULER" base ad:0x47406000 width 16. group.long 0x00++0x3 line.long 0x00 "DMA_SCHED_CTRL,CPPI DMA Scheduler Control Register" bitfld.long 0x00 31. " ENABLE ,Scheduler enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " LAST_ENTRY ,Last valid entry in the scheduler table" width 11. wgroup.long 0x800++0xff line.long 0x0 "WORD[0],CPPI DMA Scheduler Table Word 0 Register" bitfld.long 0x0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x4 "WORD[1],CPPI DMA Scheduler Table Word 1 Register" bitfld.long 0x4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x8 "WORD[2],CPPI DMA Scheduler Table Word 2 Register" bitfld.long 0x8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x14 "WORD[5],CPPI DMA Scheduler Table Word 5 Register" bitfld.long 0x14 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x14 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x14 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x14 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x18 "WORD[6],CPPI DMA Scheduler Table Word 6 Register" bitfld.long 0x18 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x18 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x18 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x18 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x1C "WORD[7],CPPI DMA Scheduler Table Word 7 Register" bitfld.long 0x1C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x1C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x1C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x1C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x20 "WORD[8],CPPI DMA Scheduler Table Word 8 Register" bitfld.long 0x20 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x20 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x20 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x20 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x24 "WORD[9],CPPI DMA Scheduler Table Word 9 Register" bitfld.long 0x24 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x24 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x24 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x24 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x28 "WORD[10],CPPI DMA Scheduler Table Word 10 Register" bitfld.long 0x28 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x28 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x28 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x28 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x2C "WORD[11],CPPI DMA Scheduler Table Word 11 Register" bitfld.long 0x2C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x2C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x2C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x2C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x30 "WORD[12],CPPI DMA Scheduler Table Word 12 Register" bitfld.long 0x30 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x30 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x30 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x30 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x34 "WORD[13],CPPI DMA Scheduler Table Word 13 Register" bitfld.long 0x34 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x34 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x34 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x34 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x38 "WORD[14],CPPI DMA Scheduler Table Word 14 Register" bitfld.long 0x38 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x38 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x38 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x38 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x3C "WORD[15],CPPI DMA Scheduler Table Word 15 Register" bitfld.long 0x3C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x3C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x3C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x3C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x40 "WORD[16],CPPI DMA Scheduler Table Word 16 Register" bitfld.long 0x40 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x40 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x40 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x40 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x44 "WORD[17],CPPI DMA Scheduler Table Word 17 Register" bitfld.long 0x44 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x44 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x44 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x44 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x48 "WORD[18],CPPI DMA Scheduler Table Word 18 Register" bitfld.long 0x48 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x48 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x48 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x48 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x4C "WORD[19],CPPI DMA Scheduler Table Word 19 Register" bitfld.long 0x4C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x4C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x4C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x4C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x50 "WORD[20],CPPI DMA Scheduler Table Word 20 Register" bitfld.long 0x50 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x50 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x50 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x50 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x54 "WORD[21],CPPI DMA Scheduler Table Word 21 Register" bitfld.long 0x54 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x54 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x54 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x54 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x58 "WORD[22],CPPI DMA Scheduler Table Word 22 Register" bitfld.long 0x58 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x58 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x58 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x58 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x5C "WORD[23],CPPI DMA Scheduler Table Word 23 Register" bitfld.long 0x5C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x5C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x5C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x5C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x60 "WORD[24],CPPI DMA Scheduler Table Word 24 Register" bitfld.long 0x60 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x60 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x60 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x60 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x64 "WORD[25],CPPI DMA Scheduler Table Word 25 Register" bitfld.long 0x64 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x64 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x64 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x64 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x68 "WORD[26],CPPI DMA Scheduler Table Word 26 Register" bitfld.long 0x68 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x68 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x68 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x68 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x6C "WORD[27],CPPI DMA Scheduler Table Word 27 Register" bitfld.long 0x6C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x6C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x6C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x6C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x70 "WORD[28],CPPI DMA Scheduler Table Word 28 Register" bitfld.long 0x70 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x70 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x70 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x70 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x74 "WORD[29],CPPI DMA Scheduler Table Word 29 Register" bitfld.long 0x74 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x74 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x74 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x74 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x78 "WORD[30],CPPI DMA Scheduler Table Word 30 Register" bitfld.long 0x78 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x78 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x78 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x78 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x7C "WORD[31],CPPI DMA Scheduler Table Word 31 Register" bitfld.long 0x7C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x7C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x7C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x7C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x80 "WORD[32],CPPI DMA Scheduler Table Word 32 Register" bitfld.long 0x80 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x80 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x80 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x80 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x84 "WORD[33],CPPI DMA Scheduler Table Word 33 Register" bitfld.long 0x84 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x84 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x84 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x84 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x88 "WORD[34],CPPI DMA Scheduler Table Word 34 Register" bitfld.long 0x88 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x88 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x88 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x88 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x8C "WORD[35],CPPI DMA Scheduler Table Word 35 Register" bitfld.long 0x8C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x8C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x8C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x8C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x90 "WORD[36],CPPI DMA Scheduler Table Word 36 Register" bitfld.long 0x90 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x90 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x90 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x90 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x94 "WORD[37],CPPI DMA Scheduler Table Word 37 Register" bitfld.long 0x94 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x94 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x94 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x94 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x98 "WORD[38],CPPI DMA Scheduler Table Word 38 Register" bitfld.long 0x98 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x98 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x98 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x98 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0x9C "WORD[39],CPPI DMA Scheduler Table Word 39 Register" bitfld.long 0x9C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x9C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0x9C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0x9C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xA0 "WORD[40],CPPI DMA Scheduler Table Word 40 Register" bitfld.long 0xA0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xA0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xA0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xA0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xA4 "WORD[41],CPPI DMA Scheduler Table Word 41 Register" bitfld.long 0xA4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xA4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xA4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xA4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xA8 "WORD[42],CPPI DMA Scheduler Table Word 42 Register" bitfld.long 0xA8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xA8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xA8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xA8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xAC "WORD[43],CPPI DMA Scheduler Table Word 43 Register" bitfld.long 0xAC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xAC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xAC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xAC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xB0 "WORD[44],CPPI DMA Scheduler Table Word 44 Register" bitfld.long 0xB0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xB0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xB0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xB0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xB4 "WORD[45],CPPI DMA Scheduler Table Word 45 Register" bitfld.long 0xB4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xB4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xB4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xB4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xB8 "WORD[46],CPPI DMA Scheduler Table Word 46 Register" bitfld.long 0xB8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xB8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xB8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xB8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xBC "WORD[47],CPPI DMA Scheduler Table Word 47 Register" bitfld.long 0xBC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xBC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xBC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xBC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xC0 "WORD[48],CPPI DMA Scheduler Table Word 48 Register" bitfld.long 0xC0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xC0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xC0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xC0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xC4 "WORD[49],CPPI DMA Scheduler Table Word 49 Register" bitfld.long 0xC4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xC4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xC4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xC4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xC8 "WORD[50],CPPI DMA Scheduler Table Word 50 Register" bitfld.long 0xC8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xC8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xC8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xC8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xCC "WORD[51],CPPI DMA Scheduler Table Word 51 Register" bitfld.long 0xCC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xCC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xCC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xCC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xD0 "WORD[52],CPPI DMA Scheduler Table Word 52 Register" bitfld.long 0xD0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xD0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xD0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xD0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xD4 "WORD[53],CPPI DMA Scheduler Table Word 53 Register" bitfld.long 0xD4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xD4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xD4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xD4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xD8 "WORD[54],CPPI DMA Scheduler Table Word 54 Register" bitfld.long 0xD8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xD8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xD8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xD8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xDC "WORD[55],CPPI DMA Scheduler Table Word 55 Register" bitfld.long 0xDC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xDC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xDC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xDC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xE0 "WORD[56],CPPI DMA Scheduler Table Word 56 Register" bitfld.long 0xE0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xE0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xE0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xE0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xE4 "WORD[57],CPPI DMA Scheduler Table Word 57 Register" bitfld.long 0xE4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xE4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xE4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xE4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xE8 "WORD[58],CPPI DMA Scheduler Table Word 58 Register" bitfld.long 0xE8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xE8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xE8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xE8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xEC "WORD[59],CPPI DMA Scheduler Table Word 59 Register" bitfld.long 0xEC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xEC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xEC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xEC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xF0 "WORD[60],CPPI DMA Scheduler Table Word 60 Register" bitfld.long 0xF0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xF0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xF0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xF0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xF4 "WORD[61],CPPI DMA Scheduler Table Word 61 Register" bitfld.long 0xF4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xF4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xF4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xF4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xF8 "WORD[62],CPPI DMA Scheduler Table Word 62 Register" bitfld.long 0xF8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xF8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xF8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xF8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" line.long 0xFC "WORD[63],CPPI DMA Scheduler Table Word 63 Register" bitfld.long 0xFC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xFC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" textline " " bitfld.long 0xFC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" bitfld.long 0xFC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive" width 0xb tree.end tree "Queue Manager" base ad:0x47404000 width 22. rgroup.long 0x00++0x03 line.long 0x00 "QMGRREVID,Queue Manager Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme that this register is compliant with" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNCTION ,Software compatible module family function" bitfld.long 0x00 11.--15. " REVRTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " REVCUSTOM ,Custom revision" "0,1,2,3" bitfld.long 0x00 0.--5. " RVMIN ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x08++0x03 line.long 0x00 "QMGRRST,Queue Manager Reset Register" bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail" hexmask.long.word 0x00 16.--29. 1. " DEST_QNUM ,Destination Queue Number" hexmask.long.word 0x00 0.--13. 1. " SOURCE_QNUM ,Source Queue Number" hgroup.long 0x20++0x03 hide.long 0x00 "FDBSC0,Queue Manager Free Descriptor/Buffer Starvation Count Register 0" in hgroup.long 0x24++0x03 hide.long 0x00 "FDBSC1,Queue Manager Free Descriptor/Buffer Starvation Count Register 1" in hgroup.long 0x28++0x03 hide.long 0x00 "FDBSC2,Queue Manager Free Descriptor/Buffer Starvation Count Register 2" in hgroup.long 0x2c++0x03 hide.long 0x00 "FDBSC3,Queue Manager Free Descriptor/Buffer Starvation Count Register 3" in hgroup.long 0x30++0x03 hide.long 0x00 "FDBSC4,Queue Manager Free Descriptor/Buffer Starvation Count Register 4" in hgroup.long 0x34++0x03 hide.long 0x00 "FDBSC5,Queue Manager Free Descriptor/Buffer Starvation Count Register 5" in hgroup.long 0x38++0x03 hide.long 0x00 "FDBSC6,Queue Manager Free Descriptor/Buffer Starvation Count Register 6" in hgroup.long 0x3c++0x03 hide.long 0x00 "FDBSC7,Queue Manager Free Descriptor/Buffer Starvation Count Register 7" in group.long 0x80++0xb line.long 0x00 "LRAM0BASE,Queue Manager Linking RAM Region 0 Base Address Register" hexmask.long 0x00 2.--31. 4. " REGION0_BASE ,Base address for the first region of the linking RAM" line.long 0x04 "LRAM0SIZE,Queue Manager Linking RAM Region 0 Size Register" hexmask.long.word 0x04 0.--13. 1. " REGION0_SIZE ,Number of entries that are contained in the linking RAM region 0" line.long 0x08 "LRAM1BASE,Queue Manager Linking RAM Region 1 Base Address Register" hexmask.long 0x08 2.--31. 4. " REGION1_BASE ,Base address for the second region of the linking RAM" rgroup.long 0x90++0xb line.long 0x00 "PEND0,Queue Manager Queue Pending Register 0" bitfld.long 0x00 31. " QPEND31 ,Queue 31 pending status" "Not pending,Pending" bitfld.long 0x00 30. " QPEND30 ,Queue 30 pending status" "Not pending,Pending" bitfld.long 0x00 29. " QPEND29 ,Queue 29 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 28. " QPEND28 ,Queue 28 pending status" "Not pending,Pending" bitfld.long 0x00 27. " QPEND27 ,Queue 27 pending status" "Not pending,Pending" bitfld.long 0x00 26. " QPEND26 ,Queue 26 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 25. " QPEND25 ,Queue 25 pending status" "Not pending,Pending" bitfld.long 0x00 24. " QPEND24 ,Queue 24 pending status" "Not pending,Pending" bitfld.long 0x00 23. " QPEND23 ,Queue 23 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 22. " QPEND22 ,Queue 22 pending status" "Not pending,Pending" bitfld.long 0x00 21. " QPEND21 ,Queue 21 pending status" "Not pending,Pending" bitfld.long 0x00 20. " QPEND20 ,Queue 20 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 19. " QPEND19 ,Queue 19 pending status" "Not pending,Pending" bitfld.long 0x00 18. " QPEND18 ,Queue 18 pending status" "Not pending,Pending" bitfld.long 0x00 17. " QPEND17 ,Queue 17 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 16. " QPEND16 ,Queue 16 pending status" "Not pending,Pending" bitfld.long 0x00 15. " QPEND15 ,Queue 15 pending status" "Not pending,Pending" bitfld.long 0x00 14. " QPEND14 ,Queue 14 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 13. " QPEND13 ,Queue 13 pending status" "Not pending,Pending" bitfld.long 0x00 12. " QPEND12 ,Queue 12 pending status" "Not pending,Pending" bitfld.long 0x00 11. " QPEND11 ,Queue 11 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 10. " QPEND10 ,Queue 10 pending status" "Not pending,Pending" bitfld.long 0x00 9. " QPEND9 ,Queue 9 pending status" "Not pending,Pending" bitfld.long 0x00 8. " QPEND8 ,Queue 8 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 7. " QPEND7 ,Queue 7 pending status" "Not pending,Pending" bitfld.long 0x00 6. " QPEND6 ,Queue 6 pending status" "Not pending,Pending" bitfld.long 0x00 5. " QPEND5 ,Queue 5 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 4. " QPEND4 ,Queue 4 pending status" "Not pending,Pending" bitfld.long 0x00 3. " QPEND3 ,Queue 3 pending status" "Not pending,Pending" bitfld.long 0x00 2. " QPEND2 ,Queue 2 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 1. " QPEND1 ,Queue 1 pending status" "Not pending,Pending" bitfld.long 0x00 0. " QPEND0 ,Queue 0 pending status" "Not pending,Pending" line.long 0x04 "PEND1,Queue Manager Queue Pending Register 1" bitfld.long 0x04 31. " QPEND63 ,Queue 63 pending status" "Not pending,Pending" bitfld.long 0x04 30. " QPEND62 ,Queue 62 pending status" "Not pending,Pending" bitfld.long 0x04 29. " QPEND61 ,Queue 61 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 28. " QPEND60 ,Queue 60 pending status" "Not pending,Pending" bitfld.long 0x04 27. " QPEND59 ,Queue 59 pending status" "Not pending,Pending" bitfld.long 0x04 26. " QPEND58 ,Queue 58 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 25. " QPEND57 ,Queue 57 pending status" "Not pending,Pending" bitfld.long 0x04 24. " QPEND56 ,Queue 56 pending status" "Not pending,Pending" bitfld.long 0x04 23. " QPEND55 ,Queue 55 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 22. " QPEND54 ,Queue 54 pending status" "Not pending,Pending" bitfld.long 0x04 21. " QPEND53 ,Queue 53 pending status" "Not pending,Pending" bitfld.long 0x04 20. " QPEND52 ,Queue 52 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 19. " QPEND51 ,Queue 51 pending status" "Not pending,Pending" bitfld.long 0x04 18. " QPEND50 ,Queue 50 pending status" "Not pending,Pending" bitfld.long 0x04 17. " QPEND49 ,Queue 49 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 16. " QPEND48 ,Queue 48 pending status" "Not pending,Pending" bitfld.long 0x04 15. " QPEND47 ,Queue 47 pending status" "Not pending,Pending" bitfld.long 0x04 14. " QPEND46 ,Queue 46 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 13. " QPEND45 ,Queue 45 pending status" "Not pending,Pending" bitfld.long 0x04 12. " QPEND44 ,Queue 44 pending status" "Not pending,Pending" bitfld.long 0x04 11. " QPEND43 ,Queue 43 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 10. " QPEND42 ,Queue 42 pending status" "Not pending,Pending" bitfld.long 0x04 9. " QPEND41 ,Queue 41 pending status" "Not pending,Pending" bitfld.long 0x04 8. " QPEND40 ,Queue 40 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 7. " QPEND39 ,Queue 39 pending status" "Not pending,Pending" bitfld.long 0x04 6. " QPEND38 ,Queue 38 pending status" "Not pending,Pending" bitfld.long 0x04 5. " QPEND37 ,Queue 37 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 4. " QPEND36 ,Queue 36 pending status" "Not pending,Pending" bitfld.long 0x04 3. " QPEND35 ,Queue 35 pending status" "Not pending,Pending" bitfld.long 0x04 2. " QPEND34 ,Queue 34 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 1. " QPEND33 ,Queue 33 pending status" "Not pending,Pending" bitfld.long 0x04 0. " QPEND32 ,Queue 32 pending status" "Not pending,Pending" line.long 0x08 "PEND2,Queue Manager Queue Pending Register 2" bitfld.long 0x08 31. " QPEND95 ,Queue 95 pending status" "Not pending,Pending" bitfld.long 0x08 30. " QPEND94 ,Queue 94 pending status" "Not pending,Pending" bitfld.long 0x08 29. " QPEND93 ,Queue 93 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 28. " QPEND92 ,Queue 92 pending status" "Not pending,Pending" bitfld.long 0x08 27. " QPEND91 ,Queue 91 pending status" "Not pending,Pending" bitfld.long 0x08 26. " QPEND90 ,Queue 90 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 25. " QPEND89 ,Queue 89 pending status" "Not pending,Pending" bitfld.long 0x08 24. " QPEND88 ,Queue 88 pending status" "Not pending,Pending" bitfld.long 0x08 23. " QPEND87 ,Queue 87 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 22. " QPEND86 ,Queue 86 pending status" "Not pending,Pending" bitfld.long 0x08 21. " QPEND85 ,Queue 85 pending status" "Not pending,Pending" bitfld.long 0x08 20. " QPEND84 ,Queue 84 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 19. " QPEND83 ,Queue 83 pending status" "Not pending,Pending" bitfld.long 0x08 18. " QPEND82 ,Queue 82 pending status" "Not pending,Pending" bitfld.long 0x08 17. " QPEND81 ,Queue 81 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 16. " QPEND80 ,Queue 80 pending status" "Not pending,Pending" bitfld.long 0x08 15. " QPEND79 ,Queue 79 pending status" "Not pending,Pending" bitfld.long 0x08 14. " QPEND78 ,Queue 78 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 13. " QPEND77 ,Queue 77 pending status" "Not pending,Pending" bitfld.long 0x08 12. " QPEND76 ,Queue 76 pending status" "Not pending,Pending" bitfld.long 0x08 11. " QPEND75 ,Queue 75 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 10. " QPEND74 ,Queue 74 pending status" "Not pending,Pending" bitfld.long 0x08 9. " QPEND73 ,Queue 73 pending status" "Not pending,Pending" bitfld.long 0x08 8. " QPEND72 ,Queue 72 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 7. " QPEND71 ,Queue 71 pending status" "Not pending,Pending" bitfld.long 0x08 6. " QPEND70 ,Queue 70 pending status" "Not pending,Pending" bitfld.long 0x08 5. " QPEND69 ,Queue 69 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 4. " QPEND68 ,Queue 68 pending status" "Not pending,Pending" bitfld.long 0x08 3. " QPEND67 ,Queue 67 pending status" "Not pending,Pending" bitfld.long 0x08 2. " QPEND66 ,Queue 66 pending status" "Not pending,Pending" textline " " bitfld.long 0x08 1. " QPEND65 ,Queue 65 pending status" "Not pending,Pending" bitfld.long 0x08 0. " QPEND64 ,Queue 64 pending status" "Not pending,Pending" rgroup.long 0x9c++0x7 line.long 0x00 "PEND3,Queue Manager Queue Pending Register 3" bitfld.long 0x00 31. " QPEND127 ,Queue 127 pending status" "Not pending,Pending" bitfld.long 0x00 30. " QPEND126 ,Queue 126 pending status" "Not pending,Pending" bitfld.long 0x00 29. " QPEND125 ,Queue 125 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 28. " QPEND124 ,Queue 124 pending status" "Not pending,Pending" bitfld.long 0x00 27. " QPEND123 ,Queue 123 pending status" "Not pending,Pending" bitfld.long 0x00 26. " QPEND122 ,Queue 122 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 25. " QPEND121 ,Queue 121 pending status" "Not pending,Pending" bitfld.long 0x00 24. " QPEND120 ,Queue 120 pending status" "Not pending,Pending" bitfld.long 0x00 23. " QPEND119 ,Queue 119 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 22. " QPEND118 ,Queue 118 pending status" "Not pending,Pending" bitfld.long 0x00 21. " QPEND117 ,Queue 117 pending status" "Not pending,Pending" bitfld.long 0x00 20. " QPEND116 ,Queue 116 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 19. " QPEND115 ,Queue 115 pending status" "Not pending,Pending" bitfld.long 0x00 18. " QPEND114 ,Queue 114 pending status" "Not pending,Pending" bitfld.long 0x00 17. " QPEND113 ,Queue 113 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 16. " QPEND112 ,Queue 112 pending status" "Not pending,Pending" bitfld.long 0x00 15. " QPEND111 ,Queue 111 pending status" "Not pending,Pending" bitfld.long 0x00 14. " QPEND110 ,Queue 110 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 13. " QPEND109 ,Queue 109 pending status" "Not pending,Pending" bitfld.long 0x00 12. " QPEND108 ,Queue 108 pending status" "Not pending,Pending" bitfld.long 0x00 11. " QPEND107 ,Queue 107 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 10. " QPEND106 ,Queue 106 pending status" "Not pending,Pending" bitfld.long 0x00 9. " QPEND105 ,Queue 105 pending status" "Not pending,Pending" bitfld.long 0x00 8. " QPEND104 ,Queue 104 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 7. " QPEND103 ,Queue 103 pending status" "Not pending,Pending" bitfld.long 0x00 6. " QPEND102 ,Queue 102 pending status" "Not pending,Pending" bitfld.long 0x00 5. " QPEND101 ,Queue 101 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 4. " QPEND100 ,Queue 100 pending status" "Not pending,Pending" bitfld.long 0x00 3. " QPEND99 ,Queue 99 pending status" "Not pending,Pending" bitfld.long 0x00 2. " QPEND98 ,Queue 98 pending status" "Not pending,Pending" textline " " bitfld.long 0x00 1. " QPEND97 ,Queue 97 pending status" "Not pending,Pending" bitfld.long 0x00 0. " QPEND96 ,Queue 96 pending status" "Not pending,Pending" line.long 0x04 "PEND4,Queue Manager Queue Pending Register 4" bitfld.long 0x04 31. " QPEND159 ,Queue 159 pending status" "Not pending,Pending" bitfld.long 0x04 30. " QPEND158 ,Queue 158 pending status" "Not pending,Pending" bitfld.long 0x04 29. " QPEND157 ,Queue 157 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 28. " QPEND156 ,Queue 156 pending status" "Not pending,Pending" bitfld.long 0x04 27. " QPEND155 ,Queue 155 pending status" "Not pending,Pending" bitfld.long 0x04 26. " QPEND154 ,Queue 154 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 25. " QPEND153 ,Queue 153 pending status" "Not pending,Pending" bitfld.long 0x04 24. " QPEND152 ,Queue 152 pending status" "Not pending,Pending" bitfld.long 0x04 23. " QPEND151 ,Queue 151 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 22. " QPEND150 ,Queue 150 pending status" "Not pending,Pending" bitfld.long 0x04 21. " QPEND149 ,Queue 149 pending status" "Not pending,Pending" bitfld.long 0x04 20. " QPEND148 ,Queue 148 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 19. " QPEND147 ,Queue 147 pending status" "Not pending,Pending" bitfld.long 0x04 18. " QPEND146 ,Queue 146 pending status" "Not pending,Pending" bitfld.long 0x04 17. " QPEND145 ,Queue 145 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 16. " QPEND144 ,Queue 144 pending status" "Not pending,Pending" bitfld.long 0x04 15. " QPEND143 ,Queue 143 pending status" "Not pending,Pending" bitfld.long 0x04 14. " QPEND142 ,Queue 142 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 13. " QPEND141 ,Queue 141 pending status" "Not pending,Pending" bitfld.long 0x04 12. " QPEND140 ,Queue 140 pending status" "Not pending,Pending" bitfld.long 0x04 11. " QPEND139 ,Queue 139 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 10. " QPEND138 ,Queue 138 pending status" "Not pending,Pending" bitfld.long 0x04 9. " QPEND137 ,Queue 137 pending status" "Not pending,Pending" bitfld.long 0x04 8. " QPEND136 ,Queue 136 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 7. " QPEND135 ,Queue 135 pending status" "Not pending,Pending" bitfld.long 0x04 6. " QPEND134 ,Queue 134 pending status" "Not pending,Pending" bitfld.long 0x04 5. " QPEND133 ,Queue 133 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 4. " QPEND132 ,Queue 132 pending status" "Not pending,Pending" bitfld.long 0x04 3. " QPEND131 ,Queue 131 pending status" "Not pending,Pending" bitfld.long 0x04 2. " QPEND130 ,Queue 130 pending status" "Not pending,Pending" textline " " bitfld.long 0x04 1. " QPEND129 ,Queue 129 pending status" "Not pending,Pending" bitfld.long 0x04 0. " QPEND128 ,Queue 128 pending status" "Not pending,Pending" sif (cpuis("AM335*")) group.long 0x1000++0x3 line.long 0x00 "QMEMRBASE[0],QMEMRBASE0 Base Address Register" hexmask.long 0x00 5.--31. 0x20 " REG ,Base address of the memory region R" else group.long 0x1000++0x3 line.long 0x00 "QUEUE_[0],Queue Manager Memory Region 0 Base Address Register" endif group.long 0x1000++0x3 line.long 0x00 "QMEMRCTRL[0],Queue Manager Memory Region 0 Control Register" hexmask.long.word 0x00 16.--29. 1. " START_INDEX ,Memory region 0 start index" bitfld.long 0x00 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..." bitfld.long 0x00 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K" sif (cpuis("AM335*")) group.long 0x1010++0x3 line.long 0x00 "QMEMRBASE[1],QMEMRBASE1 Base Address Register" hexmask.long 0x00 5.--31. 0x20 " REG ,Base address of the memory region R" else group.long 0x1010++0x3 line.long 0x00 "QUEUE_[1],Queue Manager Memory Region 1 Base Address Register" endif group.long 0x1010++0x3 line.long 0x00 "QMEMRCTRL[1],Queue Manager Memory Region 1 Control Register" hexmask.long.word 0x00 16.--29. 1. " START_INDEX ,Memory region 1 start index" bitfld.long 0x00 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..." bitfld.long 0x00 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K" sif (cpuis("AM335*")) group.long 0x1020++0x3 line.long 0x00 "QMEMRBASE[2],QMEMRBASE2 Base Address Register" hexmask.long 0x00 5.--31. 0x20 " REG ,Base address of the memory region R" else group.long 0x1020++0x3 line.long 0x00 "QUEUE_[2],Queue Manager Memory Region 2 Base Address Register" endif group.long 0x1020++0x3 line.long 0x00 "QMEMRCTRL[2],Queue Manager Memory Region 2 Control Register" hexmask.long.word 0x00 16.--29. 1. " START_INDEX ,Memory region 2 start index" bitfld.long 0x00 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..." bitfld.long 0x00 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K" sif (cpuis("AM335*")) group.long 0x1030++0x3 line.long 0x00 "QMEMRBASE[3],QMEMRBASE3 Base Address Register" hexmask.long 0x00 5.--31. 0x20 " REG ,Base address of the memory region R" else group.long 0x1030++0x3 line.long 0x00 "QUEUE_[3],Queue Manager Memory Region 3 Base Address Register" endif group.long 0x1030++0x3 line.long 0x00 "QMEMRCTRL[3],Queue Manager Memory Region 3 Control Register" hexmask.long.word 0x00 16.--29. 1. " START_INDEX ,Memory region 3 start index" bitfld.long 0x00 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..." bitfld.long 0x00 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K" sif (cpuis("AM335*")) group.long 0x1040++0x3 line.long 0x00 "QMEMRBASE[4],QMEMRBASE4 Base Address Register" hexmask.long 0x00 5.--31. 0x20 " REG ,Base address of the memory region R" else group.long 0x1040++0x3 line.long 0x00 "QUEUE_[4],Queue Manager Memory Region 4 Base Address Register" endif group.long 0x1040++0x3 line.long 0x00 "QMEMRCTRL[4],Queue Manager Memory Region 4 Control Register" hexmask.long.word 0x00 16.--29. 1. " START_INDEX ,Memory region 4 start index" bitfld.long 0x00 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..." bitfld.long 0x00 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K" sif (cpuis("AM335*")) group.long 0x1050++0x3 line.long 0x00 "QMEMRBASE[5],QMEMRBASE5 Base Address Register" hexmask.long 0x00 5.--31. 0x20 " REG ,Base address of the memory region R" else group.long 0x1050++0x3 line.long 0x00 "QUEUE_[5],Queue Manager Memory Region 5 Base Address Register" endif group.long 0x1050++0x3 line.long 0x00 "QMEMRCTRL[5],Queue Manager Memory Region 5 Control Register" hexmask.long.word 0x00 16.--29. 1. " START_INDEX ,Memory region 5 start index" bitfld.long 0x00 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..." bitfld.long 0x00 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K" sif (cpuis("AM335*")) group.long 0x1060++0x3 line.long 0x00 "QMEMRBASE[6],QMEMRBASE6 Base Address Register" hexmask.long 0x00 5.--31. 0x20 " REG ,Base address of the memory region R" else group.long 0x1060++0x3 line.long 0x00 "QUEUE_[6],Queue Manager Memory Region 6 Base Address Register" endif group.long 0x1060++0x3 line.long 0x00 "QMEMRCTRL[6],Queue Manager Memory Region 6 Control Register" hexmask.long.word 0x00 16.--29. 1. " START_INDEX ,Memory region 6 start index" bitfld.long 0x00 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..." bitfld.long 0x00 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K" sif (cpuis("AM335*")) group.long 0x1070++0x3 line.long 0x00 "QMEMRBASE[7],QMEMRBASE7 Base Address Register" hexmask.long 0x00 5.--31. 0x20 " REG ,Base address of the memory region R" else group.long 0x1070++0x3 line.long 0x00 "QUEUE_[7],Queue Manager Memory Region 7 Base Address Register" endif group.long 0x1070++0x3 line.long 0x00 "QMEMRCTRL[7],Queue Manager Memory Region 7 Control Register" hexmask.long.word 0x00 16.--29. 1. " START_INDEX ,Memory region 7 start index" bitfld.long 0x00 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..." bitfld.long 0x00 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K" tree "Queues" tree "Queue 0 Registers" rgroup.long 0x2000++0xB line.long 0x00 "QUEUE_0_A,Queue Manager Queue 0 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_0_B,Queue Manager Queue 0 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_0_C,Queue Manager Queue 0 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2000+0x0C)++0x3 line.long 0x00 "QUEUE_0_D,Queue Manager Queue 0 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3000++0xB line.long 0x00 "QUEUE_0_STATUS_A,Queue Manager Queue 0 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_0_STATUS_B,Queue Manager Queue 0 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_0_STATUS_C,Queue Manager Queue 0 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 1 Registers" rgroup.long 0x2010++0xB line.long 0x00 "QUEUE_1_A,Queue Manager Queue 1 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_1_B,Queue Manager Queue 1 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_1_C,Queue Manager Queue 1 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2010+0x0C)++0x3 line.long 0x00 "QUEUE_1_D,Queue Manager Queue 1 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3010++0xB line.long 0x00 "QUEUE_1_STATUS_A,Queue Manager Queue 1 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_1_STATUS_B,Queue Manager Queue 1 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_1_STATUS_C,Queue Manager Queue 1 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 2 Registers" rgroup.long 0x2020++0xB line.long 0x00 "QUEUE_2_A,Queue Manager Queue 2 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_2_B,Queue Manager Queue 2 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_2_C,Queue Manager Queue 2 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2020+0x0C)++0x3 line.long 0x00 "QUEUE_2_D,Queue Manager Queue 2 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3020++0xB line.long 0x00 "QUEUE_2_STATUS_A,Queue Manager Queue 2 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_2_STATUS_B,Queue Manager Queue 2 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_2_STATUS_C,Queue Manager Queue 2 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 3 Registers" rgroup.long 0x2030++0xB line.long 0x00 "QUEUE_3_A,Queue Manager Queue 3 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_3_B,Queue Manager Queue 3 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_3_C,Queue Manager Queue 3 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2030+0x0C)++0x3 line.long 0x00 "QUEUE_3_D,Queue Manager Queue 3 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3030++0xB line.long 0x00 "QUEUE_3_STATUS_A,Queue Manager Queue 3 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_3_STATUS_B,Queue Manager Queue 3 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_3_STATUS_C,Queue Manager Queue 3 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 4 Registers" rgroup.long 0x2040++0xB line.long 0x00 "QUEUE_4_A,Queue Manager Queue 4 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_4_B,Queue Manager Queue 4 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_4_C,Queue Manager Queue 4 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2040+0x0C)++0x3 line.long 0x00 "QUEUE_4_D,Queue Manager Queue 4 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3040++0xB line.long 0x00 "QUEUE_4_STATUS_A,Queue Manager Queue 4 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_4_STATUS_B,Queue Manager Queue 4 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_4_STATUS_C,Queue Manager Queue 4 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 5 Registers" rgroup.long 0x2050++0xB line.long 0x00 "QUEUE_5_A,Queue Manager Queue 5 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_5_B,Queue Manager Queue 5 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_5_C,Queue Manager Queue 5 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2050+0x0C)++0x3 line.long 0x00 "QUEUE_5_D,Queue Manager Queue 5 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3050++0xB line.long 0x00 "QUEUE_5_STATUS_A,Queue Manager Queue 5 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_5_STATUS_B,Queue Manager Queue 5 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_5_STATUS_C,Queue Manager Queue 5 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 6 Registers" rgroup.long 0x2060++0xB line.long 0x00 "QUEUE_6_A,Queue Manager Queue 6 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_6_B,Queue Manager Queue 6 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_6_C,Queue Manager Queue 6 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2060+0x0C)++0x3 line.long 0x00 "QUEUE_6_D,Queue Manager Queue 6 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3060++0xB line.long 0x00 "QUEUE_6_STATUS_A,Queue Manager Queue 6 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_6_STATUS_B,Queue Manager Queue 6 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_6_STATUS_C,Queue Manager Queue 6 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 7 Registers" rgroup.long 0x2070++0xB line.long 0x00 "QUEUE_7_A,Queue Manager Queue 7 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_7_B,Queue Manager Queue 7 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_7_C,Queue Manager Queue 7 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2070+0x0C)++0x3 line.long 0x00 "QUEUE_7_D,Queue Manager Queue 7 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3070++0xB line.long 0x00 "QUEUE_7_STATUS_A,Queue Manager Queue 7 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_7_STATUS_B,Queue Manager Queue 7 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_7_STATUS_C,Queue Manager Queue 7 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 8 Registers" rgroup.long 0x2080++0xB line.long 0x00 "QUEUE_8_A,Queue Manager Queue 8 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_8_B,Queue Manager Queue 8 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_8_C,Queue Manager Queue 8 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2080+0x0C)++0x3 line.long 0x00 "QUEUE_8_D,Queue Manager Queue 8 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3080++0xB line.long 0x00 "QUEUE_8_STATUS_A,Queue Manager Queue 8 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_8_STATUS_B,Queue Manager Queue 8 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_8_STATUS_C,Queue Manager Queue 8 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 9 Registers" rgroup.long 0x2090++0xB line.long 0x00 "QUEUE_9_A,Queue Manager Queue 9 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_9_B,Queue Manager Queue 9 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_9_C,Queue Manager Queue 9 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2090+0x0C)++0x3 line.long 0x00 "QUEUE_9_D,Queue Manager Queue 9 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3090++0xB line.long 0x00 "QUEUE_9_STATUS_A,Queue Manager Queue 9 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_9_STATUS_B,Queue Manager Queue 9 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_9_STATUS_C,Queue Manager Queue 9 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 10 Registers" rgroup.long 0x20A0++0xB line.long 0x00 "QUEUE_10_A,Queue Manager Queue 10 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_10_B,Queue Manager Queue 10 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_10_C,Queue Manager Queue 10 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x20A0+0x0C)++0x3 line.long 0x00 "QUEUE_10_D,Queue Manager Queue 10 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x30A0++0xB line.long 0x00 "QUEUE_10_STATUS_A,Queue Manager Queue 10 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_10_STATUS_B,Queue Manager Queue 10 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_10_STATUS_C,Queue Manager Queue 10 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 11 Registers" rgroup.long 0x20B0++0xB line.long 0x00 "QUEUE_11_A,Queue Manager Queue 11 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_11_B,Queue Manager Queue 11 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_11_C,Queue Manager Queue 11 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x20B0+0x0C)++0x3 line.long 0x00 "QUEUE_11_D,Queue Manager Queue 11 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x30B0++0xB line.long 0x00 "QUEUE_11_STATUS_A,Queue Manager Queue 11 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_11_STATUS_B,Queue Manager Queue 11 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_11_STATUS_C,Queue Manager Queue 11 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 12 Registers" rgroup.long 0x20C0++0xB line.long 0x00 "QUEUE_12_A,Queue Manager Queue 12 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_12_B,Queue Manager Queue 12 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_12_C,Queue Manager Queue 12 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x20C0+0x0C)++0x3 line.long 0x00 "QUEUE_12_D,Queue Manager Queue 12 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x30C0++0xB line.long 0x00 "QUEUE_12_STATUS_A,Queue Manager Queue 12 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_12_STATUS_B,Queue Manager Queue 12 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_12_STATUS_C,Queue Manager Queue 12 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 13 Registers" rgroup.long 0x20D0++0xB line.long 0x00 "QUEUE_13_A,Queue Manager Queue 13 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_13_B,Queue Manager Queue 13 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_13_C,Queue Manager Queue 13 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x20D0+0x0C)++0x3 line.long 0x00 "QUEUE_13_D,Queue Manager Queue 13 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x30D0++0xB line.long 0x00 "QUEUE_13_STATUS_A,Queue Manager Queue 13 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_13_STATUS_B,Queue Manager Queue 13 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_13_STATUS_C,Queue Manager Queue 13 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 14 Registers" rgroup.long 0x20E0++0xB line.long 0x00 "QUEUE_14_A,Queue Manager Queue 14 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_14_B,Queue Manager Queue 14 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_14_C,Queue Manager Queue 14 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x20E0+0x0C)++0x3 line.long 0x00 "QUEUE_14_D,Queue Manager Queue 14 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x30E0++0xB line.long 0x00 "QUEUE_14_STATUS_A,Queue Manager Queue 14 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_14_STATUS_B,Queue Manager Queue 14 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_14_STATUS_C,Queue Manager Queue 14 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 15 Registers" rgroup.long 0x20F0++0xB line.long 0x00 "QUEUE_15_A,Queue Manager Queue 15 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_15_B,Queue Manager Queue 15 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_15_C,Queue Manager Queue 15 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x20F0+0x0C)++0x3 line.long 0x00 "QUEUE_15_D,Queue Manager Queue 15 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x30F0++0xB line.long 0x00 "QUEUE_15_STATUS_A,Queue Manager Queue 15 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_15_STATUS_B,Queue Manager Queue 15 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_15_STATUS_C,Queue Manager Queue 15 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 16 Registers" rgroup.long 0x2100++0xB line.long 0x00 "QUEUE_16_A,Queue Manager Queue 16 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_16_B,Queue Manager Queue 16 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_16_C,Queue Manager Queue 16 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2100+0x0C)++0x3 line.long 0x00 "QUEUE_16_D,Queue Manager Queue 16 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3100++0xB line.long 0x00 "QUEUE_16_STATUS_A,Queue Manager Queue 16 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_16_STATUS_B,Queue Manager Queue 16 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_16_STATUS_C,Queue Manager Queue 16 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 17 Registers" rgroup.long 0x2110++0xB line.long 0x00 "QUEUE_17_A,Queue Manager Queue 17 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_17_B,Queue Manager Queue 17 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_17_C,Queue Manager Queue 17 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2110+0x0C)++0x3 line.long 0x00 "QUEUE_17_D,Queue Manager Queue 17 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3110++0xB line.long 0x00 "QUEUE_17_STATUS_A,Queue Manager Queue 17 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_17_STATUS_B,Queue Manager Queue 17 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_17_STATUS_C,Queue Manager Queue 17 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 18 Registers" rgroup.long 0x2120++0xB line.long 0x00 "QUEUE_18_A,Queue Manager Queue 18 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_18_B,Queue Manager Queue 18 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_18_C,Queue Manager Queue 18 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2120+0x0C)++0x3 line.long 0x00 "QUEUE_18_D,Queue Manager Queue 18 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3120++0xB line.long 0x00 "QUEUE_18_STATUS_A,Queue Manager Queue 18 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_18_STATUS_B,Queue Manager Queue 18 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_18_STATUS_C,Queue Manager Queue 18 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 19 Registers" rgroup.long 0x2130++0xB line.long 0x00 "QUEUE_19_A,Queue Manager Queue 19 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_19_B,Queue Manager Queue 19 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_19_C,Queue Manager Queue 19 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2130+0x0C)++0x3 line.long 0x00 "QUEUE_19_D,Queue Manager Queue 19 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3130++0xB line.long 0x00 "QUEUE_19_STATUS_A,Queue Manager Queue 19 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_19_STATUS_B,Queue Manager Queue 19 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_19_STATUS_C,Queue Manager Queue 19 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 20 Registers" rgroup.long 0x2140++0xB line.long 0x00 "QUEUE_20_A,Queue Manager Queue 20 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_20_B,Queue Manager Queue 20 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_20_C,Queue Manager Queue 20 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2140+0x0C)++0x3 line.long 0x00 "QUEUE_20_D,Queue Manager Queue 20 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3140++0xB line.long 0x00 "QUEUE_20_STATUS_A,Queue Manager Queue 20 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_20_STATUS_B,Queue Manager Queue 20 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_20_STATUS_C,Queue Manager Queue 20 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 21 Registers" rgroup.long 0x2150++0xB line.long 0x00 "QUEUE_21_A,Queue Manager Queue 21 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_21_B,Queue Manager Queue 21 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_21_C,Queue Manager Queue 21 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2150+0x0C)++0x3 line.long 0x00 "QUEUE_21_D,Queue Manager Queue 21 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3150++0xB line.long 0x00 "QUEUE_21_STATUS_A,Queue Manager Queue 21 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_21_STATUS_B,Queue Manager Queue 21 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_21_STATUS_C,Queue Manager Queue 21 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 22 Registers" rgroup.long 0x2160++0xB line.long 0x00 "QUEUE_22_A,Queue Manager Queue 22 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_22_B,Queue Manager Queue 22 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_22_C,Queue Manager Queue 22 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2160+0x0C)++0x3 line.long 0x00 "QUEUE_22_D,Queue Manager Queue 22 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3160++0xB line.long 0x00 "QUEUE_22_STATUS_A,Queue Manager Queue 22 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_22_STATUS_B,Queue Manager Queue 22 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_22_STATUS_C,Queue Manager Queue 22 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 23 Registers" rgroup.long 0x2170++0xB line.long 0x00 "QUEUE_23_A,Queue Manager Queue 23 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_23_B,Queue Manager Queue 23 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_23_C,Queue Manager Queue 23 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2170+0x0C)++0x3 line.long 0x00 "QUEUE_23_D,Queue Manager Queue 23 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3170++0xB line.long 0x00 "QUEUE_23_STATUS_A,Queue Manager Queue 23 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_23_STATUS_B,Queue Manager Queue 23 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_23_STATUS_C,Queue Manager Queue 23 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 24 Registers" rgroup.long 0x2180++0xB line.long 0x00 "QUEUE_24_A,Queue Manager Queue 24 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_24_B,Queue Manager Queue 24 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_24_C,Queue Manager Queue 24 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2180+0x0C)++0x3 line.long 0x00 "QUEUE_24_D,Queue Manager Queue 24 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3180++0xB line.long 0x00 "QUEUE_24_STATUS_A,Queue Manager Queue 24 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_24_STATUS_B,Queue Manager Queue 24 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_24_STATUS_C,Queue Manager Queue 24 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 25 Registers" rgroup.long 0x2190++0xB line.long 0x00 "QUEUE_25_A,Queue Manager Queue 25 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_25_B,Queue Manager Queue 25 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_25_C,Queue Manager Queue 25 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2190+0x0C)++0x3 line.long 0x00 "QUEUE_25_D,Queue Manager Queue 25 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3190++0xB line.long 0x00 "QUEUE_25_STATUS_A,Queue Manager Queue 25 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_25_STATUS_B,Queue Manager Queue 25 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_25_STATUS_C,Queue Manager Queue 25 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 26 Registers" rgroup.long 0x21A0++0xB line.long 0x00 "QUEUE_26_A,Queue Manager Queue 26 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_26_B,Queue Manager Queue 26 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_26_C,Queue Manager Queue 26 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x21A0+0x0C)++0x3 line.long 0x00 "QUEUE_26_D,Queue Manager Queue 26 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x31A0++0xB line.long 0x00 "QUEUE_26_STATUS_A,Queue Manager Queue 26 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_26_STATUS_B,Queue Manager Queue 26 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_26_STATUS_C,Queue Manager Queue 26 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 27 Registers" rgroup.long 0x21B0++0xB line.long 0x00 "QUEUE_27_A,Queue Manager Queue 27 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_27_B,Queue Manager Queue 27 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_27_C,Queue Manager Queue 27 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x21B0+0x0C)++0x3 line.long 0x00 "QUEUE_27_D,Queue Manager Queue 27 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x31B0++0xB line.long 0x00 "QUEUE_27_STATUS_A,Queue Manager Queue 27 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_27_STATUS_B,Queue Manager Queue 27 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_27_STATUS_C,Queue Manager Queue 27 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 28 Registers" rgroup.long 0x21C0++0xB line.long 0x00 "QUEUE_28_A,Queue Manager Queue 28 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_28_B,Queue Manager Queue 28 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_28_C,Queue Manager Queue 28 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x21C0+0x0C)++0x3 line.long 0x00 "QUEUE_28_D,Queue Manager Queue 28 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x31C0++0xB line.long 0x00 "QUEUE_28_STATUS_A,Queue Manager Queue 28 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_28_STATUS_B,Queue Manager Queue 28 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_28_STATUS_C,Queue Manager Queue 28 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 29 Registers" rgroup.long 0x21D0++0xB line.long 0x00 "QUEUE_29_A,Queue Manager Queue 29 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_29_B,Queue Manager Queue 29 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_29_C,Queue Manager Queue 29 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x21D0+0x0C)++0x3 line.long 0x00 "QUEUE_29_D,Queue Manager Queue 29 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x31D0++0xB line.long 0x00 "QUEUE_29_STATUS_A,Queue Manager Queue 29 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_29_STATUS_B,Queue Manager Queue 29 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_29_STATUS_C,Queue Manager Queue 29 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 30 Registers" rgroup.long 0x21E0++0xB line.long 0x00 "QUEUE_30_A,Queue Manager Queue 30 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_30_B,Queue Manager Queue 30 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_30_C,Queue Manager Queue 30 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x21E0+0x0C)++0x3 line.long 0x00 "QUEUE_30_D,Queue Manager Queue 30 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x31E0++0xB line.long 0x00 "QUEUE_30_STATUS_A,Queue Manager Queue 30 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_30_STATUS_B,Queue Manager Queue 30 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_30_STATUS_C,Queue Manager Queue 30 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 31 Registers" rgroup.long 0x21F0++0xB line.long 0x00 "QUEUE_31_A,Queue Manager Queue 31 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_31_B,Queue Manager Queue 31 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_31_C,Queue Manager Queue 31 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x21F0+0x0C)++0x3 line.long 0x00 "QUEUE_31_D,Queue Manager Queue 31 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x31F0++0xB line.long 0x00 "QUEUE_31_STATUS_A,Queue Manager Queue 31 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_31_STATUS_B,Queue Manager Queue 31 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_31_STATUS_C,Queue Manager Queue 31 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 32 Registers" rgroup.long 0x2200++0xB line.long 0x00 "QUEUE_32_A,Queue Manager Queue 32 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_32_B,Queue Manager Queue 32 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_32_C,Queue Manager Queue 32 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2200+0x0C)++0x3 line.long 0x00 "QUEUE_32_D,Queue Manager Queue 32 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3200++0xB line.long 0x00 "QUEUE_32_STATUS_A,Queue Manager Queue 32 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_32_STATUS_B,Queue Manager Queue 32 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_32_STATUS_C,Queue Manager Queue 32 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 33 Registers" rgroup.long 0x2210++0xB line.long 0x00 "QUEUE_33_A,Queue Manager Queue 33 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_33_B,Queue Manager Queue 33 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_33_C,Queue Manager Queue 33 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2210+0x0C)++0x3 line.long 0x00 "QUEUE_33_D,Queue Manager Queue 33 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3210++0xB line.long 0x00 "QUEUE_33_STATUS_A,Queue Manager Queue 33 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_33_STATUS_B,Queue Manager Queue 33 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_33_STATUS_C,Queue Manager Queue 33 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 34 Registers" rgroup.long 0x2220++0xB line.long 0x00 "QUEUE_34_A,Queue Manager Queue 34 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_34_B,Queue Manager Queue 34 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_34_C,Queue Manager Queue 34 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2220+0x0C)++0x3 line.long 0x00 "QUEUE_34_D,Queue Manager Queue 34 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3220++0xB line.long 0x00 "QUEUE_34_STATUS_A,Queue Manager Queue 34 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_34_STATUS_B,Queue Manager Queue 34 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_34_STATUS_C,Queue Manager Queue 34 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 35 Registers" rgroup.long 0x2230++0xB line.long 0x00 "QUEUE_35_A,Queue Manager Queue 35 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_35_B,Queue Manager Queue 35 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_35_C,Queue Manager Queue 35 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2230+0x0C)++0x3 line.long 0x00 "QUEUE_35_D,Queue Manager Queue 35 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3230++0xB line.long 0x00 "QUEUE_35_STATUS_A,Queue Manager Queue 35 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_35_STATUS_B,Queue Manager Queue 35 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_35_STATUS_C,Queue Manager Queue 35 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 36 Registers" rgroup.long 0x2240++0xB line.long 0x00 "QUEUE_36_A,Queue Manager Queue 36 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_36_B,Queue Manager Queue 36 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_36_C,Queue Manager Queue 36 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2240+0x0C)++0x3 line.long 0x00 "QUEUE_36_D,Queue Manager Queue 36 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3240++0xB line.long 0x00 "QUEUE_36_STATUS_A,Queue Manager Queue 36 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_36_STATUS_B,Queue Manager Queue 36 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_36_STATUS_C,Queue Manager Queue 36 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 37 Registers" rgroup.long 0x2250++0xB line.long 0x00 "QUEUE_37_A,Queue Manager Queue 37 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_37_B,Queue Manager Queue 37 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_37_C,Queue Manager Queue 37 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2250+0x0C)++0x3 line.long 0x00 "QUEUE_37_D,Queue Manager Queue 37 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3250++0xB line.long 0x00 "QUEUE_37_STATUS_A,Queue Manager Queue 37 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_37_STATUS_B,Queue Manager Queue 37 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_37_STATUS_C,Queue Manager Queue 37 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 38 Registers" rgroup.long 0x2260++0xB line.long 0x00 "QUEUE_38_A,Queue Manager Queue 38 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_38_B,Queue Manager Queue 38 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_38_C,Queue Manager Queue 38 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2260+0x0C)++0x3 line.long 0x00 "QUEUE_38_D,Queue Manager Queue 38 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3260++0xB line.long 0x00 "QUEUE_38_STATUS_A,Queue Manager Queue 38 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_38_STATUS_B,Queue Manager Queue 38 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_38_STATUS_C,Queue Manager Queue 38 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 39 Registers" rgroup.long 0x2270++0xB line.long 0x00 "QUEUE_39_A,Queue Manager Queue 39 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_39_B,Queue Manager Queue 39 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_39_C,Queue Manager Queue 39 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2270+0x0C)++0x3 line.long 0x00 "QUEUE_39_D,Queue Manager Queue 39 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3270++0xB line.long 0x00 "QUEUE_39_STATUS_A,Queue Manager Queue 39 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_39_STATUS_B,Queue Manager Queue 39 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_39_STATUS_C,Queue Manager Queue 39 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 40 Registers" rgroup.long 0x2280++0xB line.long 0x00 "QUEUE_40_A,Queue Manager Queue 40 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_40_B,Queue Manager Queue 40 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_40_C,Queue Manager Queue 40 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2280+0x0C)++0x3 line.long 0x00 "QUEUE_40_D,Queue Manager Queue 40 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3280++0xB line.long 0x00 "QUEUE_40_STATUS_A,Queue Manager Queue 40 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_40_STATUS_B,Queue Manager Queue 40 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_40_STATUS_C,Queue Manager Queue 40 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 41 Registers" rgroup.long 0x2290++0xB line.long 0x00 "QUEUE_41_A,Queue Manager Queue 41 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_41_B,Queue Manager Queue 41 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_41_C,Queue Manager Queue 41 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2290+0x0C)++0x3 line.long 0x00 "QUEUE_41_D,Queue Manager Queue 41 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3290++0xB line.long 0x00 "QUEUE_41_STATUS_A,Queue Manager Queue 41 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_41_STATUS_B,Queue Manager Queue 41 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_41_STATUS_C,Queue Manager Queue 41 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 42 Registers" rgroup.long 0x22A0++0xB line.long 0x00 "QUEUE_42_A,Queue Manager Queue 42 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_42_B,Queue Manager Queue 42 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_42_C,Queue Manager Queue 42 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x22A0+0x0C)++0x3 line.long 0x00 "QUEUE_42_D,Queue Manager Queue 42 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x32A0++0xB line.long 0x00 "QUEUE_42_STATUS_A,Queue Manager Queue 42 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_42_STATUS_B,Queue Manager Queue 42 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_42_STATUS_C,Queue Manager Queue 42 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 43 Registers" rgroup.long 0x22B0++0xB line.long 0x00 "QUEUE_43_A,Queue Manager Queue 43 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_43_B,Queue Manager Queue 43 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_43_C,Queue Manager Queue 43 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x22B0+0x0C)++0x3 line.long 0x00 "QUEUE_43_D,Queue Manager Queue 43 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x32B0++0xB line.long 0x00 "QUEUE_43_STATUS_A,Queue Manager Queue 43 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_43_STATUS_B,Queue Manager Queue 43 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_43_STATUS_C,Queue Manager Queue 43 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 44 Registers" rgroup.long 0x22C0++0xB line.long 0x00 "QUEUE_44_A,Queue Manager Queue 44 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_44_B,Queue Manager Queue 44 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_44_C,Queue Manager Queue 44 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x22C0+0x0C)++0x3 line.long 0x00 "QUEUE_44_D,Queue Manager Queue 44 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x32C0++0xB line.long 0x00 "QUEUE_44_STATUS_A,Queue Manager Queue 44 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_44_STATUS_B,Queue Manager Queue 44 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_44_STATUS_C,Queue Manager Queue 44 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 45 Registers" rgroup.long 0x22D0++0xB line.long 0x00 "QUEUE_45_A,Queue Manager Queue 45 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_45_B,Queue Manager Queue 45 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_45_C,Queue Manager Queue 45 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x22D0+0x0C)++0x3 line.long 0x00 "QUEUE_45_D,Queue Manager Queue 45 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x32D0++0xB line.long 0x00 "QUEUE_45_STATUS_A,Queue Manager Queue 45 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_45_STATUS_B,Queue Manager Queue 45 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_45_STATUS_C,Queue Manager Queue 45 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 46 Registers" rgroup.long 0x22E0++0xB line.long 0x00 "QUEUE_46_A,Queue Manager Queue 46 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_46_B,Queue Manager Queue 46 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_46_C,Queue Manager Queue 46 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x22E0+0x0C)++0x3 line.long 0x00 "QUEUE_46_D,Queue Manager Queue 46 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x32E0++0xB line.long 0x00 "QUEUE_46_STATUS_A,Queue Manager Queue 46 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_46_STATUS_B,Queue Manager Queue 46 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_46_STATUS_C,Queue Manager Queue 46 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 47 Registers" rgroup.long 0x22F0++0xB line.long 0x00 "QUEUE_47_A,Queue Manager Queue 47 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_47_B,Queue Manager Queue 47 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_47_C,Queue Manager Queue 47 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x22F0+0x0C)++0x3 line.long 0x00 "QUEUE_47_D,Queue Manager Queue 47 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x32F0++0xB line.long 0x00 "QUEUE_47_STATUS_A,Queue Manager Queue 47 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_47_STATUS_B,Queue Manager Queue 47 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_47_STATUS_C,Queue Manager Queue 47 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 48 Registers" rgroup.long 0x2300++0xB line.long 0x00 "QUEUE_48_A,Queue Manager Queue 48 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_48_B,Queue Manager Queue 48 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_48_C,Queue Manager Queue 48 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2300+0x0C)++0x3 line.long 0x00 "QUEUE_48_D,Queue Manager Queue 48 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3300++0xB line.long 0x00 "QUEUE_48_STATUS_A,Queue Manager Queue 48 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_48_STATUS_B,Queue Manager Queue 48 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_48_STATUS_C,Queue Manager Queue 48 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 49 Registers" rgroup.long 0x2310++0xB line.long 0x00 "QUEUE_49_A,Queue Manager Queue 49 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_49_B,Queue Manager Queue 49 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_49_C,Queue Manager Queue 49 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2310+0x0C)++0x3 line.long 0x00 "QUEUE_49_D,Queue Manager Queue 49 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3310++0xB line.long 0x00 "QUEUE_49_STATUS_A,Queue Manager Queue 49 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_49_STATUS_B,Queue Manager Queue 49 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_49_STATUS_C,Queue Manager Queue 49 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 50 Registers" rgroup.long 0x2320++0xB line.long 0x00 "QUEUE_50_A,Queue Manager Queue 50 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_50_B,Queue Manager Queue 50 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_50_C,Queue Manager Queue 50 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2320+0x0C)++0x3 line.long 0x00 "QUEUE_50_D,Queue Manager Queue 50 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3320++0xB line.long 0x00 "QUEUE_50_STATUS_A,Queue Manager Queue 50 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_50_STATUS_B,Queue Manager Queue 50 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_50_STATUS_C,Queue Manager Queue 50 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 51 Registers" rgroup.long 0x2330++0xB line.long 0x00 "QUEUE_51_A,Queue Manager Queue 51 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_51_B,Queue Manager Queue 51 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_51_C,Queue Manager Queue 51 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2330+0x0C)++0x3 line.long 0x00 "QUEUE_51_D,Queue Manager Queue 51 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3330++0xB line.long 0x00 "QUEUE_51_STATUS_A,Queue Manager Queue 51 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_51_STATUS_B,Queue Manager Queue 51 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_51_STATUS_C,Queue Manager Queue 51 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 52 Registers" rgroup.long 0x2340++0xB line.long 0x00 "QUEUE_52_A,Queue Manager Queue 52 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_52_B,Queue Manager Queue 52 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_52_C,Queue Manager Queue 52 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2340+0x0C)++0x3 line.long 0x00 "QUEUE_52_D,Queue Manager Queue 52 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3340++0xB line.long 0x00 "QUEUE_52_STATUS_A,Queue Manager Queue 52 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_52_STATUS_B,Queue Manager Queue 52 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_52_STATUS_C,Queue Manager Queue 52 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 53 Registers" rgroup.long 0x2350++0xB line.long 0x00 "QUEUE_53_A,Queue Manager Queue 53 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_53_B,Queue Manager Queue 53 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_53_C,Queue Manager Queue 53 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2350+0x0C)++0x3 line.long 0x00 "QUEUE_53_D,Queue Manager Queue 53 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3350++0xB line.long 0x00 "QUEUE_53_STATUS_A,Queue Manager Queue 53 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_53_STATUS_B,Queue Manager Queue 53 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_53_STATUS_C,Queue Manager Queue 53 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 54 Registers" rgroup.long 0x2360++0xB line.long 0x00 "QUEUE_54_A,Queue Manager Queue 54 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_54_B,Queue Manager Queue 54 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_54_C,Queue Manager Queue 54 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2360+0x0C)++0x3 line.long 0x00 "QUEUE_54_D,Queue Manager Queue 54 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3360++0xB line.long 0x00 "QUEUE_54_STATUS_A,Queue Manager Queue 54 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_54_STATUS_B,Queue Manager Queue 54 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_54_STATUS_C,Queue Manager Queue 54 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 55 Registers" rgroup.long 0x2370++0xB line.long 0x00 "QUEUE_55_A,Queue Manager Queue 55 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_55_B,Queue Manager Queue 55 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_55_C,Queue Manager Queue 55 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2370+0x0C)++0x3 line.long 0x00 "QUEUE_55_D,Queue Manager Queue 55 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3370++0xB line.long 0x00 "QUEUE_55_STATUS_A,Queue Manager Queue 55 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_55_STATUS_B,Queue Manager Queue 55 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_55_STATUS_C,Queue Manager Queue 55 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 56 Registers" rgroup.long 0x2380++0xB line.long 0x00 "QUEUE_56_A,Queue Manager Queue 56 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_56_B,Queue Manager Queue 56 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_56_C,Queue Manager Queue 56 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2380+0x0C)++0x3 line.long 0x00 "QUEUE_56_D,Queue Manager Queue 56 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3380++0xB line.long 0x00 "QUEUE_56_STATUS_A,Queue Manager Queue 56 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_56_STATUS_B,Queue Manager Queue 56 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_56_STATUS_C,Queue Manager Queue 56 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 57 Registers" rgroup.long 0x2390++0xB line.long 0x00 "QUEUE_57_A,Queue Manager Queue 57 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_57_B,Queue Manager Queue 57 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_57_C,Queue Manager Queue 57 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2390+0x0C)++0x3 line.long 0x00 "QUEUE_57_D,Queue Manager Queue 57 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3390++0xB line.long 0x00 "QUEUE_57_STATUS_A,Queue Manager Queue 57 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_57_STATUS_B,Queue Manager Queue 57 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_57_STATUS_C,Queue Manager Queue 57 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 58 Registers" rgroup.long 0x23A0++0xB line.long 0x00 "QUEUE_58_A,Queue Manager Queue 58 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_58_B,Queue Manager Queue 58 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_58_C,Queue Manager Queue 58 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x23A0+0x0C)++0x3 line.long 0x00 "QUEUE_58_D,Queue Manager Queue 58 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x33A0++0xB line.long 0x00 "QUEUE_58_STATUS_A,Queue Manager Queue 58 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_58_STATUS_B,Queue Manager Queue 58 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_58_STATUS_C,Queue Manager Queue 58 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 59 Registers" rgroup.long 0x23B0++0xB line.long 0x00 "QUEUE_59_A,Queue Manager Queue 59 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_59_B,Queue Manager Queue 59 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_59_C,Queue Manager Queue 59 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x23B0+0x0C)++0x3 line.long 0x00 "QUEUE_59_D,Queue Manager Queue 59 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x33B0++0xB line.long 0x00 "QUEUE_59_STATUS_A,Queue Manager Queue 59 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_59_STATUS_B,Queue Manager Queue 59 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_59_STATUS_C,Queue Manager Queue 59 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 60 Registers" rgroup.long 0x23C0++0xB line.long 0x00 "QUEUE_60_A,Queue Manager Queue 60 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_60_B,Queue Manager Queue 60 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_60_C,Queue Manager Queue 60 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x23C0+0x0C)++0x3 line.long 0x00 "QUEUE_60_D,Queue Manager Queue 60 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x33C0++0xB line.long 0x00 "QUEUE_60_STATUS_A,Queue Manager Queue 60 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_60_STATUS_B,Queue Manager Queue 60 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_60_STATUS_C,Queue Manager Queue 60 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 61 Registers" rgroup.long 0x23D0++0xB line.long 0x00 "QUEUE_61_A,Queue Manager Queue 61 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_61_B,Queue Manager Queue 61 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_61_C,Queue Manager Queue 61 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x23D0+0x0C)++0x3 line.long 0x00 "QUEUE_61_D,Queue Manager Queue 61 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x33D0++0xB line.long 0x00 "QUEUE_61_STATUS_A,Queue Manager Queue 61 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_61_STATUS_B,Queue Manager Queue 61 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_61_STATUS_C,Queue Manager Queue 61 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 62 Registers" rgroup.long 0x23E0++0xB line.long 0x00 "QUEUE_62_A,Queue Manager Queue 62 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_62_B,Queue Manager Queue 62 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_62_C,Queue Manager Queue 62 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x23E0+0x0C)++0x3 line.long 0x00 "QUEUE_62_D,Queue Manager Queue 62 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x33E0++0xB line.long 0x00 "QUEUE_62_STATUS_A,Queue Manager Queue 62 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_62_STATUS_B,Queue Manager Queue 62 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_62_STATUS_C,Queue Manager Queue 62 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 63 Registers" rgroup.long 0x23F0++0xB line.long 0x00 "QUEUE_63_A,Queue Manager Queue 63 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_63_B,Queue Manager Queue 63 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_63_C,Queue Manager Queue 63 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x23F0+0x0C)++0x3 line.long 0x00 "QUEUE_63_D,Queue Manager Queue 63 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x33F0++0xB line.long 0x00 "QUEUE_63_STATUS_A,Queue Manager Queue 63 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_63_STATUS_B,Queue Manager Queue 63 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_63_STATUS_C,Queue Manager Queue 63 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 64 Registers" rgroup.long 0x2400++0xB line.long 0x00 "QUEUE_64_A,Queue Manager Queue 64 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_64_B,Queue Manager Queue 64 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_64_C,Queue Manager Queue 64 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2400+0x0C)++0x3 line.long 0x00 "QUEUE_64_D,Queue Manager Queue 64 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3400++0xB line.long 0x00 "QUEUE_64_STATUS_A,Queue Manager Queue 64 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_64_STATUS_B,Queue Manager Queue 64 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_64_STATUS_C,Queue Manager Queue 64 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 65 Registers" rgroup.long 0x2410++0xB line.long 0x00 "QUEUE_65_A,Queue Manager Queue 65 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_65_B,Queue Manager Queue 65 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_65_C,Queue Manager Queue 65 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2410+0x0C)++0x3 line.long 0x00 "QUEUE_65_D,Queue Manager Queue 65 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3410++0xB line.long 0x00 "QUEUE_65_STATUS_A,Queue Manager Queue 65 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_65_STATUS_B,Queue Manager Queue 65 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_65_STATUS_C,Queue Manager Queue 65 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 66 Registers" rgroup.long 0x2420++0xB line.long 0x00 "QUEUE_66_A,Queue Manager Queue 66 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_66_B,Queue Manager Queue 66 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_66_C,Queue Manager Queue 66 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2420+0x0C)++0x3 line.long 0x00 "QUEUE_66_D,Queue Manager Queue 66 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3420++0xB line.long 0x00 "QUEUE_66_STATUS_A,Queue Manager Queue 66 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_66_STATUS_B,Queue Manager Queue 66 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_66_STATUS_C,Queue Manager Queue 66 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 67 Registers" rgroup.long 0x2430++0xB line.long 0x00 "QUEUE_67_A,Queue Manager Queue 67 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_67_B,Queue Manager Queue 67 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_67_C,Queue Manager Queue 67 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2430+0x0C)++0x3 line.long 0x00 "QUEUE_67_D,Queue Manager Queue 67 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3430++0xB line.long 0x00 "QUEUE_67_STATUS_A,Queue Manager Queue 67 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_67_STATUS_B,Queue Manager Queue 67 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_67_STATUS_C,Queue Manager Queue 67 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 68 Registers" rgroup.long 0x2440++0xB line.long 0x00 "QUEUE_68_A,Queue Manager Queue 68 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_68_B,Queue Manager Queue 68 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_68_C,Queue Manager Queue 68 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2440+0x0C)++0x3 line.long 0x00 "QUEUE_68_D,Queue Manager Queue 68 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3440++0xB line.long 0x00 "QUEUE_68_STATUS_A,Queue Manager Queue 68 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_68_STATUS_B,Queue Manager Queue 68 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_68_STATUS_C,Queue Manager Queue 68 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 69 Registers" rgroup.long 0x2450++0xB line.long 0x00 "QUEUE_69_A,Queue Manager Queue 69 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_69_B,Queue Manager Queue 69 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_69_C,Queue Manager Queue 69 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2450+0x0C)++0x3 line.long 0x00 "QUEUE_69_D,Queue Manager Queue 69 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3450++0xB line.long 0x00 "QUEUE_69_STATUS_A,Queue Manager Queue 69 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_69_STATUS_B,Queue Manager Queue 69 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_69_STATUS_C,Queue Manager Queue 69 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 70 Registers" rgroup.long 0x2460++0xB line.long 0x00 "QUEUE_70_A,Queue Manager Queue 70 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_70_B,Queue Manager Queue 70 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_70_C,Queue Manager Queue 70 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2460+0x0C)++0x3 line.long 0x00 "QUEUE_70_D,Queue Manager Queue 70 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3460++0xB line.long 0x00 "QUEUE_70_STATUS_A,Queue Manager Queue 70 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_70_STATUS_B,Queue Manager Queue 70 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_70_STATUS_C,Queue Manager Queue 70 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 71 Registers" rgroup.long 0x2470++0xB line.long 0x00 "QUEUE_71_A,Queue Manager Queue 71 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_71_B,Queue Manager Queue 71 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_71_C,Queue Manager Queue 71 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2470+0x0C)++0x3 line.long 0x00 "QUEUE_71_D,Queue Manager Queue 71 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3470++0xB line.long 0x00 "QUEUE_71_STATUS_A,Queue Manager Queue 71 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_71_STATUS_B,Queue Manager Queue 71 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_71_STATUS_C,Queue Manager Queue 71 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 72 Registers" rgroup.long 0x2480++0xB line.long 0x00 "QUEUE_72_A,Queue Manager Queue 72 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_72_B,Queue Manager Queue 72 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_72_C,Queue Manager Queue 72 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2480+0x0C)++0x3 line.long 0x00 "QUEUE_72_D,Queue Manager Queue 72 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3480++0xB line.long 0x00 "QUEUE_72_STATUS_A,Queue Manager Queue 72 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_72_STATUS_B,Queue Manager Queue 72 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_72_STATUS_C,Queue Manager Queue 72 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 73 Registers" rgroup.long 0x2490++0xB line.long 0x00 "QUEUE_73_A,Queue Manager Queue 73 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_73_B,Queue Manager Queue 73 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_73_C,Queue Manager Queue 73 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2490+0x0C)++0x3 line.long 0x00 "QUEUE_73_D,Queue Manager Queue 73 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3490++0xB line.long 0x00 "QUEUE_73_STATUS_A,Queue Manager Queue 73 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_73_STATUS_B,Queue Manager Queue 73 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_73_STATUS_C,Queue Manager Queue 73 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 74 Registers" rgroup.long 0x24A0++0xB line.long 0x00 "QUEUE_74_A,Queue Manager Queue 74 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_74_B,Queue Manager Queue 74 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_74_C,Queue Manager Queue 74 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x24A0+0x0C)++0x3 line.long 0x00 "QUEUE_74_D,Queue Manager Queue 74 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x34A0++0xB line.long 0x00 "QUEUE_74_STATUS_A,Queue Manager Queue 74 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_74_STATUS_B,Queue Manager Queue 74 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_74_STATUS_C,Queue Manager Queue 74 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 75 Registers" rgroup.long 0x24B0++0xB line.long 0x00 "QUEUE_75_A,Queue Manager Queue 75 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_75_B,Queue Manager Queue 75 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_75_C,Queue Manager Queue 75 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x24B0+0x0C)++0x3 line.long 0x00 "QUEUE_75_D,Queue Manager Queue 75 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x34B0++0xB line.long 0x00 "QUEUE_75_STATUS_A,Queue Manager Queue 75 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_75_STATUS_B,Queue Manager Queue 75 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_75_STATUS_C,Queue Manager Queue 75 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 76 Registers" rgroup.long 0x24C0++0xB line.long 0x00 "QUEUE_76_A,Queue Manager Queue 76 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_76_B,Queue Manager Queue 76 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_76_C,Queue Manager Queue 76 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x24C0+0x0C)++0x3 line.long 0x00 "QUEUE_76_D,Queue Manager Queue 76 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x34C0++0xB line.long 0x00 "QUEUE_76_STATUS_A,Queue Manager Queue 76 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_76_STATUS_B,Queue Manager Queue 76 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_76_STATUS_C,Queue Manager Queue 76 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 77 Registers" rgroup.long 0x24D0++0xB line.long 0x00 "QUEUE_77_A,Queue Manager Queue 77 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_77_B,Queue Manager Queue 77 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_77_C,Queue Manager Queue 77 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x24D0+0x0C)++0x3 line.long 0x00 "QUEUE_77_D,Queue Manager Queue 77 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x34D0++0xB line.long 0x00 "QUEUE_77_STATUS_A,Queue Manager Queue 77 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_77_STATUS_B,Queue Manager Queue 77 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_77_STATUS_C,Queue Manager Queue 77 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 78 Registers" rgroup.long 0x24E0++0xB line.long 0x00 "QUEUE_78_A,Queue Manager Queue 78 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_78_B,Queue Manager Queue 78 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_78_C,Queue Manager Queue 78 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x24E0+0x0C)++0x3 line.long 0x00 "QUEUE_78_D,Queue Manager Queue 78 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x34E0++0xB line.long 0x00 "QUEUE_78_STATUS_A,Queue Manager Queue 78 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_78_STATUS_B,Queue Manager Queue 78 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_78_STATUS_C,Queue Manager Queue 78 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 79 Registers" rgroup.long 0x24F0++0xB line.long 0x00 "QUEUE_79_A,Queue Manager Queue 79 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_79_B,Queue Manager Queue 79 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_79_C,Queue Manager Queue 79 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x24F0+0x0C)++0x3 line.long 0x00 "QUEUE_79_D,Queue Manager Queue 79 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x34F0++0xB line.long 0x00 "QUEUE_79_STATUS_A,Queue Manager Queue 79 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_79_STATUS_B,Queue Manager Queue 79 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_79_STATUS_C,Queue Manager Queue 79 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 80 Registers" rgroup.long 0x2500++0xB line.long 0x00 "QUEUE_80_A,Queue Manager Queue 80 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_80_B,Queue Manager Queue 80 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_80_C,Queue Manager Queue 80 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2500+0x0C)++0x3 line.long 0x00 "QUEUE_80_D,Queue Manager Queue 80 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3500++0xB line.long 0x00 "QUEUE_80_STATUS_A,Queue Manager Queue 80 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_80_STATUS_B,Queue Manager Queue 80 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_80_STATUS_C,Queue Manager Queue 80 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 81 Registers" rgroup.long 0x2510++0xB line.long 0x00 "QUEUE_81_A,Queue Manager Queue 81 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_81_B,Queue Manager Queue 81 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_81_C,Queue Manager Queue 81 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2510+0x0C)++0x3 line.long 0x00 "QUEUE_81_D,Queue Manager Queue 81 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3510++0xB line.long 0x00 "QUEUE_81_STATUS_A,Queue Manager Queue 81 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_81_STATUS_B,Queue Manager Queue 81 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_81_STATUS_C,Queue Manager Queue 81 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 82 Registers" rgroup.long 0x2520++0xB line.long 0x00 "QUEUE_82_A,Queue Manager Queue 82 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_82_B,Queue Manager Queue 82 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_82_C,Queue Manager Queue 82 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2520+0x0C)++0x3 line.long 0x00 "QUEUE_82_D,Queue Manager Queue 82 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3520++0xB line.long 0x00 "QUEUE_82_STATUS_A,Queue Manager Queue 82 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_82_STATUS_B,Queue Manager Queue 82 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_82_STATUS_C,Queue Manager Queue 82 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 83 Registers" rgroup.long 0x2530++0xB line.long 0x00 "QUEUE_83_A,Queue Manager Queue 83 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_83_B,Queue Manager Queue 83 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_83_C,Queue Manager Queue 83 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2530+0x0C)++0x3 line.long 0x00 "QUEUE_83_D,Queue Manager Queue 83 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3530++0xB line.long 0x00 "QUEUE_83_STATUS_A,Queue Manager Queue 83 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_83_STATUS_B,Queue Manager Queue 83 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_83_STATUS_C,Queue Manager Queue 83 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 84 Registers" rgroup.long 0x2540++0xB line.long 0x00 "QUEUE_84_A,Queue Manager Queue 84 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_84_B,Queue Manager Queue 84 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_84_C,Queue Manager Queue 84 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2540+0x0C)++0x3 line.long 0x00 "QUEUE_84_D,Queue Manager Queue 84 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3540++0xB line.long 0x00 "QUEUE_84_STATUS_A,Queue Manager Queue 84 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_84_STATUS_B,Queue Manager Queue 84 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_84_STATUS_C,Queue Manager Queue 84 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 85 Registers" rgroup.long 0x2550++0xB line.long 0x00 "QUEUE_85_A,Queue Manager Queue 85 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_85_B,Queue Manager Queue 85 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_85_C,Queue Manager Queue 85 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2550+0x0C)++0x3 line.long 0x00 "QUEUE_85_D,Queue Manager Queue 85 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3550++0xB line.long 0x00 "QUEUE_85_STATUS_A,Queue Manager Queue 85 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_85_STATUS_B,Queue Manager Queue 85 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_85_STATUS_C,Queue Manager Queue 85 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 86 Registers" rgroup.long 0x2560++0xB line.long 0x00 "QUEUE_86_A,Queue Manager Queue 86 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_86_B,Queue Manager Queue 86 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_86_C,Queue Manager Queue 86 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2560+0x0C)++0x3 line.long 0x00 "QUEUE_86_D,Queue Manager Queue 86 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3560++0xB line.long 0x00 "QUEUE_86_STATUS_A,Queue Manager Queue 86 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_86_STATUS_B,Queue Manager Queue 86 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_86_STATUS_C,Queue Manager Queue 86 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 87 Registers" rgroup.long 0x2570++0xB line.long 0x00 "QUEUE_87_A,Queue Manager Queue 87 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_87_B,Queue Manager Queue 87 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_87_C,Queue Manager Queue 87 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2570+0x0C)++0x3 line.long 0x00 "QUEUE_87_D,Queue Manager Queue 87 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3570++0xB line.long 0x00 "QUEUE_87_STATUS_A,Queue Manager Queue 87 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_87_STATUS_B,Queue Manager Queue 87 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_87_STATUS_C,Queue Manager Queue 87 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 88 Registers" rgroup.long 0x2580++0xB line.long 0x00 "QUEUE_88_A,Queue Manager Queue 88 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_88_B,Queue Manager Queue 88 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_88_C,Queue Manager Queue 88 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2580+0x0C)++0x3 line.long 0x00 "QUEUE_88_D,Queue Manager Queue 88 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3580++0xB line.long 0x00 "QUEUE_88_STATUS_A,Queue Manager Queue 88 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_88_STATUS_B,Queue Manager Queue 88 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_88_STATUS_C,Queue Manager Queue 88 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 89 Registers" rgroup.long 0x2590++0xB line.long 0x00 "QUEUE_89_A,Queue Manager Queue 89 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_89_B,Queue Manager Queue 89 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_89_C,Queue Manager Queue 89 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2590+0x0C)++0x3 line.long 0x00 "QUEUE_89_D,Queue Manager Queue 89 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3590++0xB line.long 0x00 "QUEUE_89_STATUS_A,Queue Manager Queue 89 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_89_STATUS_B,Queue Manager Queue 89 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_89_STATUS_C,Queue Manager Queue 89 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 90 Registers" rgroup.long 0x25A0++0xB line.long 0x00 "QUEUE_90_A,Queue Manager Queue 90 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_90_B,Queue Manager Queue 90 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_90_C,Queue Manager Queue 90 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x25A0+0x0C)++0x3 line.long 0x00 "QUEUE_90_D,Queue Manager Queue 90 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x35A0++0xB line.long 0x00 "QUEUE_90_STATUS_A,Queue Manager Queue 90 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_90_STATUS_B,Queue Manager Queue 90 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_90_STATUS_C,Queue Manager Queue 90 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 91 Registers" rgroup.long 0x25B0++0xB line.long 0x00 "QUEUE_91_A,Queue Manager Queue 91 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_91_B,Queue Manager Queue 91 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_91_C,Queue Manager Queue 91 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x25B0+0x0C)++0x3 line.long 0x00 "QUEUE_91_D,Queue Manager Queue 91 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x35B0++0xB line.long 0x00 "QUEUE_91_STATUS_A,Queue Manager Queue 91 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_91_STATUS_B,Queue Manager Queue 91 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_91_STATUS_C,Queue Manager Queue 91 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 92 Registers" rgroup.long 0x25C0++0xB line.long 0x00 "QUEUE_92_A,Queue Manager Queue 92 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_92_B,Queue Manager Queue 92 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_92_C,Queue Manager Queue 92 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x25C0+0x0C)++0x3 line.long 0x00 "QUEUE_92_D,Queue Manager Queue 92 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x35C0++0xB line.long 0x00 "QUEUE_92_STATUS_A,Queue Manager Queue 92 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_92_STATUS_B,Queue Manager Queue 92 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_92_STATUS_C,Queue Manager Queue 92 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 93 Registers" rgroup.long 0x25D0++0xB line.long 0x00 "QUEUE_93_A,Queue Manager Queue 93 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_93_B,Queue Manager Queue 93 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_93_C,Queue Manager Queue 93 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x25D0+0x0C)++0x3 line.long 0x00 "QUEUE_93_D,Queue Manager Queue 93 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x35D0++0xB line.long 0x00 "QUEUE_93_STATUS_A,Queue Manager Queue 93 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_93_STATUS_B,Queue Manager Queue 93 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_93_STATUS_C,Queue Manager Queue 93 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 94 Registers" rgroup.long 0x25E0++0xB line.long 0x00 "QUEUE_94_A,Queue Manager Queue 94 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_94_B,Queue Manager Queue 94 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_94_C,Queue Manager Queue 94 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x25E0+0x0C)++0x3 line.long 0x00 "QUEUE_94_D,Queue Manager Queue 94 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x35E0++0xB line.long 0x00 "QUEUE_94_STATUS_A,Queue Manager Queue 94 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_94_STATUS_B,Queue Manager Queue 94 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_94_STATUS_C,Queue Manager Queue 94 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 95 Registers" rgroup.long 0x25F0++0xB line.long 0x00 "QUEUE_95_A,Queue Manager Queue 95 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_95_B,Queue Manager Queue 95 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_95_C,Queue Manager Queue 95 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x25F0+0x0C)++0x3 line.long 0x00 "QUEUE_95_D,Queue Manager Queue 95 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x35F0++0xB line.long 0x00 "QUEUE_95_STATUS_A,Queue Manager Queue 95 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_95_STATUS_B,Queue Manager Queue 95 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_95_STATUS_C,Queue Manager Queue 95 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 96 Registers" rgroup.long 0x2600++0xB line.long 0x00 "QUEUE_96_A,Queue Manager Queue 96 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_96_B,Queue Manager Queue 96 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_96_C,Queue Manager Queue 96 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2600+0x0C)++0x3 line.long 0x00 "QUEUE_96_D,Queue Manager Queue 96 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3600++0xB line.long 0x00 "QUEUE_96_STATUS_A,Queue Manager Queue 96 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_96_STATUS_B,Queue Manager Queue 96 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_96_STATUS_C,Queue Manager Queue 96 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 97 Registers" rgroup.long 0x2610++0xB line.long 0x00 "QUEUE_97_A,Queue Manager Queue 97 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_97_B,Queue Manager Queue 97 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_97_C,Queue Manager Queue 97 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2610+0x0C)++0x3 line.long 0x00 "QUEUE_97_D,Queue Manager Queue 97 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3610++0xB line.long 0x00 "QUEUE_97_STATUS_A,Queue Manager Queue 97 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_97_STATUS_B,Queue Manager Queue 97 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_97_STATUS_C,Queue Manager Queue 97 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 98 Registers" rgroup.long 0x2620++0xB line.long 0x00 "QUEUE_98_A,Queue Manager Queue 98 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_98_B,Queue Manager Queue 98 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_98_C,Queue Manager Queue 98 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2620+0x0C)++0x3 line.long 0x00 "QUEUE_98_D,Queue Manager Queue 98 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3620++0xB line.long 0x00 "QUEUE_98_STATUS_A,Queue Manager Queue 98 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_98_STATUS_B,Queue Manager Queue 98 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_98_STATUS_C,Queue Manager Queue 98 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 99 Registers" rgroup.long 0x2630++0xB line.long 0x00 "QUEUE_99_A,Queue Manager Queue 99 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_99_B,Queue Manager Queue 99 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_99_C,Queue Manager Queue 99 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2630+0x0C)++0x3 line.long 0x00 "QUEUE_99_D,Queue Manager Queue 99 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3630++0xB line.long 0x00 "QUEUE_99_STATUS_A,Queue Manager Queue 99 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_99_STATUS_B,Queue Manager Queue 99 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_99_STATUS_C,Queue Manager Queue 99 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 100 Registers" rgroup.long 0x2640++0xB line.long 0x00 "QUEUE_100_A,Queue Manager Queue 100 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_100_B,Queue Manager Queue 100 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_100_C,Queue Manager Queue 100 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2640+0x0C)++0x3 line.long 0x00 "QUEUE_100_D,Queue Manager Queue 100 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3640++0xB line.long 0x00 "QUEUE_100_STATUS_A,Queue Manager Queue 100 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_100_STATUS_B,Queue Manager Queue 100 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_100_STATUS_C,Queue Manager Queue 100 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 101 Registers" rgroup.long 0x2650++0xB line.long 0x00 "QUEUE_101_A,Queue Manager Queue 101 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_101_B,Queue Manager Queue 101 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_101_C,Queue Manager Queue 101 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2650+0x0C)++0x3 line.long 0x00 "QUEUE_101_D,Queue Manager Queue 101 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3650++0xB line.long 0x00 "QUEUE_101_STATUS_A,Queue Manager Queue 101 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_101_STATUS_B,Queue Manager Queue 101 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_101_STATUS_C,Queue Manager Queue 101 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 102 Registers" rgroup.long 0x2660++0xB line.long 0x00 "QUEUE_102_A,Queue Manager Queue 102 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_102_B,Queue Manager Queue 102 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_102_C,Queue Manager Queue 102 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2660+0x0C)++0x3 line.long 0x00 "QUEUE_102_D,Queue Manager Queue 102 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3660++0xB line.long 0x00 "QUEUE_102_STATUS_A,Queue Manager Queue 102 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_102_STATUS_B,Queue Manager Queue 102 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_102_STATUS_C,Queue Manager Queue 102 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 103 Registers" rgroup.long 0x2670++0xB line.long 0x00 "QUEUE_103_A,Queue Manager Queue 103 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_103_B,Queue Manager Queue 103 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_103_C,Queue Manager Queue 103 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2670+0x0C)++0x3 line.long 0x00 "QUEUE_103_D,Queue Manager Queue 103 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3670++0xB line.long 0x00 "QUEUE_103_STATUS_A,Queue Manager Queue 103 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_103_STATUS_B,Queue Manager Queue 103 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_103_STATUS_C,Queue Manager Queue 103 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 104 Registers" rgroup.long 0x2680++0xB line.long 0x00 "QUEUE_104_A,Queue Manager Queue 104 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_104_B,Queue Manager Queue 104 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_104_C,Queue Manager Queue 104 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2680+0x0C)++0x3 line.long 0x00 "QUEUE_104_D,Queue Manager Queue 104 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3680++0xB line.long 0x00 "QUEUE_104_STATUS_A,Queue Manager Queue 104 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_104_STATUS_B,Queue Manager Queue 104 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_104_STATUS_C,Queue Manager Queue 104 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 105 Registers" rgroup.long 0x2690++0xB line.long 0x00 "QUEUE_105_A,Queue Manager Queue 105 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_105_B,Queue Manager Queue 105 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_105_C,Queue Manager Queue 105 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2690+0x0C)++0x3 line.long 0x00 "QUEUE_105_D,Queue Manager Queue 105 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3690++0xB line.long 0x00 "QUEUE_105_STATUS_A,Queue Manager Queue 105 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_105_STATUS_B,Queue Manager Queue 105 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_105_STATUS_C,Queue Manager Queue 105 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 106 Registers" rgroup.long 0x26A0++0xB line.long 0x00 "QUEUE_106_A,Queue Manager Queue 106 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_106_B,Queue Manager Queue 106 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_106_C,Queue Manager Queue 106 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x26A0+0x0C)++0x3 line.long 0x00 "QUEUE_106_D,Queue Manager Queue 106 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x36A0++0xB line.long 0x00 "QUEUE_106_STATUS_A,Queue Manager Queue 106 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_106_STATUS_B,Queue Manager Queue 106 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_106_STATUS_C,Queue Manager Queue 106 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 107 Registers" rgroup.long 0x26B0++0xB line.long 0x00 "QUEUE_107_A,Queue Manager Queue 107 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_107_B,Queue Manager Queue 107 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_107_C,Queue Manager Queue 107 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x26B0+0x0C)++0x3 line.long 0x00 "QUEUE_107_D,Queue Manager Queue 107 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x36B0++0xB line.long 0x00 "QUEUE_107_STATUS_A,Queue Manager Queue 107 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_107_STATUS_B,Queue Manager Queue 107 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_107_STATUS_C,Queue Manager Queue 107 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 108 Registers" rgroup.long 0x26C0++0xB line.long 0x00 "QUEUE_108_A,Queue Manager Queue 108 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_108_B,Queue Manager Queue 108 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_108_C,Queue Manager Queue 108 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x26C0+0x0C)++0x3 line.long 0x00 "QUEUE_108_D,Queue Manager Queue 108 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x36C0++0xB line.long 0x00 "QUEUE_108_STATUS_A,Queue Manager Queue 108 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_108_STATUS_B,Queue Manager Queue 108 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_108_STATUS_C,Queue Manager Queue 108 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 109 Registers" rgroup.long 0x26D0++0xB line.long 0x00 "QUEUE_109_A,Queue Manager Queue 109 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_109_B,Queue Manager Queue 109 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_109_C,Queue Manager Queue 109 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x26D0+0x0C)++0x3 line.long 0x00 "QUEUE_109_D,Queue Manager Queue 109 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x36D0++0xB line.long 0x00 "QUEUE_109_STATUS_A,Queue Manager Queue 109 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_109_STATUS_B,Queue Manager Queue 109 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_109_STATUS_C,Queue Manager Queue 109 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 110 Registers" rgroup.long 0x26E0++0xB line.long 0x00 "QUEUE_110_A,Queue Manager Queue 110 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_110_B,Queue Manager Queue 110 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_110_C,Queue Manager Queue 110 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x26E0+0x0C)++0x3 line.long 0x00 "QUEUE_110_D,Queue Manager Queue 110 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x36E0++0xB line.long 0x00 "QUEUE_110_STATUS_A,Queue Manager Queue 110 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_110_STATUS_B,Queue Manager Queue 110 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_110_STATUS_C,Queue Manager Queue 110 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 111 Registers" rgroup.long 0x26F0++0xB line.long 0x00 "QUEUE_111_A,Queue Manager Queue 111 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_111_B,Queue Manager Queue 111 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_111_C,Queue Manager Queue 111 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x26F0+0x0C)++0x3 line.long 0x00 "QUEUE_111_D,Queue Manager Queue 111 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x36F0++0xB line.long 0x00 "QUEUE_111_STATUS_A,Queue Manager Queue 111 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_111_STATUS_B,Queue Manager Queue 111 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_111_STATUS_C,Queue Manager Queue 111 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 112 Registers" rgroup.long 0x2700++0xB line.long 0x00 "QUEUE_112_A,Queue Manager Queue 112 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_112_B,Queue Manager Queue 112 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_112_C,Queue Manager Queue 112 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2700+0x0C)++0x3 line.long 0x00 "QUEUE_112_D,Queue Manager Queue 112 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3700++0xB line.long 0x00 "QUEUE_112_STATUS_A,Queue Manager Queue 112 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_112_STATUS_B,Queue Manager Queue 112 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_112_STATUS_C,Queue Manager Queue 112 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 113 Registers" rgroup.long 0x2710++0xB line.long 0x00 "QUEUE_113_A,Queue Manager Queue 113 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_113_B,Queue Manager Queue 113 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_113_C,Queue Manager Queue 113 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2710+0x0C)++0x3 line.long 0x00 "QUEUE_113_D,Queue Manager Queue 113 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3710++0xB line.long 0x00 "QUEUE_113_STATUS_A,Queue Manager Queue 113 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_113_STATUS_B,Queue Manager Queue 113 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_113_STATUS_C,Queue Manager Queue 113 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 114 Registers" rgroup.long 0x2720++0xB line.long 0x00 "QUEUE_114_A,Queue Manager Queue 114 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_114_B,Queue Manager Queue 114 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_114_C,Queue Manager Queue 114 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2720+0x0C)++0x3 line.long 0x00 "QUEUE_114_D,Queue Manager Queue 114 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3720++0xB line.long 0x00 "QUEUE_114_STATUS_A,Queue Manager Queue 114 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_114_STATUS_B,Queue Manager Queue 114 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_114_STATUS_C,Queue Manager Queue 114 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 115 Registers" rgroup.long 0x2730++0xB line.long 0x00 "QUEUE_115_A,Queue Manager Queue 115 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_115_B,Queue Manager Queue 115 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_115_C,Queue Manager Queue 115 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2730+0x0C)++0x3 line.long 0x00 "QUEUE_115_D,Queue Manager Queue 115 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3730++0xB line.long 0x00 "QUEUE_115_STATUS_A,Queue Manager Queue 115 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_115_STATUS_B,Queue Manager Queue 115 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_115_STATUS_C,Queue Manager Queue 115 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 116 Registers" rgroup.long 0x2740++0xB line.long 0x00 "QUEUE_116_A,Queue Manager Queue 116 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_116_B,Queue Manager Queue 116 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_116_C,Queue Manager Queue 116 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2740+0x0C)++0x3 line.long 0x00 "QUEUE_116_D,Queue Manager Queue 116 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3740++0xB line.long 0x00 "QUEUE_116_STATUS_A,Queue Manager Queue 116 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_116_STATUS_B,Queue Manager Queue 116 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_116_STATUS_C,Queue Manager Queue 116 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 117 Registers" rgroup.long 0x2750++0xB line.long 0x00 "QUEUE_117_A,Queue Manager Queue 117 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_117_B,Queue Manager Queue 117 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_117_C,Queue Manager Queue 117 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2750+0x0C)++0x3 line.long 0x00 "QUEUE_117_D,Queue Manager Queue 117 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3750++0xB line.long 0x00 "QUEUE_117_STATUS_A,Queue Manager Queue 117 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_117_STATUS_B,Queue Manager Queue 117 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_117_STATUS_C,Queue Manager Queue 117 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 118 Registers" rgroup.long 0x2760++0xB line.long 0x00 "QUEUE_118_A,Queue Manager Queue 118 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_118_B,Queue Manager Queue 118 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_118_C,Queue Manager Queue 118 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2760+0x0C)++0x3 line.long 0x00 "QUEUE_118_D,Queue Manager Queue 118 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3760++0xB line.long 0x00 "QUEUE_118_STATUS_A,Queue Manager Queue 118 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_118_STATUS_B,Queue Manager Queue 118 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_118_STATUS_C,Queue Manager Queue 118 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 119 Registers" rgroup.long 0x2770++0xB line.long 0x00 "QUEUE_119_A,Queue Manager Queue 119 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_119_B,Queue Manager Queue 119 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_119_C,Queue Manager Queue 119 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2770+0x0C)++0x3 line.long 0x00 "QUEUE_119_D,Queue Manager Queue 119 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3770++0xB line.long 0x00 "QUEUE_119_STATUS_A,Queue Manager Queue 119 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_119_STATUS_B,Queue Manager Queue 119 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_119_STATUS_C,Queue Manager Queue 119 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 120 Registers" rgroup.long 0x2780++0xB line.long 0x00 "QUEUE_120_A,Queue Manager Queue 120 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_120_B,Queue Manager Queue 120 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_120_C,Queue Manager Queue 120 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2780+0x0C)++0x3 line.long 0x00 "QUEUE_120_D,Queue Manager Queue 120 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3780++0xB line.long 0x00 "QUEUE_120_STATUS_A,Queue Manager Queue 120 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_120_STATUS_B,Queue Manager Queue 120 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_120_STATUS_C,Queue Manager Queue 120 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 121 Registers" rgroup.long 0x2790++0xB line.long 0x00 "QUEUE_121_A,Queue Manager Queue 121 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_121_B,Queue Manager Queue 121 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_121_C,Queue Manager Queue 121 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2790+0x0C)++0x3 line.long 0x00 "QUEUE_121_D,Queue Manager Queue 121 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3790++0xB line.long 0x00 "QUEUE_121_STATUS_A,Queue Manager Queue 121 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_121_STATUS_B,Queue Manager Queue 121 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_121_STATUS_C,Queue Manager Queue 121 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 122 Registers" rgroup.long 0x27A0++0xB line.long 0x00 "QUEUE_122_A,Queue Manager Queue 122 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_122_B,Queue Manager Queue 122 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_122_C,Queue Manager Queue 122 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x27A0+0x0C)++0x3 line.long 0x00 "QUEUE_122_D,Queue Manager Queue 122 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x37A0++0xB line.long 0x00 "QUEUE_122_STATUS_A,Queue Manager Queue 122 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_122_STATUS_B,Queue Manager Queue 122 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_122_STATUS_C,Queue Manager Queue 122 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 123 Registers" rgroup.long 0x27B0++0xB line.long 0x00 "QUEUE_123_A,Queue Manager Queue 123 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_123_B,Queue Manager Queue 123 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_123_C,Queue Manager Queue 123 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x27B0+0x0C)++0x3 line.long 0x00 "QUEUE_123_D,Queue Manager Queue 123 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x37B0++0xB line.long 0x00 "QUEUE_123_STATUS_A,Queue Manager Queue 123 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_123_STATUS_B,Queue Manager Queue 123 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_123_STATUS_C,Queue Manager Queue 123 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 124 Registers" rgroup.long 0x27C0++0xB line.long 0x00 "QUEUE_124_A,Queue Manager Queue 124 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_124_B,Queue Manager Queue 124 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_124_C,Queue Manager Queue 124 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x27C0+0x0C)++0x3 line.long 0x00 "QUEUE_124_D,Queue Manager Queue 124 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x37C0++0xB line.long 0x00 "QUEUE_124_STATUS_A,Queue Manager Queue 124 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_124_STATUS_B,Queue Manager Queue 124 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_124_STATUS_C,Queue Manager Queue 124 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 125 Registers" rgroup.long 0x27D0++0xB line.long 0x00 "QUEUE_125_A,Queue Manager Queue 125 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_125_B,Queue Manager Queue 125 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_125_C,Queue Manager Queue 125 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x27D0+0x0C)++0x3 line.long 0x00 "QUEUE_125_D,Queue Manager Queue 125 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x37D0++0xB line.long 0x00 "QUEUE_125_STATUS_A,Queue Manager Queue 125 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_125_STATUS_B,Queue Manager Queue 125 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_125_STATUS_C,Queue Manager Queue 125 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 126 Registers" rgroup.long 0x27E0++0xB line.long 0x00 "QUEUE_126_A,Queue Manager Queue 126 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_126_B,Queue Manager Queue 126 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_126_C,Queue Manager Queue 126 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x27E0+0x0C)++0x3 line.long 0x00 "QUEUE_126_D,Queue Manager Queue 126 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x37E0++0xB line.long 0x00 "QUEUE_126_STATUS_A,Queue Manager Queue 126 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_126_STATUS_B,Queue Manager Queue 126 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_126_STATUS_C,Queue Manager Queue 126 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 127 Registers" rgroup.long 0x27F0++0xB line.long 0x00 "QUEUE_127_A,Queue Manager Queue 127 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_127_B,Queue Manager Queue 127 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_127_C,Queue Manager Queue 127 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x27F0+0x0C)++0x3 line.long 0x00 "QUEUE_127_D,Queue Manager Queue 127 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x37F0++0xB line.long 0x00 "QUEUE_127_STATUS_A,Queue Manager Queue 127 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_127_STATUS_B,Queue Manager Queue 127 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_127_STATUS_C,Queue Manager Queue 127 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 128 Registers" rgroup.long 0x2800++0xB line.long 0x00 "QUEUE_128_A,Queue Manager Queue 128 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_128_B,Queue Manager Queue 128 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_128_C,Queue Manager Queue 128 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2800+0x0C)++0x3 line.long 0x00 "QUEUE_128_D,Queue Manager Queue 128 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3800++0xB line.long 0x00 "QUEUE_128_STATUS_A,Queue Manager Queue 128 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_128_STATUS_B,Queue Manager Queue 128 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_128_STATUS_C,Queue Manager Queue 128 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 129 Registers" rgroup.long 0x2810++0xB line.long 0x00 "QUEUE_129_A,Queue Manager Queue 129 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_129_B,Queue Manager Queue 129 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_129_C,Queue Manager Queue 129 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2810+0x0C)++0x3 line.long 0x00 "QUEUE_129_D,Queue Manager Queue 129 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3810++0xB line.long 0x00 "QUEUE_129_STATUS_A,Queue Manager Queue 129 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_129_STATUS_B,Queue Manager Queue 129 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_129_STATUS_C,Queue Manager Queue 129 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 130 Registers" rgroup.long 0x2820++0xB line.long 0x00 "QUEUE_130_A,Queue Manager Queue 130 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_130_B,Queue Manager Queue 130 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_130_C,Queue Manager Queue 130 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2820+0x0C)++0x3 line.long 0x00 "QUEUE_130_D,Queue Manager Queue 130 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3820++0xB line.long 0x00 "QUEUE_130_STATUS_A,Queue Manager Queue 130 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_130_STATUS_B,Queue Manager Queue 130 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_130_STATUS_C,Queue Manager Queue 130 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 131 Registers" rgroup.long 0x2830++0xB line.long 0x00 "QUEUE_131_A,Queue Manager Queue 131 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_131_B,Queue Manager Queue 131 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_131_C,Queue Manager Queue 131 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2830+0x0C)++0x3 line.long 0x00 "QUEUE_131_D,Queue Manager Queue 131 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3830++0xB line.long 0x00 "QUEUE_131_STATUS_A,Queue Manager Queue 131 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_131_STATUS_B,Queue Manager Queue 131 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_131_STATUS_C,Queue Manager Queue 131 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 132 Registers" rgroup.long 0x2840++0xB line.long 0x00 "QUEUE_132_A,Queue Manager Queue 132 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_132_B,Queue Manager Queue 132 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_132_C,Queue Manager Queue 132 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2840+0x0C)++0x3 line.long 0x00 "QUEUE_132_D,Queue Manager Queue 132 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3840++0xB line.long 0x00 "QUEUE_132_STATUS_A,Queue Manager Queue 132 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_132_STATUS_B,Queue Manager Queue 132 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_132_STATUS_C,Queue Manager Queue 132 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 133 Registers" rgroup.long 0x2850++0xB line.long 0x00 "QUEUE_133_A,Queue Manager Queue 133 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_133_B,Queue Manager Queue 133 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_133_C,Queue Manager Queue 133 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2850+0x0C)++0x3 line.long 0x00 "QUEUE_133_D,Queue Manager Queue 133 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3850++0xB line.long 0x00 "QUEUE_133_STATUS_A,Queue Manager Queue 133 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_133_STATUS_B,Queue Manager Queue 133 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_133_STATUS_C,Queue Manager Queue 133 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 134 Registers" rgroup.long 0x2860++0xB line.long 0x00 "QUEUE_134_A,Queue Manager Queue 134 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_134_B,Queue Manager Queue 134 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_134_C,Queue Manager Queue 134 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2860+0x0C)++0x3 line.long 0x00 "QUEUE_134_D,Queue Manager Queue 134 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3860++0xB line.long 0x00 "QUEUE_134_STATUS_A,Queue Manager Queue 134 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_134_STATUS_B,Queue Manager Queue 134 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_134_STATUS_C,Queue Manager Queue 134 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 135 Registers" rgroup.long 0x2870++0xB line.long 0x00 "QUEUE_135_A,Queue Manager Queue 135 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_135_B,Queue Manager Queue 135 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_135_C,Queue Manager Queue 135 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2870+0x0C)++0x3 line.long 0x00 "QUEUE_135_D,Queue Manager Queue 135 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3870++0xB line.long 0x00 "QUEUE_135_STATUS_A,Queue Manager Queue 135 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_135_STATUS_B,Queue Manager Queue 135 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_135_STATUS_C,Queue Manager Queue 135 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 136 Registers" rgroup.long 0x2880++0xB line.long 0x00 "QUEUE_136_A,Queue Manager Queue 136 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_136_B,Queue Manager Queue 136 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_136_C,Queue Manager Queue 136 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2880+0x0C)++0x3 line.long 0x00 "QUEUE_136_D,Queue Manager Queue 136 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3880++0xB line.long 0x00 "QUEUE_136_STATUS_A,Queue Manager Queue 136 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_136_STATUS_B,Queue Manager Queue 136 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_136_STATUS_C,Queue Manager Queue 136 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 137 Registers" rgroup.long 0x2890++0xB line.long 0x00 "QUEUE_137_A,Queue Manager Queue 137 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_137_B,Queue Manager Queue 137 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_137_C,Queue Manager Queue 137 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2890+0x0C)++0x3 line.long 0x00 "QUEUE_137_D,Queue Manager Queue 137 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3890++0xB line.long 0x00 "QUEUE_137_STATUS_A,Queue Manager Queue 137 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_137_STATUS_B,Queue Manager Queue 137 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_137_STATUS_C,Queue Manager Queue 137 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 138 Registers" rgroup.long 0x28A0++0xB line.long 0x00 "QUEUE_138_A,Queue Manager Queue 138 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_138_B,Queue Manager Queue 138 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_138_C,Queue Manager Queue 138 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x28A0+0x0C)++0x3 line.long 0x00 "QUEUE_138_D,Queue Manager Queue 138 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x38A0++0xB line.long 0x00 "QUEUE_138_STATUS_A,Queue Manager Queue 138 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_138_STATUS_B,Queue Manager Queue 138 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_138_STATUS_C,Queue Manager Queue 138 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 139 Registers" rgroup.long 0x28B0++0xB line.long 0x00 "QUEUE_139_A,Queue Manager Queue 139 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_139_B,Queue Manager Queue 139 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_139_C,Queue Manager Queue 139 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x28B0+0x0C)++0x3 line.long 0x00 "QUEUE_139_D,Queue Manager Queue 139 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x38B0++0xB line.long 0x00 "QUEUE_139_STATUS_A,Queue Manager Queue 139 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_139_STATUS_B,Queue Manager Queue 139 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_139_STATUS_C,Queue Manager Queue 139 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 140 Registers" rgroup.long 0x28C0++0xB line.long 0x00 "QUEUE_140_A,Queue Manager Queue 140 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_140_B,Queue Manager Queue 140 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_140_C,Queue Manager Queue 140 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x28C0+0x0C)++0x3 line.long 0x00 "QUEUE_140_D,Queue Manager Queue 140 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x38C0++0xB line.long 0x00 "QUEUE_140_STATUS_A,Queue Manager Queue 140 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_140_STATUS_B,Queue Manager Queue 140 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_140_STATUS_C,Queue Manager Queue 140 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 141 Registers" rgroup.long 0x28D0++0xB line.long 0x00 "QUEUE_141_A,Queue Manager Queue 141 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_141_B,Queue Manager Queue 141 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_141_C,Queue Manager Queue 141 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x28D0+0x0C)++0x3 line.long 0x00 "QUEUE_141_D,Queue Manager Queue 141 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x38D0++0xB line.long 0x00 "QUEUE_141_STATUS_A,Queue Manager Queue 141 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_141_STATUS_B,Queue Manager Queue 141 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_141_STATUS_C,Queue Manager Queue 141 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 142 Registers" rgroup.long 0x28E0++0xB line.long 0x00 "QUEUE_142_A,Queue Manager Queue 142 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_142_B,Queue Manager Queue 142 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_142_C,Queue Manager Queue 142 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x28E0+0x0C)++0x3 line.long 0x00 "QUEUE_142_D,Queue Manager Queue 142 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x38E0++0xB line.long 0x00 "QUEUE_142_STATUS_A,Queue Manager Queue 142 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_142_STATUS_B,Queue Manager Queue 142 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_142_STATUS_C,Queue Manager Queue 142 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 143 Registers" rgroup.long 0x28F0++0xB line.long 0x00 "QUEUE_143_A,Queue Manager Queue 143 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_143_B,Queue Manager Queue 143 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_143_C,Queue Manager Queue 143 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x28F0+0x0C)++0x3 line.long 0x00 "QUEUE_143_D,Queue Manager Queue 143 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x38F0++0xB line.long 0x00 "QUEUE_143_STATUS_A,Queue Manager Queue 143 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_143_STATUS_B,Queue Manager Queue 143 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_143_STATUS_C,Queue Manager Queue 143 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 144 Registers" rgroup.long 0x2900++0xB line.long 0x00 "QUEUE_144_A,Queue Manager Queue 144 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_144_B,Queue Manager Queue 144 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_144_C,Queue Manager Queue 144 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2900+0x0C)++0x3 line.long 0x00 "QUEUE_144_D,Queue Manager Queue 144 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3900++0xB line.long 0x00 "QUEUE_144_STATUS_A,Queue Manager Queue 144 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_144_STATUS_B,Queue Manager Queue 144 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_144_STATUS_C,Queue Manager Queue 144 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 145 Registers" rgroup.long 0x2910++0xB line.long 0x00 "QUEUE_145_A,Queue Manager Queue 145 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_145_B,Queue Manager Queue 145 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_145_C,Queue Manager Queue 145 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2910+0x0C)++0x3 line.long 0x00 "QUEUE_145_D,Queue Manager Queue 145 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3910++0xB line.long 0x00 "QUEUE_145_STATUS_A,Queue Manager Queue 145 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_145_STATUS_B,Queue Manager Queue 145 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_145_STATUS_C,Queue Manager Queue 145 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 146 Registers" rgroup.long 0x2920++0xB line.long 0x00 "QUEUE_146_A,Queue Manager Queue 146 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_146_B,Queue Manager Queue 146 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_146_C,Queue Manager Queue 146 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2920+0x0C)++0x3 line.long 0x00 "QUEUE_146_D,Queue Manager Queue 146 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3920++0xB line.long 0x00 "QUEUE_146_STATUS_A,Queue Manager Queue 146 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_146_STATUS_B,Queue Manager Queue 146 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_146_STATUS_C,Queue Manager Queue 146 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 147 Registers" rgroup.long 0x2930++0xB line.long 0x00 "QUEUE_147_A,Queue Manager Queue 147 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_147_B,Queue Manager Queue 147 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_147_C,Queue Manager Queue 147 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2930+0x0C)++0x3 line.long 0x00 "QUEUE_147_D,Queue Manager Queue 147 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3930++0xB line.long 0x00 "QUEUE_147_STATUS_A,Queue Manager Queue 147 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_147_STATUS_B,Queue Manager Queue 147 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_147_STATUS_C,Queue Manager Queue 147 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 148 Registers" rgroup.long 0x2940++0xB line.long 0x00 "QUEUE_148_A,Queue Manager Queue 148 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_148_B,Queue Manager Queue 148 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_148_C,Queue Manager Queue 148 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2940+0x0C)++0x3 line.long 0x00 "QUEUE_148_D,Queue Manager Queue 148 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3940++0xB line.long 0x00 "QUEUE_148_STATUS_A,Queue Manager Queue 148 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_148_STATUS_B,Queue Manager Queue 148 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_148_STATUS_C,Queue Manager Queue 148 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 149 Registers" rgroup.long 0x2950++0xB line.long 0x00 "QUEUE_149_A,Queue Manager Queue 149 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_149_B,Queue Manager Queue 149 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_149_C,Queue Manager Queue 149 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2950+0x0C)++0x3 line.long 0x00 "QUEUE_149_D,Queue Manager Queue 149 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3950++0xB line.long 0x00 "QUEUE_149_STATUS_A,Queue Manager Queue 149 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_149_STATUS_B,Queue Manager Queue 149 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_149_STATUS_C,Queue Manager Queue 149 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 150 Registers" rgroup.long 0x2960++0xB line.long 0x00 "QUEUE_150_A,Queue Manager Queue 150 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_150_B,Queue Manager Queue 150 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_150_C,Queue Manager Queue 150 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2960+0x0C)++0x3 line.long 0x00 "QUEUE_150_D,Queue Manager Queue 150 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3960++0xB line.long 0x00 "QUEUE_150_STATUS_A,Queue Manager Queue 150 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_150_STATUS_B,Queue Manager Queue 150 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_150_STATUS_C,Queue Manager Queue 150 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 151 Registers" rgroup.long 0x2970++0xB line.long 0x00 "QUEUE_151_A,Queue Manager Queue 151 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_151_B,Queue Manager Queue 151 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_151_C,Queue Manager Queue 151 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2970+0x0C)++0x3 line.long 0x00 "QUEUE_151_D,Queue Manager Queue 151 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3970++0xB line.long 0x00 "QUEUE_151_STATUS_A,Queue Manager Queue 151 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_151_STATUS_B,Queue Manager Queue 151 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_151_STATUS_C,Queue Manager Queue 151 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 152 Registers" rgroup.long 0x2980++0xB line.long 0x00 "QUEUE_152_A,Queue Manager Queue 152 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_152_B,Queue Manager Queue 152 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_152_C,Queue Manager Queue 152 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2980+0x0C)++0x3 line.long 0x00 "QUEUE_152_D,Queue Manager Queue 152 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3980++0xB line.long 0x00 "QUEUE_152_STATUS_A,Queue Manager Queue 152 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_152_STATUS_B,Queue Manager Queue 152 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_152_STATUS_C,Queue Manager Queue 152 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 153 Registers" rgroup.long 0x2990++0xB line.long 0x00 "QUEUE_153_A,Queue Manager Queue 153 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_153_B,Queue Manager Queue 153 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_153_C,Queue Manager Queue 153 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x2990+0x0C)++0x3 line.long 0x00 "QUEUE_153_D,Queue Manager Queue 153 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x3990++0xB line.long 0x00 "QUEUE_153_STATUS_A,Queue Manager Queue 153 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_153_STATUS_B,Queue Manager Queue 153 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_153_STATUS_C,Queue Manager Queue 153 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 154 Registers" rgroup.long 0x29A0++0xB line.long 0x00 "QUEUE_154_A,Queue Manager Queue 154 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_154_B,Queue Manager Queue 154 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_154_C,Queue Manager Queue 154 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x29A0+0x0C)++0x3 line.long 0x00 "QUEUE_154_D,Queue Manager Queue 154 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x39A0++0xB line.long 0x00 "QUEUE_154_STATUS_A,Queue Manager Queue 154 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_154_STATUS_B,Queue Manager Queue 154 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_154_STATUS_C,Queue Manager Queue 154 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree "Queue 155 Registers" rgroup.long 0x29B0++0xB line.long 0x00 "QUEUE_155_A,Queue Manager Queue 155 Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_155_B,Queue Manager Queue 155 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets" line.long 0x08 "QUEUE_155_C,Queue Manager Queue 155 Status Register C" bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Head,Tail" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation" group.long (0x29B0+0x0C)++0x3 line.long 0x00 "QUEUE_155_D,Queue Manager Queue 155 Control Register D" hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer" bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148" rgroup.long 0x39B0++0xB line.long 0x00 "QUEUE_155_STATUS_A,Queue Manager Queue 155 Status Register A" hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue" line.long 0x04 "QUEUE_155_STATUS_B,Queue Manager Queue 155 Status Register B" hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets" line.long 0x08 "QUEUE_155_STATUS_C,Queue Manager Queue 155 Status Register C" hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue" tree.end tree.end width 0xb tree.end tree.end tree "Interprocessor Communication" tree "MAILBOX" base ad:0x480C8000 width 23. rgroup.long 0x00++0x3 line.long 0x00 "REVISION,Mailbox IP Revision Code" sif (cpuis("AM335*")) hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Version Value" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Version Value" else hexmask.long.byte 0x00 8.--15. 1. " MAJOR ,Major Version Value" hexmask.long.byte 0x00 0.--7. 1. " MINOR ,Minor Version Value" endif group.long 0x10++0x3 line.long 0x00 "SYSCONFIG,Mailbox System Configuration Register" bitfld.long 0x00 2.--3. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..." bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Normal,Reset" group.long 0x40++0x2f line.long 0x0 "MESSAGE_0,Mailbox Message 0 Register" line.long 0x4 "MESSAGE_1,Mailbox Message 1 Register" line.long 0x8 "MESSAGE_2,Mailbox Message 2 Register" line.long 0xC "MESSAGE_3,Mailbox Message 3 Register" line.long 0x10 "MESSAGE_4,Mailbox Message 4 Register" line.long 0x14 "MESSAGE_5,Mailbox Message 5 Register" line.long 0x18 "MESSAGE_6,Mailbox Message 6 Register" line.long 0x1C "MESSAGE_7,Mailbox Message 7 Register" group.long 0x80++0x2f line.long 0x0 "FIFOSTATUS_0 ,Mailbox FIFO Status 0 Register" hexmask.long 0x0 1.--31. 1. " MESSAGEVALUEMBM0x0 ,Message in Mailbox 0x0" bitfld.long 0x0 0. " FIFOFULLMB0 ,Full flag for Mailbox" "Not full,Full" line.long 0x4 "FIFOSTATUS_1 ,Mailbox FIFO Status 1 Register" hexmask.long 0x4 1.--31. 1. " MESSAGEVALUEMBM0x4 ,Message in Mailbox 0x4" bitfld.long 0x4 0. " FIFOFULLMB1 ,Full flag for Mailbox" "Not full,Full" line.long 0x8 "FIFOSTATUS_2 ,Mailbox FIFO Status 2 Register" hexmask.long 0x8 1.--31. 1. " MESSAGEVALUEMBM0x8 ,Message in Mailbox 0x8" bitfld.long 0x8 0. " FIFOFULLMB2 ,Full flag for Mailbox" "Not full,Full" line.long 0xC "FIFOSTATUS_3 ,Mailbox FIFO Status 3 Register" hexmask.long 0xC 1.--31. 1. " MESSAGEVALUEMBM0xC ,Message in Mailbox 0xC" bitfld.long 0xC 0. " FIFOFULLMB3 ,Full flag for Mailbox" "Not full,Full" line.long 0x10 "FIFOSTATUS_4 ,Mailbox FIFO Status 4 Register" hexmask.long 0x10 1.--31. 1. " MESSAGEVALUEMBM0x10 ,Message in Mailbox 0x10" bitfld.long 0x10 0. " FIFOFULLMB4 ,Full flag for Mailbox" "Not full,Full" line.long 0x14 "FIFOSTATUS_5 ,Mailbox FIFO Status 5 Register" hexmask.long 0x14 1.--31. 1. " MESSAGEVALUEMBM0x14 ,Message in Mailbox 0x14" bitfld.long 0x14 0. " FIFOFULLMB5 ,Full flag for Mailbox" "Not full,Full" line.long 0x18 "FIFOSTATUS_6 ,Mailbox FIFO Status 6 Register" hexmask.long 0x18 1.--31. 1. " MESSAGEVALUEMBM0x18 ,Message in Mailbox 0x18" bitfld.long 0x18 0. " FIFOFULLMB6 ,Full flag for Mailbox" "Not full,Full" line.long 0x1C "FIFOSTATUS_7 ,Mailbox FIFO Status 7 Register" hexmask.long 0x1C 1.--31. 1. " MESSAGEVALUEMBM0x1C ,Message in Mailbox 0x1C" bitfld.long 0x1C 0. " FIFOFULLMB7 ,Full flag for Mailbox" "Not full,Full" rgroup.long 0xC0++0x2f line.long 0x0 "MSGSTATUS_0 ,Mailbox Message Status 0 Register" bitfld.long 0x0 0.--2. " NBOFMSGMBM0 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..." line.long 0x4 "MSGSTATUS_1 ,Mailbox Message Status 1 Register" bitfld.long 0x4 0.--2. " NBOFMSGMBM1 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..." line.long 0x8 "MSGSTATUS_2 ,Mailbox Message Status 2 Register" bitfld.long 0x8 0.--2. " NBOFMSGMBM2 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..." line.long 0xC "MSGSTATUS_3 ,Mailbox Message Status 3 Register" bitfld.long 0xC 0.--2. " NBOFMSGMBM3 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..." line.long 0x10 "MSGSTATUS_4 ,Mailbox Message Status 4 Register" bitfld.long 0x10 0.--2. " NBOFMSGMBM4 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..." line.long 0x14 "MSGSTATUS_5 ,Mailbox Message Status 5 Register" bitfld.long 0x14 0.--2. " NBOFMSGMBM5 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..." line.long 0x18 "MSGSTATUS_6 ,Mailbox Message Status 6 Register" bitfld.long 0x18 0.--2. " NBOFMSGMBM6 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..." line.long 0x1C "MSGSTATUS_7 ,Mailbox Message Status 7 Register" bitfld.long 0x1C 0.--2. " NBOFMSGMBM7 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..." width 18. tree "User 0 Mailbox Interrupts" group.long (0x100+0x0)++0xf line.long 0x00 "IRQSTATUS_RAW_0,Mailbox IRQ RAW Status Register" bitfld.long 0x00 15. " NOTFULLSTATUSU0MB7 ,NotFull Raw Status bit for User 0 Mailbox 7" "Full,Not full" bitfld.long 0x00 14. " NEWMSGSTATUSU0MB7 ,NewMessage Raw Status bit for User 0 Mailbox 7" "No action,New message" textline " " bitfld.long 0x00 13. " NOTFULLSTATUSU0MB6 ,NotFull Raw Status bit for User 0 Mailbox 6" "Full,Not full" bitfld.long 0x00 12. " NEWMSGSTATUSU0MB6 ,NewMessage Raw Status bit for User 0 Mailbox 6" "No action,New message" textline " " bitfld.long 0x00 11. " NOTFULLSTATUSU0MB5 ,NotFull Raw Status bit for User 0 Mailbox 5" "Full,Not full" bitfld.long 0x00 10. " NEWMSGSTATUSU0MB5 ,NewMessage Raw Status bit for User 0 Mailbox 5" "No action,New message" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSU0MB4 ,NotFull Raw Status bit for User 0 Mailbox 4" "Full,Not full" bitfld.long 0x00 8. " NEWMSGSTATUSU0MB4 ,NewMessage Raw Status bit for User 0 Mailbox 4" "No action,New message" textline " " bitfld.long 0x00 7. " NOTFULLSTATUSU0MB3 ,NotFull Raw Status bit for User 0 Mailbox 3" "Full,Not full" bitfld.long 0x00 6. " NEWMSGSTATUSU0MB3 ,NewMessage Raw Status bit for User 0 Mailbox 3" "No action,New message" textline " " bitfld.long 0x00 5. " NOTFULLSTATUSU0MB2 ,NotFull Raw Status bit for User 0 Mailbox 2" "Full,Not full" bitfld.long 0x00 4. " NEWMSGSTATUSU0MB2 ,NewMessage Raw Status bit for User 0 Mailbox 2" "No action,New message" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSU0MB1 ,NotFull Raw Status bit for User 0 Mailbox 1" "Full,Not full" bitfld.long 0x00 2. " NEWMSGSTATUSU0MB1 ,NewMessage Raw Status bit for User 0 Mailbox 1" "No action,New message" textline " " bitfld.long 0x00 1. " NOTFULLSTATUSU0MB0 ,NotFull Raw Status bit for User 0 Mailbox 0" "Full,Not full" bitfld.long 0x00 0. " NEWMSGSTATUSU0MB0 ,NewMessage Raw Status bit for User 0 Mailbox 0" "No action,New message" line.long 0x04 "IRQSTATUS_CLR_0,Mailbox IRQ Clear Status Register" eventfld.long 0x04 15. " NOTFULLSTATUSU0MB7 ,NotFull Clear Status bit for User 0 Mailbox 7" "Not pending,Pending" eventfld.long 0x04 14. " NEWMSGSTATUSU0MB7 ,NewMessage Clear Status bit for User 0 Mailbox 7" "Not pending,Pending" textline " " eventfld.long 0x04 13. " NOTFULLSTATUSU0MB6 ,NotFull Clear Status bit for User 0 Mailbox 6" "Not pending,Pending" eventfld.long 0x04 12. " NEWMSGSTATUSU0MB6 ,NewMessage Clear Status bit for User 0 Mailbox 6" "Not pending,Pending" textline " " eventfld.long 0x04 11. " NOTFULLSTATUSU0MB5 ,NotFull Clear Status bit for User 0 Mailbox 5" "Not pending,Pending" eventfld.long 0x04 10. " NEWMSGSTATUSU0MB5 ,NewMessage Clear Status bit for User 0 Mailbox 5" "Not pending,Pending" textline " " eventfld.long 0x04 9. " NOTFULLSTATUSU0MB4 ,NotFull Clear Status bit for User 0 Mailbox 4" "Not pending,Pending" eventfld.long 0x04 8. " NEWMSGSTATUSU0MB4 ,NewMessage Clear Status bit for User 0 Mailbox 4" "Not pending,Pending" textline " " eventfld.long 0x04 7. " NOTFULLSTATUSU0MB3 ,NotFull Clear Status bit for User 0 Mailbox 3" "Not pending,Pending" eventfld.long 0x04 6. " NEWMSGSTATUSU0MB3 ,NewMessage Clear Status bit for User 0 Mailbox 3" "Not pending,Pending" textline " " eventfld.long 0x04 5. " NOTFULLSTATUSU0MB2 ,NotFull Clear Status bit for User 0 Mailbox 2" "Not pending,Pending" eventfld.long 0x04 4. " NEWMSGSTATUSU0MB2 ,NewMessage Clear Status bit for User 0 Mailbox 2" "Not pending,Pending" textline " " eventfld.long 0x04 3. " NOTFULLSTATUSU0MB1 ,NotFull Clear Status bit for User 0 Mailbox 1" "Not pending,Pending" eventfld.long 0x04 2. " NEWMSGSTATUSU0MB1 ,NewMessage Clear Status bit for User 0 Mailbox 1" "Not pending,Pending" textline " " eventfld.long 0x04 1. " NOTFULLSTATUSU0MB0 ,NotFull Clear Status bit for User 0 Mailbox 0" "Not pending,Pending" eventfld.long 0x04 0. " NEWMSGSTATUSU0MB0 ,NewMessage Clear Status bit for User 0 Mailbox 0" "Not pending,Pending" line.long 0x08 "IRQENABLE_SET_0,Mailbox IRQ Enable Set Register" bitfld.long 0x08 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled" bitfld.long 0x08 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled" bitfld.long 0x08 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled" bitfld.long 0x08 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled" bitfld.long 0x08 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled" bitfld.long 0x08 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled" bitfld.long 0x08 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled" bitfld.long 0x08 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled" bitfld.long 0x08 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled" line.long 0x0c "IRQENABLE_CLR_0,Mailbox IRQ Enable Clear Register" eventfld.long 0x0c 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending" eventfld.long 0x0c 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending" textline " " eventfld.long 0x0c 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending" eventfld.long 0x0c 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending" textline " " eventfld.long 0x0c 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending" eventfld.long 0x0c 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending" textline " " eventfld.long 0x0c 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending" eventfld.long 0x0c 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending" textline " " eventfld.long 0x0c 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending" eventfld.long 0x0c 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending" textline " " eventfld.long 0x0c 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending" eventfld.long 0x0c 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending" textline " " eventfld.long 0x0c 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending" eventfld.long 0x0c 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending" textline " " eventfld.long 0x0c 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending" eventfld.long 0x0c 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending" tree.end tree "User 1 Mailbox Interrupts" group.long (0x100+0x10)++0xf line.long 0x00 "IRQSTATUS_RAW_1,Mailbox IRQ RAW Status Register" bitfld.long 0x00 15. " NOTFULLSTATUSU1MB7 ,NotFull Raw Status bit for User 1 Mailbox 7" "Full,Not full" bitfld.long 0x00 14. " NEWMSGSTATUSU1MB7 ,NewMessage Raw Status bit for User 1 Mailbox 7" "No action,New message" textline " " bitfld.long 0x00 13. " NOTFULLSTATUSU1MB6 ,NotFull Raw Status bit for User 1 Mailbox 6" "Full,Not full" bitfld.long 0x00 12. " NEWMSGSTATUSU1MB6 ,NewMessage Raw Status bit for User 1 Mailbox 6" "No action,New message" textline " " bitfld.long 0x00 11. " NOTFULLSTATUSU1MB5 ,NotFull Raw Status bit for User 1 Mailbox 5" "Full,Not full" bitfld.long 0x00 10. " NEWMSGSTATUSU1MB5 ,NewMessage Raw Status bit for User 1 Mailbox 5" "No action,New message" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSU1MB4 ,NotFull Raw Status bit for User 1 Mailbox 4" "Full,Not full" bitfld.long 0x00 8. " NEWMSGSTATUSU1MB4 ,NewMessage Raw Status bit for User 1 Mailbox 4" "No action,New message" textline " " bitfld.long 0x00 7. " NOTFULLSTATUSU1MB3 ,NotFull Raw Status bit for User 1 Mailbox 3" "Full,Not full" bitfld.long 0x00 6. " NEWMSGSTATUSU1MB3 ,NewMessage Raw Status bit for User 1 Mailbox 3" "No action,New message" textline " " bitfld.long 0x00 5. " NOTFULLSTATUSU1MB2 ,NotFull Raw Status bit for User 1 Mailbox 2" "Full,Not full" bitfld.long 0x00 4. " NEWMSGSTATUSU1MB2 ,NewMessage Raw Status bit for User 1 Mailbox 2" "No action,New message" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSU1MB1 ,NotFull Raw Status bit for User 1 Mailbox 1" "Full,Not full" bitfld.long 0x00 2. " NEWMSGSTATUSU1MB1 ,NewMessage Raw Status bit for User 1 Mailbox 1" "No action,New message" textline " " bitfld.long 0x00 1. " NOTFULLSTATUSU1MB0 ,NotFull Raw Status bit for User 1 Mailbox 0" "Full,Not full" bitfld.long 0x00 0. " NEWMSGSTATUSU1MB0 ,NewMessage Raw Status bit for User 1 Mailbox 0" "No action,New message" line.long 0x04 "IRQSTATUS_CLR_1,Mailbox IRQ Clear Status Register" eventfld.long 0x04 15. " NOTFULLSTATUSU1MB7 ,NotFull Clear Status bit for User 1 Mailbox 7" "Not pending,Pending" eventfld.long 0x04 14. " NEWMSGSTATUSU1MB7 ,NewMessage Clear Status bit for User 1 Mailbox 7" "Not pending,Pending" textline " " eventfld.long 0x04 13. " NOTFULLSTATUSU1MB6 ,NotFull Clear Status bit for User 1 Mailbox 6" "Not pending,Pending" eventfld.long 0x04 12. " NEWMSGSTATUSU1MB6 ,NewMessage Clear Status bit for User 1 Mailbox 6" "Not pending,Pending" textline " " eventfld.long 0x04 11. " NOTFULLSTATUSU1MB5 ,NotFull Clear Status bit for User 1 Mailbox 5" "Not pending,Pending" eventfld.long 0x04 10. " NEWMSGSTATUSU1MB5 ,NewMessage Clear Status bit for User 1 Mailbox 5" "Not pending,Pending" textline " " eventfld.long 0x04 9. " NOTFULLSTATUSU1MB4 ,NotFull Clear Status bit for User 1 Mailbox 4" "Not pending,Pending" eventfld.long 0x04 8. " NEWMSGSTATUSU1MB4 ,NewMessage Clear Status bit for User 1 Mailbox 4" "Not pending,Pending" textline " " eventfld.long 0x04 7. " NOTFULLSTATUSU1MB3 ,NotFull Clear Status bit for User 1 Mailbox 3" "Not pending,Pending" eventfld.long 0x04 6. " NEWMSGSTATUSU1MB3 ,NewMessage Clear Status bit for User 1 Mailbox 3" "Not pending,Pending" textline " " eventfld.long 0x04 5. " NOTFULLSTATUSU1MB2 ,NotFull Clear Status bit for User 1 Mailbox 2" "Not pending,Pending" eventfld.long 0x04 4. " NEWMSGSTATUSU1MB2 ,NewMessage Clear Status bit for User 1 Mailbox 2" "Not pending,Pending" textline " " eventfld.long 0x04 3. " NOTFULLSTATUSU1MB1 ,NotFull Clear Status bit for User 1 Mailbox 1" "Not pending,Pending" eventfld.long 0x04 2. " NEWMSGSTATUSU1MB1 ,NewMessage Clear Status bit for User 1 Mailbox 1" "Not pending,Pending" textline " " eventfld.long 0x04 1. " NOTFULLSTATUSU1MB0 ,NotFull Clear Status bit for User 1 Mailbox 0" "Not pending,Pending" eventfld.long 0x04 0. " NEWMSGSTATUSU1MB0 ,NewMessage Clear Status bit for User 1 Mailbox 0" "Not pending,Pending" line.long 0x08 "IRQENABLE_SET_1,Mailbox IRQ Enable Set Register" bitfld.long 0x08 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled" bitfld.long 0x08 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled" bitfld.long 0x08 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled" bitfld.long 0x08 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled" bitfld.long 0x08 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled" bitfld.long 0x08 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled" bitfld.long 0x08 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled" bitfld.long 0x08 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled" bitfld.long 0x08 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled" line.long 0x0c "IRQENABLE_CLR_1,Mailbox IRQ Enable Clear Register" eventfld.long 0x0c 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending" eventfld.long 0x0c 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending" textline " " eventfld.long 0x0c 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending" eventfld.long 0x0c 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending" textline " " eventfld.long 0x0c 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending" eventfld.long 0x0c 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending" textline " " eventfld.long 0x0c 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending" eventfld.long 0x0c 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending" textline " " eventfld.long 0x0c 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending" eventfld.long 0x0c 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending" textline " " eventfld.long 0x0c 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending" eventfld.long 0x0c 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending" textline " " eventfld.long 0x0c 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending" eventfld.long 0x0c 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending" textline " " eventfld.long 0x0c 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending" eventfld.long 0x0c 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending" tree.end tree "User 2 Mailbox Interrupts" group.long (0x100+0x20)++0xf line.long 0x00 "IRQSTATUS_RAW_2,Mailbox IRQ RAW Status Register" bitfld.long 0x00 15. " NOTFULLSTATUSU2MB7 ,NotFull Raw Status bit for User 2 Mailbox 7" "Full,Not full" bitfld.long 0x00 14. " NEWMSGSTATUSU2MB7 ,NewMessage Raw Status bit for User 2 Mailbox 7" "No action,New message" textline " " bitfld.long 0x00 13. " NOTFULLSTATUSU2MB6 ,NotFull Raw Status bit for User 2 Mailbox 6" "Full,Not full" bitfld.long 0x00 12. " NEWMSGSTATUSU2MB6 ,NewMessage Raw Status bit for User 2 Mailbox 6" "No action,New message" textline " " bitfld.long 0x00 11. " NOTFULLSTATUSU2MB5 ,NotFull Raw Status bit for User 2 Mailbox 5" "Full,Not full" bitfld.long 0x00 10. " NEWMSGSTATUSU2MB5 ,NewMessage Raw Status bit for User 2 Mailbox 5" "No action,New message" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSU2MB4 ,NotFull Raw Status bit for User 2 Mailbox 4" "Full,Not full" bitfld.long 0x00 8. " NEWMSGSTATUSU2MB4 ,NewMessage Raw Status bit for User 2 Mailbox 4" "No action,New message" textline " " bitfld.long 0x00 7. " NOTFULLSTATUSU2MB3 ,NotFull Raw Status bit for User 2 Mailbox 3" "Full,Not full" bitfld.long 0x00 6. " NEWMSGSTATUSU2MB3 ,NewMessage Raw Status bit for User 2 Mailbox 3" "No action,New message" textline " " bitfld.long 0x00 5. " NOTFULLSTATUSU2MB2 ,NotFull Raw Status bit for User 2 Mailbox 2" "Full,Not full" bitfld.long 0x00 4. " NEWMSGSTATUSU2MB2 ,NewMessage Raw Status bit for User 2 Mailbox 2" "No action,New message" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSU2MB1 ,NotFull Raw Status bit for User 2 Mailbox 1" "Full,Not full" bitfld.long 0x00 2. " NEWMSGSTATUSU2MB1 ,NewMessage Raw Status bit for User 2 Mailbox 1" "No action,New message" textline " " bitfld.long 0x00 1. " NOTFULLSTATUSU2MB0 ,NotFull Raw Status bit for User 2 Mailbox 0" "Full,Not full" bitfld.long 0x00 0. " NEWMSGSTATUSU2MB0 ,NewMessage Raw Status bit for User 2 Mailbox 0" "No action,New message" line.long 0x04 "IRQSTATUS_CLR_2,Mailbox IRQ Clear Status Register" eventfld.long 0x04 15. " NOTFULLSTATUSU2MB7 ,NotFull Clear Status bit for User 2 Mailbox 7" "Not pending,Pending" eventfld.long 0x04 14. " NEWMSGSTATUSU2MB7 ,NewMessage Clear Status bit for User 2 Mailbox 7" "Not pending,Pending" textline " " eventfld.long 0x04 13. " NOTFULLSTATUSU2MB6 ,NotFull Clear Status bit for User 2 Mailbox 6" "Not pending,Pending" eventfld.long 0x04 12. " NEWMSGSTATUSU2MB6 ,NewMessage Clear Status bit for User 2 Mailbox 6" "Not pending,Pending" textline " " eventfld.long 0x04 11. " NOTFULLSTATUSU2MB5 ,NotFull Clear Status bit for User 2 Mailbox 5" "Not pending,Pending" eventfld.long 0x04 10. " NEWMSGSTATUSU2MB5 ,NewMessage Clear Status bit for User 2 Mailbox 5" "Not pending,Pending" textline " " eventfld.long 0x04 9. " NOTFULLSTATUSU2MB4 ,NotFull Clear Status bit for User 2 Mailbox 4" "Not pending,Pending" eventfld.long 0x04 8. " NEWMSGSTATUSU2MB4 ,NewMessage Clear Status bit for User 2 Mailbox 4" "Not pending,Pending" textline " " eventfld.long 0x04 7. " NOTFULLSTATUSU2MB3 ,NotFull Clear Status bit for User 2 Mailbox 3" "Not pending,Pending" eventfld.long 0x04 6. " NEWMSGSTATUSU2MB3 ,NewMessage Clear Status bit for User 2 Mailbox 3" "Not pending,Pending" textline " " eventfld.long 0x04 5. " NOTFULLSTATUSU2MB2 ,NotFull Clear Status bit for User 2 Mailbox 2" "Not pending,Pending" eventfld.long 0x04 4. " NEWMSGSTATUSU2MB2 ,NewMessage Clear Status bit for User 2 Mailbox 2" "Not pending,Pending" textline " " eventfld.long 0x04 3. " NOTFULLSTATUSU2MB1 ,NotFull Clear Status bit for User 2 Mailbox 1" "Not pending,Pending" eventfld.long 0x04 2. " NEWMSGSTATUSU2MB1 ,NewMessage Clear Status bit for User 2 Mailbox 1" "Not pending,Pending" textline " " eventfld.long 0x04 1. " NOTFULLSTATUSU2MB0 ,NotFull Clear Status bit for User 2 Mailbox 0" "Not pending,Pending" eventfld.long 0x04 0. " NEWMSGSTATUSU2MB0 ,NewMessage Clear Status bit for User 2 Mailbox 0" "Not pending,Pending" line.long 0x08 "IRQENABLE_SET_2,Mailbox IRQ Enable Set Register" bitfld.long 0x08 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled" bitfld.long 0x08 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled" bitfld.long 0x08 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled" bitfld.long 0x08 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled" bitfld.long 0x08 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled" bitfld.long 0x08 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled" bitfld.long 0x08 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled" bitfld.long 0x08 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled" bitfld.long 0x08 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled" line.long 0x0c "IRQENABLE_CLR_2,Mailbox IRQ Enable Clear Register" eventfld.long 0x0c 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending" eventfld.long 0x0c 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending" textline " " eventfld.long 0x0c 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending" eventfld.long 0x0c 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending" textline " " eventfld.long 0x0c 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending" eventfld.long 0x0c 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending" textline " " eventfld.long 0x0c 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending" eventfld.long 0x0c 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending" textline " " eventfld.long 0x0c 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending" eventfld.long 0x0c 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending" textline " " eventfld.long 0x0c 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending" eventfld.long 0x0c 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending" textline " " eventfld.long 0x0c 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending" eventfld.long 0x0c 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending" textline " " eventfld.long 0x0c 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending" eventfld.long 0x0c 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending" tree.end tree "User 3 Mailbox Interrupts" group.long (0x100+0x30)++0xf line.long 0x00 "IRQSTATUS_RAW_3,Mailbox IRQ RAW Status Register" bitfld.long 0x00 15. " NOTFULLSTATUSU3MB7 ,NotFull Raw Status bit for User 3 Mailbox 7" "Full,Not full" bitfld.long 0x00 14. " NEWMSGSTATUSU3MB7 ,NewMessage Raw Status bit for User 3 Mailbox 7" "No action,New message" textline " " bitfld.long 0x00 13. " NOTFULLSTATUSU3MB6 ,NotFull Raw Status bit for User 3 Mailbox 6" "Full,Not full" bitfld.long 0x00 12. " NEWMSGSTATUSU3MB6 ,NewMessage Raw Status bit for User 3 Mailbox 6" "No action,New message" textline " " bitfld.long 0x00 11. " NOTFULLSTATUSU3MB5 ,NotFull Raw Status bit for User 3 Mailbox 5" "Full,Not full" bitfld.long 0x00 10. " NEWMSGSTATUSU3MB5 ,NewMessage Raw Status bit for User 3 Mailbox 5" "No action,New message" textline " " bitfld.long 0x00 9. " NOTFULLSTATUSU3MB4 ,NotFull Raw Status bit for User 3 Mailbox 4" "Full,Not full" bitfld.long 0x00 8. " NEWMSGSTATUSU3MB4 ,NewMessage Raw Status bit for User 3 Mailbox 4" "No action,New message" textline " " bitfld.long 0x00 7. " NOTFULLSTATUSU3MB3 ,NotFull Raw Status bit for User 3 Mailbox 3" "Full,Not full" bitfld.long 0x00 6. " NEWMSGSTATUSU3MB3 ,NewMessage Raw Status bit for User 3 Mailbox 3" "No action,New message" textline " " bitfld.long 0x00 5. " NOTFULLSTATUSU3MB2 ,NotFull Raw Status bit for User 3 Mailbox 2" "Full,Not full" bitfld.long 0x00 4. " NEWMSGSTATUSU3MB2 ,NewMessage Raw Status bit for User 3 Mailbox 2" "No action,New message" textline " " bitfld.long 0x00 3. " NOTFULLSTATUSU3MB1 ,NotFull Raw Status bit for User 3 Mailbox 1" "Full,Not full" bitfld.long 0x00 2. " NEWMSGSTATUSU3MB1 ,NewMessage Raw Status bit for User 3 Mailbox 1" "No action,New message" textline " " bitfld.long 0x00 1. " NOTFULLSTATUSU3MB0 ,NotFull Raw Status bit for User 3 Mailbox 0" "Full,Not full" bitfld.long 0x00 0. " NEWMSGSTATUSU3MB0 ,NewMessage Raw Status bit for User 3 Mailbox 0" "No action,New message" line.long 0x04 "IRQSTATUS_CLR_3,Mailbox IRQ Clear Status Register" eventfld.long 0x04 15. " NOTFULLSTATUSU3MB7 ,NotFull Clear Status bit for User 3 Mailbox 7" "Not pending,Pending" eventfld.long 0x04 14. " NEWMSGSTATUSU3MB7 ,NewMessage Clear Status bit for User 3 Mailbox 7" "Not pending,Pending" textline " " eventfld.long 0x04 13. " NOTFULLSTATUSU3MB6 ,NotFull Clear Status bit for User 3 Mailbox 6" "Not pending,Pending" eventfld.long 0x04 12. " NEWMSGSTATUSU3MB6 ,NewMessage Clear Status bit for User 3 Mailbox 6" "Not pending,Pending" textline " " eventfld.long 0x04 11. " NOTFULLSTATUSU3MB5 ,NotFull Clear Status bit for User 3 Mailbox 5" "Not pending,Pending" eventfld.long 0x04 10. " NEWMSGSTATUSU3MB5 ,NewMessage Clear Status bit for User 3 Mailbox 5" "Not pending,Pending" textline " " eventfld.long 0x04 9. " NOTFULLSTATUSU3MB4 ,NotFull Clear Status bit for User 3 Mailbox 4" "Not pending,Pending" eventfld.long 0x04 8. " NEWMSGSTATUSU3MB4 ,NewMessage Clear Status bit for User 3 Mailbox 4" "Not pending,Pending" textline " " eventfld.long 0x04 7. " NOTFULLSTATUSU3MB3 ,NotFull Clear Status bit for User 3 Mailbox 3" "Not pending,Pending" eventfld.long 0x04 6. " NEWMSGSTATUSU3MB3 ,NewMessage Clear Status bit for User 3 Mailbox 3" "Not pending,Pending" textline " " eventfld.long 0x04 5. " NOTFULLSTATUSU3MB2 ,NotFull Clear Status bit for User 3 Mailbox 2" "Not pending,Pending" eventfld.long 0x04 4. " NEWMSGSTATUSU3MB2 ,NewMessage Clear Status bit for User 3 Mailbox 2" "Not pending,Pending" textline " " eventfld.long 0x04 3. " NOTFULLSTATUSU3MB1 ,NotFull Clear Status bit for User 3 Mailbox 1" "Not pending,Pending" eventfld.long 0x04 2. " NEWMSGSTATUSU3MB1 ,NewMessage Clear Status bit for User 3 Mailbox 1" "Not pending,Pending" textline " " eventfld.long 0x04 1. " NOTFULLSTATUSU3MB0 ,NotFull Clear Status bit for User 3 Mailbox 0" "Not pending,Pending" eventfld.long 0x04 0. " NEWMSGSTATUSU3MB0 ,NewMessage Clear Status bit for User 3 Mailbox 0" "Not pending,Pending" line.long 0x08 "IRQENABLE_SET_3,Mailbox IRQ Enable Set Register" bitfld.long 0x08 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled" bitfld.long 0x08 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled" bitfld.long 0x08 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled" bitfld.long 0x08 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled" bitfld.long 0x08 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled" bitfld.long 0x08 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled" bitfld.long 0x08 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled" bitfld.long 0x08 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled" bitfld.long 0x08 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled" line.long 0x0c "IRQENABLE_CLR_3,Mailbox IRQ Enable Clear Register" eventfld.long 0x0c 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending" eventfld.long 0x0c 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending" textline " " eventfld.long 0x0c 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending" eventfld.long 0x0c 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending" textline " " eventfld.long 0x0c 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending" eventfld.long 0x0c 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending" textline " " eventfld.long 0x0c 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending" eventfld.long 0x0c 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending" textline " " eventfld.long 0x0c 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending" eventfld.long 0x0c 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending" textline " " eventfld.long 0x0c 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending" eventfld.long 0x0c 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending" textline " " eventfld.long 0x0c 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending" eventfld.long 0x0c 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending" textline " " eventfld.long 0x0c 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending" eventfld.long 0x0c 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending" tree.end width 0xb tree.end tree "SPINLOCK" base ad:0x480CA000 width 18. rgroup.long 0x00++0x3 line.long 0x00 "SPINLOCK_REV,IP Revision Register" group.long 0x10++0x3 line.long 0x00 "SPINLOCK_SYSCFG,System Configuration Register" rbitfld.long 0x00 8. " CLOCKACTIVITY ,Clock activity during IDLE mode" "Not required,Required" rbitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..." rbitfld.long 0x00 2. " ENWAKEUP ,Asynchronous wakeup generation" "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No action,Reset" rbitfld.long 0x00 0. " AUTOGATING ,Internal interface clock gating strategy" "Free-running,Applied" rgroup.long 0x14++0x3 line.long 0x00 "SPINLOCK_SYSSTAT,System Status Register" hexmask.long.byte 0x00 24.--31. 1. " NUMLOCKS ,Number of lock registers implemented" bitfld.long 0x00 15. " IU7 ,In-Use flag 7" "Low,High" bitfld.long 0x00 14. " IU6 ,In-Use flag 6" "Low,High" bitfld.long 0x00 13. " IU5 ,In-Use flag 5" "Low,High" bitfld.long 0x00 12. " IU4 ,In-Use flag 4" "Low,High" textline " " bitfld.long 0x00 11. " IU3 ,In-Use flag 3" "Low,High" bitfld.long 0x00 10. " IU2 ,In-Use flag 2" "Low,High" bitfld.long 0x00 9. " IU1 ,In-Use flag 1" "Low,High" bitfld.long 0x00 8. " IU0 ,In-Use flag 0" "Low,High" bitfld.long 0x00 0. " RESETDONE ,Reset done status" "In progress,Completed" width 22. tree "Lock Registers" group.long (0x800+0x0)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_0,Lock Register 0" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x4)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_1,Lock Register 1" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x8)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_2,Lock Register 2" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0xC)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_3,Lock Register 3" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x10)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_4,Lock Register 4" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x14)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_5,Lock Register 5" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x18)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_6,Lock Register 6" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x1C)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_7,Lock Register 7" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x20)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_8,Lock Register 8" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x24)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_9,Lock Register 9" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x28)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_10,Lock Register 10" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x2C)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_11,Lock Register 11" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x30)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_12,Lock Register 12" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x34)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_13,Lock Register 13" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x38)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_14,Lock Register 14" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x3C)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_15,Lock Register 15" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x40)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_16,Lock Register 16" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x44)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_17,Lock Register 17" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x48)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_18,Lock Register 18" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x4C)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_19,Lock Register 19" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x50)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_20,Lock Register 20" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x54)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_21,Lock Register 21" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x58)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_22,Lock Register 22" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x5C)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_23,Lock Register 23" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x60)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_24,Lock Register 24" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x64)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_25,Lock Register 25" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x68)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_26,Lock Register 26" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x6C)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_27,Lock Register 27" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x70)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_28,Lock Register 28" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x74)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_29,Lock Register 29" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x78)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_30,Lock Register 30" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" group.long (0x800+0x7C)++0x3 line.long 0x00 "SPINLOCK_LOCK_REG_31,Lock Register 31" bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken" tree.end width 11. tree.end tree.end tree "MMC (Multimedia Card)" tree "MMCHS0" base ad:0x48060000 width 17. sif !(cpuis("AM335*")) rgroup.long 0x00++0x7 line.long 0x00 "SD_HL_REV,IP Revision Identifier Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" bitfld.long 0x00 11.--15. " R_RTL ,R_RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" line.long 0x04 "SD_HL_HWINFO,Hardware Configuration Register" sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x04 2.--5. " MEM_SIZE ,Memory Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 1. " MERGE_MEM ,Merge memory" "Low,High" textline " " else bitfld.long 0x04 1. " MEM_SIZE ,Memory Size" "Low,High" textline " " endif bitfld.long 0x04 0. " MADMA_EN ,MADMA Enable" "Disabled,Enabled" group.long 0x10++0x3 line.long 0x00 "SD_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Standby mode" "Mode0,Mode1,Mode2,Mode3" bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode" "Mode0,Mode1,Mode2,Mode3" bitfld.long 0x00 1. " FREEEMU ,Free EMU" "Low,High" textline " " bitfld.long 0x00 0. " SOFTRESET ,Soft reset" "No reset,Reset" endif width 17. group.long 0x110++0x3 line.long 0x00 "SD_SYSCONFIG,System Configuration Register" bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power management standby/wait control (when MADMA is enabled)" "Force-standby,No standby,Smart-standby,Smart-standby wake-up-capable" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Inactive,Interface,Functional,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle wake-up-capable" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up capability enable" "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Automatic" rgroup.long 0x114++0x3 line.long 0x00 "SD_SYSSTATUS,System Status Register" bitfld.long 0x00 0. " RESETDONE ,Reset status" "On-going,Done" group.long 0x124++0x7 line.long 0x00 "SD_CSRE,Card Status Response Error Register" width 17. line.long 0x04 "SD_SYSTEST,System Test Register" bitfld.long 0x04 16. " OBI ,Out of band interrupt data value input/output" "Low,High" bitfld.long 0x04 15. " SDCD ,Card detect input/output signal data value" "Low,High" bitfld.long 0x04 14. " SDWP ,Write protect input/output signal data value" "Low,High" textline " " bitfld.long 0x04 13. " WAKD ,Wake request input/output signal data value" "Low,High" bitfld.long 0x04 12. " SSB ,Set status bit" "Clear,Force" bitfld.long 0x04 11. " D7D ,DAT7 input/output signal data value" "Low,High" textline " " bitfld.long 0x04 10. " D6D ,DAT6 input/output signal data value" "Low,High" bitfld.long 0x04 9. " D5D ,DAT5 input/output signal data value" "Low,High" bitfld.long 0x04 8. " D4D ,DAT4 input/output signal data value" "Low,High" textline " " bitfld.long 0x04 7. " D3D ,DAT3 input/output signal data value" "Low,High" bitfld.long 0x04 6. " D2D ,DAT2 input/output signal data value" "Low,High" bitfld.long 0x04 5. " D1D ,DAT1 input/output signal data value" "Low,High" textline " " bitfld.long 0x04 4. " D0D ,DAT0 input/output signal data value" "Low,High" bitfld.long 0x04 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input" bitfld.long 0x04 2. " CDAT ,CMD input/output signal data value" "Low,High" textline " " bitfld.long 0x04 1. " CDIR ,Control of the CMD pin direction" "Output,Input" bitfld.long 0x04 0. " MCKD ,Clock input/output signal data value" "Low,High" width 17. group.long 0x12c++0x7 line.long 0x00 "SD_CON,Configuration Register" bitfld.long 0x00 21. " SDMA_LNE ,Select Slave DMA Level/Edge Request" "Edge,Level" bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection(when MADMA is enabled)" "Slave,?..." bitfld.long 0x00 19. " DDR ,Dual data rate transmission mode" "Single edge,Both" textline " " bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status supported" "Not forced,Forced" bitfld.long 0x00 17. " BOOT_ACK ,Boot acknowledge receive" "NO ACK,ACK" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained" sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") textline " " bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced" bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA" endif textline " " bitfld.long 0x00 11. " CTPL ,Control Power for SD_DAT1 line" "Disabled,Enabled" bitfld.long 0x00 9.--10. " DVAL ,Debounce period for filter SDCD" "33 us,231 us,1 ms,8.4 ms" bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low" textline " " bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low" sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 6. " MIT ,MMC Interrupt Command" "Enabled,Disabled" textline " " bitfld.long 0x00 5. " DW8 ,8-bit mode select (MMC cars only)" "1-bit/4-bit,8-bit" endif bitfld.long 0x00 4. " MODE ,Mode select(all cards)" "Functional,SYSTEST" sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 3. " STR ,Stream command (MMC cars only)" "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cars only)" "Disabled,Enabled" bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent" else bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent" endif sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cars only)" "Disabled,Enabled" endif line.long 0x04 "SD_PWCNT,Power Counter Register" hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter" rgroup.long 0x200++0x3 line.long 0x00 "SD_SDMASA,SDMA System Address Register" if (((d.l(ad:0x48060000+0x20c))&0x20)==0x20) group.long 0x204++0x3 line.long 0x00 "SD_BLK,Transfer Length Configuration Register" hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" else group.long 0x204++0x3 line.long 0x00 "SD_BLK,Transfer Length Configuration Register" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" endif group.long 0x208++0x7 line.long 0x00 "SD_ARG,Command Argument Register" line.long 0x04 "SD_CMD,Command and Transfer Mode Register" bitfld.long 0x04 24.--29. " INDEX ,Command number sent to card" "Cmd0 or acmd0,Cmd1 or acmd1,Cmd2 or acmd2,Cmd3 or acmd3,Cmd4 or acmd4,Cmd5 or acmd5,Cmd6 or acmd6,Cmd7 or acmd7,Cmd8 or acmd8,Cmd9 or acmd9,Cmd10 or acmd10,Cmd11 or acmd11,Cmd12 or acmd12,Cmd13 or acmd13,Cmd14 or acmd14,Cmd15 or acmd15,Cmd16 or acmd16,Cmd17 or acmd17,Cmd18 or acmd18,Cmd19 or acmd19,Cmd20 or acmd20,Cmd21 or acmd21,Cmd22 or acmd22,Cmd23 or acmd23,Cmd24 or acmd24,Cmd25 or acmd25,Cmd26 or acmd26,Cmd27 or acmd27,Cmd28 or acmd28,Cmd29 or acmd29,Cmd30 or acmd30,Cmd31 or acmd31,Cmd32 or acmd32,Cmd33 or acmd33,Cmd34 or acmd34,Cmd35 or acmd35,Cmd36 or acmd36,Cmd37 or acmd37,Cmd38 or acmd38,Cmd39 or acmd39,Cmd40 or acmd40,Cmd41 or acmd41,Cmd42 or acmd42,Cmd43 or acmd43,Cmd44 or acmd44,Cmd45 or acmd45,Cmd46 or acmd46,Cmd47 or acmd47,Cmd48 or acmd48,Cmd49 or acmd49,Cmd50 or acmd50,Cmd51 or acmd51,Cmd52 or acmd52,Cmd53 or acmd53,Cmd54 or acmd54,Cmd55 or acmd55,Cmd56 or acmd56,Cmd57 or acmd57,Cmd58 or acmd58,Cmd59 or acmd59,Cmd60 or acmd60,Cmd61 or acmd61,Cmd62 or acmd62,Cmd63 or acmd63" bitfld.long 0x04 22.--23. " CMD_TYPE ,Command type" "Other,Bus suspend,Function select,I/O Abort" bitfld.long 0x04 21. " DP ,Data present select" "No data,Present" textline " " bitfld.long 0x04 20. " CICE ,Command index check enable" "Disabled,Enabled" bitfld.long 0x04 19. " CCCE ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x04 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits (busy)" textline " " bitfld.long 0x04 5. " MSBS ,Multi/Single block select" "Single,Multi" bitfld.long 0x04 4. " DDIR ,Data transfer direction" "Write,Read" bitfld.long 0x04 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " BCE ,Block Count Enable (Multiple block transfers only)" "Disabled,Enabled" bitfld.long 0x04 0. " DE ,DMA Enable" "Disabled,Enabled" rgroup.long 0x210++0xf line.long 0x00 "SD_RSP10,Command Response 0 and 1 Register" hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response[31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response[15:0]" line.long 0x04 "SD_RSP32,Command Response 2 and 3 Register" hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command Response[63:48]" hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command Response[47:32]" line.long 0x08 "SD_RSP54,Command Response 4 and 5 Register" hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command Response[95:80]" hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command Response[79:64]" line.long 0x0c "SD_RSP76,Command Response 6 and 7 Register" hexmask.long.word 0x0c 16.--31. 1. " RSP7 ,Command Response[127:112]" hexmask.long.word 0x0c 0.--15. 1. " RSP6 ,Command Response[111:96]" width 17. group.long 0x220++0x3 line.long 0x00 "SD_DATA,Data Register" if (((d.l(ad:0x48060000+0x12c))&0x180)==0x180) rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CINS ,Detect card" "Detected,Not detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" elif (((d.l(ad:0x48060000+0x12c))&0x180)==0x100) rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" elif (((d.l(ad:0x48060000+0x12c))&0x180)==0x80) rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CI ,Detect card" "Detected,Not detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" else rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" endif group.long 0x228++0x13 line.long 0x00 "SD_HCTL,Host Control Register" bitfld.long 0x00 27. " OBWE ,Wake-up event enable for OBI" "Disabled,Enabled" bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " IBG ,Interrupt block at gap (in 4-bit mode only)" "Disabled,Enabled" bitfld.long 0x00 18. " RWC ,Read wait control (SDIO cards)" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CR ,Transfer continue request" "No affect,Restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stopped" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On" bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SDCD,CDTL" bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select" "Reserved,Reserved,32-bit ADMA2,?..." bitfld.long 0x00 2. " HSPE ,High speed enable" "Normal,High" bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit" line.long 0x04 "SD_SYSCTL,SD System Control Register" bitfld.long 0x04 26. " SRD ,Software reset for SD_DAT line" "No reset,Reset" bitfld.long 0x04 25. " SRC ,Software reset for SD_CMD line" "No reset,Reset" bitfld.long 0x04 24. " SRA ,Software reset for all" "No reset,Reset" textline " " bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCFx2^13,TCFx2^14,TCFx2^15,TCFx2^16,TCFx2^17,TCFx2^18,TCFx2^19,TCFx2^20,TCFx2^21,TCFx2^22,TCFx2^23,TCFx2^24,TCFx2^25,TCFx2^26,TCFx2^27,?..." hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select" bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable" else bitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable" endif bitfld.long 0x04 0. " ICE ,Internal clock enable" "Disabled,Enabled" line.long 0x08 "SD_STAT,Interrupt Status Register" eventfld.long 0x08 29. " BADA ,Bad access to data space interrupt" "No interrupt,Interrupt" eventfld.long 0x08 28. " CERR ,Card error" "No interrupt,Interrupt" eventfld.long 0x08 25. " ADMAE ,ADMA error" "No interrupt,Interrupt" textline " " eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No interrupt,Interrupt" eventfld.long 0x08 22. " DEB ,Data end bit error" "No interrupt,Interrupt" eventfld.long 0x08 21. " DCRC ,Data CRC error" "No interrupt,Interrupt" textline " " eventfld.long 0x08 20. " DTO ,Data timeout error" "No interrupt,Interrupt" eventfld.long 0x08 19. " CIE ,Command index error" "No interrupt,Interrupt" eventfld.long 0x08 18. " CEB ,Command end bit error" "No interrupt,Interrupt" textline " " eventfld.long 0x08 17. " CCRC ,Command CRC error" "No interrupt,Interrupt" eventfld.long 0x08 16. " CTO ,Command timeout error" "No interrupt,Interrupt" sif (cpuis("DRA62*")||cpuis("AM355*")) rbitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt" eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt" else bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt" eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt" bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt" endif textline " " eventfld.long 0x08 7. " CREM ,Card removal" "No interrupt,Interrupt" eventfld.long 0x08 6. " CINS ,Card insertion" "No interrupt,Interrupt" eventfld.long 0x08 5. " BRR ,Buffer read ready" "No interrupt,Interrupt" textline " " eventfld.long 0x08 4. " BWR ,Buffer write ready" "No interrupt,Interrupt" eventfld.long 0x08 3. " DMA ,DMA interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BGE ,Block gap event" "No interrupt,Interrupt" textline " " eventfld.long 0x08 1. " TC ,Transfer completed" "No interrupt,Interrupt" eventfld.long 0x08 0. " CC ,Command completed" "No interrupt,Interrupt" width 17. line.long 0x0c "SD_IE,Interrupt SD Enable Register" bitfld.long 0x0c 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled" bitfld.long 0x0c 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 25. " ADMA_ENABLE ,ADMA error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x0c 15. " NULL ,Null" "0,1" else bitfld.long 0x0c 15. " NULL ,Null" "0,1" endif textline " " bitfld.long 0x0c 10. " BSR_ENABLE ,Boot status received interrupt enable" "Masked,Enabled" bitfld.long 0x0c 9. " OBI_ENABLE ,Out of band interrupt enable" "Masked,Enabled" bitfld.long 0x0c 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 7. " CREM_ENABLE ,Card removal interrupt enable" "Masked,Enabled" bitfld.long 0x0c 6. " CINS_ENABLE ,Card insertion interrupt enable" "Masked,Enabled" bitfld.long 0x0c 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled" bitfld.long 0x0c 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled" bitfld.long 0x0c 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled" bitfld.long 0x0c 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled" line.long 0x10 "SD_ISE,Interrupt Signal Enable Register" bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Disabled,Enabled" bitfld.long 0x10 28. " CERR_SIGEN ,Card error signal status enable" "Disabled,Enabled" bitfld.long 0x10 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled" bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled" bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled" bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled" bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled" bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x10 15. " NULL ,Null" "0,1" else bitfld.long 0x10 15. " NULL ,Null" "0,1" endif textline " " bitfld.long 0x10 10. " BSR_SIGEN ,Boot status received signal status enable" "Disabled,Enabled" bitfld.long 0x10 9. " OBI_SIGEN ,Out of band signal status enable" "Disabled,Enabled" bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " CREM_SIGEN ,Card removal signal status enable" "Disabled,Enabled" bitfld.long 0x10 6. " CINS_SIGEN ,Card insertion signal status enable" "Disabled,Enabled" bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled" bitfld.long 0x10 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled" bitfld.long 0x10 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled" bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled" width 17. if ((((d.l(ad:(ad:0x48060000+0x20c)))&0x4)==0x4)&&(((d.l(ad:(ad:0x48060000+0x230)))&0x1000000)==0x1000000)) rgroup.long 0x23c++0x3 line.long 0x00 "SD_AC12,AutoCMD12 Error Status Register" bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error" textline " " bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error" textline " " bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed" else hgroup.long 0x23c++0x3 hide.long 0x00 "SD_AC12,AutoCMD12 Error Status Register" endif group.long 0x240++0x3 line.long 0x00 "SD_CAPA,Capabilities Register" bitfld.long 0x00 28. " 64BIT ,64 Bit System Bus Support" "32-bit,64-bit" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported" textline " " bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V" "Not supported,Supported" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported" rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported" textline " " rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" rbitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported" textline " " rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz" rbitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else bitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported" bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported" textline " " bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" bitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported" textline " " bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz" bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif sif (cpuis("DRA62*")) hgroup.long 0x248++0x3 hide.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register" else group.long 0x248++0x3 line.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register" hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V" hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V" textline " " hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V" endif wgroup.long 0x250++0x3 line.long 0x00 "SD_FE,Force Event Register for Error Interrupt Status" bitfld.long 0x00 29. " FE_BADA ,Force Event bad acces to data space interrupt" "No effect,Force" bitfld.long 0x00 28. " FE_CERR ,Force Event card error interrupt" "No effect,Force" textline " " bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error interrupt" "No effect,Force" bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error interrupt" "No effect,Force" textline " " bitfld.long 0x00 22. " FE_DEB ,Force Event Data end bit error interrupt" "No effect,Force" bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error interrupt" "No effect,Force" textline " " bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error interrupt" "No effect,Force" bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error interrupt" "No effect,Force" textline " " bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error interrupt" "No effect,Force" bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC error interrupt" "No effect,Force" textline " " bitfld.long 0x00 16. " FE_CTO ,Force Event Command timeout error interrupt" "No effect,Force" bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by AUTOCMD12 index error interrupt" "No effect,Force" textline " " bitfld.long 0x00 4. " FE_ACIE ,Force Event AutoCMD12 index error interrupt" "No effect,Force" bitfld.long 0x00 3. " FE_ACEB ,Force Event AutoCMD12 end bit error interrupt" "No effect,Force" textline " " bitfld.long 0x00 2. " FE_ACCE ,Force Event AutoCMD12 CRC error interrupt" "No effect,Force" bitfld.long 0x00 1. " FE_ACTO ,Force Event AutoCMD12 timeout error interrupt" "No effect,Force" textline " " bitfld.long 0x00 0. " FE_ACNE ,Force Event AutoCMD12 not executed interrupt" "No effect,Force" group.long 0x254++0x7 line.long 0x00 "SD_ADMAES,ADMA Error Status Register" bitfld.long 0x00 2. " LME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "Stop DMA,Stop DMA,Reserved,Transfer Data" line.long 0x04 "SD_ADMASAL,ADMA System Address Low Bits Register" sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") rgroup.long 0x25C++0x03 line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register" else group.long 0x25C++0x03 line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register" endif rgroup.long 0x2fc++0x3 line.long 0x00 "SD_REV,Versions Register" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number" bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Low,High" width 0xb tree.end tree "MMCHS2" base ad:0x47810000 width 17. sif !(cpuis("AM335*")) rgroup.long 0x00++0x7 line.long 0x00 "SD_HL_REV,IP Revision Identifier Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" bitfld.long 0x00 11.--15. " R_RTL ,R_RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" line.long 0x04 "SD_HL_HWINFO,Hardware Configuration Register" sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x04 2.--5. " MEM_SIZE ,Memory Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 1. " MERGE_MEM ,Merge memory" "Low,High" textline " " else bitfld.long 0x04 1. " MEM_SIZE ,Memory Size" "Low,High" textline " " endif bitfld.long 0x04 0. " MADMA_EN ,MADMA Enable" "Disabled,Enabled" group.long 0x10++0x3 line.long 0x00 "SD_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Standby mode" "Mode0,Mode1,Mode2,Mode3" bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode" "Mode0,Mode1,Mode2,Mode3" bitfld.long 0x00 1. " FREEEMU ,Free EMU" "Low,High" textline " " bitfld.long 0x00 0. " SOFTRESET ,Soft reset" "No reset,Reset" endif width 17. group.long 0x110++0x3 line.long 0x00 "SD_SYSCONFIG,System Configuration Register" bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power management standby/wait control (when MADMA is enabled)" "Force-standby,No standby,Smart-standby,Smart-standby wake-up-capable" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Inactive,Interface,Functional,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle wake-up-capable" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up capability enable" "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Automatic" rgroup.long 0x114++0x3 line.long 0x00 "SD_SYSSTATUS,System Status Register" bitfld.long 0x00 0. " RESETDONE ,Reset status" "On-going,Done" group.long 0x124++0x7 line.long 0x00 "SD_CSRE,Card Status Response Error Register" width 17. line.long 0x04 "SD_SYSTEST,System Test Register" bitfld.long 0x04 16. " OBI ,Out of band interrupt data value input/output" "Low,High" bitfld.long 0x04 15. " SDCD ,Card detect input/output signal data value" "Low,High" bitfld.long 0x04 14. " SDWP ,Write protect input/output signal data value" "Low,High" textline " " bitfld.long 0x04 13. " WAKD ,Wake request input/output signal data value" "Low,High" bitfld.long 0x04 12. " SSB ,Set status bit" "Clear,Force" bitfld.long 0x04 11. " D7D ,DAT7 input/output signal data value" "Low,High" textline " " bitfld.long 0x04 10. " D6D ,DAT6 input/output signal data value" "Low,High" bitfld.long 0x04 9. " D5D ,DAT5 input/output signal data value" "Low,High" bitfld.long 0x04 8. " D4D ,DAT4 input/output signal data value" "Low,High" textline " " bitfld.long 0x04 7. " D3D ,DAT3 input/output signal data value" "Low,High" bitfld.long 0x04 6. " D2D ,DAT2 input/output signal data value" "Low,High" bitfld.long 0x04 5. " D1D ,DAT1 input/output signal data value" "Low,High" textline " " bitfld.long 0x04 4. " D0D ,DAT0 input/output signal data value" "Low,High" bitfld.long 0x04 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input" bitfld.long 0x04 2. " CDAT ,CMD input/output signal data value" "Low,High" textline " " bitfld.long 0x04 1. " CDIR ,Control of the CMD pin direction" "Output,Input" bitfld.long 0x04 0. " MCKD ,Clock input/output signal data value" "Low,High" width 17. group.long 0x12c++0x7 line.long 0x00 "SD_CON,Configuration Register" bitfld.long 0x00 21. " SDMA_LNE ,Select Slave DMA Level/Edge Request" "Edge,Level" bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection(when MADMA is enabled)" "Slave,?..." bitfld.long 0x00 19. " DDR ,Dual data rate transmission mode" "Single edge,Both" textline " " bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status supported" "Not forced,Forced" bitfld.long 0x00 17. " BOOT_ACK ,Boot acknowledge receive" "NO ACK,ACK" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained" sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") textline " " bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced" bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA" endif textline " " bitfld.long 0x00 11. " CTPL ,Control Power for SD_DAT1 line" "Disabled,Enabled" bitfld.long 0x00 9.--10. " DVAL ,Debounce period for filter SDCD" "33 us,231 us,1 ms,8.4 ms" bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low" textline " " bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low" sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 6. " MIT ,MMC Interrupt Command" "Enabled,Disabled" textline " " bitfld.long 0x00 5. " DW8 ,8-bit mode select (MMC cars only)" "1-bit/4-bit,8-bit" endif bitfld.long 0x00 4. " MODE ,Mode select(all cards)" "Functional,SYSTEST" sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 3. " STR ,Stream command (MMC cars only)" "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cars only)" "Disabled,Enabled" bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent" else bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent" endif sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cars only)" "Disabled,Enabled" endif line.long 0x04 "SD_PWCNT,Power Counter Register" hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter" rgroup.long 0x200++0x3 line.long 0x00 "SD_SDMASA,SDMA System Address Register" if (((d.l(ad:0x47810000+0x20c))&0x20)==0x20) group.long 0x204++0x3 line.long 0x00 "SD_BLK,Transfer Length Configuration Register" hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" else group.long 0x204++0x3 line.long 0x00 "SD_BLK,Transfer Length Configuration Register" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" endif group.long 0x208++0x7 line.long 0x00 "SD_ARG,Command Argument Register" line.long 0x04 "SD_CMD,Command and Transfer Mode Register" bitfld.long 0x04 24.--29. " INDEX ,Command number sent to card" "Cmd0 or acmd0,Cmd1 or acmd1,Cmd2 or acmd2,Cmd3 or acmd3,Cmd4 or acmd4,Cmd5 or acmd5,Cmd6 or acmd6,Cmd7 or acmd7,Cmd8 or acmd8,Cmd9 or acmd9,Cmd10 or acmd10,Cmd11 or acmd11,Cmd12 or acmd12,Cmd13 or acmd13,Cmd14 or acmd14,Cmd15 or acmd15,Cmd16 or acmd16,Cmd17 or acmd17,Cmd18 or acmd18,Cmd19 or acmd19,Cmd20 or acmd20,Cmd21 or acmd21,Cmd22 or acmd22,Cmd23 or acmd23,Cmd24 or acmd24,Cmd25 or acmd25,Cmd26 or acmd26,Cmd27 or acmd27,Cmd28 or acmd28,Cmd29 or acmd29,Cmd30 or acmd30,Cmd31 or acmd31,Cmd32 or acmd32,Cmd33 or acmd33,Cmd34 or acmd34,Cmd35 or acmd35,Cmd36 or acmd36,Cmd37 or acmd37,Cmd38 or acmd38,Cmd39 or acmd39,Cmd40 or acmd40,Cmd41 or acmd41,Cmd42 or acmd42,Cmd43 or acmd43,Cmd44 or acmd44,Cmd45 or acmd45,Cmd46 or acmd46,Cmd47 or acmd47,Cmd48 or acmd48,Cmd49 or acmd49,Cmd50 or acmd50,Cmd51 or acmd51,Cmd52 or acmd52,Cmd53 or acmd53,Cmd54 or acmd54,Cmd55 or acmd55,Cmd56 or acmd56,Cmd57 or acmd57,Cmd58 or acmd58,Cmd59 or acmd59,Cmd60 or acmd60,Cmd61 or acmd61,Cmd62 or acmd62,Cmd63 or acmd63" bitfld.long 0x04 22.--23. " CMD_TYPE ,Command type" "Other,Bus suspend,Function select,I/O Abort" bitfld.long 0x04 21. " DP ,Data present select" "No data,Present" textline " " bitfld.long 0x04 20. " CICE ,Command index check enable" "Disabled,Enabled" bitfld.long 0x04 19. " CCCE ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x04 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits (busy)" textline " " bitfld.long 0x04 5. " MSBS ,Multi/Single block select" "Single,Multi" bitfld.long 0x04 4. " DDIR ,Data transfer direction" "Write,Read" bitfld.long 0x04 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " BCE ,Block Count Enable (Multiple block transfers only)" "Disabled,Enabled" bitfld.long 0x04 0. " DE ,DMA Enable" "Disabled,Enabled" rgroup.long 0x210++0xf line.long 0x00 "SD_RSP10,Command Response 0 and 1 Register" hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response[31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response[15:0]" line.long 0x04 "SD_RSP32,Command Response 2 and 3 Register" hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command Response[63:48]" hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command Response[47:32]" line.long 0x08 "SD_RSP54,Command Response 4 and 5 Register" hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command Response[95:80]" hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command Response[79:64]" line.long 0x0c "SD_RSP76,Command Response 6 and 7 Register" hexmask.long.word 0x0c 16.--31. 1. " RSP7 ,Command Response[127:112]" hexmask.long.word 0x0c 0.--15. 1. " RSP6 ,Command Response[111:96]" width 17. group.long 0x220++0x3 line.long 0x00 "SD_DATA,Data Register" if (((d.l(ad:0x47810000+0x12c))&0x180)==0x180) rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CINS ,Detect card" "Detected,Not detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" elif (((d.l(ad:0x47810000+0x12c))&0x180)==0x100) rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" elif (((d.l(ad:0x47810000+0x12c))&0x180)==0x80) rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CI ,Detect card" "Detected,Not detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" else rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" endif group.long 0x228++0x13 line.long 0x00 "SD_HCTL,Host Control Register" bitfld.long 0x00 27. " OBWE ,Wake-up event enable for OBI" "Disabled,Enabled" bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " IBG ,Interrupt block at gap (in 4-bit mode only)" "Disabled,Enabled" bitfld.long 0x00 18. " RWC ,Read wait control (SDIO cards)" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CR ,Transfer continue request" "No affect,Restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stopped" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On" bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SDCD,CDTL" bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select" "Reserved,Reserved,32-bit ADMA2,?..." bitfld.long 0x00 2. " HSPE ,High speed enable" "Normal,High" bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit" line.long 0x04 "SD_SYSCTL,SD System Control Register" bitfld.long 0x04 26. " SRD ,Software reset for SD_DAT line" "No reset,Reset" bitfld.long 0x04 25. " SRC ,Software reset for SD_CMD line" "No reset,Reset" bitfld.long 0x04 24. " SRA ,Software reset for all" "No reset,Reset" textline " " bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCFx2^13,TCFx2^14,TCFx2^15,TCFx2^16,TCFx2^17,TCFx2^18,TCFx2^19,TCFx2^20,TCFx2^21,TCFx2^22,TCFx2^23,TCFx2^24,TCFx2^25,TCFx2^26,TCFx2^27,?..." hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select" bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable" else bitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable" endif bitfld.long 0x04 0. " ICE ,Internal clock enable" "Disabled,Enabled" line.long 0x08 "SD_STAT,Interrupt Status Register" eventfld.long 0x08 29. " BADA ,Bad access to data space interrupt" "No interrupt,Interrupt" eventfld.long 0x08 28. " CERR ,Card error" "No interrupt,Interrupt" eventfld.long 0x08 25. " ADMAE ,ADMA error" "No interrupt,Interrupt" textline " " eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No interrupt,Interrupt" eventfld.long 0x08 22. " DEB ,Data end bit error" "No interrupt,Interrupt" eventfld.long 0x08 21. " DCRC ,Data CRC error" "No interrupt,Interrupt" textline " " eventfld.long 0x08 20. " DTO ,Data timeout error" "No interrupt,Interrupt" eventfld.long 0x08 19. " CIE ,Command index error" "No interrupt,Interrupt" eventfld.long 0x08 18. " CEB ,Command end bit error" "No interrupt,Interrupt" textline " " eventfld.long 0x08 17. " CCRC ,Command CRC error" "No interrupt,Interrupt" eventfld.long 0x08 16. " CTO ,Command timeout error" "No interrupt,Interrupt" sif (cpuis("DRA62*")||cpuis("AM355*")) rbitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt" eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt" else bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt" eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt" bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt" endif textline " " eventfld.long 0x08 7. " CREM ,Card removal" "No interrupt,Interrupt" eventfld.long 0x08 6. " CINS ,Card insertion" "No interrupt,Interrupt" eventfld.long 0x08 5. " BRR ,Buffer read ready" "No interrupt,Interrupt" textline " " eventfld.long 0x08 4. " BWR ,Buffer write ready" "No interrupt,Interrupt" eventfld.long 0x08 3. " DMA ,DMA interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BGE ,Block gap event" "No interrupt,Interrupt" textline " " eventfld.long 0x08 1. " TC ,Transfer completed" "No interrupt,Interrupt" eventfld.long 0x08 0. " CC ,Command completed" "No interrupt,Interrupt" width 17. line.long 0x0c "SD_IE,Interrupt SD Enable Register" bitfld.long 0x0c 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled" bitfld.long 0x0c 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 25. " ADMA_ENABLE ,ADMA error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x0c 15. " NULL ,Null" "0,1" else bitfld.long 0x0c 15. " NULL ,Null" "0,1" endif textline " " bitfld.long 0x0c 10. " BSR_ENABLE ,Boot status received interrupt enable" "Masked,Enabled" bitfld.long 0x0c 9. " OBI_ENABLE ,Out of band interrupt enable" "Masked,Enabled" bitfld.long 0x0c 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 7. " CREM_ENABLE ,Card removal interrupt enable" "Masked,Enabled" bitfld.long 0x0c 6. " CINS_ENABLE ,Card insertion interrupt enable" "Masked,Enabled" bitfld.long 0x0c 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled" bitfld.long 0x0c 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled" bitfld.long 0x0c 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled" bitfld.long 0x0c 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled" line.long 0x10 "SD_ISE,Interrupt Signal Enable Register" bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Disabled,Enabled" bitfld.long 0x10 28. " CERR_SIGEN ,Card error signal status enable" "Disabled,Enabled" bitfld.long 0x10 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled" bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled" bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled" bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled" bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled" bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x10 15. " NULL ,Null" "0,1" else bitfld.long 0x10 15. " NULL ,Null" "0,1" endif textline " " bitfld.long 0x10 10. " BSR_SIGEN ,Boot status received signal status enable" "Disabled,Enabled" bitfld.long 0x10 9. " OBI_SIGEN ,Out of band signal status enable" "Disabled,Enabled" bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " CREM_SIGEN ,Card removal signal status enable" "Disabled,Enabled" bitfld.long 0x10 6. " CINS_SIGEN ,Card insertion signal status enable" "Disabled,Enabled" bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled" bitfld.long 0x10 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled" bitfld.long 0x10 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled" bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled" width 17. if ((((d.l(ad:(ad:0x47810000+0x20c)))&0x4)==0x4)&&(((d.l(ad:(ad:0x47810000+0x230)))&0x1000000)==0x1000000)) rgroup.long 0x23c++0x3 line.long 0x00 "SD_AC12,AutoCMD12 Error Status Register" bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error" textline " " bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error" textline " " bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed" else hgroup.long 0x23c++0x3 hide.long 0x00 "SD_AC12,AutoCMD12 Error Status Register" endif group.long 0x240++0x3 line.long 0x00 "SD_CAPA,Capabilities Register" bitfld.long 0x00 28. " 64BIT ,64 Bit System Bus Support" "32-bit,64-bit" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported" textline " " bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V" "Not supported,Supported" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported" rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported" textline " " rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" rbitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported" textline " " rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz" rbitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else bitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported" bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported" textline " " bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" bitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported" textline " " bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz" bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif sif (cpuis("DRA62*")) hgroup.long 0x248++0x3 hide.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register" else group.long 0x248++0x3 line.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register" hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V" hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V" textline " " hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V" endif wgroup.long 0x250++0x3 line.long 0x00 "SD_FE,Force Event Register for Error Interrupt Status" bitfld.long 0x00 29. " FE_BADA ,Force Event bad acces to data space interrupt" "No effect,Force" bitfld.long 0x00 28. " FE_CERR ,Force Event card error interrupt" "No effect,Force" textline " " bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error interrupt" "No effect,Force" bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error interrupt" "No effect,Force" textline " " bitfld.long 0x00 22. " FE_DEB ,Force Event Data end bit error interrupt" "No effect,Force" bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error interrupt" "No effect,Force" textline " " bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error interrupt" "No effect,Force" bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error interrupt" "No effect,Force" textline " " bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error interrupt" "No effect,Force" bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC error interrupt" "No effect,Force" textline " " bitfld.long 0x00 16. " FE_CTO ,Force Event Command timeout error interrupt" "No effect,Force" bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by AUTOCMD12 index error interrupt" "No effect,Force" textline " " bitfld.long 0x00 4. " FE_ACIE ,Force Event AutoCMD12 index error interrupt" "No effect,Force" bitfld.long 0x00 3. " FE_ACEB ,Force Event AutoCMD12 end bit error interrupt" "No effect,Force" textline " " bitfld.long 0x00 2. " FE_ACCE ,Force Event AutoCMD12 CRC error interrupt" "No effect,Force" bitfld.long 0x00 1. " FE_ACTO ,Force Event AutoCMD12 timeout error interrupt" "No effect,Force" textline " " bitfld.long 0x00 0. " FE_ACNE ,Force Event AutoCMD12 not executed interrupt" "No effect,Force" group.long 0x254++0x7 line.long 0x00 "SD_ADMAES,ADMA Error Status Register" bitfld.long 0x00 2. " LME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "Stop DMA,Stop DMA,Reserved,Transfer Data" line.long 0x04 "SD_ADMASAL,ADMA System Address Low Bits Register" sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") rgroup.long 0x25C++0x03 line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register" else group.long 0x25C++0x03 line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register" endif rgroup.long 0x2fc++0x3 line.long 0x00 "SD_REV,Versions Register" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number" bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Low,High" width 0xb tree.end tree "MMC1" base ad:0x481D8000 width 17. sif !(cpuis("AM335*")) rgroup.long 0x00++0x7 line.long 0x00 "SD_HL_REV,IP Revision Identifier Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" bitfld.long 0x00 11.--15. " R_RTL ,R_RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" line.long 0x04 "SD_HL_HWINFO,Hardware Configuration Register" sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x04 2.--5. " MEM_SIZE ,Memory Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 1. " MERGE_MEM ,Merge memory" "Low,High" textline " " else bitfld.long 0x04 1. " MEM_SIZE ,Memory Size" "Low,High" textline " " endif bitfld.long 0x04 0. " MADMA_EN ,MADMA Enable" "Disabled,Enabled" group.long 0x10++0x3 line.long 0x00 "SD_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x00 4.--5. " STANDBYMODE ,Standby mode" "Mode0,Mode1,Mode2,Mode3" bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode" "Mode0,Mode1,Mode2,Mode3" bitfld.long 0x00 1. " FREEEMU ,Free EMU" "Low,High" textline " " bitfld.long 0x00 0. " SOFTRESET ,Soft reset" "No reset,Reset" endif width 17. group.long 0x110++0x3 line.long 0x00 "SD_SYSCONFIG,System Configuration Register" bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power management standby/wait control (when MADMA is enabled)" "Force-standby,No standby,Smart-standby,Smart-standby wake-up-capable" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Inactive,Interface,Functional,Both" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle wake-up-capable" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up capability enable" "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Automatic" rgroup.long 0x114++0x3 line.long 0x00 "SD_SYSSTATUS,System Status Register" bitfld.long 0x00 0. " RESETDONE ,Reset status" "On-going,Done" group.long 0x124++0x7 line.long 0x00 "SD_CSRE,Card Status Response Error Register" width 17. line.long 0x04 "SD_SYSTEST,System Test Register" bitfld.long 0x04 16. " OBI ,Out of band interrupt data value input/output" "Low,High" bitfld.long 0x04 15. " SDCD ,Card detect input/output signal data value" "Low,High" bitfld.long 0x04 14. " SDWP ,Write protect input/output signal data value" "Low,High" textline " " bitfld.long 0x04 13. " WAKD ,Wake request input/output signal data value" "Low,High" bitfld.long 0x04 12. " SSB ,Set status bit" "Clear,Force" bitfld.long 0x04 11. " D7D ,DAT7 input/output signal data value" "Low,High" textline " " bitfld.long 0x04 10. " D6D ,DAT6 input/output signal data value" "Low,High" bitfld.long 0x04 9. " D5D ,DAT5 input/output signal data value" "Low,High" bitfld.long 0x04 8. " D4D ,DAT4 input/output signal data value" "Low,High" textline " " bitfld.long 0x04 7. " D3D ,DAT3 input/output signal data value" "Low,High" bitfld.long 0x04 6. " D2D ,DAT2 input/output signal data value" "Low,High" bitfld.long 0x04 5. " D1D ,DAT1 input/output signal data value" "Low,High" textline " " bitfld.long 0x04 4. " D0D ,DAT0 input/output signal data value" "Low,High" bitfld.long 0x04 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input" bitfld.long 0x04 2. " CDAT ,CMD input/output signal data value" "Low,High" textline " " bitfld.long 0x04 1. " CDIR ,Control of the CMD pin direction" "Output,Input" bitfld.long 0x04 0. " MCKD ,Clock input/output signal data value" "Low,High" width 17. group.long 0x12c++0x7 line.long 0x00 "SD_CON,Configuration Register" bitfld.long 0x00 21. " SDMA_LNE ,Select Slave DMA Level/Edge Request" "Edge,Level" bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection(when MADMA is enabled)" "Slave,?..." bitfld.long 0x00 19. " DDR ,Dual data rate transmission mode" "Single edge,Both" textline " " bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status supported" "Not forced,Forced" bitfld.long 0x00 17. " BOOT_ACK ,Boot acknowledge receive" "NO ACK,ACK" bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained" sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") textline " " bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced" bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA" endif textline " " bitfld.long 0x00 11. " CTPL ,Control Power for SD_DAT1 line" "Disabled,Enabled" bitfld.long 0x00 9.--10. " DVAL ,Debounce period for filter SDCD" "33 us,231 us,1 ms,8.4 ms" bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low" textline " " bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low" sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 6. " MIT ,MMC Interrupt Command" "Enabled,Disabled" textline " " bitfld.long 0x00 5. " DW8 ,8-bit mode select (MMC cars only)" "1-bit/4-bit,8-bit" endif bitfld.long 0x00 4. " MODE ,Mode select(all cards)" "Functional,SYSTEST" sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 3. " STR ,Stream command (MMC cars only)" "Block,Stream" textline " " bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cars only)" "Disabled,Enabled" bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent" else bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent" endif sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cars only)" "Disabled,Enabled" endif line.long 0x04 "SD_PWCNT,Power Counter Register" hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter" rgroup.long 0x200++0x3 line.long 0x00 "SD_SDMASA,SDMA System Address Register" if (((d.l(ad:0x481D8000+0x20c))&0x20)==0x20) group.long 0x204++0x3 line.long 0x00 "SD_BLK,Transfer Length Configuration Register" hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" else group.long 0x204++0x3 line.long 0x00 "SD_BLK,Transfer Length Configuration Register" hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size" endif group.long 0x208++0x7 line.long 0x00 "SD_ARG,Command Argument Register" line.long 0x04 "SD_CMD,Command and Transfer Mode Register" bitfld.long 0x04 24.--29. " INDEX ,Command number sent to card" "Cmd0 or acmd0,Cmd1 or acmd1,Cmd2 or acmd2,Cmd3 or acmd3,Cmd4 or acmd4,Cmd5 or acmd5,Cmd6 or acmd6,Cmd7 or acmd7,Cmd8 or acmd8,Cmd9 or acmd9,Cmd10 or acmd10,Cmd11 or acmd11,Cmd12 or acmd12,Cmd13 or acmd13,Cmd14 or acmd14,Cmd15 or acmd15,Cmd16 or acmd16,Cmd17 or acmd17,Cmd18 or acmd18,Cmd19 or acmd19,Cmd20 or acmd20,Cmd21 or acmd21,Cmd22 or acmd22,Cmd23 or acmd23,Cmd24 or acmd24,Cmd25 or acmd25,Cmd26 or acmd26,Cmd27 or acmd27,Cmd28 or acmd28,Cmd29 or acmd29,Cmd30 or acmd30,Cmd31 or acmd31,Cmd32 or acmd32,Cmd33 or acmd33,Cmd34 or acmd34,Cmd35 or acmd35,Cmd36 or acmd36,Cmd37 or acmd37,Cmd38 or acmd38,Cmd39 or acmd39,Cmd40 or acmd40,Cmd41 or acmd41,Cmd42 or acmd42,Cmd43 or acmd43,Cmd44 or acmd44,Cmd45 or acmd45,Cmd46 or acmd46,Cmd47 or acmd47,Cmd48 or acmd48,Cmd49 or acmd49,Cmd50 or acmd50,Cmd51 or acmd51,Cmd52 or acmd52,Cmd53 or acmd53,Cmd54 or acmd54,Cmd55 or acmd55,Cmd56 or acmd56,Cmd57 or acmd57,Cmd58 or acmd58,Cmd59 or acmd59,Cmd60 or acmd60,Cmd61 or acmd61,Cmd62 or acmd62,Cmd63 or acmd63" bitfld.long 0x04 22.--23. " CMD_TYPE ,Command type" "Other,Bus suspend,Function select,I/O Abort" bitfld.long 0x04 21. " DP ,Data present select" "No data,Present" textline " " bitfld.long 0x04 20. " CICE ,Command index check enable" "Disabled,Enabled" bitfld.long 0x04 19. " CCCE ,Command CRC check enable" "Disabled,Enabled" bitfld.long 0x04 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits (busy)" textline " " bitfld.long 0x04 5. " MSBS ,Multi/Single block select" "Single,Multi" bitfld.long 0x04 4. " DDIR ,Data transfer direction" "Write,Read" bitfld.long 0x04 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " BCE ,Block Count Enable (Multiple block transfers only)" "Disabled,Enabled" bitfld.long 0x04 0. " DE ,DMA Enable" "Disabled,Enabled" rgroup.long 0x210++0xf line.long 0x00 "SD_RSP10,Command Response 0 and 1 Register" hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response[31:16]" hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response[15:0]" line.long 0x04 "SD_RSP32,Command Response 2 and 3 Register" hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command Response[63:48]" hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command Response[47:32]" line.long 0x08 "SD_RSP54,Command Response 4 and 5 Register" hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command Response[95:80]" hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command Response[79:64]" line.long 0x0c "SD_RSP76,Command Response 6 and 7 Register" hexmask.long.word 0x0c 16.--31. 1. " RSP7 ,Command Response[127:112]" hexmask.long.word 0x0c 0.--15. 1. " RSP6 ,Command Response[111:96]" width 17. group.long 0x220++0x3 line.long 0x00 "SD_DATA,Data Register" if (((d.l(ad:0x481D8000+0x12c))&0x180)==0x180) rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CINS ,Detect card" "Detected,Not detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" elif (((d.l(ad:0x481D8000+0x12c))&0x180)==0x100) rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" elif (((d.l(ad:0x481D8000+0x12c))&0x180)==0x80) rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CI ,Detect card" "Detected,Not detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" else rgroup.long 0x224++0x3 line.long 0x00 "SD_PSTATE,Present State Register" bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1" bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1" bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1" textline " " bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1" bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1" bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected" textline " " bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0" bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable" bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected" textline " " bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled" bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going" textline " " bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going" bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active" bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed" textline " " bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed" endif group.long 0x228++0x13 line.long 0x00 "SD_HCTL,Host Control Register" bitfld.long 0x00 27. " OBWE ,Wake-up event enable for OBI" "Disabled,Enabled" bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled" bitfld.long 0x00 19. " IBG ,Interrupt block at gap (in 4-bit mode only)" "Disabled,Enabled" bitfld.long 0x00 18. " RWC ,Read wait control (SDIO cards)" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CR ,Transfer continue request" "No affect,Restart" bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stopped" bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V" textline " " bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On" bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SDCD,CDTL" bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected" textline " " bitfld.long 0x00 3.--4. " DMAS ,DMA Select" "Reserved,Reserved,32-bit ADMA2,?..." bitfld.long 0x00 2. " HSPE ,High speed enable" "Normal,High" bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit" line.long 0x04 "SD_SYSCTL,SD System Control Register" bitfld.long 0x04 26. " SRD ,Software reset for SD_DAT line" "No reset,Reset" bitfld.long 0x04 25. " SRC ,Software reset for SD_CMD line" "No reset,Reset" bitfld.long 0x04 24. " SRA ,Software reset for all" "No reset,Reset" textline " " bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCFx2^13,TCFx2^14,TCFx2^15,TCFx2^16,TCFx2^17,TCFx2^18,TCFx2^19,TCFx2^20,TCFx2^21,TCFx2^22,TCFx2^23,TCFx2^24,TCFx2^25,TCFx2^26,TCFx2^27,?..." hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select" bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable" else bitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable" endif bitfld.long 0x04 0. " ICE ,Internal clock enable" "Disabled,Enabled" line.long 0x08 "SD_STAT,Interrupt Status Register" eventfld.long 0x08 29. " BADA ,Bad access to data space interrupt" "No interrupt,Interrupt" eventfld.long 0x08 28. " CERR ,Card error" "No interrupt,Interrupt" eventfld.long 0x08 25. " ADMAE ,ADMA error" "No interrupt,Interrupt" textline " " eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No interrupt,Interrupt" eventfld.long 0x08 22. " DEB ,Data end bit error" "No interrupt,Interrupt" eventfld.long 0x08 21. " DCRC ,Data CRC error" "No interrupt,Interrupt" textline " " eventfld.long 0x08 20. " DTO ,Data timeout error" "No interrupt,Interrupt" eventfld.long 0x08 19. " CIE ,Command index error" "No interrupt,Interrupt" eventfld.long 0x08 18. " CEB ,Command end bit error" "No interrupt,Interrupt" textline " " eventfld.long 0x08 17. " CCRC ,Command CRC error" "No interrupt,Interrupt" eventfld.long 0x08 16. " CTO ,Command timeout error" "No interrupt,Interrupt" sif (cpuis("DRA62*")||cpuis("AM355*")) rbitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt" eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt" else bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt" eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt" bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt" endif textline " " eventfld.long 0x08 7. " CREM ,Card removal" "No interrupt,Interrupt" eventfld.long 0x08 6. " CINS ,Card insertion" "No interrupt,Interrupt" eventfld.long 0x08 5. " BRR ,Buffer read ready" "No interrupt,Interrupt" textline " " eventfld.long 0x08 4. " BWR ,Buffer write ready" "No interrupt,Interrupt" eventfld.long 0x08 3. " DMA ,DMA interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BGE ,Block gap event" "No interrupt,Interrupt" textline " " eventfld.long 0x08 1. " TC ,Transfer completed" "No interrupt,Interrupt" eventfld.long 0x08 0. " CC ,Command completed" "No interrupt,Interrupt" width 17. line.long 0x0c "SD_IE,Interrupt SD Enable Register" bitfld.long 0x0c 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled" bitfld.long 0x0c 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 25. " ADMA_ENABLE ,ADMA error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled" bitfld.long 0x0c 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x0c 15. " NULL ,Null" "0,1" else bitfld.long 0x0c 15. " NULL ,Null" "0,1" endif textline " " bitfld.long 0x0c 10. " BSR_ENABLE ,Boot status received interrupt enable" "Masked,Enabled" bitfld.long 0x0c 9. " OBI_ENABLE ,Out of band interrupt enable" "Masked,Enabled" bitfld.long 0x0c 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 7. " CREM_ENABLE ,Card removal interrupt enable" "Masked,Enabled" bitfld.long 0x0c 6. " CINS_ENABLE ,Card insertion interrupt enable" "Masked,Enabled" bitfld.long 0x0c 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled" bitfld.long 0x0c 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled" bitfld.long 0x0c 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled" textline " " bitfld.long 0x0c 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled" bitfld.long 0x0c 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled" line.long 0x10 "SD_ISE,Interrupt Signal Enable Register" bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Disabled,Enabled" bitfld.long 0x10 28. " CERR_SIGEN ,Card error signal status enable" "Disabled,Enabled" bitfld.long 0x10 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled" bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled" bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled" bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled" bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled" bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled" sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x10 15. " NULL ,Null" "0,1" else bitfld.long 0x10 15. " NULL ,Null" "0,1" endif textline " " bitfld.long 0x10 10. " BSR_SIGEN ,Boot status received signal status enable" "Disabled,Enabled" bitfld.long 0x10 9. " OBI_SIGEN ,Out of band signal status enable" "Disabled,Enabled" bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " CREM_SIGEN ,Card removal signal status enable" "Disabled,Enabled" bitfld.long 0x10 6. " CINS_SIGEN ,Card insertion signal status enable" "Disabled,Enabled" bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled" bitfld.long 0x10 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled" bitfld.long 0x10 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled" bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled" width 17. if ((((d.l(ad:(ad:0x481D8000+0x20c)))&0x4)==0x4)&&(((d.l(ad:(ad:0x481D8000+0x230)))&0x1000000)==0x1000000)) rgroup.long 0x23c++0x3 line.long 0x00 "SD_AC12,AutoCMD12 Error Status Register" bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error" textline " " bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error" textline " " bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed" else hgroup.long 0x23c++0x3 hide.long 0x00 "SD_AC12,AutoCMD12 Error Status Register" endif group.long 0x240++0x3 line.long 0x00 "SD_CAPA,Capabilities Register" bitfld.long 0x00 28. " 64BIT ,64 Bit System Bus Support" "32-bit,64-bit" bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported" textline " " bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported" bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V" "Not supported,Supported" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")) rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported" rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported" textline " " rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" rbitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported" textline " " rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz" rbitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else bitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported" bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported" textline " " bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" bitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported" textline " " bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..." bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz" bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif sif (cpuis("DRA62*")) hgroup.long 0x248++0x3 hide.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register" else group.long 0x248++0x3 line.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register" hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V" hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V" textline " " hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V" endif wgroup.long 0x250++0x3 line.long 0x00 "SD_FE,Force Event Register for Error Interrupt Status" bitfld.long 0x00 29. " FE_BADA ,Force Event bad acces to data space interrupt" "No effect,Force" bitfld.long 0x00 28. " FE_CERR ,Force Event card error interrupt" "No effect,Force" textline " " bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error interrupt" "No effect,Force" bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error interrupt" "No effect,Force" textline " " bitfld.long 0x00 22. " FE_DEB ,Force Event Data end bit error interrupt" "No effect,Force" bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error interrupt" "No effect,Force" textline " " bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error interrupt" "No effect,Force" bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error interrupt" "No effect,Force" textline " " bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error interrupt" "No effect,Force" bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC error interrupt" "No effect,Force" textline " " bitfld.long 0x00 16. " FE_CTO ,Force Event Command timeout error interrupt" "No effect,Force" bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by AUTOCMD12 index error interrupt" "No effect,Force" textline " " bitfld.long 0x00 4. " FE_ACIE ,Force Event AutoCMD12 index error interrupt" "No effect,Force" bitfld.long 0x00 3. " FE_ACEB ,Force Event AutoCMD12 end bit error interrupt" "No effect,Force" textline " " bitfld.long 0x00 2. " FE_ACCE ,Force Event AutoCMD12 CRC error interrupt" "No effect,Force" bitfld.long 0x00 1. " FE_ACTO ,Force Event AutoCMD12 timeout error interrupt" "No effect,Force" textline " " bitfld.long 0x00 0. " FE_ACNE ,Force Event AutoCMD12 not executed interrupt" "No effect,Force" group.long 0x254++0x7 line.long 0x00 "SD_ADMAES,ADMA Error Status Register" bitfld.long 0x00 2. " LME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "Stop DMA,Stop DMA,Reserved,Transfer Data" line.long 0x04 "SD_ADMASAL,ADMA System Address Low Bits Register" sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143") rgroup.long 0x25C++0x03 line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register" else group.long 0x25C++0x03 line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register" endif rgroup.long 0x2fc++0x3 line.long 0x00 "SD_REV,Versions Register" hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number" hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number" bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Low,High" width 0xb tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" tree "UART 0" base ad:0x44E09000 width 15. if (((d.w((ad:0x44E09000+0x0c)))&0x80)==0x00) hgroup.word 0x00++0x01 hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register" in else group.word 0x00++0x01 line.word 0x00 "DLL,Divisor Latch LSB Value Register" hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value" endif if ((((d.w((ad:0x44E09000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==(0x0||0x2||0x3))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled" bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled" bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled" textline " " bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled" bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled" elif ((((d.w((ad:0x44E09000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x44E09000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==0x6)) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x44E09000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==0x7)) hgroup.word 0x04++0x01 hide.word 0x00 "IER,Interrupt Enable Register" else group.word 0x04++0x01 line.word 0x00 "DLH,Divisor Latch MSB Value Register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value" endif if ((((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..." textline " " bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active" textline " " bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==0x6)) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==0x7)) hgroup.word 0x08++0x01 hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register" else group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced Feature Register" bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled" bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled" bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" endif group.word 0x0C++0x01 line.word 0x00 "LCR,Line Control Register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced" bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0" textline " " bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled" bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits" if (((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf) group.word 0x10++0x01 line.word 0x00 "MCR,Modem Control Register" bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled" bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled" bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low" textline " " bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low" bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low" textline " " bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low" else group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)" endif if ((((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error" bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty" textline " " bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty" bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break" textline " " bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error" bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error" textline " " bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error" bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full" textline " " bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received" bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error" textline " " bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==0x6)) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed" textline " " bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==0x7)) hgroup.word 0x14++0x01 hide.word 0x00 "LSR,Line Status Register" else group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)" endif if ((((d.w((ad:0x44E09000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x44E09000+0x10)))&0x40)==0x0)) hgroup.word 0x18++0x01 hide.word 0x00 "MSR,Modem Status Register" in group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad Register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" elif ((((d.w((ad:0x44E09000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x44E09000+0x10)))&0x40)==0x0)) group.word 0x18++0x01 line.word 0x00 "XOFF1,XOFF1 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)" group.word 0x1c++0x01 line.word 0x00 "XOFF2,XOFF2 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)" else group.word 0x18++0x01 line.word 0x00 "TCR,Transmission Control Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.word 0x1C++0x01 line.word 0x00 "TLR,Trigger Level Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" endif if (((d.w((ad:0x44E09000+0x20)))&0x7)==(0x4||0x5)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x44E09000+0x20)))&0x7)==0x1) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x44E09000+0x20)))&0x7)==0x6) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles" elif (((d.w((ad:0x44E09000+0x20)))&0x7)==(0x0||0x2||0x3)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse" else group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode Definition Register 2" endif rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,Status FIFO Line Status Register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs" rgroup.word 0x2c++0x01 line.word 0x00 "RESUME,Resume register" hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2c++0x01 line.word 0x00 "TXFLH,Transmit Frame Length High Register" hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,Status FIFO Register Low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO Register High" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,Received Frame Length High Register" bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((d.w((ad:0x44E09000+0x0c)))&0x80)==0x00) group.word 0x38++0x01 line.word 0x00 "BLR,BOF Control Register" bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0" else rgroup.word 0x38++0x01 line.word 0x00 "UASR,UART Autobauding Status Register" bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd" bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit" textline " " bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..." endif if (((d.w((ad:0x44E09000+0x0c)))&0x80)==0x00) group.word 0x3c++0x01 line.word 0x00 "ACREG,Auxiliary Control Register" bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us" bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low" textline " " bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes" bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes" textline " " bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent" bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled" bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred" else hgroup.word 0x3c++0x01 hide.word 0x00 "ACREG,Auxiliary Control Register" endif width 15. group.word 0x40++0x01 line.word 0x00 "SCR,Supplementary Control Register" bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled" bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled" bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3" textline " " bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]" group.word 0x44++0x01 line.word 0x00 "SSR,Supplementary Status Register" bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset" bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred" textline " " bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full" width 15. if ((((d.w((ad:0x44E09000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags" elif ((((d.w((ad:0x44E09000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x44E09000+0x20)))&0x7)==0x6)) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt" else hgroup.word 0x48++0x01 hide.word 0x00 "EBLR,BOF Length Register" endif rgroup.word 0x50++0x01 line.word 0x00 "MVR,Module Version Register" hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number" hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number" group.word 0x54++0x01 line.word 0x00 "SYSC,System Configuration Register" bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied" rgroup.word 0x58++0x01 line.word 0x00 "SYSS,System Status Register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed" group.word 0x5c++0x01 line.word 0x00 "WER,Wake-Up Enable Register" bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed" bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed" if (((d.w((ad:0x44E09000+0x20)))&0x7)==0x6) group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier Frequency Prescaler" hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler" else hgroup.word 0x60++0x01 hide.word 0x00 "CFPS,Carrier Frequency Prescaler" endif sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) group.word 0x80++0x01 line.word 0x00 "MDR3,Mode Definition Register 3" bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different" bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable" endif sif (cpuis("AM335*")) width 18. group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh." hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" endif width 0xb tree.end tree "UART 1" base ad:0x48022000 width 15. if (((d.w((ad:0x48022000+0x0c)))&0x80)==0x00) hgroup.word 0x00++0x01 hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register" in else group.word 0x00++0x01 line.word 0x00 "DLL,Divisor Latch LSB Value Register" hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value" endif if ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled" bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled" bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled" textline " " bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled" bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled" elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6)) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x7)) hgroup.word 0x04++0x01 hide.word 0x00 "IER,Interrupt Enable Register" else group.word 0x04++0x01 line.word 0x00 "DLH,Divisor Latch MSB Value Register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value" endif if ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..." textline " " bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active" textline " " bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6)) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x7)) hgroup.word 0x08++0x01 hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register" else group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced Feature Register" bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled" bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled" bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" endif group.word 0x0C++0x01 line.word 0x00 "LCR,Line Control Register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced" bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0" textline " " bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled" bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits" if (((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf) group.word 0x10++0x01 line.word 0x00 "MCR,Modem Control Register" bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled" bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled" bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low" textline " " bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low" bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low" textline " " bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low" else group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)" endif if ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error" bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty" textline " " bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty" bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break" textline " " bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error" bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error" textline " " bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error" bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full" textline " " bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received" bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error" textline " " bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6)) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed" textline " " bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x7)) hgroup.word 0x14++0x01 hide.word 0x00 "LSR,Line Status Register" else group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)" endif if ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x10)))&0x40)==0x0)) hgroup.word 0x18++0x01 hide.word 0x00 "MSR,Modem Status Register" in group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad Register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" elif ((((d.w((ad:0x48022000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48022000+0x10)))&0x40)==0x0)) group.word 0x18++0x01 line.word 0x00 "XOFF1,XOFF1 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)" group.word 0x1c++0x01 line.word 0x00 "XOFF2,XOFF2 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)" else group.word 0x18++0x01 line.word 0x00 "TCR,Transmission Control Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.word 0x1C++0x01 line.word 0x00 "TLR,Trigger Level Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" endif if (((d.w((ad:0x48022000+0x20)))&0x7)==(0x4||0x5)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x48022000+0x20)))&0x7)==0x1) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x48022000+0x20)))&0x7)==0x6) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles" elif (((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse" else group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode Definition Register 2" endif rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,Status FIFO Line Status Register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs" rgroup.word 0x2c++0x01 line.word 0x00 "RESUME,Resume register" hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2c++0x01 line.word 0x00 "TXFLH,Transmit Frame Length High Register" hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,Status FIFO Register Low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO Register High" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,Received Frame Length High Register" bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((d.w((ad:0x48022000+0x0c)))&0x80)==0x00) group.word 0x38++0x01 line.word 0x00 "BLR,BOF Control Register" bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0" else rgroup.word 0x38++0x01 line.word 0x00 "UASR,UART Autobauding Status Register" bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd" bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit" textline " " bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..." endif if (((d.w((ad:0x48022000+0x0c)))&0x80)==0x00) group.word 0x3c++0x01 line.word 0x00 "ACREG,Auxiliary Control Register" bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us" bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low" textline " " bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes" bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes" textline " " bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent" bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled" bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred" else hgroup.word 0x3c++0x01 hide.word 0x00 "ACREG,Auxiliary Control Register" endif width 15. group.word 0x40++0x01 line.word 0x00 "SCR,Supplementary Control Register" bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled" bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled" bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3" textline " " bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]" group.word 0x44++0x01 line.word 0x00 "SSR,Supplementary Status Register" bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset" bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred" textline " " bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full" width 15. if ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags" elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6)) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt" else hgroup.word 0x48++0x01 hide.word 0x00 "EBLR,BOF Length Register" endif rgroup.word 0x50++0x01 line.word 0x00 "MVR,Module Version Register" hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number" hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number" group.word 0x54++0x01 line.word 0x00 "SYSC,System Configuration Register" bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied" rgroup.word 0x58++0x01 line.word 0x00 "SYSS,System Status Register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed" group.word 0x5c++0x01 line.word 0x00 "WER,Wake-Up Enable Register" bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed" bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed" if (((d.w((ad:0x48022000+0x20)))&0x7)==0x6) group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier Frequency Prescaler" hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler" else hgroup.word 0x60++0x01 hide.word 0x00 "CFPS,Carrier Frequency Prescaler" endif sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) group.word 0x80++0x01 line.word 0x00 "MDR3,Mode Definition Register 3" bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different" bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable" endif sif (cpuis("AM335*")) width 18. group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh." hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" endif width 0xb tree.end tree "UART 2" base ad:0x48024000 width 15. if (((d.w((ad:0x48024000+0x0c)))&0x80)==0x00) hgroup.word 0x00++0x01 hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register" in else group.word 0x00++0x01 line.word 0x00 "DLL,Divisor Latch LSB Value Register" hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value" endif if ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled" bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled" bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled" textline " " bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled" bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled" elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6)) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x7)) hgroup.word 0x04++0x01 hide.word 0x00 "IER,Interrupt Enable Register" else group.word 0x04++0x01 line.word 0x00 "DLH,Divisor Latch MSB Value Register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value" endif if ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..." textline " " bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active" textline " " bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6)) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x7)) hgroup.word 0x08++0x01 hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register" else group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced Feature Register" bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled" bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled" bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" endif group.word 0x0C++0x01 line.word 0x00 "LCR,Line Control Register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced" bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0" textline " " bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled" bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits" if (((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf) group.word 0x10++0x01 line.word 0x00 "MCR,Modem Control Register" bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled" bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled" bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low" textline " " bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low" bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low" textline " " bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low" else group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)" endif if ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error" bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty" textline " " bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty" bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break" textline " " bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error" bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error" textline " " bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error" bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full" textline " " bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received" bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error" textline " " bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6)) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed" textline " " bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x7)) hgroup.word 0x14++0x01 hide.word 0x00 "LSR,Line Status Register" else group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)" endif if ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x10)))&0x40)==0x0)) hgroup.word 0x18++0x01 hide.word 0x00 "MSR,Modem Status Register" in group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad Register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" elif ((((d.w((ad:0x48024000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48024000+0x10)))&0x40)==0x0)) group.word 0x18++0x01 line.word 0x00 "XOFF1,XOFF1 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)" group.word 0x1c++0x01 line.word 0x00 "XOFF2,XOFF2 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)" else group.word 0x18++0x01 line.word 0x00 "TCR,Transmission Control Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.word 0x1C++0x01 line.word 0x00 "TLR,Trigger Level Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" endif if (((d.w((ad:0x48024000+0x20)))&0x7)==(0x4||0x5)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x48024000+0x20)))&0x7)==0x1) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x48024000+0x20)))&0x7)==0x6) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles" elif (((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse" else group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode Definition Register 2" endif rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,Status FIFO Line Status Register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs" rgroup.word 0x2c++0x01 line.word 0x00 "RESUME,Resume register" hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2c++0x01 line.word 0x00 "TXFLH,Transmit Frame Length High Register" hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,Status FIFO Register Low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO Register High" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,Received Frame Length High Register" bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((d.w((ad:0x48024000+0x0c)))&0x80)==0x00) group.word 0x38++0x01 line.word 0x00 "BLR,BOF Control Register" bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0" else rgroup.word 0x38++0x01 line.word 0x00 "UASR,UART Autobauding Status Register" bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd" bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit" textline " " bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..." endif if (((d.w((ad:0x48024000+0x0c)))&0x80)==0x00) group.word 0x3c++0x01 line.word 0x00 "ACREG,Auxiliary Control Register" bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us" bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low" textline " " bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes" bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes" textline " " bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent" bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled" bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred" else hgroup.word 0x3c++0x01 hide.word 0x00 "ACREG,Auxiliary Control Register" endif width 15. group.word 0x40++0x01 line.word 0x00 "SCR,Supplementary Control Register" bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled" bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled" bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3" textline " " bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]" group.word 0x44++0x01 line.word 0x00 "SSR,Supplementary Status Register" bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset" bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred" textline " " bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full" width 15. if ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags" elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6)) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt" else hgroup.word 0x48++0x01 hide.word 0x00 "EBLR,BOF Length Register" endif rgroup.word 0x50++0x01 line.word 0x00 "MVR,Module Version Register" hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number" hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number" group.word 0x54++0x01 line.word 0x00 "SYSC,System Configuration Register" bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied" rgroup.word 0x58++0x01 line.word 0x00 "SYSS,System Status Register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed" group.word 0x5c++0x01 line.word 0x00 "WER,Wake-Up Enable Register" bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed" bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed" if (((d.w((ad:0x48024000+0x20)))&0x7)==0x6) group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier Frequency Prescaler" hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler" else hgroup.word 0x60++0x01 hide.word 0x00 "CFPS,Carrier Frequency Prescaler" endif sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) group.word 0x80++0x01 line.word 0x00 "MDR3,Mode Definition Register 3" bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different" bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable" endif sif (cpuis("AM335*")) width 18. group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh." hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" endif width 0xb tree.end tree "UART 3" base ad:0x481A6000 width 15. if (((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00) hgroup.word 0x00++0x01 hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register" in else group.word 0x00++0x01 line.word 0x00 "DLL,Divisor Latch LSB Value Register" hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value" endif if ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x0||0x2||0x3))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled" bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled" bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled" textline " " bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled" bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled" elif ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x6)) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x7)) hgroup.word 0x04++0x01 hide.word 0x00 "IER,Interrupt Enable Register" else group.word 0x04++0x01 line.word 0x00 "DLH,Divisor Latch MSB Value Register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value" endif if ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..." textline " " bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active" textline " " bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x6)) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x7)) hgroup.word 0x08++0x01 hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register" else group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced Feature Register" bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled" bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled" bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" endif group.word 0x0C++0x01 line.word 0x00 "LCR,Line Control Register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced" bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0" textline " " bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled" bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits" if (((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf) group.word 0x10++0x01 line.word 0x00 "MCR,Modem Control Register" bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled" bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled" bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low" textline " " bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low" bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low" textline " " bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low" else group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)" endif if ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error" bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty" textline " " bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty" bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break" textline " " bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error" bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error" textline " " bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error" bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full" textline " " bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received" bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error" textline " " bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x6)) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed" textline " " bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x7)) hgroup.word 0x14++0x01 hide.word 0x00 "LSR,Line Status Register" else group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)" endif if ((((d.w((ad:0x481A6000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A6000+0x10)))&0x40)==0x0)) hgroup.word 0x18++0x01 hide.word 0x00 "MSR,Modem Status Register" in group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad Register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" elif ((((d.w((ad:0x481A6000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x481A6000+0x10)))&0x40)==0x0)) group.word 0x18++0x01 line.word 0x00 "XOFF1,XOFF1 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)" group.word 0x1c++0x01 line.word 0x00 "XOFF2,XOFF2 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)" else group.word 0x18++0x01 line.word 0x00 "TCR,Transmission Control Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.word 0x1C++0x01 line.word 0x00 "TLR,Trigger Level Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" endif if (((d.w((ad:0x481A6000+0x20)))&0x7)==(0x4||0x5)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x481A6000+0x20)))&0x7)==0x1) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x481A6000+0x20)))&0x7)==0x6) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles" elif (((d.w((ad:0x481A6000+0x20)))&0x7)==(0x0||0x2||0x3)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse" else group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode Definition Register 2" endif rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,Status FIFO Line Status Register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs" rgroup.word 0x2c++0x01 line.word 0x00 "RESUME,Resume register" hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2c++0x01 line.word 0x00 "TXFLH,Transmit Frame Length High Register" hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,Status FIFO Register Low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO Register High" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,Received Frame Length High Register" bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00) group.word 0x38++0x01 line.word 0x00 "BLR,BOF Control Register" bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0" else rgroup.word 0x38++0x01 line.word 0x00 "UASR,UART Autobauding Status Register" bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd" bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit" textline " " bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..." endif if (((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00) group.word 0x3c++0x01 line.word 0x00 "ACREG,Auxiliary Control Register" bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us" bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low" textline " " bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes" bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes" textline " " bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent" bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled" bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred" else hgroup.word 0x3c++0x01 hide.word 0x00 "ACREG,Auxiliary Control Register" endif width 15. group.word 0x40++0x01 line.word 0x00 "SCR,Supplementary Control Register" bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled" bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled" bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3" textline " " bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]" group.word 0x44++0x01 line.word 0x00 "SSR,Supplementary Status Register" bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset" bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred" textline " " bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full" width 15. if ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags" elif ((((d.w((ad:0x481A6000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A6000+0x20)))&0x7)==0x6)) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt" else hgroup.word 0x48++0x01 hide.word 0x00 "EBLR,BOF Length Register" endif rgroup.word 0x50++0x01 line.word 0x00 "MVR,Module Version Register" hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number" hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number" group.word 0x54++0x01 line.word 0x00 "SYSC,System Configuration Register" bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied" rgroup.word 0x58++0x01 line.word 0x00 "SYSS,System Status Register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed" group.word 0x5c++0x01 line.word 0x00 "WER,Wake-Up Enable Register" bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed" bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed" if (((d.w((ad:0x481A6000+0x20)))&0x7)==0x6) group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier Frequency Prescaler" hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler" else hgroup.word 0x60++0x01 hide.word 0x00 "CFPS,Carrier Frequency Prescaler" endif sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) group.word 0x80++0x01 line.word 0x00 "MDR3,Mode Definition Register 3" bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different" bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable" endif sif (cpuis("AM335*")) width 18. group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh." hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" endif width 0xb tree.end tree "UART 4" base ad:0x481A8000 width 15. if (((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00) hgroup.word 0x00++0x01 hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register" in else group.word 0x00++0x01 line.word 0x00 "DLL,Divisor Latch LSB Value Register" hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value" endif if ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x0||0x2||0x3))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled" bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled" bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled" textline " " bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled" bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled" elif ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x6)) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x7)) hgroup.word 0x04++0x01 hide.word 0x00 "IER,Interrupt Enable Register" else group.word 0x04++0x01 line.word 0x00 "DLH,Divisor Latch MSB Value Register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value" endif if ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..." textline " " bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active" textline " " bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x6)) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x7)) hgroup.word 0x08++0x01 hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register" else group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced Feature Register" bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled" bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled" bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" endif group.word 0x0C++0x01 line.word 0x00 "LCR,Line Control Register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced" bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0" textline " " bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled" bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits" if (((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf) group.word 0x10++0x01 line.word 0x00 "MCR,Modem Control Register" bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled" bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled" bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low" textline " " bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low" bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low" textline " " bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low" else group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)" endif if ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error" bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty" textline " " bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty" bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break" textline " " bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error" bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error" textline " " bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error" bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full" textline " " bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received" bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error" textline " " bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x6)) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed" textline " " bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x7)) hgroup.word 0x14++0x01 hide.word 0x00 "LSR,Line Status Register" else group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)" endif if ((((d.w((ad:0x481A8000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481A8000+0x10)))&0x40)==0x0)) hgroup.word 0x18++0x01 hide.word 0x00 "MSR,Modem Status Register" in group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad Register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" elif ((((d.w((ad:0x481A8000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x481A8000+0x10)))&0x40)==0x0)) group.word 0x18++0x01 line.word 0x00 "XOFF1,XOFF1 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)" group.word 0x1c++0x01 line.word 0x00 "XOFF2,XOFF2 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)" else group.word 0x18++0x01 line.word 0x00 "TCR,Transmission Control Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.word 0x1C++0x01 line.word 0x00 "TLR,Trigger Level Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" endif if (((d.w((ad:0x481A8000+0x20)))&0x7)==(0x4||0x5)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x481A8000+0x20)))&0x7)==0x1) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x481A8000+0x20)))&0x7)==0x6) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles" elif (((d.w((ad:0x481A8000+0x20)))&0x7)==(0x0||0x2||0x3)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse" else group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode Definition Register 2" endif rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,Status FIFO Line Status Register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs" rgroup.word 0x2c++0x01 line.word 0x00 "RESUME,Resume register" hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2c++0x01 line.word 0x00 "TXFLH,Transmit Frame Length High Register" hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,Status FIFO Register Low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO Register High" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,Received Frame Length High Register" bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00) group.word 0x38++0x01 line.word 0x00 "BLR,BOF Control Register" bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0" else rgroup.word 0x38++0x01 line.word 0x00 "UASR,UART Autobauding Status Register" bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd" bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit" textline " " bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..." endif if (((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00) group.word 0x3c++0x01 line.word 0x00 "ACREG,Auxiliary Control Register" bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us" bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low" textline " " bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes" bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes" textline " " bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent" bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled" bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred" else hgroup.word 0x3c++0x01 hide.word 0x00 "ACREG,Auxiliary Control Register" endif width 15. group.word 0x40++0x01 line.word 0x00 "SCR,Supplementary Control Register" bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled" bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled" bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3" textline " " bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]" group.word 0x44++0x01 line.word 0x00 "SSR,Supplementary Status Register" bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset" bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred" textline " " bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full" width 15. if ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags" elif ((((d.w((ad:0x481A8000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481A8000+0x20)))&0x7)==0x6)) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt" else hgroup.word 0x48++0x01 hide.word 0x00 "EBLR,BOF Length Register" endif rgroup.word 0x50++0x01 line.word 0x00 "MVR,Module Version Register" hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number" hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number" group.word 0x54++0x01 line.word 0x00 "SYSC,System Configuration Register" bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied" rgroup.word 0x58++0x01 line.word 0x00 "SYSS,System Status Register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed" group.word 0x5c++0x01 line.word 0x00 "WER,Wake-Up Enable Register" bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed" bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed" if (((d.w((ad:0x481A8000+0x20)))&0x7)==0x6) group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier Frequency Prescaler" hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler" else hgroup.word 0x60++0x01 hide.word 0x00 "CFPS,Carrier Frequency Prescaler" endif sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) group.word 0x80++0x01 line.word 0x00 "MDR3,Mode Definition Register 3" bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different" bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable" endif sif (cpuis("AM335*")) width 18. group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh." hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" endif width 0xb tree.end tree "UART 5" base ad:0x481AA000 width 15. if (((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00) hgroup.word 0x00++0x01 hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register" in else group.word 0x00++0x01 line.word 0x00 "DLL,Divisor Latch LSB Value Register" hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value" endif if ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x0||0x2||0x3))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled" bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled" bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled" textline " " bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled" bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled" textline " " bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled" bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled" elif ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x6)) group.word 0x04++0x01 line.word 0x00 "IER,Interrupt Enable Register" bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled" elif ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x7)) hgroup.word 0x04++0x01 hide.word 0x00 "IER,Interrupt Enable Register" else group.word 0x04++0x01 line.word 0x00 "DLH,Divisor Latch MSB Value Register" hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value" endif if ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3" bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..." textline " " bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active" bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active" textline " " bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active" textline " " bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active" textline " " bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active" bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x6)) rgroup.word 0x08++0x01 line.word 0x00 "IIR,Interrupt Identification Register" bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active" bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active" textline " " bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active" bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active" textline " " bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active" wgroup.word 0x08++0x01 line.word 0x00 "FCR,FIFO Control Register" bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters" bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces" textline " " bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1" bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear" textline " " bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear" bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled" elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x7)) hgroup.word 0x08++0x01 hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register" else group.word 0x08++0x01 line.word 0x00 "EFR,Enhanced Feature Register" bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled" bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled" bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled" textline " " bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2" endif group.word 0x0C++0x01 line.word 0x00 "LCR,Line Control Register" bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled" bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced" bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0" textline " " bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled" bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2" textline " " bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits" if (((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf) group.word 0x10++0x01 line.word 0x00 "MCR,Modem Control Register" bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled" bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled" bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low" textline " " bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low" bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low" textline " " bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low" else group.word 0x10++0x01 line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)" endif if ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x0||0x2||0x3))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error" bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty" textline " " bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty" bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break" textline " " bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error" bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error" textline " " bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error" bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x1||0x4||0x5))) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full" textline " " bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received" bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error" textline " " bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort" bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error" textline " " bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty" bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x6)) rgroup.word 0x14++0x01 line.word 0x00 "LSR,Line Status Register" bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty" bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed" textline " " bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty" elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x7)) hgroup.word 0x14++0x01 hide.word 0x00 "LSR,Line Status Register" else group.word 0x14++0x01 line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register" hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)" endif if ((((d.w((ad:0x481AA000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x481AA000+0x10)))&0x40)==0x0)) hgroup.word 0x18++0x01 hide.word 0x00 "MSR,Modem Status Register" in group.word 0x1C++0x01 line.word 0x00 "SPR,Scratchpad Register" hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register" elif ((((d.w((ad:0x481AA000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x481AA000+0x10)))&0x40)==0x0)) group.word 0x18++0x01 line.word 0x00 "XOFF1,XOFF1 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)" group.word 0x1c++0x01 line.word 0x00 "XOFF2,XOFF2 Register" hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)" else group.word 0x18++0x01 line.word 0x00 "TCR,Transmission Control Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" group.word 0x1C++0x01 line.word 0x00 "TLR,Trigger Level Register" bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60" endif if (((d.w((ad:0x481AA000+0x20)))&0x7)==(0x4||0x5)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x481AA000+0x20)))&0x7)==0x1) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT" textline " " bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries" bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt" elif (((d.w((ad:0x481AA000+0x20)))&0x7)==0x6) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High" textline " " bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate" bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion" textline " " bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles" elif (((d.w((ad:0x481AA000+0x20)))&0x7)==(0x0||0x2||0x3)) group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" group.word 0x24++0x01 line.word 0x00 "MDR2,Mode Definition Register 2" bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse" else group.word 0x20++0x01 line.word 0x00 "MDR1,Mode Definition Register 1" bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled" hgroup.word 0x24++0x01 hide.word 0x00 "MDR2,Mode Definition Register 2" endif rgroup.word 0x28++0x01 line.word 0x00 "SFLSR,Status FIFO Line Status Register" bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error" bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error" textline " " bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected" bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error" wgroup.word 0x28++0x01 line.word 0x00 "TXFLL,Transmit Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs" rgroup.word 0x2c++0x01 line.word 0x00 "RESUME,Resume register" hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" wgroup.word 0x2c++0x01 line.word 0x00 "TXFLH,Transmit Frame Length High Register" hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs" rgroup.word 0x30++0x01 line.word 0x00 "SFREGL,Status FIFO Register Low" hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length" wgroup.word 0x30++0x01 line.word 0x00 "RXFLL,Received Frame Length Low Register" hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception" rgroup.word 0x34++0x01 line.word 0x00 "SFREGH,Status FIFO Register High" bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" wgroup.word 0x34++0x01 line.word 0x00 "RXFLH,Received Frame Length High Register" bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00) group.word 0x38++0x01 line.word 0x00 "BLR,BOF Control Register" bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset" bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0" else rgroup.word 0x38++0x01 line.word 0x00 "UASR,UART Autobauding Status Register" bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd" bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit" textline " " bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..." endif if (((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00) group.word 0x3c++0x01 line.word 0x00 "ACREG,Auxiliary Control Register" bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us" bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low" textline " " bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes" bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes" textline " " bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent" bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled" bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred" else hgroup.word 0x3c++0x01 hide.word 0x00 "ACREG,Auxiliary Control Register" endif width 15. group.word 0x40++0x01 line.word 0x00 "SCR,Supplementary Control Register" bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled" bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled" bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled" bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3" textline " " bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]" group.word 0x44++0x01 line.word 0x00 "SSR,Supplementary Status Register" bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset" bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred" textline " " bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full" width 15. if ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==(0x1||0x4||0x5))) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags" elif ((((d.w((ad:0x481AA000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x481AA000+0x20)))&0x7)==0x6)) group.word 0x48++0x01 line.word 0x00 "EBLR,BOF Length Register" hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt" else hgroup.word 0x48++0x01 hide.word 0x00 "EBLR,BOF Length Register" endif rgroup.word 0x50++0x01 line.word 0x00 "MVR,Module Version Register" hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number" hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number" group.word 0x54++0x01 line.word 0x00 "SYSC,System Configuration Register" bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup" bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset" bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied" rgroup.word 0x58++0x01 line.word 0x00 "SYSS,System Status Register" bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed" group.word 0x5c++0x01 line.word 0x00 "WER,Wake-Up Enable Register" bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed" bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed" textline " " bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed" bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed" if (((d.w((ad:0x481AA000+0x20)))&0x7)==0x6) group.word 0x60++0x01 line.word 0x00 "CFPS,Carrier Frequency Prescaler" hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler" else hgroup.word 0x60++0x01 hide.word 0x00 "CFPS,Carrier Frequency Prescaler" endif sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) group.word 0x80++0x01 line.word 0x00 "MDR3,Mode Definition Register 3" bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different" bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault" bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable" endif sif (cpuis("AM335*")) width 18. group.word 0x84++0x01 line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh." hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" endif width 0xb tree.end tree.end tree "Timers" tree "DMTimer 0-7" tree "DMTimer 0" base ad:0x44E05000 width 15. group.long 0x00++0x03 line.long 0x00 "TIDR,Identification Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x20++0x03 line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect" endif group.long 0x24++0x03 line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register" eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt" eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register" eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled" eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled" textline " " eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled" group.long 0x34++0x03 line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "TCLR,Timer Control Register" bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event" textline " " bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..." textline " " bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both" bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative" textline " " bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload" textline " " bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started" group.long 0x3C++0x03 line.long 0x00 "TCRR,Timer Counter Register" group.long 0x40++0x03 line.long 0x00 "TLDR,Timer Load Register" rgroup.long 0x44++0x03 line.long 0x00 "TTGR,Timer Trigger Register" group.long 0x48++0x03 line.long 0x00 "TWPS,Timer Write Posted Status Register" bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending" bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending" textline " " bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending" bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending" textline " " bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending" group.long 0x4C++0x03 line.long 0x00 "TMAR,Timer Match Register" group.long 0x50++0x03 line.long 0x00 "TCAR1,Timer Capture Register 1" group.long 0x54++0x03 line.long 0x00 "TSICR,Timer Synchronous Interface Control Register " bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active" textline " " bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset" group.long 0x58++0x03 line.long 0x00 "TCAR2,Timer Capture Register 2" width 0xb tree.end tree "DMTimer 2" base ad:0x48040000 width 15. group.long 0x00++0x03 line.long 0x00 "TIDR,Identification Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x20++0x03 line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect" endif group.long 0x24++0x03 line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register" eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt" eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register" eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled" eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled" textline " " eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled" group.long 0x34++0x03 line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "TCLR,Timer Control Register" bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event" textline " " bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..." textline " " bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both" bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative" textline " " bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload" textline " " bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started" group.long 0x3C++0x03 line.long 0x00 "TCRR,Timer Counter Register" group.long 0x40++0x03 line.long 0x00 "TLDR,Timer Load Register" rgroup.long 0x44++0x03 line.long 0x00 "TTGR,Timer Trigger Register" group.long 0x48++0x03 line.long 0x00 "TWPS,Timer Write Posted Status Register" bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending" bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending" textline " " bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending" bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending" textline " " bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending" group.long 0x4C++0x03 line.long 0x00 "TMAR,Timer Match Register" group.long 0x50++0x03 line.long 0x00 "TCAR1,Timer Capture Register 1" group.long 0x54++0x03 line.long 0x00 "TSICR,Timer Synchronous Interface Control Register " bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active" textline " " bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset" group.long 0x58++0x03 line.long 0x00 "TCAR2,Timer Capture Register 2" width 0xb tree.end tree "DMTimer 3" base ad:0x48042000 width 15. group.long 0x00++0x03 line.long 0x00 "TIDR,Identification Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x20++0x03 line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect" endif group.long 0x24++0x03 line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register" eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt" eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register" eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled" eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled" textline " " eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled" group.long 0x34++0x03 line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "TCLR,Timer Control Register" bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event" textline " " bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..." textline " " bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both" bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative" textline " " bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload" textline " " bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started" group.long 0x3C++0x03 line.long 0x00 "TCRR,Timer Counter Register" group.long 0x40++0x03 line.long 0x00 "TLDR,Timer Load Register" rgroup.long 0x44++0x03 line.long 0x00 "TTGR,Timer Trigger Register" group.long 0x48++0x03 line.long 0x00 "TWPS,Timer Write Posted Status Register" bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending" bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending" textline " " bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending" bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending" textline " " bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending" group.long 0x4C++0x03 line.long 0x00 "TMAR,Timer Match Register" group.long 0x50++0x03 line.long 0x00 "TCAR1,Timer Capture Register 1" group.long 0x54++0x03 line.long 0x00 "TSICR,Timer Synchronous Interface Control Register " bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active" textline " " bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset" group.long 0x58++0x03 line.long 0x00 "TCAR2,Timer Capture Register 2" width 0xb tree.end tree "DMTimer 4" base ad:0x48044000 width 15. group.long 0x00++0x03 line.long 0x00 "TIDR,Identification Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x20++0x03 line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect" endif group.long 0x24++0x03 line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register" eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt" eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register" eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled" eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled" textline " " eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled" group.long 0x34++0x03 line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "TCLR,Timer Control Register" bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event" textline " " bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..." textline " " bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both" bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative" textline " " bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload" textline " " bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started" group.long 0x3C++0x03 line.long 0x00 "TCRR,Timer Counter Register" group.long 0x40++0x03 line.long 0x00 "TLDR,Timer Load Register" rgroup.long 0x44++0x03 line.long 0x00 "TTGR,Timer Trigger Register" group.long 0x48++0x03 line.long 0x00 "TWPS,Timer Write Posted Status Register" bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending" bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending" textline " " bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending" bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending" textline " " bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending" group.long 0x4C++0x03 line.long 0x00 "TMAR,Timer Match Register" group.long 0x50++0x03 line.long 0x00 "TCAR1,Timer Capture Register 1" group.long 0x54++0x03 line.long 0x00 "TSICR,Timer Synchronous Interface Control Register " bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active" textline " " bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset" group.long 0x58++0x03 line.long 0x00 "TCAR2,Timer Capture Register 2" width 0xb tree.end tree "DMTimer 5" base ad:0x48046000 width 15. group.long 0x00++0x03 line.long 0x00 "TIDR,Identification Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x20++0x03 line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect" endif group.long 0x24++0x03 line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register" eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt" eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register" eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled" eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled" textline " " eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled" group.long 0x34++0x03 line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "TCLR,Timer Control Register" bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event" textline " " bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..." textline " " bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both" bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative" textline " " bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload" textline " " bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started" group.long 0x3C++0x03 line.long 0x00 "TCRR,Timer Counter Register" group.long 0x40++0x03 line.long 0x00 "TLDR,Timer Load Register" rgroup.long 0x44++0x03 line.long 0x00 "TTGR,Timer Trigger Register" group.long 0x48++0x03 line.long 0x00 "TWPS,Timer Write Posted Status Register" bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending" bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending" textline " " bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending" bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending" textline " " bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending" group.long 0x4C++0x03 line.long 0x00 "TMAR,Timer Match Register" group.long 0x50++0x03 line.long 0x00 "TCAR1,Timer Capture Register 1" group.long 0x54++0x03 line.long 0x00 "TSICR,Timer Synchronous Interface Control Register " bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active" textline " " bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset" group.long 0x58++0x03 line.long 0x00 "TCAR2,Timer Capture Register 2" width 0xb tree.end tree "DMTimer 6" base ad:0x48048000 width 15. group.long 0x00++0x03 line.long 0x00 "TIDR,Identification Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x20++0x03 line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect" endif group.long 0x24++0x03 line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register" eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt" eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register" eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled" eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled" textline " " eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled" group.long 0x34++0x03 line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "TCLR,Timer Control Register" bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event" textline " " bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..." textline " " bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both" bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative" textline " " bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload" textline " " bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started" group.long 0x3C++0x03 line.long 0x00 "TCRR,Timer Counter Register" group.long 0x40++0x03 line.long 0x00 "TLDR,Timer Load Register" rgroup.long 0x44++0x03 line.long 0x00 "TTGR,Timer Trigger Register" group.long 0x48++0x03 line.long 0x00 "TWPS,Timer Write Posted Status Register" bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending" bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending" textline " " bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending" bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending" textline " " bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending" group.long 0x4C++0x03 line.long 0x00 "TMAR,Timer Match Register" group.long 0x50++0x03 line.long 0x00 "TCAR1,Timer Capture Register 1" group.long 0x54++0x03 line.long 0x00 "TSICR,Timer Synchronous Interface Control Register " bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active" textline " " bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset" group.long 0x58++0x03 line.long 0x00 "TCAR2,Timer Capture Register 2" width 0xb tree.end tree "DMTimer 7" base ad:0x4804A000 width 15. group.long 0x00++0x03 line.long 0x00 "TIDR,Identification Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function" textline " " bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register" bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running" textline " " bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x20++0x03 line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect" endif group.long 0x24++0x03 line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register" bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt" bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register" eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt" eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register" bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register" eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled" eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled" textline " " eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled" group.long 0x34++0x03 line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register" bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled" bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "TCLR,Timer Control Register" bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1" bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event" textline " " bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle" bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..." textline " " bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both" bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative" textline " " bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled" bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload" textline " " bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started" group.long 0x3C++0x03 line.long 0x00 "TCRR,Timer Counter Register" group.long 0x40++0x03 line.long 0x00 "TLDR,Timer Load Register" rgroup.long 0x44++0x03 line.long 0x00 "TTGR,Timer Trigger Register" group.long 0x48++0x03 line.long 0x00 "TWPS,Timer Write Posted Status Register" bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending" bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending" textline " " bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending" bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending" textline " " bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending" group.long 0x4C++0x03 line.long 0x00 "TMAR,Timer Match Register" group.long 0x50++0x03 line.long 0x00 "TCAR1,Timer Capture Register 1" group.long 0x54++0x03 line.long 0x00 "TSICR,Timer Synchronous Interface Control Register " bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active" textline " " bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset" group.long 0x58++0x03 line.long 0x00 "TCAR2,Timer Capture Register 2" width 0xb tree.end tree.end tree "DMTimer 1ms" base ad:0x44E31000 width 11. rgroup.long 0x00++0x03 line.long 0x00 "TIDR,Timer Identification Register" hexmask.long.byte 0x00 0.--7. 1. " TID_REV ,Module HW revision number" group.long 0x10++0x03 line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Functional clock/OCP clock" "Off/Off,Off/On,On/Off,On/On" bitfld.long 0x00 5. " EMUFREE ,Timer mode" "timer_frozen,timer_free" bitfld.long 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "IDLE,No IDLE,Smart IDLE,?..." textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled" bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal mode,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Interface clocks gating strategy" "Clkfree,Clkgate" rgroup.long 0x14++0x03 line.long 0x00 "TISTAT,Timer System Status Register" bitfld.long 0x00 0. " RESETDONE ,Internal global reset monitoring" "Not done,Done" group.long 0x0018++0x1b line.long 0x00 "TISR,Timer Status Register" bitfld.long 0x00 2. " TCAR_IT_FLAG ,Capture interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " OVF_IT_FLAG ,Overflow interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare interrupt" "No interrupt,Interrupt" line.long 0x04 "TIER,Timer Interrupt Enable Register" bitfld.long 0x04 2. " TCAR_IT_ENA ,Capture interrupt enable" "Disabled,Enabled" bitfld.long 0x04 1. " OVF_IT_ENA ,Overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " MAT_IT_ENA ,Match interrupt enable" "Disabled,Enabled" line.long 0x08 "TWER,Timer Wake-Up Enable Register" bitfld.long 0x08 2. " TCAR_WUP_ENA ,Capture interrupt wake-up generation enable" "Disabled,Enabled" bitfld.long 0x08 1. " OVF_WUP_ENA ,Overflow interrupt wake-up generation enable" "Disabled,Enabled" bitfld.long 0x08 0. " MAT_WUP_ENA ,Match interrupt wake-up generation enable" "Disabled,Enabled" line.long 0x0C "TCLR,Timer Control Register" bitfld.long 0x0C 14. " GPO_CFG ,GPO configuration" "Drives 0,Drives 1" bitfld.long 0x0C 13. " CAPT_MODE ,Capture mode" "First,Second" bitfld.long 0x0C 12. " PT ,Pulse or toggle mode on timer PWM output pin" "Pulse,Toggle" bitfld.long 0x0C 10.--11. " TRG ,Trigger output mode on timer PWM output pin" "Disabled,OV,OV/match,?..." textline " " bitfld.long 0x0C 8.--9. " TCM ,Transition capture mode on event capture input pin" "Not captured,Rising edge,Falling edge,Both edge" bitfld.long 0x0C 7. " SCPWM ,Control timer PWM output pin and pulse mode" "Set/Negative,Cleared/Positive" bitfld.long 0x0C 6. " CE ,Enable compare mode" "Disabled,Enabled" bitfld.long 0x0C 5. " PRE ,Prescaler enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 2.--4. " PTV ,Prescale clock Divider timer value" "2,4,8,16,32,64,128,256" bitfld.long 0x0C 1. " AR ,Autoreload timer" "One-shot,Autoreload" bitfld.long 0x0C 0. " ST ,Start timer" "Stopped,Started" line.long 0x10 "TCRR,Timer Counter Register" line.long 0x14 "TLDR,Timer Load Register" line.long 0x18 "TTGR,Timer Trigger Register" rgroup.long 0x34++0x2b line.long 0x00 "TWPS,Timer Write Pending Status Register" bitfld.long 0x00 9. " W_PEND_TOWR ,Write pending to TOWR" "Not pending,Pending" bitfld.long 0x00 8. " W_PEND_TOCR ,Write pending to TOCR" "Not pending,Pending" bitfld.long 0x00 7. " W_PEND_TCVR ,Write pending to TCVR" "Not pending,Pending" bitfld.long 0x00 6. " W_PEND_TNIR ,Write pending to TNIR" "Not pending,Pending" textline " " bitfld.long 0x00 5. " W_PEND_TPIR ,Write pending to TPIR" "Not pending,Pending" bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending to TMAR" "Not pending,Pending" bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending to TTGR" "Not pending,Pending" bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending to TLDR" "Not pending,Pending" textline " " bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending to TCRR" "Not pending,Pending" bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending to TCLR" "Not pending,Pending" line.long 0x04 "TMAR,The value of the match register" line.long 0x08 "TCAR1,The value of first captured counter register" line.long 0x0c "TSICR,Timer Synchronization Interface Control Register" bitfld.long 0x0c 2. " POSTED ,Posted mode" "Inactive,Active" bitfld.long 0x0c 1. " SFT ,Enable software reset" "Disabled,Enabled" line.long 0x10 "TCAR2,The value of second captured counter register" line.long 0x14 "TPIR,The value of the positive increment" line.long 0x18 "TNIR,The value of the negative increment" line.long 0x1c "TCVR,The value of CVR counter" line.long 0x20 "TOCR,The number of overflow events" hexmask.long.tbyte 0x20 0.--23. 1. " OVF_COUNTER_VALUE ,The number of overflow events" line.long 0x24 "TOWR,The number of masked interrupts" hexmask.long.tbyte 0x24 0.--23. 1. " OVF_WRAPPING_VALUE ,The number of masked interrupts" width 0xb tree.end tree "Real Time Clock (RTC)" base ad:0x44E3E000 width 20. if (((d.l(ad:(ad:0x44E3E000+0x00)))&0x70)<0x60) group.long 0x00++0x03 line.long 0x00 "SECONDS_REG,RTC Seconds Register" bitfld.long 0x00 4.--6. " SEC ,2nd digit of seconds" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of seconds" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." else group.long 0x00++0x03 line.long 0x00 "SECONDS_REG,RTC Seconds Register" bitfld.long 0x00 4.--6. " SEC ,2nd digit of seconds" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of seconds" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif if (((d.l(ad:(ad:0x44E3E000+0x04)))&0x70)<0x60) group.long 0x04++0x03 line.long 0x00 "MINUTES_REG,RTC Minutes Register" bitfld.long 0x00 4.--6. " MIN ,2nd digit of minutes" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." else group.long 0x04++0x03 line.long 0x00 "MINUTES_REG,RTC Minutes Register" bitfld.long 0x00 4.--6. " MIN ,2nd digit of minutes" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of minutes" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif if ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x8)&&(((d.l(ad:(ad:0x44E3E000+0x08)))&0x30)<0x10)) group.long 0x08++0x03 line.long 0x00 "HOURS_REG,RTC Hours Register" bitfld.long 0x00 7. " PM_/AM ,Only in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,-,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x8)&&(((d.l(ad:(ad:0x44E3E000+0x08)))&0x30)>0x0F)) group.long 0x08++0x03 line.long 0x00 "HOURS_REG,RTC Hours Register" bitfld.long 0x00 7. " PM_/AM ,Only in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,-,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x8)&&(((d.l(ad:(ad:0x44E3E000+0x08)))&0x30)>0x12)) group.long 0x08++0x03 line.long 0x00 "HOURS_REG,RTC Hours Register" bitfld.long 0x00 7. " PM_/AM ,Only in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,-,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x0)&&(((d.l(ad:(ad:0x44E3E000+0x08)))&0x30)<0x20)) group.long 0x08++0x03 line.long 0x00 "HOURS_REG,RTC Hours Register" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x0)&&(((d.l(ad:(ad:0x44E3E000+0x08)))&0x30)>0x1F)&&(((d.l(ad:(ad:0x44E3E000+0x08)))&0x30)<0x24)) group.long 0x08++0x03 line.long 0x00 "HOURS_REG,RTC Hours Register" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x0)&&(((d.l(ad:(ad:0x44E3E000+0x08)))&0x30)==0x30)) group.long 0x08++0x03 line.long 0x00 "HOURS_REG,RTC Hours Register" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif ; jan,mar,may,jun,jul,oct,dec if ((((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x1&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x3&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x5&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x7&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x8&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x10&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x12&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)) group.long 0x0C++0x03 line.long 0x00 "DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. ",1st digit of days" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..." ;others elif (((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x02&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)<0x2a) group.long 0x0C++0x03 line.long 0x00 "DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of days" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif (((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x02&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)>0x2a) group.long 0x0C++0x03 line.long 0x00 "DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "-,?..." bitfld.long 0x00 0.--3. ",1st digit of days" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x4&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x6&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x9&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x10)))&0x1F)==0x11&&((d.l(ad:(ad:0x44E3E000+0xC)))&0x30)==0x30)) group.long 0x0C++0x03 line.long 0x00 "DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. ",1st digit of days" "0,-,-,-,-,-,-,-,-,-,-,-,-,?..." else group.long 0x0C++0x03 line.long 0x00 "DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. ",1st digit of days" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." endif if (((d.l(ad:(ad:0x44E3E000+0x10)))&0x10)==0x10) group.long 0x10++0x03 line.long 0x00 "MONTHS_REG,RTC Months Register" bitfld.long 0x00 4. " MONTH ,2nd digit of months" "0,1" bitfld.long 0x00 0.--3. ",1st digit of months" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..." else group.long 0x10++0x03 line.long 0x00 "MONTHS_REG,RTC Months Register" bitfld.long 0x00 4. " MONTH ,2nd digit of months" "0,1" bitfld.long 0x00 0.--3. ",1st digit of months" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." endif group.long 0x14++0x03 line.long 0x00 "YEARS_REG,RTC Years Register" bitfld.long 0x00 4.--7. " YEAR ,2nd digit of years" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x00 0.--3. ",1st digit of years" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." group.long 0x18++0x03 line.long 0x00 "WEEKS_REG,RTC Weeks Register" bitfld.long 0x00 0.--2. " WEEK ,Day of week" "Sunday,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,-" if (((d.l(ad:(ad:0x44E3E000+0x20)))&0x70)<0x60) group.long 0x20++0x03 line.long 0x00 "ALARM_SECONDS_REG,RTC Alarm Seconds Register" bitfld.long 0x00 4.--6. " ALARM_SEC1 ,2nd digit of seconds" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of seconds" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." else group.long 0x20++0x03 line.long 0x00 "ALARM_SECONDS_REG,RTC Alarm Seconds Register" bitfld.long 0x00 4.--6. " ALARM_SEC1 ,2nd digit of seconds" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of seconds" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif if (((d.l(ad:(ad:0x44E3E000+0x24)))&0x70)<0x60) group.long 0x24++0x03 line.long 0x00 "ALARM_MINUTES_REG,RTC Alarm Minutes Register" bitfld.long 0x00 4.--6. " ALARM_MIN1 ,2nd digit of minutes" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." else group.long 0x24++0x03 line.long 0x00 "ALARM_MINUTES_REG,RTC Alarm Minutes Register" bitfld.long 0x00 4.--6. " ALARM_MIN1 ,2nd digit of minutes" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." endif if ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x8)&&(((d.l(ad:(ad:0x44E3E000+0x28)))&0x30)<0x10)) group.long 0x08++0x03 line.long 0x00 "ALARM_HOURS_REG,RTC Hours Register" bitfld.long 0x00 7. " PM_/AM ,Only in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,-,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x8)&&(((d.l(ad:(ad:0x44E3E000+0x28)))&0x30)>0x0F)) group.long 0x08++0x03 line.long 0x00 "ALARM_HOURS_REG,RTC Hours Register" bitfld.long 0x00 7. " PM_/AM ,Only in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,-,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x8)&&(((d.l(ad:(ad:0x44E3E000+0x28)))&0x30)>0x12)) group.long 0x08++0x03 line.long 0x00 "ALARM_HOURS_REG,RTC Hours Register" bitfld.long 0x00 7. " PM_/AM ,Only in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,-,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x0)&&(((d.l(ad:(ad:0x44E3E000+0x28)))&0x30)<0x20)) group.long 0x08++0x03 line.long 0x00 "ALARM_HOURS_REG,RTC Hours Register" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x0)&&(((d.l(ad:(ad:0x44E3E000+0x28)))&0x30)>0x1F)&&(((d.l(ad:(ad:0x44E3E000+0x28)))&0x30)<0x24)) group.long 0x08++0x03 line.long 0x00 "ALARM_HOURS_REG,RTC Hours Register" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x0)&&(((d.l(ad:(ad:0x44E3E000+0x28)))&0x30)==0x30)) group.long 0x08++0x03 line.long 0x00 "ALARM_HOURS_REG,RTC Hours Register" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif if ((((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x1&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x3&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x5&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x7&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x8&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x10&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x12&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)) group.long 0x2C++0x03 line.long 0x00 "ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. ",1st digit of days" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..." ;others elif (((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x02&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)<0x2a) group.long 0x2C++0x03 line.long 0x00 "ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of days" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif (((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x02&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)>0x2a) group.long 0x2C++0x03 line.long 0x00 "ALARM_ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "-,?..." bitfld.long 0x00 0.--3. ",1st digit of days" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x4&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x6&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x9&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x30)))&0x1F)==0x11&&((d.l(ad:(ad:0x44E3E000+0x2c)))&0x30)==0x30)) group.long 0x2C++0x03 line.long 0x00 "ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. ",1st digit of days" "0,-,-,-,-,-,-,-,-,-,-,-,-,?..." else group.long 0x2C++0x03 line.long 0x00 "ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. ",1st digit of days" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." endif if (((d.l(ad:(ad:0x44E3E000+0x30)))&0x10)==0x10) group.long 0x30++0x3 line.long 0x00 "ALARM_MONTHS_REG,RTC Alarm Months Register" bitfld.long 0x00 4. " ALARM_MONTH1 ,2nd digit of months" "0,1" bitfld.long 0x00 0.--3. ",1st digit of months" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..." else group.long 0x30++0x3 line.long 0x00 "ALARM_MONTHS_REG,RTC Alarm Months Register" bitfld.long 0x00 4. " ALARM_MONTH1 ,2nd digit of months" "0,1" bitfld.long 0x00 0.--3. ",1st digit of months" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." endif group.long 0x34++0x3 line.long 0x00 "ALARM_YEARS_REG,RTC Alarm Years Register" bitfld.long 0x00 4.--7. " ALARM_YEAR1 ,2nd digit of years" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x00 0.--3. ",1st digit of years" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." group.long 0x40++0x17 line.long 0x00 "RTC_CTRL_REG,RTC Control Register" bitfld.long 0x00 6. " RTC_DISABLE ,Disable RTC" "No,Yes" bitfld.long 0x00 5. " SET_32_COUNTER ,Set the 32-kHz counter with COMP_REG value" "No action,Set" bitfld.long 0x00 4. " TEST_MODE ,Test mode" "Functional,Test" bitfld.long 0x00 3. " MODE_12_24 ,12 or 24 hour mode" "24-hour,12-hour (PM/AM)" textline " " bitfld.long 0x00 2. " AUTO_COMP ,Enable autocompensation" "Disabled,Enabled" bitfld.long 0x00 1. " ROUND_30S ,Round the time to the closest minute" "Not round,Round" bitfld.long 0x00 0. " STOP_RTC ,RTC is frozen/running" "Frozen,Running" line.long 0x04 "STATUS_REG,RTC Status Register" bitfld.long 0x04 7. " ALARM2 ,An alarm 2 interrupt has been generated" "Not generated,Generated" bitfld.long 0x04 6. " ALARM ,An alarm interrupt has been generated" "Not generated,Generated" textline " " bitfld.long 0x04 5. " 1D_EVENT ,One day has occurred" "Not occurred,Occurred" bitfld.long 0x04 4. " 1H_EVENT ,One hour has occurred" "Not occurred,Occurred" textline " " bitfld.long 0x04 3. " 1M_EVENT ,One minute has occurred" "Not occurred,Occurred" bitfld.long 0x04 2. " 1S_EVENT ,One second has occurred" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " RUN ,RTC is frozen/running" "Frozen,Running" bitfld.long 0x04 0. " BUSY ,Updating event in more than 15us" ">15us,Now" line.long 0x08 "INTERRUPTS_REG,RTC Interrupts Register" bitfld.long 0x08 3. " IT_ALARM2 ,Enable one interrupt when the alarm 2 value is reached" "Disabled,Enabled" bitfld.long 0x08 3. " IT_ALARM ,Enable one interrupt when the alarm value is reached" "Disabled,Enabled" bitfld.long 0x08 2. " IT_TIMER ,Enable periodic interrupt" "Disabled,Enabled" textline " " bitfld.long 0x08 0.--1. " EVERY ,Interrupt period" "Second,Minute,Hour,Day" line.long 0x0c "COMP_LSB_REG,RTC Compensation LSB Register" hexmask.long.byte 0x0c 0.--7. 1. " RTC_COMP_LSB ,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour (signed value)" line.long 0x10 "COMP_MSB_REG,RTC Compensation LSB Register" hexmask.long.byte 0x10 0.--7. 1. " RTC_COMP_MSB ,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour (signed value)" line.long 0x14 "OSC_REG,RTC Oscillator Register" bitfld.long 0x14 6. " 32KCLK_EN ,32-kHz clock enable post clock mux" "Enabled,Disabled" bitfld.long 0x14 4. " OSC32K_GZ ,Disable the oscillator and apply high impedance to the output" "No,Yes" bitfld.long 0x14 3. " 32KCLK_SEL ,32-kHz clock source select" "Internal,External" bitfld.long 0x14 2. " RES_SELECT ,External feedback resistor" "Internal,External" textline " " bitfld.long 0x14 1. " SW2 ,Inverter size adjustment 2" "0,1" bitfld.long 0x14 0. " SW1 ,Inverter size adjustment 1" "0,1" group.long 0x60++0x23 line.long 0x00 "SCRATCH0_REG,Scratch 0 Register" line.long 0x04 "SCRATCH1_REG,Scratch 1 Register" line.long 0x08 "SCRATCH2_REG,Scratch 2 Register" line.long 0x0c "KICK0,Kick 0 Register" line.long 0x10 "KICK1,Kick 1 Register" line.long 0x14 "RTC_REVISION,RTC Revision Register" bitfld.long 0x14 30.--31. " SCHEME ,Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x14 16.--27. 1. " FUNC ,Functional Number" bitfld.long 0x14 11.--15. " R_RTL ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--10. " MAJOR ,Major revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x14 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" hexmask.long.byte 0x14 0.--5. 1. " MINOR ,Minor revision" line.long 0x18 "RTCYSCONFIG,RTC System Configuration Register" bitfld.long 0x18 0.--1. " IDLEMODE ,Select IDLE mode" "Force Idle,No Idle Mode,Smart-Idle,Smart Idle with Wakeup" line.long 0x1c "RTC_IRQWAKEEN,Wakeup Enable Register" bitfld.long 0x1c 1. " ALARM_WAKEEN ,Wakeup generation for event Alarm" "Disabled,Enabled" bitfld.long 0x1c 0. " ALARM_TIMER ,Wakeup generation for event Timer" "Disabled,Enabled" if (((d.l(ad:(ad:0x44E3E000+0x80)))&0x70)<0x60) group.long 0x80++0x03 line.long 0x00 "ALARM2_SECONDS_REG,RTC Alarm Seconds Register" bitfld.long 0x00 4.--6. " ALARM2_SEC1 ,2nd digit of seconds" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of seconds" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." else group.long 0x80++0x03 line.long 0x00 "ALARM2_SECONDS_REG,RTC Alarm Seconds Register" bitfld.long 0x00 4.--6. " ALARM2_SEC1 ,2nd digit of seconds" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of seconds" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif if (((d.l(ad:(ad:0x44E3E000+0x84)))&0x70)<0x60) group.long 0x84++0x03 line.long 0x00 "ALARM2_MINUTES_REG,RTC Alarm Minutes Register" bitfld.long 0x00 4.--6. " ALARM2_MIN1 ,2nd digit of minutes" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." else group.long 0x84++0x03 line.long 0x00 "ALARM2_MINUTES_REG,RTC Alarm Minutes Register" bitfld.long 0x00 4.--6. " ALARM2_MIN1 ,2nd digit of minutes" "0,1,2,3,4,5,-,-" bitfld.long 0x00 0.--3. ",1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." endif if ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x8)&&(((d.l(ad:(ad:0x44E3E000+0x88)))&0x30)<0x10)) group.long 0x88++0x03 line.long 0x00 "ALARM2_HOURS_REG,RTC Hours Register" bitfld.long 0x00 7. " PM_/AM ,Only in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,-,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x8)&&(((d.l(ad:(ad:0x44E3E000+0x88)))&0x30)>0x0F)) group.long 0x88++0x03 line.long 0x00 "ALARM2_HOURS_REG,RTC Hours Register" bitfld.long 0x00 7. " PM_/AM ,Only in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,-,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x8)&&(((d.l(ad:(ad:0x44E3E000+0x88)))&0x30)>0x12)) group.long 0x88++0x03 line.long 0x00 "ALARM2_HOURS_REG,RTC Hours Register" bitfld.long 0x00 7. " PM_/AM ,Only in PM_AM mode" "AM,PM" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,-,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x0)&&(((d.l(ad:(ad:0x44E3E000+0x88)))&0x30)<0x20)) group.long 0x88++0x03 line.long 0x00 "ALARM2_HOURS_REG,RTC Hours Register" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x0)&&(((d.l(ad:(ad:0x44E3E000+0x88)))&0x30)>0x1F)&&(((d.l(ad:(ad:0x44E3E000+0x88)))&0x30)<0x24)) group.long 0x88++0x03 line.long 0x00 "ALARM2_HOURS_REG,RTC Hours Register" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x40)))&0x8)==0x0)&&(((d.l(ad:(ad:0x44E3E000+0x88)))&0x30)==0x30)) group.long 0x88++0x03 line.long 0x00 "ALARM2_HOURS_REG,RTC Hours Register" bitfld.long 0x00 4.--5. " HOUR ,2nd digit of hours" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif if ((((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x1&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x3&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x5&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x7&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x8&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x10&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x12&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)) group.long 0x8C++0x03 line.long 0x00 "ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. ",1st digit of days" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..." ;others elif (((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x02&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)<0x2a) group.long 0x8C++0x03 line.long 0x00 "ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,-" bitfld.long 0x00 0.--3. ",1st digit of days" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif (((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x02&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)>0x2a) group.long 0x8C++0x03 line.long 0x00 "ALARM_ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "-,?..." bitfld.long 0x00 0.--3. ",1st digit of days" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x4&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x6&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x9&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)||(((d.l(ad:(ad:0x44E3E000+0x90)))&0x1F)==0x11&&((d.l(ad:(ad:0x44E3E000+0x8c)))&0x30)==0x30)) group.long 0x8C++0x03 line.long 0x00 "ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. ",1st digit of days" "0,-,-,-,-,-,-,-,-,-,-,-,-,?..." else group.long 0x8C++0x03 line.long 0x00 "ALARM_DAYS_REG,RTC Days Register" bitfld.long 0x00 4.--5. " DAY ,2nd digit of days" "0,1,2,3" bitfld.long 0x00 0.--3. ",1st digit of days" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." endif if (((d.l(ad:(ad:0x44E3E000+0x90)))&0x10)==0x10) group.long 0x90++0x3 line.long 0x00 "ALARM2_MONTHS_REG,RTC Alarm Months Register" bitfld.long 0x00 4. " ALARM2_MONTH1 ,2nd digit of months" "0,1" bitfld.long 0x00 0.--3. ",1st digit of months" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..." else group.long 0x90++0x3 line.long 0x00 "ALARM2_MONTHS_REG,RTC Alarm Months Register" bitfld.long 0x00 4. " ALARM2_MONTH1 ,2nd digit of months" "0,1" bitfld.long 0x00 0.--3. ",1st digit of months" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." endif group.long 0x94++0x3 line.long 0x00 "ALARM2_YEARS_REG,RTC Alarm 2 Years Register" bitfld.long 0x00 4.--7. " ALARM2_YEAR1 ,2nd digit of years" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.long 0x00 0.--3. ",1st digit of years" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." group.long 0x98++0x7 line.long 0x00 "RTC_PMIC,RTC PMIC Register" bitfld.long 0x00 17.--18. " PWR_ENABLE_SM ,Power state machine state" "Idle/Default,Shutdown,Time-based wakeup,External-event-based wakeup" bitfld.long 0x00 16. " PWR_ENABLE_EN ,Pwr_enable enable" "Disabled,Enabled" eventfld.long 0x00 15. " EXT_WAKEUP_3 ,External wakeup 3 status" "Not occurred,Occurred" eventfld.long 0x00 14. " EXT_WAKEUP_2 ,External wakeup 2 status" "Not occurred,Occurred" textline " " eventfld.long 0x00 13. " EXT_WAKEUP_1 ,External wakeup 1 status" "Not occurred,Occurred" eventfld.long 0x00 12. " EXT_WAKEUP_0 ,External wakeup 0 status" "Not occurred,Occurred" bitfld.long 0x00 11. " EXT_WAKEUP_DB_EN3 ,External wakeup debounce enabled" "Disabled,Enabled" bitfld.long 0x00 10. " EXT_WAKEUP_DB_EN2 ,External wakeup debounce enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EXT_WAKEUP_DB_EN1 ,External wakeup debounce enabled" "Disabled,Enabled" bitfld.long 0x00 8. " EXT_WAKEUP_DB_EN0 ,External wakeup debounce enabled" "Disabled,Enabled" bitfld.long 0x00 7. " EXT_WAKEUP_POL3 ,External wakeup inputs polarity" "Active high,Active low" bitfld.long 0x00 6. " EXT_WAKEUP_POL2 ,External wakeup inputs polarity" "Active high,Active low" textline " " bitfld.long 0x00 5. " EXT_WAKEUP_POL1 ,External wakeup inputs polarity" "Active high,Active low" bitfld.long 0x00 4. " EXT_WAKEUP_POL0 ,External wakeup inputs polarity" "Active high,Active low" bitfld.long 0x00 3. " EXT_WAKEUP_EN3 ,Enable external wakeup inputs" "Disabled,Enabled" bitfld.long 0x00 2. " EXT_WAKEUP_EN2 ,Enable external wakeup inputs" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " EXT_WAKEUP_EN1 ,Enable external wakeup inputs" "Disabled,Enabled" bitfld.long 0x00 0. " EXT_WAKEUP_EN0 ,Enable external wakeup inputs" "Disabled,Enabled" line.long 0x04 "RTC_DEBOUNCE,RTC Debounce Register" hexmask.long.byte 0x04 0.--7. 1. " DEBOUNCE_REG ,Debounce time" width 0xb tree.end tree "WATCHDOG" base ad:0x44E35000 width 17. rgroup.long 0x0++0x3 line.long 0x00 "WDT_WIDR,IP revision identifier" group.long 0x10++0x3 line.long 0x00 "WDT_WDSC,OCP interface parameters" bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running" textline " " sif (cpuis("AM335*")) bitfld.long 0x00 3.--4. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable" textline " " endif bitfld.long 0x00 1. " SOFTRESET ,Software reset (Optional)" "Reset,No reset" rgroup.long 0x14++0x3 line.long 0x00 "WDT_WDST,Status information" bitfld.long 0x00 0. " RESETDONE ,Internal module reset monitoring" "Ongoing,Completed" group.long 0x18++0x7 line.long 0x00 "WDT_WISR,Interrupt events pending" eventfld.long 0x00 1. " DLY_IT_FLAG ,Pending delay interrupt status" "Not pending,Pending" eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending" line.long 0x04 "WDT_WIER,Interrupt events control" bitfld.long 0x04 1. " DLY_IT_ENA ,Delay interrupt enable/disable" "Disabled,Enabled" bitfld.long 0x04 0. " OVF_IT_ENA ,Overflow interrupt enable/disable" "Disabled,Enabled" sif (cpuis("DRA62*")) group.long 0x20++0x3 line.long 0x00 "WDT_WWER,Wake-up events control" bitfld.long 0x00 1. " DLY_WK_ENA ,Delay wake-up enable/disable" "Disabled,Enabled" bitfld.long 0x00 0. " OVF_WK_ENA ,Overflow wake-up enable/disable" "Disabled,Enabled" endif group.long 0x24++0x3 line.long 0x00 "WDT_WCLR,Counter prescaler control" bitfld.long 0x00 5. " PRE ,Prescaler enable/disable configuration" "Disabled,Enabled" bitfld.long 0x00 2.--4. " PTV ,Prescaler value" "0,1,2,3,4,5,6,7" group.long 0x28++0xB line.long 0x00 "WDT_WCRR,Internal counter value" line.long 0x04 "WDT_WLDR,Timer load value" line.long 0x08 "WDT_WTGR,Watchdog counter reload" rgroup.long 0x34++0x3 line.long 0x00 "WDT_WWPS,Write posting bits" bitfld.long 0x00 5. " W_PEND_WDLY ,Write pending for register WDLY" "Not pending,Pending" bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "Not pending,Pending" bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "Not pending,Pending" textline " " bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "Not pending,Pending" bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "Not pending,Pending" bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "Not pending,Pending" group.long 0x44++0x7 line.long 0x00 "WDT_WDLY,Event detection delay value" line.long 0x04 "WDT_WSPR,Start-stop value" group.long 0x54++0xF line.long 0x00 "WDT_WIRQSTATRAW,IRQ unmasked status" bitfld.long 0x00 1. " EVENT_DLY ,Settable raw status for delay event" "Not pending,Pending" bitfld.long 0x00 0. " EVENT_OVF ,Settable raw status for overflow event" "Not pending,Pending" line.long 0x04 "WDT_WIRQSTAT,IRQ masked status" eventfld.long 0x04 1. " EVENT_DLY ,Clearable enabled status for delay event" "Not pending,Pending" eventfld.long 0x04 0. " EVENT_OVF ,Clearable enabled status for overflow event" "Not pending,Pending" line.long 0x08 "WDT_WIRQENSET,IRQ enable" bitfld.long 0x08 1. " ENABLE_DLY ,Enable for delay event" "Disabled,Enabled" bitfld.long 0x08 0. " ENABLE_OVF ,Enable for overflow event" "Disabled,Enabled" line.long 0x0C "WDT_WIRQENCLR,IRQ enable clear" eventfld.long 0x0C 1. " ENABLE_DLY ,Enable (Clear) for delay event" "Disabled,Enabled" eventfld.long 0x0C 0. " ENABLE_OVF ,Enable (Clear) for overflow event" "Disabled,Enabled" sif (cpuis("DRA62*")) group.long 0x64++0x3 line.long 0x00 "WDT_WIRQWAKEEN,Wake-up events control" bitfld.long 0x00 1. " DLY_WK_ENA ,Delay wake-up enable/disable" "Disabled,Enabled" bitfld.long 0x00 0. " OVF_WK_ENA ,Overflow wake-up enable/disable" "Disabled,Enabled" endif width 0xb tree.end tree.end tree "I2C (Inter Integrated Circuit)" tree "I2C 0" base ad:0x44E0B000 width 22. rgroup.long 0x00++0x07 line.long 0x00 "I2C_REVNB_LO,Module Revision Register (LOW BYTES)" bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision" line.long 0x04 "I2C_REVNB_HI,Module Revision Register (HIGH BYTES)" bitfld.long 0x04 14.--15. " SCHEME ,Distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x04 0.--11. 1. " FUNC ,Indicates a software compatible module family" group.long 0x10++0x03 line.long 0x00 "I2C_SYSC,System Configuration Register" bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both off,Ocp on,Sys on,Both on" bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No idle,Smart idle,Smartidle_wakeup" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled" bitfld.long 0x00 1. " SRST ,SoftReset bit" "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled" width 22. sif (!cpuis("AM335*")) wgroup.long 0x20++0x03 line.long 0x00 "I2C_EOI,I2C End of Interrupt Register" bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "Disabled,Enabled" endif group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTATUS_RAW,I2C Status Raw Register" bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive draining IRQ status" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy" else bitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy" endif bitfld.long 0x00 11. " ROVR ,Receive overrun status" "Normal,Received" textline " " bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus Free IRQ status" "No action,Free" bitfld.long 0x00 7. " AERR ,Access Error IRQ status" "No action,Error" textline " " bitfld.long 0x00 6. " STC ,Start Condition IRQ status" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status" "Not detected,Detected" textline " " eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not ready,Ready" eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ status" "Not ready,Ready" textline " " eventfld.long 0x00 2. " ARDY ,Register access ready IRQ status" "Not ready,Ready" eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ status" "Normal,Detected" textline " " bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status" "Normal,Detected" group.long 0x28++0x0b line.long 0x00 "I2C_IRQSTATUS,I2C Status Register" eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled" eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " BB ,Bus busy enabled status" "Not busy,Busy" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP") bitfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received" else eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received" endif textline " " eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "No underflow,Underflow" eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Recognized" textline " " eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free" eventfld.long 0x00 7. " AERR ,Access Error IRQ enabled status" "No action,Error" textline " " eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected" textline " " eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "Not ready,Ready" eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "Not ready,Ready" textline " " eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Not ready,Ready" eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ enabled status" "Normal,Detected" textline " " eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected" line.long 0x04 "I2C_IRQENABLE_SET,I2C Interrupt Enable Set Register" bitfld.long 0x04 14. " XDR_IE ,Transmit draining IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 13. " RDR_IE ,Receive draining IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " ROVR ,Receive overrun enable set" "Disabled,Enabled" bitfld.long 0x04 10. " XUDF ,Transmit underflow enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " AAS_IE ,Address recognized as slave IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 8. " BF_IE ,Bus Free IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " AERR_IE ,Access Error IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 6. " STC_IE ,Start Condition IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " GC_IE ,General call IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 4. " XRDY_IE ,Transmit data ready IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " RRDY_IE ,Receive data ready IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 2. " ARDY_IE ,Register access ready IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " NACK_IE ,No acknowledgement IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 0. " AL_IE ,Arbitration lost IRQ enable set" "Disabled,Enabled" line.long 0x08 "I2C_IRQENABLE_CLR,I2C Interrupt Enable Clear Register" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpuis("AM335*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP") bitfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled" bitfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled" else eventfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled" eventfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled" endif group.long 0x34++0x1b line.long 0x00 "I2C_WE,I2C Wakeup Enable Register" bitfld.long 0x00 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" width 22. line.long 0x04 "I2C_DMARXENABLE_SET,Receive DMA Enable Set Register" bitfld.long 0x04 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set" "Disabled,Enabled" line.long 0x08 "I2C_DMATXENABLE_SET,Transmit DMA Enable Set Register" bitfld.long 0x08 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set" "Disabled,Enabled" line.long 0x0c "I2C_DMARXENABLE_CLR,Receive DMA Enable Clear Register" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") bitfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear" else eventfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear" endif line.long 0x10 "I2C_DMATXENABLE_CLR,Transmit DMA Enable Clear Register" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") bitfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear" else eventfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear" endif width 22. line.long 0x14 "I2C_DMARXWAKE_EN,Receive DMA Wakeup Register" bitfld.long 0x14 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled" bitfld.long 0x14 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x14 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" line.long 0x18 "I2C_DMATXWAKE_EN,Transmit DMA Wakeup Register" bitfld.long 0x18 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled" bitfld.long 0x18 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x18 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" group.long 0x90++0x0b line.long 0x00 "I2C_SYSS,System Status Register" bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed" line.long 0x04 "I2C_BUF,Buffer Configuration Register" bitfld.long 0x04 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled" bitfld.long 0x04 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset" textline " " hexmask.long.byte 0x04 8.--13. 1. " RXTRSH ,Threshold value for FIFO buffer in RX mode" bitfld.long 0x04 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset" bitfld.long 0x04 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "I2C_CNT,Data Counter Register" hexmask.long.word 0x08 0.--15. 1. " DCOUNT ,Data count (Master mode only)" hgroup.long 0x9C++0x03 hide.long 0x00 "I2C_DATA,Data Access Register" in width 22. if (((d.l(ad:0x44E0B000+0xa4))&0x400)==0x400) group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C Configuration Register" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..." textline " " bitfld.long 0x00 11. " STB ,Start byte mode" "Normal,Start byte" bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master" textline " " bitfld.long 0x00 9. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter" bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit" textline " " bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit" textline " " bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit" textline " " bitfld.long 0x00 1. " STP ,Stop condition" "No action/stop detected,Stop queried" textline " " bitfld.long 0x00 0. " STT ,Start condition" "No action/start detected,Start queried" else group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C Configuration Register" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..." textline " " bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master" bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit" textline " " bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit" textline " " bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit" endif width 22. if (((d.l(ad:0x44E0B000+0xa4))&0x80)==0x80) group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C Own Address Register" hexmask.long.word 0x00 0.--9. 1. " OA ,Own address" else group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C Own Address Register" hexmask.long.byte 0x00 0.--6. 1. " OA ,Own address" endif if (((d.l(ad:0x44E0B000+0xa4))&0x100)==0x100) group.long 0xAC++0x03 line.long 0x00 "I2C_SA,Slave Address Register" hexmask.long.word 0x00 0.--9. 1. " SA ,Slave address" else group.long 0xAC++0x03 line.long 0x00 "I2C_SA,Slave Address Register" hexmask.long.byte 0x00 0.--6. 1. " SA ,Slave address" endif group.long 0xB0++0x03 line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value" if (((d.l(ad:0x44E0B000+0xa4))&0x400)==0x400) group.long 0xB4++0x07 line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register" hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time" line.long 0x04 "I2C_SCLH,I2C SCL High Time Register" hexmask.long.byte 0x04 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time" else hgroup.long 0xB4++0x07 hide.long 0x00 "I2C_SCLL,I2C SCL Low Time Register" hide.long 0x04 "I2C_SCLH,I2C SCL High Time Register" endif group.long 0xBC++0x03 line.long 0x00 "I2C_SYSTEST,I2C System Test Register" bitfld.long 0x00 15. " ST_EN ,System test enable" "Disabled,Enabled" bitfld.long 0x00 14. " FREE ,Free running mode" "Stop,Free" textline " " bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test,Loopback" bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Set" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High" rbitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High" textline " " rbitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High" rbitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High" textline " " rbitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High" rbitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High" textline " " rbitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High" rbitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High" else bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High" bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High" textline " " bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High" bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High" textline " " bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High" bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High" textline " " bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High" bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High" endif rgroup.long 0xc0++0x03 line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register" bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.long 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--5. " TXSTAT ,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((d.l(ad:0x44E0B000+0xa4))&0x40)==0x00) group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.byte 0x00 0.--6. 1. " OA1 ,Own address 1" else group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x00 0.--9. 1. " OA1 ,Own address 1" endif if (((d.l(ad:0x44E0B000+0xa4))&0x20)==0x00) group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.byte 0x00 0.--6. 1. " OA2 ,Own address 2" else group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x00 0.--9. 1. " OA2 ,Own address 2" endif if (((d.l(ad:0x44E0B000+0xa4))&0x10)==0x00) group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.byte 0x00 0.--6. 1. " OA3 ,Own address 3" else group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x00 0.--9. 1. " OA3 ,Own address 3" endif rgroup.long 0xD0++0x03 line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register" bitfld.long 0x00 3. " OA3_ACT ,Own Address 3 active" "Inactive,Active" bitfld.long 0x00 2. " OA2_ACT ,Own Address 2 active" "Inactive,Active" textline " " bitfld.long 0x00 1. " OA1_ACT ,Own Address 1 active" "Inactive,Active" bitfld.long 0x00 0. " OA0_ACT ,Own Address 0 active" "Inactive,Active" group.long 0xD4++0x03 line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register" bitfld.long 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3" "Released,Blocked" bitfld.long 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2" "Released,Blocked" textline " " bitfld.long 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1" "Released,Blocked" bitfld.long 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0" "Released,Blocked" width 0xb tree.end tree "I2C 1" base ad:0x4802A000 width 22. rgroup.long 0x00++0x07 line.long 0x00 "I2C_REVNB_LO,Module Revision Register (LOW BYTES)" bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision" line.long 0x04 "I2C_REVNB_HI,Module Revision Register (HIGH BYTES)" bitfld.long 0x04 14.--15. " SCHEME ,Distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x04 0.--11. 1. " FUNC ,Indicates a software compatible module family" group.long 0x10++0x03 line.long 0x00 "I2C_SYSC,System Configuration Register" bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both off,Ocp on,Sys on,Both on" bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No idle,Smart idle,Smartidle_wakeup" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled" bitfld.long 0x00 1. " SRST ,SoftReset bit" "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled" width 22. sif (!cpuis("AM335*")) wgroup.long 0x20++0x03 line.long 0x00 "I2C_EOI,I2C End of Interrupt Register" bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "Disabled,Enabled" endif group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTATUS_RAW,I2C Status Raw Register" bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive draining IRQ status" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy" else bitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy" endif bitfld.long 0x00 11. " ROVR ,Receive overrun status" "Normal,Received" textline " " bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus Free IRQ status" "No action,Free" bitfld.long 0x00 7. " AERR ,Access Error IRQ status" "No action,Error" textline " " bitfld.long 0x00 6. " STC ,Start Condition IRQ status" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status" "Not detected,Detected" textline " " eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not ready,Ready" eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ status" "Not ready,Ready" textline " " eventfld.long 0x00 2. " ARDY ,Register access ready IRQ status" "Not ready,Ready" eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ status" "Normal,Detected" textline " " bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status" "Normal,Detected" group.long 0x28++0x0b line.long 0x00 "I2C_IRQSTATUS,I2C Status Register" eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled" eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " BB ,Bus busy enabled status" "Not busy,Busy" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP") bitfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received" else eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received" endif textline " " eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "No underflow,Underflow" eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Recognized" textline " " eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free" eventfld.long 0x00 7. " AERR ,Access Error IRQ enabled status" "No action,Error" textline " " eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected" textline " " eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "Not ready,Ready" eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "Not ready,Ready" textline " " eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Not ready,Ready" eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ enabled status" "Normal,Detected" textline " " eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected" line.long 0x04 "I2C_IRQENABLE_SET,I2C Interrupt Enable Set Register" bitfld.long 0x04 14. " XDR_IE ,Transmit draining IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 13. " RDR_IE ,Receive draining IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " ROVR ,Receive overrun enable set" "Disabled,Enabled" bitfld.long 0x04 10. " XUDF ,Transmit underflow enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " AAS_IE ,Address recognized as slave IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 8. " BF_IE ,Bus Free IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " AERR_IE ,Access Error IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 6. " STC_IE ,Start Condition IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " GC_IE ,General call IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 4. " XRDY_IE ,Transmit data ready IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " RRDY_IE ,Receive data ready IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 2. " ARDY_IE ,Register access ready IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " NACK_IE ,No acknowledgement IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 0. " AL_IE ,Arbitration lost IRQ enable set" "Disabled,Enabled" line.long 0x08 "I2C_IRQENABLE_CLR,I2C Interrupt Enable Clear Register" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpuis("AM335*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP") bitfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled" bitfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled" else eventfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled" eventfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled" endif group.long 0x34++0x1b line.long 0x00 "I2C_WE,I2C Wakeup Enable Register" bitfld.long 0x00 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" width 22. line.long 0x04 "I2C_DMARXENABLE_SET,Receive DMA Enable Set Register" bitfld.long 0x04 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set" "Disabled,Enabled" line.long 0x08 "I2C_DMATXENABLE_SET,Transmit DMA Enable Set Register" bitfld.long 0x08 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set" "Disabled,Enabled" line.long 0x0c "I2C_DMARXENABLE_CLR,Receive DMA Enable Clear Register" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") bitfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear" else eventfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear" endif line.long 0x10 "I2C_DMATXENABLE_CLR,Transmit DMA Enable Clear Register" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") bitfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear" else eventfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear" endif width 22. line.long 0x14 "I2C_DMARXWAKE_EN,Receive DMA Wakeup Register" bitfld.long 0x14 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled" bitfld.long 0x14 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x14 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" line.long 0x18 "I2C_DMATXWAKE_EN,Transmit DMA Wakeup Register" bitfld.long 0x18 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled" bitfld.long 0x18 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x18 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" group.long 0x90++0x0b line.long 0x00 "I2C_SYSS,System Status Register" bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed" line.long 0x04 "I2C_BUF,Buffer Configuration Register" bitfld.long 0x04 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled" bitfld.long 0x04 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset" textline " " hexmask.long.byte 0x04 8.--13. 1. " RXTRSH ,Threshold value for FIFO buffer in RX mode" bitfld.long 0x04 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset" bitfld.long 0x04 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "I2C_CNT,Data Counter Register" hexmask.long.word 0x08 0.--15. 1. " DCOUNT ,Data count (Master mode only)" hgroup.long 0x9C++0x03 hide.long 0x00 "I2C_DATA,Data Access Register" in width 22. if (((d.l(ad:0x4802A000+0xa4))&0x400)==0x400) group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C Configuration Register" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..." textline " " bitfld.long 0x00 11. " STB ,Start byte mode" "Normal,Start byte" bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master" textline " " bitfld.long 0x00 9. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter" bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit" textline " " bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit" textline " " bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit" textline " " bitfld.long 0x00 1. " STP ,Stop condition" "No action/stop detected,Stop queried" textline " " bitfld.long 0x00 0. " STT ,Start condition" "No action/start detected,Start queried" else group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C Configuration Register" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..." textline " " bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master" bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit" textline " " bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit" textline " " bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit" endif width 22. if (((d.l(ad:0x4802A000+0xa4))&0x80)==0x80) group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C Own Address Register" hexmask.long.word 0x00 0.--9. 1. " OA ,Own address" else group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C Own Address Register" hexmask.long.byte 0x00 0.--6. 1. " OA ,Own address" endif if (((d.l(ad:0x4802A000+0xa4))&0x100)==0x100) group.long 0xAC++0x03 line.long 0x00 "I2C_SA,Slave Address Register" hexmask.long.word 0x00 0.--9. 1. " SA ,Slave address" else group.long 0xAC++0x03 line.long 0x00 "I2C_SA,Slave Address Register" hexmask.long.byte 0x00 0.--6. 1. " SA ,Slave address" endif group.long 0xB0++0x03 line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value" if (((d.l(ad:0x4802A000+0xa4))&0x400)==0x400) group.long 0xB4++0x07 line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register" hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time" line.long 0x04 "I2C_SCLH,I2C SCL High Time Register" hexmask.long.byte 0x04 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time" else hgroup.long 0xB4++0x07 hide.long 0x00 "I2C_SCLL,I2C SCL Low Time Register" hide.long 0x04 "I2C_SCLH,I2C SCL High Time Register" endif group.long 0xBC++0x03 line.long 0x00 "I2C_SYSTEST,I2C System Test Register" bitfld.long 0x00 15. " ST_EN ,System test enable" "Disabled,Enabled" bitfld.long 0x00 14. " FREE ,Free running mode" "Stop,Free" textline " " bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test,Loopback" bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Set" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High" rbitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High" textline " " rbitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High" rbitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High" textline " " rbitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High" rbitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High" textline " " rbitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High" rbitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High" else bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High" bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High" textline " " bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High" bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High" textline " " bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High" bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High" textline " " bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High" bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High" endif rgroup.long 0xc0++0x03 line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register" bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.long 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--5. " TXSTAT ,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((d.l(ad:0x4802A000+0xa4))&0x40)==0x00) group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.byte 0x00 0.--6. 1. " OA1 ,Own address 1" else group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x00 0.--9. 1. " OA1 ,Own address 1" endif if (((d.l(ad:0x4802A000+0xa4))&0x20)==0x00) group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.byte 0x00 0.--6. 1. " OA2 ,Own address 2" else group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x00 0.--9. 1. " OA2 ,Own address 2" endif if (((d.l(ad:0x4802A000+0xa4))&0x10)==0x00) group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.byte 0x00 0.--6. 1. " OA3 ,Own address 3" else group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x00 0.--9. 1. " OA3 ,Own address 3" endif rgroup.long 0xD0++0x03 line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register" bitfld.long 0x00 3. " OA3_ACT ,Own Address 3 active" "Inactive,Active" bitfld.long 0x00 2. " OA2_ACT ,Own Address 2 active" "Inactive,Active" textline " " bitfld.long 0x00 1. " OA1_ACT ,Own Address 1 active" "Inactive,Active" bitfld.long 0x00 0. " OA0_ACT ,Own Address 0 active" "Inactive,Active" group.long 0xD4++0x03 line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register" bitfld.long 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3" "Released,Blocked" bitfld.long 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2" "Released,Blocked" textline " " bitfld.long 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1" "Released,Blocked" bitfld.long 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0" "Released,Blocked" width 0xb tree.end tree "I2C 2" base ad:0x4819C000 width 22. rgroup.long 0x00++0x07 line.long 0x00 "I2C_REVNB_LO,Module Revision Register (LOW BYTES)" bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision" line.long 0x04 "I2C_REVNB_HI,Module Revision Register (HIGH BYTES)" bitfld.long 0x04 14.--15. " SCHEME ,Distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x04 0.--11. 1. " FUNC ,Indicates a software compatible module family" group.long 0x10++0x03 line.long 0x00 "I2C_SYSC,System Configuration Register" bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both off,Ocp on,Sys on,Both on" bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No idle,Smart idle,Smartidle_wakeup" textline " " bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled" bitfld.long 0x00 1. " SRST ,SoftReset bit" "Normal,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled" width 22. sif (!cpuis("AM335*")) wgroup.long 0x20++0x03 line.long 0x00 "I2C_EOI,I2C End of Interrupt Register" bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "Disabled,Enabled" endif group.long 0x24++0x03 line.long 0x00 "I2C_IRQSTATUS_RAW,I2C Status Raw Register" bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive draining IRQ status" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy" else bitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy" endif bitfld.long 0x00 11. " ROVR ,Receive overrun status" "Normal,Received" textline " " bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow" bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status" "No action,Recognized" textline " " bitfld.long 0x00 8. " BF ,Bus Free IRQ status" "No action,Free" bitfld.long 0x00 7. " AERR ,Access Error IRQ status" "No action,Error" textline " " bitfld.long 0x00 6. " STC ,Start Condition IRQ status" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ status" "Not detected,Detected" textline " " eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not ready,Ready" eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ status" "Not ready,Ready" textline " " eventfld.long 0x00 2. " ARDY ,Register access ready IRQ status" "Not ready,Ready" eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ status" "Normal,Detected" textline " " bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status" "Normal,Detected" group.long 0x28++0x0b line.long 0x00 "I2C_IRQSTATUS,I2C Status Register" eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled" eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " BB ,Bus busy enabled status" "Not busy,Busy" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP") bitfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received" else eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received" endif textline " " eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "No underflow,Underflow" eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Recognized" textline " " eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free" eventfld.long 0x00 7. " AERR ,Access Error IRQ enabled status" "No action,Error" textline " " eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected" eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected" textline " " eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "Not ready,Ready" eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "Not ready,Ready" textline " " eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Not ready,Ready" eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ enabled status" "Normal,Detected" textline " " eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected" line.long 0x04 "I2C_IRQENABLE_SET,I2C Interrupt Enable Set Register" bitfld.long 0x04 14. " XDR_IE ,Transmit draining IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 13. " RDR_IE ,Receive draining IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " ROVR ,Receive overrun enable set" "Disabled,Enabled" bitfld.long 0x04 10. " XUDF ,Transmit underflow enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " AAS_IE ,Address recognized as slave IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 8. " BF_IE ,Bus Free IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " AERR_IE ,Access Error IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 6. " STC_IE ,Start Condition IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " GC_IE ,General call IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 4. " XRDY_IE ,Transmit data ready IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " RRDY_IE ,Receive data ready IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 2. " ARDY_IE ,Register access ready IRQ enable set" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " NACK_IE ,No acknowledgement IRQ enable set" "Disabled,Enabled" bitfld.long 0x04 0. " AL_IE ,Arbitration lost IRQ enable set" "Disabled,Enabled" line.long 0x08 "I2C_IRQENABLE_CLR,I2C Interrupt Enable Clear Register" sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpuis("AM335*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP") bitfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled" bitfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled" bitfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled" else eventfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled" eventfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled" textline " " eventfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled" eventfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled" endif group.long 0x34++0x1b line.long 0x00 "I2C_WE,I2C Wakeup Enable Register" bitfld.long 0x00 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled" bitfld.long 0x00 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" width 22. line.long 0x04 "I2C_DMARXENABLE_SET,Receive DMA Enable Set Register" bitfld.long 0x04 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set" "Disabled,Enabled" line.long 0x08 "I2C_DMATXENABLE_SET,Transmit DMA Enable Set Register" bitfld.long 0x08 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set" "Disabled,Enabled" line.long 0x0c "I2C_DMARXENABLE_CLR,Receive DMA Enable Clear Register" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") bitfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear" else eventfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear" endif line.long 0x10 "I2C_DMATXENABLE_CLR,Transmit DMA Enable Clear Register" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") bitfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear" else eventfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear" endif width 22. line.long 0x14 "I2C_DMARXWAKE_EN,Receive DMA Wakeup Register" bitfld.long 0x14 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled" bitfld.long 0x14 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x14 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x14 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" line.long 0x18 "I2C_DMATXWAKE_EN,Transmit DMA Wakeup Register" bitfld.long 0x18 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled" bitfld.long 0x18 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled" bitfld.long 0x18 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled" textline " " bitfld.long 0x18 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled" bitfld.long 0x18 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled" group.long 0x90++0x0b line.long 0x00 "I2C_SYSS,System Status Register" bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed" line.long 0x04 "I2C_BUF,Buffer Configuration Register" bitfld.long 0x04 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled" bitfld.long 0x04 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset" textline " " hexmask.long.byte 0x04 8.--13. 1. " RXTRSH ,Threshold value for FIFO buffer in RX mode" bitfld.long 0x04 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset" bitfld.long 0x04 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "I2C_CNT,Data Counter Register" hexmask.long.word 0x08 0.--15. 1. " DCOUNT ,Data count (Master mode only)" hgroup.long 0x9C++0x03 hide.long 0x00 "I2C_DATA,Data Access Register" in width 22. if (((d.l(ad:0x4819C000+0xa4))&0x400)==0x400) group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C Configuration Register" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..." textline " " bitfld.long 0x00 11. " STB ,Start byte mode" "Normal,Start byte" bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master" textline " " bitfld.long 0x00 9. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter" bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit" textline " " bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit" textline " " bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit" textline " " bitfld.long 0x00 1. " STP ,Stop condition" "No action/stop detected,Stop queried" textline " " bitfld.long 0x00 0. " STT ,Start condition" "No action/start detected,Start queried" else group.long 0xA4++0x03 line.long 0x00 "I2C_CON,I2C Configuration Register" bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled" bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..." textline " " bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master" bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit" textline " " bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit" bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit" textline " " bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit" bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit" endif width 22. if (((d.l(ad:0x4819C000+0xa4))&0x80)==0x80) group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C Own Address Register" hexmask.long.word 0x00 0.--9. 1. " OA ,Own address" else group.long 0xA8++0x03 line.long 0x00 "I2C_OA,I2C Own Address Register" hexmask.long.byte 0x00 0.--6. 1. " OA ,Own address" endif if (((d.l(ad:0x4819C000+0xa4))&0x100)==0x100) group.long 0xAC++0x03 line.long 0x00 "I2C_SA,Slave Address Register" hexmask.long.word 0x00 0.--9. 1. " SA ,Slave address" else group.long 0xAC++0x03 line.long 0x00 "I2C_SA,Slave Address Register" hexmask.long.byte 0x00 0.--6. 1. " SA ,Slave address" endif group.long 0xB0++0x03 line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register" hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value" if (((d.l(ad:0x4819C000+0xa4))&0x400)==0x400) group.long 0xB4++0x07 line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register" hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time" line.long 0x04 "I2C_SCLH,I2C SCL High Time Register" hexmask.long.byte 0x04 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time" else hgroup.long 0xB4++0x07 hide.long 0x00 "I2C_SCLL,I2C SCL Low Time Register" hide.long 0x04 "I2C_SCLH,I2C SCL High Time Register" endif group.long 0xBC++0x03 line.long 0x00 "I2C_SYSTEST,I2C System Test Register" bitfld.long 0x00 15. " ST_EN ,System test enable" "Disabled,Enabled" bitfld.long 0x00 14. " FREE ,Free running mode" "Stop,Free" textline " " bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test,Loopback" bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Set" textline " " sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High" rbitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High" textline " " rbitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High" rbitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High" textline " " rbitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High" rbitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High" textline " " rbitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High" rbitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High" else bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High" bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High" textline " " bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High" bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High" textline " " bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High" bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High" textline " " bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High" bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High" endif rgroup.long 0xc0++0x03 line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register" bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.long 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 0.--5. " TXSTAT ,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((d.l(ad:0x4819C000+0xa4))&0x40)==0x00) group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.byte 0x00 0.--6. 1. " OA1 ,Own address 1" else group.long 0xC4++0x03 line.long 0x00 "I2C_OA1,I2C Own Address 1 Register" hexmask.long.word 0x00 0.--9. 1. " OA1 ,Own address 1" endif if (((d.l(ad:0x4819C000+0xa4))&0x20)==0x00) group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.byte 0x00 0.--6. 1. " OA2 ,Own address 2" else group.long 0xC8++0x03 line.long 0x00 "I2C_OA2,I2C Own Address 2 Register" hexmask.long.word 0x00 0.--9. 1. " OA2 ,Own address 2" endif if (((d.l(ad:0x4819C000+0xa4))&0x10)==0x00) group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.byte 0x00 0.--6. 1. " OA3 ,Own address 3" else group.long 0xCC++0x03 line.long 0x00 "I2C_OA3,I2C Own Address 3 Register" hexmask.long.word 0x00 0.--9. 1. " OA3 ,Own address 3" endif rgroup.long 0xD0++0x03 line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register" bitfld.long 0x00 3. " OA3_ACT ,Own Address 3 active" "Inactive,Active" bitfld.long 0x00 2. " OA2_ACT ,Own Address 2 active" "Inactive,Active" textline " " bitfld.long 0x00 1. " OA1_ACT ,Own Address 1 active" "Inactive,Active" bitfld.long 0x00 0. " OA0_ACT ,Own Address 0 active" "Inactive,Active" group.long 0xD4++0x03 line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register" bitfld.long 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3" "Released,Blocked" bitfld.long 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2" "Released,Blocked" textline " " bitfld.long 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1" "Released,Blocked" bitfld.long 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0" "Released,Blocked" width 0xb tree.end tree.end tree "McASP (Multichannel Audio Serial Port)" tree "L3" tree "Channel 0" base ad:0x46000000 width 11. tree "General Registers" rgroup.long 0x00++0x3 line.long 0x00 "REV,Revision Identification Register" sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")) width 18. group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG" endif width 11. group.long 0x10++0x3 line.long 0x00 "PFUNC,Pin Function Register" bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO" bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO" bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO" bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO" bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO" bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO" bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO" bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO" bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO" bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO" bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO" bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO" bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO" bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO" bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO" bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO" bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO" group.long 0x14++0x3 line.long 0x00 "PDIR,Pin Direction Register" bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output" bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output" bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output" bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output" bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output" bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output" bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output" bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output" bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output" bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output" bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output" bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output" bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output" bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output" bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output" bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output" bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output" group.long 0x18++0x3 line.long 0x00 "PDOUT,Pin Data Output Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High" textline " " setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High" textline " " endif setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High" rgroup.long 0x1c++0x3 line.long 0x00 "PDIN,Pin Data Input Register" bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High" bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High" bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High" bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High" bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High" bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High" bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High" bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High" bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High" bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High" bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High" bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High" bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High" bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High" bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High" bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High" bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High" group.long 0x44++0x3 line.long 0x00 "GBLCTL,Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" group.long 0x48++0x3 line.long 0x00 "AMUTE,Audio Mute Control Register" bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active" else bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active" endif bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled" bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low" bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..." group.long 0x4c++0x3 line.long 0x00 "DLBCTL,Digital Loopback Control Register" bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..." bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even" bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled" group.long 0x50++0x3 line.long 0x00 "DITCTL,Digital Mode Control Register" bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1" bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1" bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled" tree.end tree "Receive Registers" group.long 0x60++0x3 line.long 0x00 "RGBLCTLR,Receiver Global Control Register" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled" rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled" rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" else bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" endif bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" group.long 0x64++0x3 line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register" bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked" group.long 0x68++0x3 line.long 0x00 "RXFMT,Receive Bit Stream Format Register" bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..." bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..." textline " " bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits" bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus" textline " " bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit" group.long 0x6c++0x3 line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select" bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word" bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally" textline " " bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge" group.long 0x70++0x3 line.long 0x00 "ACLKRCTL,Receive Clock Control Register" bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge" bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal" bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x74++0x3 line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal" bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio" group.long 0x78++0x3 line.long 0x00 "RXTDM,Receive TDM Time Slot Register" bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active" textline " " bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active" bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active" textline " " bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active" bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active" textline " " bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active" textline " " bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active" bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active" textline " " bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active" bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active" textline " " bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active" textline " " bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active" bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active" textline " " bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active" group.long 0x7c++0x3 line.long 0x00 "RINTCTL,Receiver Interrupt Control Register" bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled" group.long 0x80++0x3 line.long 0x00 "RXSTAT,Receiver Status Register" bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred" eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected" eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred" textline " " eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" else bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" endif textline " " eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred" eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred" rgroup.long 0x84++0x3 line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register" hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count" group.long 0x88++0x7 line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value" hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary" textline " " hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary" bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..." line.long 0x04 "REVTCTL,Receiver DMA Event Control Register" bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..." tree.end tree "Transmit Registers" group.long 0xa0++0x3 line.long 0x00 "XGBLCTL,Transmitter Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" else bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" endif group.long 0xa4++0x3 line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register" bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked" group.long 0xa8++0x3 line.long 0x00 "TXFMT,Transmit Bit Stream Format Register" bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..." bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..." textline " " bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits" bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus" textline " " bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit" group.long 0xac++0x3 line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select" bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word" bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally" textline " " bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge" group.long 0xb0++0x3 line.long 0x00 "ACLKXCTL,Transmit Clock Control Register" bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge" bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous" bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal" textline " " bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0xb4++0x3 line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal" bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio" group.long 0xb8++0x3 line.long 0x00 "TXTDM,Transmit TDM Time Slot Register" bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active" textline " " bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active" bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active" textline " " bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active" bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active" textline " " bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active" textline " " bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active" bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active" textline " " bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active" bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active" textline " " bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active" textline " " bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active" bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active" textline " " bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active" group.long 0xbc++0x3 line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register" bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled" group.long 0xc0++0x3 line.long 0x00 "TXSTAT,Transmitter Status Register" eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred" eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected" eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred" textline " " eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" else bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" endif textline " " eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred" eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred" rgroup.long 0xc4++0x3 line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register" sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*"))) hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count" else hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count" endif group.long 0xc8++0x7 line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value" hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary" textline " " hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary" bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..." line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register" bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..." sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")) group.long 0xD0++0x03 line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable" endif tree.end width 9. tree "Serializer Control Registers" group.long 0x180++0x03 line.long 0x00 "SRCTL0,Serializer Control Register 0" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x184++0x03 line.long 0x00 "SRCTL1,Serializer Control Register 1" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x188++0x03 line.long 0x00 "SRCTL2,Serializer Control Register 2" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x18C++0x03 line.long 0x00 "SRCTL3,Serializer Control Register 3" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x190++0x03 line.long 0x00 "SRCTL4,Serializer Control Register 4" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x194++0x03 line.long 0x00 "SRCTL5,Serializer Control Register 5" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." tree.end tree "DIT Channel Registers" group.long 0x100++0x03 line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0" group.long 0x104++0x03 line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1" group.long 0x108++0x03 line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2" group.long 0x10C++0x03 line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3" group.long 0x110++0x03 line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4" group.long 0x114++0x03 line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5" group.long 0x118++0x03 line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0" group.long 0x11C++0x03 line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1" group.long 0x120++0x03 line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2" group.long 0x124++0x03 line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3" group.long 0x128++0x03 line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4" group.long 0x12C++0x03 line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5" group.long 0x130++0x03 line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0" group.long 0x134++0x03 line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1" group.long 0x138++0x03 line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2" group.long 0x13C++0x03 line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3" group.long 0x140++0x03 line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4" group.long 0x144++0x03 line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5" group.long 0x148++0x03 line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0" group.long 0x14C++0x03 line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1" group.long 0x150++0x03 line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2" group.long 0x154++0x03 line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3" group.long 0x158++0x03 line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4" group.long 0x15C++0x03 line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5" tree.end tree "Transmit Buffer Registers" group.long 0x200++0x03 line.long 0x00 "XBUF0,Transmit Buffer Register" group.long 0x204++0x03 line.long 0x00 "XBUF1,Transmit Buffer Register" group.long 0x208++0x03 line.long 0x00 "XBUF2,Transmit Buffer Register" group.long 0x20C++0x03 line.long 0x00 "XBUF3,Transmit Buffer Register" group.long 0x210++0x03 line.long 0x00 "XBUF4,Transmit Buffer Register" group.long 0x214++0x03 line.long 0x00 "XBUF5,Transmit Buffer Register" tree.end tree "Receive Buffer Registers" group.long 0x280++0x03 line.long 0x00 "RBUF0,Receive Buffer Register" group.long 0x284++0x03 line.long 0x00 "RBUF1,Receive Buffer Register" group.long 0x288++0x03 line.long 0x00 "RBUF2,Receive Buffer Register" group.long 0x28C++0x03 line.long 0x00 "RBUF3,Receive Buffer Register" group.long 0x290++0x03 line.long 0x00 "RBUF4,Receive Buffer Register" group.long 0x294++0x03 line.long 0x00 "RBUF5,Receive Buffer Register" tree.end tree "McASP AFIFO Registers" group.long 0x1000++0x3 line.long 0x00 "WFIFOCTL,Write FIFO Control Register" bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)" hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)" rgroup.long 0x1004++0x3 line.long 0x00 "WFIFOSTS,Write FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level" group.long 0x1008++0x3 line.long 0x00 "RFIFOCTL,Read FIFO Control Register" sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))) bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled" else bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled" endif hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)" hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)" rgroup.long 0x100c++0x3 line.long 0x00 "RFIFOSTS,Read FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level" tree.end width 0xb tree.end tree "Channel 1" base ad:0x46400000 width 11. tree "General Registers" rgroup.long 0x00++0x3 line.long 0x00 "REV,Revision Identification Register" sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")) width 18. group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG" endif width 11. group.long 0x10++0x3 line.long 0x00 "PFUNC,Pin Function Register" bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO" bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO" bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO" bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO" bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO" bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO" bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO" bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO" bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO" bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO" bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO" bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO" bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO" bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO" bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO" bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO" bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO" group.long 0x14++0x3 line.long 0x00 "PDIR,Pin Direction Register" bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output" bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output" bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output" bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output" bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output" bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output" bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output" bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output" bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output" bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output" bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output" bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output" bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output" bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output" bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output" bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output" bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output" group.long 0x18++0x3 line.long 0x00 "PDOUT,Pin Data Output Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High" textline " " setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High" textline " " endif setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High" rgroup.long 0x1c++0x3 line.long 0x00 "PDIN,Pin Data Input Register" bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High" bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High" bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High" bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High" bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High" bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High" bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High" bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High" bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High" bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High" bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High" bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High" bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High" bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High" bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High" bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High" bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High" group.long 0x44++0x3 line.long 0x00 "GBLCTL,Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" group.long 0x48++0x3 line.long 0x00 "AMUTE,Audio Mute Control Register" bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active" else bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active" endif bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled" bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low" bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..." group.long 0x4c++0x3 line.long 0x00 "DLBCTL,Digital Loopback Control Register" bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..." bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even" bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled" group.long 0x50++0x3 line.long 0x00 "DITCTL,Digital Mode Control Register" bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1" bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1" bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled" tree.end tree "Receive Registers" group.long 0x60++0x3 line.long 0x00 "RGBLCTLR,Receiver Global Control Register" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled" rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled" rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" else bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" endif bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" group.long 0x64++0x3 line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register" bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked" group.long 0x68++0x3 line.long 0x00 "RXFMT,Receive Bit Stream Format Register" bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..." bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..." textline " " bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits" bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus" textline " " bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit" group.long 0x6c++0x3 line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select" bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word" bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally" textline " " bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge" group.long 0x70++0x3 line.long 0x00 "ACLKRCTL,Receive Clock Control Register" bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge" bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal" bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x74++0x3 line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal" bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio" group.long 0x78++0x3 line.long 0x00 "RXTDM,Receive TDM Time Slot Register" bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active" textline " " bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active" bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active" textline " " bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active" bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active" textline " " bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active" textline " " bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active" bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active" textline " " bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active" bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active" textline " " bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active" textline " " bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active" bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active" textline " " bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active" group.long 0x7c++0x3 line.long 0x00 "RINTCTL,Receiver Interrupt Control Register" bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled" group.long 0x80++0x3 line.long 0x00 "RXSTAT,Receiver Status Register" bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred" eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected" eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred" textline " " eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" else bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" endif textline " " eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred" eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred" rgroup.long 0x84++0x3 line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register" hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count" group.long 0x88++0x7 line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value" hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary" textline " " hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary" bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..." line.long 0x04 "REVTCTL,Receiver DMA Event Control Register" bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..." tree.end tree "Transmit Registers" group.long 0xa0++0x3 line.long 0x00 "XGBLCTL,Transmitter Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" else bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" endif group.long 0xa4++0x3 line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register" bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked" group.long 0xa8++0x3 line.long 0x00 "TXFMT,Transmit Bit Stream Format Register" bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..." bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..." textline " " bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits" bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus" textline " " bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit" group.long 0xac++0x3 line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select" bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word" bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally" textline " " bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge" group.long 0xb0++0x3 line.long 0x00 "ACLKXCTL,Transmit Clock Control Register" bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge" bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous" bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal" textline " " bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0xb4++0x3 line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal" bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio" group.long 0xb8++0x3 line.long 0x00 "TXTDM,Transmit TDM Time Slot Register" bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active" textline " " bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active" bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active" textline " " bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active" bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active" textline " " bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active" textline " " bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active" bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active" textline " " bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active" bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active" textline " " bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active" textline " " bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active" bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active" textline " " bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active" group.long 0xbc++0x3 line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register" bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled" group.long 0xc0++0x3 line.long 0x00 "TXSTAT,Transmitter Status Register" eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred" eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected" eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred" textline " " eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" else bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" endif textline " " eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred" eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred" rgroup.long 0xc4++0x3 line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register" sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*"))) hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count" else hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count" endif group.long 0xc8++0x7 line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value" hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary" textline " " hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary" bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..." line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register" bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..." sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")) group.long 0xD0++0x03 line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable" endif tree.end width 9. tree "Serializer Control Registers" group.long 0x180++0x03 line.long 0x00 "SRCTL0,Serializer Control Register 0" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x184++0x03 line.long 0x00 "SRCTL1,Serializer Control Register 1" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x188++0x03 line.long 0x00 "SRCTL2,Serializer Control Register 2" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x18C++0x03 line.long 0x00 "SRCTL3,Serializer Control Register 3" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x190++0x03 line.long 0x00 "SRCTL4,Serializer Control Register 4" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x194++0x03 line.long 0x00 "SRCTL5,Serializer Control Register 5" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." tree.end tree "DIT Channel Registers" group.long 0x100++0x03 line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0" group.long 0x104++0x03 line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1" group.long 0x108++0x03 line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2" group.long 0x10C++0x03 line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3" group.long 0x110++0x03 line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4" group.long 0x114++0x03 line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5" group.long 0x118++0x03 line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0" group.long 0x11C++0x03 line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1" group.long 0x120++0x03 line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2" group.long 0x124++0x03 line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3" group.long 0x128++0x03 line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4" group.long 0x12C++0x03 line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5" group.long 0x130++0x03 line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0" group.long 0x134++0x03 line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1" group.long 0x138++0x03 line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2" group.long 0x13C++0x03 line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3" group.long 0x140++0x03 line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4" group.long 0x144++0x03 line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5" group.long 0x148++0x03 line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0" group.long 0x14C++0x03 line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1" group.long 0x150++0x03 line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2" group.long 0x154++0x03 line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3" group.long 0x158++0x03 line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4" group.long 0x15C++0x03 line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5" tree.end tree "Transmit Buffer Registers" group.long 0x200++0x03 line.long 0x00 "XBUF0,Transmit Buffer Register" group.long 0x204++0x03 line.long 0x00 "XBUF1,Transmit Buffer Register" group.long 0x208++0x03 line.long 0x00 "XBUF2,Transmit Buffer Register" group.long 0x20C++0x03 line.long 0x00 "XBUF3,Transmit Buffer Register" group.long 0x210++0x03 line.long 0x00 "XBUF4,Transmit Buffer Register" group.long 0x214++0x03 line.long 0x00 "XBUF5,Transmit Buffer Register" tree.end tree "Receive Buffer Registers" group.long 0x280++0x03 line.long 0x00 "RBUF0,Receive Buffer Register" group.long 0x284++0x03 line.long 0x00 "RBUF1,Receive Buffer Register" group.long 0x288++0x03 line.long 0x00 "RBUF2,Receive Buffer Register" group.long 0x28C++0x03 line.long 0x00 "RBUF3,Receive Buffer Register" group.long 0x290++0x03 line.long 0x00 "RBUF4,Receive Buffer Register" group.long 0x294++0x03 line.long 0x00 "RBUF5,Receive Buffer Register" tree.end tree "McASP AFIFO Registers" group.long 0x1000++0x3 line.long 0x00 "WFIFOCTL,Write FIFO Control Register" bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)" hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)" rgroup.long 0x1004++0x3 line.long 0x00 "WFIFOSTS,Write FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level" group.long 0x1008++0x3 line.long 0x00 "RFIFOCTL,Read FIFO Control Register" sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))) bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled" else bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled" endif hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)" hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)" rgroup.long 0x100c++0x3 line.long 0x00 "RFIFOSTS,Read FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level" tree.end width 0xb tree.end tree.end tree "L4" tree "Channel 0" base ad:0x48038000 width 11. tree "General Registers" rgroup.long 0x00++0x3 line.long 0x00 "REV,Revision Identification Register" sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")) width 18. group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG" endif width 11. group.long 0x10++0x3 line.long 0x00 "PFUNC,Pin Function Register" bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO" bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO" bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO" bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO" bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO" bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO" bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO" bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO" bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO" bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO" bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO" bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO" bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO" bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO" bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO" bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO" bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO" group.long 0x14++0x3 line.long 0x00 "PDIR,Pin Direction Register" bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output" bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output" bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output" bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output" bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output" bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output" bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output" bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output" bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output" bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output" bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output" bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output" bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output" bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output" bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output" bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output" bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output" group.long 0x18++0x3 line.long 0x00 "PDOUT,Pin Data Output Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High" textline " " setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High" textline " " endif setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High" rgroup.long 0x1c++0x3 line.long 0x00 "PDIN,Pin Data Input Register" bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High" bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High" bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High" bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High" bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High" bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High" bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High" bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High" bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High" bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High" bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High" bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High" bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High" bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High" bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High" bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High" bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High" group.long 0x44++0x3 line.long 0x00 "GBLCTL,Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" group.long 0x48++0x3 line.long 0x00 "AMUTE,Audio Mute Control Register" bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active" else bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active" endif bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled" bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low" bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..." group.long 0x4c++0x3 line.long 0x00 "DLBCTL,Digital Loopback Control Register" bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..." bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even" bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled" group.long 0x50++0x3 line.long 0x00 "DITCTL,Digital Mode Control Register" bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1" bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1" bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled" tree.end tree "Receive Registers" group.long 0x60++0x3 line.long 0x00 "RGBLCTLR,Receiver Global Control Register" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled" rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled" rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" else bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" endif bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" group.long 0x64++0x3 line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register" bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked" group.long 0x68++0x3 line.long 0x00 "RXFMT,Receive Bit Stream Format Register" bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..." bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..." textline " " bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits" bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus" textline " " bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit" group.long 0x6c++0x3 line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select" bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word" bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally" textline " " bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge" group.long 0x70++0x3 line.long 0x00 "ACLKRCTL,Receive Clock Control Register" bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge" bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal" bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x74++0x3 line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal" bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio" group.long 0x78++0x3 line.long 0x00 "RXTDM,Receive TDM Time Slot Register" bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active" textline " " bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active" bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active" textline " " bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active" bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active" textline " " bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active" textline " " bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active" bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active" textline " " bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active" bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active" textline " " bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active" textline " " bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active" bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active" textline " " bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active" group.long 0x7c++0x3 line.long 0x00 "RINTCTL,Receiver Interrupt Control Register" bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled" group.long 0x80++0x3 line.long 0x00 "RXSTAT,Receiver Status Register" bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred" eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected" eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred" textline " " eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" else bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" endif textline " " eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred" eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred" rgroup.long 0x84++0x3 line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register" hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count" group.long 0x88++0x7 line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value" hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary" textline " " hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary" bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..." line.long 0x04 "REVTCTL,Receiver DMA Event Control Register" bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..." tree.end tree "Transmit Registers" group.long 0xa0++0x3 line.long 0x00 "XGBLCTL,Transmitter Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" else bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" endif group.long 0xa4++0x3 line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register" bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked" group.long 0xa8++0x3 line.long 0x00 "TXFMT,Transmit Bit Stream Format Register" bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..." bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..." textline " " bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits" bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus" textline " " bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit" group.long 0xac++0x3 line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select" bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word" bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally" textline " " bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge" group.long 0xb0++0x3 line.long 0x00 "ACLKXCTL,Transmit Clock Control Register" bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge" bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous" bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal" textline " " bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0xb4++0x3 line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal" bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio" group.long 0xb8++0x3 line.long 0x00 "TXTDM,Transmit TDM Time Slot Register" bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active" textline " " bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active" bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active" textline " " bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active" bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active" textline " " bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active" textline " " bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active" bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active" textline " " bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active" bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active" textline " " bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active" textline " " bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active" bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active" textline " " bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active" group.long 0xbc++0x3 line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register" bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled" group.long 0xc0++0x3 line.long 0x00 "TXSTAT,Transmitter Status Register" eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred" eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected" eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred" textline " " eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" else bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" endif textline " " eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred" eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred" rgroup.long 0xc4++0x3 line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register" sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*"))) hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count" else hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count" endif group.long 0xc8++0x7 line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value" hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary" textline " " hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary" bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..." line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register" bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..." sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")) group.long 0xD0++0x03 line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable" endif tree.end width 9. tree "Serializer Control Registers" group.long 0x180++0x03 line.long 0x00 "SRCTL0,Serializer Control Register 0" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x184++0x03 line.long 0x00 "SRCTL1,Serializer Control Register 1" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x188++0x03 line.long 0x00 "SRCTL2,Serializer Control Register 2" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x18C++0x03 line.long 0x00 "SRCTL3,Serializer Control Register 3" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x190++0x03 line.long 0x00 "SRCTL4,Serializer Control Register 4" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x194++0x03 line.long 0x00 "SRCTL5,Serializer Control Register 5" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." tree.end tree "DIT Channel Registers" group.long 0x100++0x03 line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0" group.long 0x104++0x03 line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1" group.long 0x108++0x03 line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2" group.long 0x10C++0x03 line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3" group.long 0x110++0x03 line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4" group.long 0x114++0x03 line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5" group.long 0x118++0x03 line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0" group.long 0x11C++0x03 line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1" group.long 0x120++0x03 line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2" group.long 0x124++0x03 line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3" group.long 0x128++0x03 line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4" group.long 0x12C++0x03 line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5" group.long 0x130++0x03 line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0" group.long 0x134++0x03 line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1" group.long 0x138++0x03 line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2" group.long 0x13C++0x03 line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3" group.long 0x140++0x03 line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4" group.long 0x144++0x03 line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5" group.long 0x148++0x03 line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0" group.long 0x14C++0x03 line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1" group.long 0x150++0x03 line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2" group.long 0x154++0x03 line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3" group.long 0x158++0x03 line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4" group.long 0x15C++0x03 line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5" tree.end tree "Transmit Buffer Registers" group.long 0x200++0x03 line.long 0x00 "XBUF0,Transmit Buffer Register" group.long 0x204++0x03 line.long 0x00 "XBUF1,Transmit Buffer Register" group.long 0x208++0x03 line.long 0x00 "XBUF2,Transmit Buffer Register" group.long 0x20C++0x03 line.long 0x00 "XBUF3,Transmit Buffer Register" group.long 0x210++0x03 line.long 0x00 "XBUF4,Transmit Buffer Register" group.long 0x214++0x03 line.long 0x00 "XBUF5,Transmit Buffer Register" tree.end tree "Receive Buffer Registers" group.long 0x280++0x03 line.long 0x00 "RBUF0,Receive Buffer Register" group.long 0x284++0x03 line.long 0x00 "RBUF1,Receive Buffer Register" group.long 0x288++0x03 line.long 0x00 "RBUF2,Receive Buffer Register" group.long 0x28C++0x03 line.long 0x00 "RBUF3,Receive Buffer Register" group.long 0x290++0x03 line.long 0x00 "RBUF4,Receive Buffer Register" group.long 0x294++0x03 line.long 0x00 "RBUF5,Receive Buffer Register" tree.end tree "McASP AFIFO Registers" group.long 0x1000++0x3 line.long 0x00 "WFIFOCTL,Write FIFO Control Register" bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)" hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)" rgroup.long 0x1004++0x3 line.long 0x00 "WFIFOSTS,Write FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level" group.long 0x1008++0x3 line.long 0x00 "RFIFOCTL,Read FIFO Control Register" sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))) bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled" else bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled" endif hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)" hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)" rgroup.long 0x100c++0x3 line.long 0x00 "RFIFOSTS,Read FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level" tree.end width 0xb tree.end tree "Channel 1" base ad:0x4803C000 width 11. tree "General Registers" rgroup.long 0x00++0x3 line.long 0x00 "REV,Revision Identification Register" sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")) width 18. group.long 0x04++0x03 line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG" endif width 11. group.long 0x10++0x3 line.long 0x00 "PFUNC,Pin Function Register" bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO" bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO" bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO" bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO" bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO" bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO" bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO" bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO" bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO" bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO" bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO" bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO" bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO" bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO" bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO" bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO" bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO" group.long 0x14++0x3 line.long 0x00 "PDIR,Pin Direction Register" bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output" bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output" bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output" bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output" bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output" bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output" bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output" bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output" bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output" bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output" bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output" bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output" bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output" bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output" bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output" bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output" bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output" group.long 0x18++0x3 line.long 0x00 "PDOUT,Pin Data Output Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High" textline " " setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High" textline " " setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High" textline " " endif setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High" rgroup.long 0x1c++0x3 line.long 0x00 "PDIN,Pin Data Input Register" bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High" bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High" bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High" bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High" textline " " bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High" bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High" bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High" textline " " sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High" bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High" bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High" bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High" textline " " bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High" bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High" bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High" bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High" textline " " bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High" bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High" textline " " endif bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High" bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High" bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High" bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High" textline " " bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High" bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High" group.long 0x44++0x3 line.long 0x00 "GBLCTL,Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" group.long 0x48++0x3 line.long 0x00 "AMUTE,Audio Mute Control Register" bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled" bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled" textline " " sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active" else bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active" endif bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled" bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low" bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..." group.long 0x4c++0x3 line.long 0x00 "DLBCTL,Digital Loopback Control Register" bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..." bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even" bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled" group.long 0x50++0x3 line.long 0x00 "DITCTL,Digital Mode Control Register" bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1" bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1" bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled" tree.end tree "Receive Registers" group.long 0x60++0x3 line.long 0x00 "RGBLCTLR,Receiver Global Control Register" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled" rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled" rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" else bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" endif bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" group.long 0x64++0x3 line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register" bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked" bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked" group.long 0x68++0x3 line.long 0x00 "RXFMT,Receive Bit Stream Format Register" bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..." bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..." textline " " bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits" bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus" textline " " bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit" group.long 0x6c++0x3 line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select" bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word" bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally" textline " " bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge" group.long 0x70++0x3 line.long 0x00 "ACLKRCTL,Receive Clock Control Register" bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge" bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal" bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0x74++0x3 line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal" bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio" group.long 0x78++0x3 line.long 0x00 "RXTDM,Receive TDM Time Slot Register" bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active" textline " " bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active" bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active" textline " " bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active" bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active" textline " " bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active" textline " " bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active" bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active" textline " " bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active" bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active" textline " " bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active" textline " " bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active" bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active" textline " " bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active" group.long 0x7c++0x3 line.long 0x00 "RINTCTL,Receiver Interrupt Control Register" bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled" group.long 0x80++0x3 line.long 0x00 "RXSTAT,Receiver Status Register" bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred" eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected" eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred" textline " " eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" else bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" endif textline " " eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred" eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred" rgroup.long 0x84++0x3 line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register" hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count" group.long 0x88++0x7 line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value" hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary" textline " " hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary" bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..." line.long 0x04 "REVTCTL,Receiver DMA Event Control Register" bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..." tree.end tree "Transmit Registers" group.long 0xa0++0x3 line.long 0x00 "XGBLCTL,Transmitter Global Control Register" bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active" bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released" bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active" textline " " bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running" bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running" sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP") rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" else bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active" textline " " bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled" bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active" bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" textline " " bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running" endif group.long 0xa4++0x3 line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register" bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked" textline " " bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked" bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked" group.long 0xa8++0x3 line.long 0x00 "TXFMT,Transmit Bit Stream Format Register" bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..." bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first" bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..." textline " " bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits" bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus" textline " " bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit" group.long 0xac++0x3 line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register" hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select" bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word" bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally" textline " " bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge" group.long 0xb0++0x3 line.long 0x00 "ACLKXCTL,Transmit Clock Control Register" bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge" bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous" bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal" textline " " bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" group.long 0xb4++0x3 line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register" bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal" bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted" hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio" group.long 0xb8++0x3 line.long 0x00 "TXTDM,Transmit TDM Time Slot Register" bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active" bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active" bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active" textline " " bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active" bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active" bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active" textline " " bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active" bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active" bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active" textline " " bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active" bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active" bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active" textline " " bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active" bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active" bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active" textline " " bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active" bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active" bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active" textline " " bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active" bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active" bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active" textline " " bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active" bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active" bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active" bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active" bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active" textline " " bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active" bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active" bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active" textline " " bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active" bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active" group.long 0xbc++0x3 line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register" bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled" group.long 0xc0++0x3 line.long 0x00 "TXSTAT,Transmitter Status Register" eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred" eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred" textline " " eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected" eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred" textline " " eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" else bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even" endif textline " " eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred" eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred" rgroup.long 0xc4++0x3 line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register" sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*"))) hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count" else hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count" endif group.long 0xc8++0x7 line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register" hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value" hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary" textline " " hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary" bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..." line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register" bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..." sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")) group.long 0xD0++0x03 line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable" endif tree.end width 9. tree "Serializer Control Registers" group.long 0x180++0x03 line.long 0x00 "SRCTL0,Serializer Control Register 0" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x184++0x03 line.long 0x00 "SRCTL1,Serializer Control Register 1" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x188++0x03 line.long 0x00 "SRCTL2,Serializer Control Register 2" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x18C++0x03 line.long 0x00 "SRCTL3,Serializer Control Register 3" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x190++0x03 line.long 0x00 "SRCTL4,Serializer Control Register 4" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." group.long 0x194++0x03 line.long 0x00 "SRCTL5,Serializer Control Register 5" sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")) rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" else bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty" bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty" endif bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High" bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..." tree.end tree "DIT Channel Registers" group.long 0x100++0x03 line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0" group.long 0x104++0x03 line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1" group.long 0x108++0x03 line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2" group.long 0x10C++0x03 line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3" group.long 0x110++0x03 line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4" group.long 0x114++0x03 line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5" group.long 0x118++0x03 line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0" group.long 0x11C++0x03 line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1" group.long 0x120++0x03 line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2" group.long 0x124++0x03 line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3" group.long 0x128++0x03 line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4" group.long 0x12C++0x03 line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5" group.long 0x130++0x03 line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0" group.long 0x134++0x03 line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1" group.long 0x138++0x03 line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2" group.long 0x13C++0x03 line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3" group.long 0x140++0x03 line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4" group.long 0x144++0x03 line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5" group.long 0x148++0x03 line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0" group.long 0x14C++0x03 line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1" group.long 0x150++0x03 line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2" group.long 0x154++0x03 line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3" group.long 0x158++0x03 line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4" group.long 0x15C++0x03 line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5" tree.end tree "Transmit Buffer Registers" group.long 0x200++0x03 line.long 0x00 "XBUF0,Transmit Buffer Register" group.long 0x204++0x03 line.long 0x00 "XBUF1,Transmit Buffer Register" group.long 0x208++0x03 line.long 0x00 "XBUF2,Transmit Buffer Register" group.long 0x20C++0x03 line.long 0x00 "XBUF3,Transmit Buffer Register" group.long 0x210++0x03 line.long 0x00 "XBUF4,Transmit Buffer Register" group.long 0x214++0x03 line.long 0x00 "XBUF5,Transmit Buffer Register" tree.end tree "Receive Buffer Registers" group.long 0x280++0x03 line.long 0x00 "RBUF0,Receive Buffer Register" group.long 0x284++0x03 line.long 0x00 "RBUF1,Receive Buffer Register" group.long 0x288++0x03 line.long 0x00 "RBUF2,Receive Buffer Register" group.long 0x28C++0x03 line.long 0x00 "RBUF3,Receive Buffer Register" group.long 0x290++0x03 line.long 0x00 "RBUF4,Receive Buffer Register" group.long 0x294++0x03 line.long 0x00 "RBUF5,Receive Buffer Register" tree.end tree "McASP AFIFO Registers" group.long 0x1000++0x3 line.long 0x00 "WFIFOCTL,Write FIFO Control Register" bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled" hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)" hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)" rgroup.long 0x1004++0x3 line.long 0x00 "WFIFOSTS,Write FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level" group.long 0x1008++0x3 line.long 0x00 "RFIFOCTL,Read FIFO Control Register" sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))) bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled" else bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled" endif hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)" hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)" rgroup.long 0x100c++0x3 line.long 0x00 "RFIFOSTS,Read FIFO Status Register" hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level" tree.end width 0xb tree.end tree.end tree.end tree "CAN (Controller Area Network)" tree "CAN 0" base ad:0x481CC000 width 23. group.long 0x00++0x03 line.long 0x00 "DCAN_CTL,CAN Control Register" sif (cpuis("AM335*")) bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity" "No wake up,Wake up" bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "Not requested,Requested" else bitfld.long 0x00 26. " WUBA ,Automatic wake up on bus activity" "No wake up,Wake up" bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "Not requested,Requested" endif textline " " bitfld.long 0x00 20. " DE3 ,DMA enable for IF3" "Disabled,Enabled" bitfld.long 0x00 19. " DE2 ,DMA enable for IF2" "Disabled,Enabled" bitfld.long 0x00 18. " DE1 ,DMA enable for IF1" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. " INITDBG ,Internal init state while debug access" "Not entered,Entered" bitfld.long 0x00 15. " SWR ,SW Reset Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled" bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE0 ,DCAN0INT Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" hgroup.long 0x04++0x03 hide.long 0x00 "DCAN_ES/PARITYERR_EOI,Error and Status/Parity Error EOI Register" in rgroup.long 0x08++0x03 line.long 0x00 "DCAN_ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive Error Passive" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " REC6-0 ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC7-0 ,Transmit Error Counter" if (((data.long(ad:0x481CC000))&0x41)==0x41) group.long 0x0c++0x03 sif (cpuis("DRA62*")||cpuis("AM335*")) line.long 0x00 "DCAN_BTR,Bit Timing Register" else line.long 0x00 "DCAN_BTBRP,Bit Timing_BRP Extension Register" endif bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The time segment after the sample point" "0,1,2,3,4,5,6,7" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline " " bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x0c++0x03 sif (cpuis("DRA62*")||cpuis("AM335*")) line.long 0x00 "DCAN_BTR,Bit Timing Register" else line.long 0x00 "DCAN_BTBRP,Bit Timing_BRP Extension Register" endif bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The time segment after the sample point" "0,1,2,3,4,5,6,7" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "Reerved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline " " bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif rgroup.long 0x10++0x03 line.long 0x00 "DCAN_INTR,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID7-0 ,Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INT0ID15-0 ,Interrupt Identifier" if (((data.long(ad:0x481CC000))&0x80)==0x80) group.long 0x14++0x03 line.long 0x00 "DCAN_TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Direct access" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" textline " " bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled" else rgroup.long 0x14++0x03 line.long 0x00 "DCAN_TEST,Test Register" sif (cpuis("DRA62*")) bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Direct access" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" textline " " bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,Dominant,Recessive" textline " " else bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Test" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,External" bitfld.long 0x00 7. " RX ,Receive Pin" "0,1" textline " " bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,0,1" endif bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled" endif rgroup.long 0x1C++0x03 line.long 0x00 "DCAN_PERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WN ,Word Number" "Reserved,1,2,3,4,5,?..." hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" group.long 0x80++0x3 line.long 0x00 "DCAN_ABOTR,Auto Bus On Time Register" rgroup.long 0x84--0xD3 line.long 0x00 "DCAN_TXRQX,Transmission Request X Register" bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request X 8" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request X 7" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request X 6" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request X 5" "0,1,2,3" bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request X 4" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request X 3" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request X 2" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request X 1" "0,1,2,3" line.long 0x04 "DCAN_TXRQ12,Transmission Request 1_2 Register" bitfld.long 0x04 31. " TXRQST32 ,Transmission Request Bit 32" "Not requested,Requested" bitfld.long 0x04 30. " TXRQST31 ,Transmission Request Bit 31" "Not requested,Requested" bitfld.long 0x04 29. " TXRQST30 ,Transmission Request Bit 30" "Not requested,Requested" textline " " bitfld.long 0x04 28. " TXRQST29 ,Transmission Request Bit 29" "Not requested,Requested" bitfld.long 0x04 27. " TXRQST28 ,Transmission Request Bit 28" "Not requested,Requested" bitfld.long 0x04 26. " TXRQST27 ,Transmission Request Bit 27" "Not requested,Requested" textline " " bitfld.long 0x04 25. " TXRQST26 ,Transmission Request Bit 26" "Not requested,Requested" bitfld.long 0x04 24. " TXRQST25 ,Transmission Request Bit 25" "Not requested,Requested" bitfld.long 0x04 23. " TXRQST24 ,Transmission Request Bit 24" "Not requested,Requested" textline " " bitfld.long 0x04 22. " TXRQST23 ,Transmission Request Bit 23" "Not requested,Requested" bitfld.long 0x04 21. " TXRQST22 ,Transmission Request Bit 22" "Not requested,Requested" bitfld.long 0x04 20. " TXRQST21 ,Transmission Request Bit 21" "Not requested,Requested" textline " " bitfld.long 0x04 19. " TXRQST20 ,Transmission Request Bit 20" "Not requested,Requested" bitfld.long 0x04 18. " TXRQST19 ,Transmission Request Bit 19" "Not requested,Requested" bitfld.long 0x04 17. " TXRQST18 ,Transmission Request Bit 18" "Not requested,Requested" textline " " bitfld.long 0x04 16. " TXRQST17 ,Transmission Request Bit 17" "Not requested,Requested" bitfld.long 0x04 15. " TXRQST16 ,Transmission Request Bit 16" "Not requested,Requested" bitfld.long 0x04 14. " TXRQST15 ,Transmission Request Bit 15" "Not requested,Requested" textline " " bitfld.long 0x04 13. " TXRQST14 ,Transmission Request Bit 14" "Not requested,Requested" bitfld.long 0x04 12. " TXRQST13 ,Transmission Request Bit 13" "Not requested,Requested" bitfld.long 0x04 11. " TXRQST12 ,Transmission Request Bit 12" "Not requested,Requested" textline " " bitfld.long 0x04 10. " TXRQST11 ,Transmission Request Bit 11" "Not requested,Requested" bitfld.long 0x04 9. " TXRQST10 ,Transmission Request Bit 10" "Not requested,Requested" bitfld.long 0x04 8. " TXRQST9 ,Transmission Request Bit 9" "Not requested,Requested" textline " " bitfld.long 0x04 7. " TXRQST8 ,Transmission Request Bit 8" "Not requested,Requested" bitfld.long 0x04 6. " TXRQST7 ,Transmission Request Bit 7" "Not requested,Requested" bitfld.long 0x04 5. " TXRQST6 ,Transmission Request Bit 6" "Not requested,Requested" textline " " bitfld.long 0x04 4. " TXRQST5 ,Transmission Request Bit 5" "Not requested,Requested" bitfld.long 0x04 3. " TXRQST4 ,Transmission Request Bit 4" "Not requested,Requested" bitfld.long 0x04 2. " TXRQST3 ,Transmission Request Bit 3" "Not requested,Requested" textline " " bitfld.long 0x04 1. " TXRQST2 ,Transmission Request Bit 2" "Not requested,Requested" bitfld.long 0x04 0. " TXRQST1 ,Transmission Request Bit 1" "Not requested,Requested" line.long 0x08 "DCAN_TXRQ34,Transmission Request 3_4 Register" bitfld.long 0x08 31. " TXRQST64 ,Transmission Request Bit 64" "Not requested,Requested" bitfld.long 0x08 30. " TXRQST63 ,Transmission Request Bit 63" "Not requested,Requested" bitfld.long 0x08 29. " TXRQST62 ,Transmission Request Bit 62" "Not requested,Requested" textline " " bitfld.long 0x08 28. " TXRQST61 ,Transmission Request Bit 61" "Not requested,Requested" bitfld.long 0x08 27. " TXRQST60 ,Transmission Request Bit 60" "Not requested,Requested" bitfld.long 0x08 26. " TXRQST59 ,Transmission Request Bit 59" "Not requested,Requested" textline " " bitfld.long 0x08 25. " TXRQST58 ,Transmission Request Bit 58" "Not requested,Requested" bitfld.long 0x08 24. " TXRQST57 ,Transmission Request Bit 57" "Not requested,Requested" bitfld.long 0x08 23. " TXRQST56 ,Transmission Request Bit 56" "Not requested,Requested" textline " " bitfld.long 0x08 22. " TXRQST55 ,Transmission Request Bit 55" "Not requested,Requested" bitfld.long 0x08 21. " TXRQST54 ,Transmission Request Bit 54" "Not requested,Requested" bitfld.long 0x08 20. " TXRQST53 ,Transmission Request Bit 53" "Not requested,Requested" textline " " bitfld.long 0x08 19. " TXRQST52 ,Transmission Request Bit 52" "Not requested,Requested" bitfld.long 0x08 18. " TXRQST51 ,Transmission Request Bit 51" "Not requested,Requested" bitfld.long 0x08 17. " TXRQST50 ,Transmission Request Bit 50" "Not requested,Requested" textline " " bitfld.long 0x08 16. " TXRQST49 ,Transmission Request Bit 49" "Not requested,Requested" bitfld.long 0x08 15. " TXRQST48 ,Transmission Request Bit 48" "Not requested,Requested" bitfld.long 0x08 14. " TXRQST47 ,Transmission Request Bit 47" "Not requested,Requested" textline " " bitfld.long 0x08 13. " TXRQST46 ,Transmission Request Bit 46" "Not requested,Requested" bitfld.long 0x08 12. " TXRQST45 ,Transmission Request Bit 45" "Not requested,Requested" bitfld.long 0x08 11. " TXRQST44 ,Transmission Request Bit 44" "Not requested,Requested" textline " " bitfld.long 0x08 10. " TXRQST43 ,Transmission Request Bit 43" "Not requested,Requested" bitfld.long 0x08 9. " TXRQST42 ,Transmission Request Bit 42" "Not requested,Requested" bitfld.long 0x08 8. " TXRQST41 ,Transmission Request Bit 41" "Not requested,Requested" textline " " bitfld.long 0x08 7. " TXRQST40 ,Transmission Request Bit 40" "Not requested,Requested" bitfld.long 0x08 6. " TXRQST39 ,Transmission Request Bit 39" "Not requested,Requested" bitfld.long 0x08 5. " TXRQST38 ,Transmission Request Bit 38" "Not requested,Requested" textline " " bitfld.long 0x08 4. " TXRQST37 ,Transmission Request Bit 37" "Not requested,Requested" bitfld.long 0x08 3. " TXRQST36 ,Transmission Request Bit 36" "Not requested,Requested" bitfld.long 0x08 2. " TXRQST35 ,Transmission Request Bit 35" "Not requested,Requested" textline " " bitfld.long 0x08 1. " TXRQST34 ,Transmission Request Bit 34" "Not requested,Requested" bitfld.long 0x08 0. " TXRQST33 ,Transmission Request Bit 33" "Not requested,Requested" line.long 0x0c "DCAN_TXRQ56,Transmission Request 5_6 Register" bitfld.long 0x0c 31. " TXRQST96 ,Transmission Request Bit 96" "Not requested,Requested" bitfld.long 0x0c 30. " TXRQST95 ,Transmission Request Bit 95" "Not requested,Requested" bitfld.long 0x0c 29. " TXRQST94 ,Transmission Request Bit 94" "Not requested,Requested" textline " " bitfld.long 0x0c 28. " TXRQST93 ,Transmission Request Bit 93" "Not requested,Requested" bitfld.long 0x0c 27. " TXRQST92 ,Transmission Request Bit 92" "Not requested,Requested" bitfld.long 0x0c 26. " TXRQST91 ,Transmission Request Bit 91" "Not requested,Requested" textline " " bitfld.long 0x0c 25. " TXRQST90 ,Transmission Request Bit 90" "Not requested,Requested" bitfld.long 0x0c 24. " TXRQST89 ,Transmission Request Bit 89" "Not requested,Requested" bitfld.long 0x0c 23. " TXRQST88 ,Transmission Request Bit 88" "Not requested,Requested" textline " " bitfld.long 0x0c 22. " TXRQST87 ,Transmission Request Bit 87" "Not requested,Requested" bitfld.long 0x0c 21. " TXRQST86 ,Transmission Request Bit 86" "Not requested,Requested" bitfld.long 0x0c 20. " TXRQST85 ,Transmission Request Bit 85" "Not requested,Requested" textline " " bitfld.long 0x0c 19. " TXRQST84 ,Transmission Request Bit 84" "Not requested,Requested" bitfld.long 0x0c 18. " TXRQST83 ,Transmission Request Bit 83" "Not requested,Requested" bitfld.long 0x0c 17. " TXRQST82 ,Transmission Request Bit 82" "Not requested,Requested" textline " " bitfld.long 0x0c 16. " TXRQST81 ,Transmission Request Bit 81" "Not requested,Requested" bitfld.long 0x0c 15. " TXRQST80 ,Transmission Request Bit 80" "Not requested,Requested" bitfld.long 0x0c 14. " TXRQST79 ,Transmission Request Bit 79" "Not requested,Requested" textline " " bitfld.long 0x0c 13. " TXRQST78 ,Transmission Request Bit 78" "Not requested,Requested" bitfld.long 0x0c 12. " TXRQST77 ,Transmission Request Bit 77" "Not requested,Requested" bitfld.long 0x0c 11. " TXRQST76 ,Transmission Request Bit 76" "Not requested,Requested" textline " " bitfld.long 0x0c 10. " TXRQST75 ,Transmission Request Bit 75" "Not requested,Requested" bitfld.long 0x0c 9. " TXRQST74 ,Transmission Request Bit 74" "Not requested,Requested" bitfld.long 0x0c 8. " TXRQST73 ,Transmission Request Bit 73" "Not requested,Requested" textline " " bitfld.long 0x0c 7. " TXRQST72 ,Transmission Request Bit 72" "Not requested,Requested" bitfld.long 0x0c 6. " TXRQST71 ,Transmission Request Bit 71" "Not requested,Requested" bitfld.long 0x0c 5. " TXRQST70 ,Transmission Request Bit 70" "Not requested,Requested" textline " " bitfld.long 0x0c 4. " TXRQST69 ,Transmission Request Bit 69" "Not requested,Requested" bitfld.long 0x0c 3. " TXRQST68 ,Transmission Request Bit 68" "Not requested,Requested" bitfld.long 0x0c 2. " TXRQST67 ,Transmission Request Bit 67" "Not requested,Requested" textline " " bitfld.long 0x0c 1. " TXRQST66 ,Transmission Request Bit 66" "Not requested,Requested" bitfld.long 0x0c 0. " TXRQST65 ,Transmission Request Bit 65" "Not requested,Requested" line.long 0x10 "DCAN_TXRQ78,Transmission Request 7_8 Register" bitfld.long 0x10 31. " TXRQST128 ,Transmission Request Bit 128" "Not requested,Requested" bitfld.long 0x10 30. " TXRQST127 ,Transmission Request Bit 127" "Not requested,Requested" bitfld.long 0x10 29. " TXRQST126 ,Transmission Request Bit 126" "Not requested,Requested" textline " " bitfld.long 0x10 28. " TXRQST125 ,Transmission Request Bit 125" "Not requested,Requested" bitfld.long 0x10 27. " TXRQST124 ,Transmission Request Bit 124" "Not requested,Requested" bitfld.long 0x10 26. " TXRQST123 ,Transmission Request Bit 123" "Not requested,Requested" textline " " bitfld.long 0x10 25. " TXRQST122 ,Transmission Request Bit 122" "Not requested,Requested" bitfld.long 0x10 24. " TXRQST121 ,Transmission Request Bit 121" "Not requested,Requested" bitfld.long 0x10 23. " TXRQST120 ,Transmission Request Bit 120" "Not requested,Requested" textline " " bitfld.long 0x10 22. " TXRQST119 ,Transmission Request Bit 119" "Not requested,Requested" bitfld.long 0x10 21. " TXRQST118 ,Transmission Request Bit 118" "Not requested,Requested" bitfld.long 0x10 20. " TXRQST117 ,Transmission Request Bit 117" "Not requested,Requested" textline " " bitfld.long 0x10 19. " TXRQST116 ,Transmission Request Bit 116" "Not requested,Requested" bitfld.long 0x10 18. " TXRQST115 ,Transmission Request Bit 115" "Not requested,Requested" bitfld.long 0x10 17. " TXRQST114 ,Transmission Request Bit 114" "Not requested,Requested" textline " " bitfld.long 0x10 16. " TXRQST113 ,Transmission Request Bit 113" "Not requested,Requested" bitfld.long 0x10 15. " TXRQST112 ,Transmission Request Bit 112" "Not requested,Requested" bitfld.long 0x10 14. " TXRQST111 ,Transmission Request Bit 111" "Not requested,Requested" textline " " bitfld.long 0x10 13. " TXRQST110 ,Transmission Request Bit 110" "Not requested,Requested" bitfld.long 0x10 12. " TXRQST109 ,Transmission Request Bit 109" "Not requested,Requested" bitfld.long 0x10 11. " TXRQST108 ,Transmission Request Bit 108" "Not requested,Requested" textline " " bitfld.long 0x10 10. " TXRQST107 ,Transmission Request Bit 107" "Not requested,Requested" bitfld.long 0x10 9. " TXRQST106 ,Transmission Request Bit 106" "Not requested,Requested" bitfld.long 0x10 8. " TXRQST105 ,Transmission Request Bit 105" "Not requested,Requested" textline " " bitfld.long 0x10 7. " TXRQST104 ,Transmission Request Bit 104" "Not requested,Requested" bitfld.long 0x10 6. " TXRQST103 ,Transmission Request Bit 103" "Not requested,Requested" bitfld.long 0x10 5. " TXRQST102 ,Transmission Request Bit 102" "Not requested,Requested" textline " " bitfld.long 0x10 4. " TXRQST101 ,Transmission Request Bit 101" "Not requested,Requested" bitfld.long 0x10 3. " TXRQST100 ,Transmission Request Bit 100" "Not requested,Requested" bitfld.long 0x10 2. " TXRQST99 ,Transmission Request Bit 99" "Not requested,Requested" textline " " bitfld.long 0x10 1. " TXRQST98 ,Transmission Request Bit 98" "Not requested,Requested" bitfld.long 0x10 0. " TXRQST97 ,Transmission Request Bit 97" "Not requested,Requested" line.long 0x14 "DCAN_NWDAT_X,New Data X Register" bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data X 8" "0,1,2,3" bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data X 7" "0,1,2,3" bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data X 6" "0,1,2,3" textline " " bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data X 5" "0,1,2,3" bitfld.long 0x14 6.--7. " NEWDATREG4 ,New Data X 4" "0,1,2,3" bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data X 3" "0,1,2,3" textline " " bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data X 2" "0,1,2,3" bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data X 1" "0,1,2,3" line.long 0x18 "DCAN_NWDAT12,New Data 1_2 Register" bitfld.long 0x18 31. " NEWDAT32 ,New Data Bit 32" "Not written,Written" bitfld.long 0x18 30. " NEWDAT31 ,New Data Bit 31" "Not written,Written" bitfld.long 0x18 29. " NEWDAT30 ,New Data Bit 30" "Not written,Written" textline " " bitfld.long 0x18 28. " NEWDAT29 ,New Data Bit 29" "Not written,Written" bitfld.long 0x18 27. " NEWDAT28 ,New Data Bit 28" "Not written,Written" bitfld.long 0x18 26. " NEWDAT27 ,New Data Bit 27" "Not written,Written" textline " " bitfld.long 0x18 25. " NEWDAT26 ,New Data Bit 26" "Not written,Written" bitfld.long 0x18 24. " NEWDAT25 ,New Data Bit 25" "Not written,Written" bitfld.long 0x18 23. " NEWDAT24 ,New Data Bit 24" "Not written,Written" textline " " bitfld.long 0x18 22. " NEWDAT23 ,New Data Bit 23" "Not written,Written" bitfld.long 0x18 21. " NEWDAT22 ,New Data Bit 22" "Not written,Written" bitfld.long 0x18 20. " NEWDAT21 ,New Data Bit 21" "Not written,Written" textline " " bitfld.long 0x18 19. " NEWDAT20 ,New Data Bit 20" "Not written,Written" bitfld.long 0x18 18. " NEWDAT19 ,New Data Bit 19" "Not written,Written" bitfld.long 0x18 17. " NEWDAT18 ,New Data Bit 18" "Not written,Written" textline " " bitfld.long 0x18 16. " NEWDAT17 ,New Data Bit 17" "Not written,Written" bitfld.long 0x18 15. " NEWDAT16 ,New Data Bit 16" "Not written,Written" bitfld.long 0x18 14. " NEWDAT15 ,New Data Bit 15" "Not written,Written" textline " " bitfld.long 0x18 13. " NEWDAT14 ,New Data Bit 14" "Not written,Written" bitfld.long 0x18 12. " NEWDAT13 ,New Data Bit 13" "Not written,Written" bitfld.long 0x18 11. " NewDat12 ,New Data Bit 12" "Not written,Written" textline " " bitfld.long 0x18 10. " NEWDAT11 ,New Data Bit 11" "Not written,Written" bitfld.long 0x18 9. " NEWDAT10 ,New Data Bit 10" "Not written,Written" bitfld.long 0x18 8. " NEWDAT9 ,New Data Bit 9" "Not written,Written" textline " " bitfld.long 0x18 7. " NEWDAT8 ,New Data Bit 8" "Not written,Written" bitfld.long 0x18 6. " NEWDAT7 ,New Data Bit 7" "Not written,Written" bitfld.long 0x18 5. " NEWDAT6 ,New Data Bit 6" "Not written,Written" textline " " bitfld.long 0x18 4. " NEWDAT5 ,New Data Bit 5" "Not written,Written" bitfld.long 0x18 3. " NEWDAT4 ,New Data Bit 4" "Not written,Written" bitfld.long 0x18 2. " NEWDAT3 ,New Data Bit 3" "Not written,Written" textline " " bitfld.long 0x18 1. " NEWDAT2 ,New Data Bit 2" "Not written,Written" bitfld.long 0x18 0. " NEWDAT1 ,New Data Bit 1" "Not written,Written" line.long 0x1c "DCAN_NWDAT34,New Data 3_4 Register" bitfld.long 0x1c 31. " NEWDAT64 ,New Data Bit 64" "Not written,Written" bitfld.long 0x1c 30. " NEWDAT63 ,New Data Bit 63" "Not written,Written" bitfld.long 0x1c 29. " NEWDAT62 ,New Data Bit 62" "Not written,Written" textline " " bitfld.long 0x1c 28. " NEWDAT61 ,New Data Bit 61" "Not written,Written" bitfld.long 0x1c 27. " NEWDAT60 ,New Data Bit 60" "Not written,Written" bitfld.long 0x1c 26. " NEWDAT59 ,New Data Bit 59" "Not written,Written" textline " " bitfld.long 0x1c 25. " NEWDAT58 ,New Data Bit 58" "Not written,Written" bitfld.long 0x1c 24. " NEWDAT57 ,New Data Bit 57" "Not written,Written" bitfld.long 0x1c 23. " NEWDAT56 ,New Data Bit 56" "Not written,Written" textline " " bitfld.long 0x1c 22. " NEWDAT55 ,New Data Bit 55" "Not written,Written" bitfld.long 0x1c 21. " NEWDAT54 ,New Data Bit 54" "Not written,Written" bitfld.long 0x1c 20. " NEWDAT53 ,New Data Bit 53" "Not written,Written" textline " " bitfld.long 0x1c 19. " NEWDAT52 ,New Data Bit 52" "Not written,Written" bitfld.long 0x1c 18. " NEWDAT51 ,New Data Bit 51" "Not written,Written" bitfld.long 0x1c 17. " NEWDAT50 ,New Data Bit 50" "Not written,Written" textline " " bitfld.long 0x1c 16. " NEWDAT49 ,New Data Bit 49" "Not written,Written" bitfld.long 0x1c 15. " NEWDAT48 ,New Data Bit 48" "Not written,Written" bitfld.long 0x1c 14. " NEWDAT47 ,New Data Bit 47" "Not written,Written" textline " " bitfld.long 0x1c 13. " NEWDAT46 ,New Data Bit 46" "Not written,Written" bitfld.long 0x1c 12. " NEWDAT45 ,New Data Bit 45" "Not written,Written" bitfld.long 0x1c 11. " NEWDAT44 ,New Data Bit 44" "Not written,Written" textline " " bitfld.long 0x1c 10. " NEWDAT43 ,New Data Bit 43" "Not written,Written" bitfld.long 0x1c 9. " NEWDAT42 ,New Data Bit 42" "Not written,Written" bitfld.long 0x1c 8. " NEWDAT41 ,New Data Bit 41" "Not written,Written" textline " " bitfld.long 0x1c 7. " NEWDAT40 ,New Data Bit 40" "Not written,Written" bitfld.long 0x1c 6. " NEWDAT39 ,New Data Bit 39" "Not written,Written" bitfld.long 0x1c 5. " NEWDAT38 ,New Data Bit 38" "Not written,Written" textline " " bitfld.long 0x1c 4. " NEWDAT37 ,New Data Bit 37" "Not written,Written" bitfld.long 0x1c 3. " NEWDAT36 ,New Data Bit 36" "Not written,Written" bitfld.long 0x1c 2. " NEWDAT35 ,New Data Bit 35" "Not written,Written" textline " " bitfld.long 0x1c 1. " NEWDAT34 ,New Data Bit 34" "Not written,Written" bitfld.long 0x1c 0. " NEWDAT33 ,New Data Bit 33" "Not written,Written" line.long 0x20 "DCAN_NWDAT56,New Data 5_6 Register" bitfld.long 0x20 31. " NEWDAT96 ,New Data Bit 96" "Not written,Written" bitfld.long 0x20 30. " NEWDAT95 ,New Data Bit 95" "Not written,Written" bitfld.long 0x20 29. " NEWDAT94 ,New Data Bit 94" "Not written,Written" textline " " bitfld.long 0x20 28. " NEWDAT93 ,New Data Bit 93" "Not written,Written" bitfld.long 0x20 27. " NEWDAT92 ,New Data Bit 92" "Not written,Written" bitfld.long 0x20 26. " NEWDAT91 ,New Data Bit 91" "Not written,Written" textline " " bitfld.long 0x20 25. " NEWDAT90 ,New Data Bit 90" "Not written,Written" bitfld.long 0x20 24. " NEWDAT89 ,New Data Bit 89" "Not written,Written" bitfld.long 0x20 23. " NEWDAT88 ,New Data Bit 88" "Not written,Written" textline " " bitfld.long 0x20 22. " NEWDAT87 ,New Data Bit 87" "Not written,Written" bitfld.long 0x20 21. " NEWDAT86 ,New Data Bit 86" "Not written,Written" bitfld.long 0x20 20. " NEWDAT85 ,New Data Bit 85" "Not written,Written" textline " " bitfld.long 0x20 19. " NEWDAT84 ,New Data Bit 84" "Not written,Written" bitfld.long 0x20 18. " NEWDAT83 ,New Data Bit 83" "Not written,Written" bitfld.long 0x20 17. " NEWDAT82 ,New Data Bit 82" "Not written,Written" textline " " bitfld.long 0x20 16. " NEWDAT81 ,New Data Bit 81" "Not written,Written" bitfld.long 0x20 15. " NEWDAT80 ,New Data Bit 80" "Not written,Written" bitfld.long 0x20 14. " NEWDAT79 ,New Data Bit 79" "Not written,Written" textline " " bitfld.long 0x20 13. " NEWDAT78 ,New Data Bit 78" "Not written,Written" bitfld.long 0x20 12. " NEWDAT77 ,New Data Bit 77" "Not written,Written" bitfld.long 0x20 11. " NEWDAT76 ,New Data Bit 76" "Not written,Written" textline " " bitfld.long 0x20 10. " NEWDAT75 ,New Data Bit 75" "Not written,Written" bitfld.long 0x20 9. " NEWDAT74 ,New Data Bit 74" "Not written,Written" bitfld.long 0x20 8. " NEWDAT73 ,New Data Bit 73" "Not written,Written" textline " " bitfld.long 0x20 7. " NEWDAT72 ,New Data Bit 72" "Not written,Written" bitfld.long 0x20 6. " NEWDAT71 ,New Data Bit 71" "Not written,Written" bitfld.long 0x20 5. " NEWDAT70 ,New Data Bit 70" "Not written,Written" textline " " bitfld.long 0x20 4. " NEWDAT69 ,New Data Bit 69" "Not written,Written" bitfld.long 0x20 3. " NEWDAT68 ,New Data Bit 68" "Not written,Written" bitfld.long 0x20 2. " NEWDAT67 ,New Data Bit 67" "Not written,Written" textline " " bitfld.long 0x20 1. " NEWDAT66 ,New Data Bit 66" "Not written,Written" bitfld.long 0x20 0. " NEWDAT65 ,New Data Bit 65" "Not written,Written" line.long 0x24 "DCAN_NWDAT78,New Data 7_8 Register" bitfld.long 0x24 31. " NEWDAT128 ,New Data Bit 128" "Not written,Written" bitfld.long 0x24 30. " NEWDAT127 ,New Data Bit 127" "Not written,Written" bitfld.long 0x24 29. " NEWDAT126 ,New Data Bit 126" "Not written,Written" textline " " bitfld.long 0x24 28. " NEWDAT125 ,New Data Bit 125" "Not written,Written" bitfld.long 0x24 27. " NEWDAT124 ,New Data Bit 124" "Not written,Written" bitfld.long 0x24 26. " NEWDAT123 ,New Data Bit 123" "Not written,Written" textline " " bitfld.long 0x24 25. " NEWDAT122 ,New Data Bit 122" "Not written,Written" bitfld.long 0x24 24. " NEWDAT121 ,New Data Bit 121" "Not written,Written" bitfld.long 0x24 23. " NEWDAT120 ,New Data Bit 120" "Not written,Written" textline " " bitfld.long 0x24 22. " NEWDAT119 ,New Data Bit 119" "Not written,Written" bitfld.long 0x24 21. " NEWDAT118 ,New Data Bit 118" "Not written,Written" bitfld.long 0x24 20. " NEWDAT117 ,New Data Bit 117" "Not written,Written" textline " " bitfld.long 0x24 19. " NEWDAT116 ,New Data Bit 116" "Not written,Written" bitfld.long 0x24 18. " NEWDAT115 ,New Data Bit 115" "Not written,Written" bitfld.long 0x24 17. " NEWDAT114 ,New Data Bit 114" "Not written,Written" textline " " bitfld.long 0x24 16. " NEWDAT113 ,New Data Bit 113" "Not written,Written" bitfld.long 0x24 15. " NEWDAT112 ,New Data Bit 112" "Not written,Written" bitfld.long 0x24 14. " NEWDAT111 ,New Data Bit 111" "Not written,Written" textline " " bitfld.long 0x24 13. " NEWDAT110 ,New Data Bit 110" "Not written,Written" bitfld.long 0x24 12. " NEWDAT109 ,New Data Bit 109" "Not written,Written" bitfld.long 0x24 11. " NEWDAT108 ,New Data Bit 108" "Not written,Written" textline " " bitfld.long 0x24 10. " NEWDAT107 ,New Data Bit 107" "Not written,Written" bitfld.long 0x24 9. " NEWDAT106 ,New Data Bit 106" "Not written,Written" bitfld.long 0x24 8. " NEWDAT105 ,New Data Bit 105" "Not written,Written" textline " " bitfld.long 0x24 7. " NEWDAT104 ,New Data Bit 104" "Not written,Written" bitfld.long 0x24 6. " NEWDAT103 ,New Data Bit 103" "Not written,Written" bitfld.long 0x24 5. " NEWDAT102 ,New Data Bit 102" "Not written,Written" textline " " bitfld.long 0x24 4. " NEWDAT101 ,New Data Bit 101" "Not written,Written" bitfld.long 0x24 3. " NEWDAT100 ,New Data Bit 100" "Not written,Written" bitfld.long 0x24 2. " NEWDAT99 ,New Data Bit 99" "Not written,Written" textline " " bitfld.long 0x24 1. " NEWDAT98 ,New Data Bit 98" "Not written,Written" bitfld.long 0x24 0. " NEWDAT97 ,New Data Bit 97" "Not written,Written" line.long 0x28 "DCAN_INTPND_X,Interrupt Pending X Register" bitfld.long 0x28 14.--15. " INTPNDREG8 ,Interrupt Pending X Register 8" "0,1,2,3" bitfld.long 0x28 12.--13. " INTPNDREG7 ,Interrupt Pending X Register 7" "0,1,2,3" bitfld.long 0x28 10.--11. " INTPNDREG6 ,Interrupt Pending X Register 6" "0,1,2,3" textline " " bitfld.long 0x28 8.--9. " INTPNDREG5 ,Interrupt Pending X Register 5" "0,1,2,3" bitfld.long 0x28 6.--7. " INTPNDREG4 ,Interrupt Pending X Register 4" "0,1,2,3" bitfld.long 0x28 4.--5. " INTPNDREG3 ,Interrupt Pending X Register 3" "0,1,2,3" textline " " bitfld.long 0x28 2.--3. " INTPNDREG2 ,Interrupt Pending X Register 2" "0,1,2,3" bitfld.long 0x28 0.--1. " INTPNDREG1 ,Interrupt Pending X Register 1" "0,1,2,3" line.long 0x2C "DCAN_INTPND12,Interrupt Pending 1_2 Register" bitfld.long 0x2c 31. " INTPND32 ,Interrupt Pending Bit 32" "Not pending,Pending" bitfld.long 0x2c 30. " INTPND31 ,Interrupt Pending Bit 31" "Not pending,Pending" bitfld.long 0x2c 29. " INTPND30 ,Interrupt Pending Bit 30" "Not pending,Pending" textline " " bitfld.long 0x2c 28. " INTPND29 ,Interrupt Pending Bit 29" "Not pending,Pending" bitfld.long 0x2c 27. " INTPND28 ,Interrupt Pending Bit 28" "Not pending,Pending" bitfld.long 0x2c 26. " INTPND27 ,Interrupt Pending Bit 27" "Not pending,Pending" textline " " bitfld.long 0x2c 25. " INTPND26 ,Interrupt Pending Bit 26" "Not pending,Pending" bitfld.long 0x2c 24. " INTPND25 ,Interrupt Pending Bit 25" "Not pending,Pending" bitfld.long 0x2c 23. " INTPND24 ,Interrupt Pending Bit 24" "Not pending,Pending" textline " " bitfld.long 0x2c 22. " INTPND23 ,Interrupt Pending Bit 23" "Not pending,Pending" bitfld.long 0x2c 21. " INTPND22 ,Interrupt Pending Bit 22" "Not pending,Pending" bitfld.long 0x2c 20. " INTPND21 ,Interrupt Pending Bit 21" "Not pending,Pending" textline " " bitfld.long 0x2c 19. " INTPND20 ,Interrupt Pending Bit 20" "Not pending,Pending" bitfld.long 0x2c 18. " INTPND19 ,Interrupt Pending Bit 19" "Not pending,Pending" bitfld.long 0x2c 17. " INTPND18 ,Interrupt Pending Bit 18" "Not pending,Pending" textline " " bitfld.long 0x2c 16. " INTPND17 ,Interrupt Pending Bit 17" "Not pending,Pending" bitfld.long 0x2c 15. " INTPND16 ,Interrupt Pending Bit 16" "Not pending,Pending" bitfld.long 0x2c 14. " INTPND15 ,Interrupt Pending Bit 15" "Not pending,Pending" textline " " bitfld.long 0x2c 13. " INTPND14 ,Interrupt Pending Bit 14" "Not pending,Pending" bitfld.long 0x2c 12. " INTPND13 ,Interrupt Pending Bit 13" "Not pending,Pending" bitfld.long 0x2c 11. " INTPND12 ,Interrupt Pending Bit 12" "Not pending,Pending" textline " " bitfld.long 0x2c 10. " INTPND11 ,Interrupt Pending Bit 11" "Not pending,Pending" bitfld.long 0x2c 9. " INTPND10 ,Interrupt Pending Bit 10" "Not pending,Pending" bitfld.long 0x2c 8. " INTPND9 ,Interrupt Pending Bit 9" "Not pending,Pending" textline " " bitfld.long 0x2c 7. " INTPND8 ,Interrupt Pending Bit 8" "Not pending,Pending" bitfld.long 0x2c 6. " INTPND7 ,Interrupt Pending Bit 7" "Not pending,Pending" bitfld.long 0x2c 5. " INTPND6 ,Interrupt Pending Bit 6" "Not pending,Pending" textline " " bitfld.long 0x2c 4. " INTPND5 ,Interrupt Pending Bit 5" "Not pending,Pending" bitfld.long 0x2c 3. " INTPND4 ,Interrupt Pending Bit 4" "Not pending,Pending" bitfld.long 0x2c 2. " INTPND3 ,Interrupt Pending Bit 3" "Not pending,Pending" textline " " bitfld.long 0x2c 1. " INTPND2 ,Interrupt Pending Bit 2" "Not pending,Pending" bitfld.long 0x2c 0. " INTPND1 ,Interrupt Pending Bit 1" "Not pending,Pending" line.long 0x30 "DCAN_INTPND34,Interrupt Pending 3_4 Register" bitfld.long 0x30 31. " INTPND64 ,Interrupt Pending Bit 64" "Not pending,Pending" bitfld.long 0x30 30. " INTPND63 ,Interrupt Pending Bit 63" "Not pending,Pending" bitfld.long 0x30 29. " INTPND62 ,Interrupt Pending Bit 62" "Not pending,Pending" textline " " bitfld.long 0x30 28. " INTPND61 ,Interrupt Pending Bit 61" "Not pending,Pending" bitfld.long 0x30 27. " INTPND60 ,Interrupt Pending Bit 60" "Not pending,Pending" bitfld.long 0x30 26. " INTPND59 ,Interrupt Pending Bit 59" "Not pending,Pending" textline " " bitfld.long 0x30 25. " INTPND58 ,Interrupt Pending Bit 58" "Not pending,Pending" bitfld.long 0x30 24. " INTPND57 ,Interrupt Pending Bit 57" "Not pending,Pending" bitfld.long 0x30 23. " INTPND56 ,Interrupt Pending Bit 56" "Not pending,Pending" textline " " bitfld.long 0x30 22. " INTPND55 ,Interrupt Pending Bit 55" "Not pending,Pending" bitfld.long 0x30 21. " INTPND54 ,Interrupt Pending Bit 54" "Not pending,Pending" bitfld.long 0x30 20. " INTPND53 ,Interrupt Pending Bit 53" "Not pending,Pending" textline " " bitfld.long 0x30 19. " INTPND52 ,Interrupt Pending Bit 52" "Not pending,Pending" bitfld.long 0x30 18. " INTPND51 ,Interrupt Pending Bit 51" "Not pending,Pending" bitfld.long 0x30 17. " INTPND50 ,Interrupt Pending Bit 50" "Not pending,Pending" textline " " bitfld.long 0x30 16. " INTPND49 ,Interrupt Pending Bit 49" "Not pending,Pending" bitfld.long 0x30 15. " INTPND48 ,Interrupt Pending Bit 48" "Not pending,Pending" bitfld.long 0x30 14. " INTPND47 ,Interrupt Pending Bit 47" "Not pending,Pending" textline " " bitfld.long 0x30 13. " INTPND46 ,Interrupt Pending Bit 46" "Not pending,Pending" bitfld.long 0x30 12. " INTPND45 ,Interrupt Pending Bit 45" "Not pending,Pending" bitfld.long 0x30 11. " INTPND44 ,Interrupt Pending Bit 44" "Not pending,Pending" textline " " bitfld.long 0x30 10. " INTPND43 ,Interrupt Pending Bit 43" "Not pending,Pending" bitfld.long 0x30 9. " INTPND42 ,Interrupt Pending Bit 42" "Not pending,Pending" bitfld.long 0x30 8. " INTPND41 ,Interrupt Pending Bit 41" "Not pending,Pending" textline " " bitfld.long 0x30 7. " INTPND40 ,Interrupt Pending Bit 40" "Not pending,Pending" bitfld.long 0x30 6. " INTPND39 ,Interrupt Pending Bit 39" "Not pending,Pending" bitfld.long 0x30 5. " INTPND38 ,Interrupt Pending Bit 38" "Not pending,Pending" textline " " bitfld.long 0x30 4. " INTPND37 ,Interrupt Pending Bit 37" "Not pending,Pending" bitfld.long 0x30 3. " INTPND36 ,Interrupt Pending Bit 36" "Not pending,Pending" bitfld.long 0x30 2. " INTPND35 ,Interrupt Pending Bit 35" "Not pending,Pending" textline " " bitfld.long 0x30 1. " INTPND34 ,Interrupt Pending Bit 34" "Not pending,Pending" bitfld.long 0x30 0. " INTPND33 ,Interrupt Pending Bit 33" "Not pending,Pending" line.long 0x34 "DCAN_INTPND56,Interrupt Pending 5_6 Register" bitfld.long 0x34 31. " INTPND96 ,Interrupt Pending Bit 96" "Not pending,Pending" bitfld.long 0x34 30. " INTPND95 ,Interrupt Pending Bit 95" "Not pending,Pending" bitfld.long 0x34 29. " INTPND94 ,Interrupt Pending Bit 94" "Not pending,Pending" textline " " bitfld.long 0x34 28. " INTPND93 ,Interrupt Pending Bit 93" "Not pending,Pending" bitfld.long 0x34 27. " INTPND92 ,Interrupt Pending Bit 92" "Not pending,Pending" bitfld.long 0x34 26. " INTPND91 ,Interrupt Pending Bit 91" "Not pending,Pending" textline " " bitfld.long 0x34 25. " INTPND90 ,Interrupt Pending Bit 90" "Not pending,Pending" bitfld.long 0x34 24. " INTPND89 ,Interrupt Pending Bit 89" "Not pending,Pending" bitfld.long 0x34 23. " INTPND88 ,Interrupt Pending Bit 88" "Not pending,Pending" textline " " bitfld.long 0x34 22. " INTPND87 ,Interrupt Pending Bit 87" "Not pending,Pending" bitfld.long 0x34 21. " INTPND86 ,Interrupt Pending Bit 86" "Not pending,Pending" bitfld.long 0x34 20. " INTPND85 ,Interrupt Pending Bit 85" "Not pending,Pending" textline " " bitfld.long 0x34 19. " INTPND84 ,Interrupt Pending Bit 84" "Not pending,Pending" bitfld.long 0x34 18. " INTPND83 ,Interrupt Pending Bit 83" "Not pending,Pending" bitfld.long 0x34 17. " INTPND82 ,Interrupt Pending Bit 82" "Not pending,Pending" textline " " bitfld.long 0x34 16. " INTPND81 ,Interrupt Pending Bit 81" "Not pending,Pending" bitfld.long 0x34 15. " INTPND80 ,Interrupt Pending Bit 80" "Not pending,Pending" bitfld.long 0x34 14. " INTPND79 ,Interrupt Pending Bit 79" "Not pending,Pending" textline " " bitfld.long 0x34 13. " INTPND78 ,Interrupt Pending Bit 78" "Not pending,Pending" bitfld.long 0x34 12. " INTPND77 ,Interrupt Pending Bit 77" "Not pending,Pending" bitfld.long 0x34 11. " INTPND76 ,Interrupt Pending Bit 76" "Not pending,Pending" textline " " bitfld.long 0x34 10. " INTPND75 ,Interrupt Pending Bit 75" "Not pending,Pending" bitfld.long 0x34 9. " INTPND74 ,Interrupt Pending Bit 74" "Not pending,Pending" bitfld.long 0x34 8. " INTPND73 ,Interrupt Pending Bit 73" "Not pending,Pending" textline " " bitfld.long 0x34 7. " INTPND72 ,Interrupt Pending Bit 72" "Not pending,Pending" bitfld.long 0x34 6. " INTPND71 ,Interrupt Pending Bit 71" "Not pending,Pending" bitfld.long 0x34 5. " INTPND70 ,Interrupt Pending Bit 70" "Not pending,Pending" textline " " bitfld.long 0x34 4. " INTPND69 ,Interrupt Pending Bit 69" "Not pending,Pending" bitfld.long 0x34 3. " INTPND68 ,Interrupt Pending Bit 68" "Not pending,Pending" bitfld.long 0x34 2. " INTPND67 ,Interrupt Pending Bit 67" "Not pending,Pending" textline " " bitfld.long 0x34 1. " INTPND66 ,Interrupt Pending Bit 66" "Not pending,Pending" bitfld.long 0x34 0. " INTPND65 ,Interrupt Pending Bit 65" "Not pending,Pending" line.long 0x38 "DCAN_INTPND78,Interrupt Pending 7_8 Register" bitfld.long 0x38 31. " INTPND128 ,Interrupt Pending Bit 128" "Not pending,Pending" bitfld.long 0x38 30. " INTPND127 ,Interrupt Pending Bit 127" "Not pending,Pending" bitfld.long 0x38 29. " INTPND126 ,Interrupt Pending Bit 126" "Not pending,Pending" textline " " bitfld.long 0x38 28. " INTPND125 ,Interrupt Pending Bit 125" "Not pending,Pending" bitfld.long 0x38 27. " INTPND124 ,Interrupt Pending Bit 124" "Not pending,Pending" bitfld.long 0x38 26. " INTPND123 ,Interrupt Pending Bit 123" "Not pending,Pending" textline " " bitfld.long 0x38 25. " INTPND122 ,Interrupt Pending Bit 122" "Not pending,Pending" bitfld.long 0x38 24. " INTPND121 ,Interrupt Pending Bit 121" "Not pending,Pending" bitfld.long 0x38 23. " INTPND120 ,Interrupt Pending Bit 120" "Not pending,Pending" textline " " bitfld.long 0x38 22. " INTPND119 ,Interrupt Pending Bit 119" "Not pending,Pending" bitfld.long 0x38 21. " INTPND118 ,Interrupt Pending Bit 118" "Not pending,Pending" bitfld.long 0x38 20. " INTPND117 ,Interrupt Pending Bit 117" "Not pending,Pending" textline " " bitfld.long 0x38 19. " INTPND116 ,Interrupt Pending Bit 116" "Not pending,Pending" bitfld.long 0x38 18. " INTPND115 ,Interrupt Pending Bit 115" "Not pending,Pending" bitfld.long 0x38 17. " INTPND114 ,Interrupt Pending Bit 114" "Not pending,Pending" textline " " bitfld.long 0x38 16. " INTPND113 ,Interrupt Pending Bit 113" "Not pending,Pending" bitfld.long 0x38 15. " INTPND112 ,Interrupt Pending Bit 112" "Not pending,Pending" bitfld.long 0x38 14. " INTPND111 ,Interrupt Pending Bit 111" "Not pending,Pending" textline " " bitfld.long 0x38 13. " INTPND110 ,Interrupt Pending Bit 110" "Not pending,Pending" bitfld.long 0x38 12. " INTPND109 ,Interrupt Pending Bit 109" "Not pending,Pending" bitfld.long 0x38 11. " INTPND108 ,Interrupt Pending Bit 108" "Not pending,Pending" textline " " bitfld.long 0x38 10. " INTPND107 ,Interrupt Pending Bit 107" "Not pending,Pending" bitfld.long 0x38 9. " INTPND106 ,Interrupt Pending Bit 106" "Not pending,Pending" bitfld.long 0x38 8. " INTPND105 ,Interrupt Pending Bit 105" "Not pending,Pending" textline " " bitfld.long 0x38 7. " INTPND104 ,Interrupt Pending Bit 104" "Not pending,Pending" bitfld.long 0x38 6. " INTPND103 ,Interrupt Pending Bit 103" "Not pending,Pending" bitfld.long 0x38 5. " INTPND102 ,Interrupt Pending Bit 102" "Not pending,Pending" textline " " bitfld.long 0x38 4. " INTPND101 ,Interrupt Pending Bit 101" "Not pending,Pending" bitfld.long 0x38 3. " INTPND100 ,Interrupt Pending Bit 100" "Not pending,Pending" bitfld.long 0x38 2. " INTPND99 ,Interrupt Pending Bit 99" "Not pending,Pending" textline " " bitfld.long 0x38 1. " INTPND98 ,Interrupt Pending Bit 98" "Not pending,Pending" bitfld.long 0x38 0. " INTPND97 ,Interrupt Pending Bit 97" "Not pending,Pending" line.long 0x3c "DCAN_MSGVAL_X,Message Valid X Register" bitfld.long 0x3c 14.--15. " MSGVALREG8 ,Message Valid X Register 8" "0,1,2,3" bitfld.long 0x3c 12.--13. " MSGVALREG7 ,Message Valid X Register 7" "0,1,2,3" bitfld.long 0x3c 10.--11. " MSGVALREG6 ,Message Valid X Register 6" "0,1,2,3" textline " " bitfld.long 0x3c 8.--9. " MSGVALREG5 ,Message Valid X Register 5" "0,1,2,3" bitfld.long 0x3c 6.--7. " MSGVALREG4 ,Message Valid X Register 4" "0,1,2,3" bitfld.long 0x3c 4.--5. " MSGVALREG3 ,Message Valid X Register 3" "0,1,2,3" textline " " bitfld.long 0x3c 2.--3. " MSGVALREG2 ,Message Valid X Register 2" "0,1,2,3" bitfld.long 0x3c 0.--1. " MSGVALREG1 ,Message Valid X Register 1" "0,1,2,3" line.long 0x40 "DCAN_MSGVAL12,Message Valid 1_2 Register" bitfld.long 0x40 31. " MSGVAL32 ,Message Valid Bit 32" "Ignored,Not ignored" bitfld.long 0x40 30. " MSGVAL31 ,Message Valid Bit 31" "Ignored,Not ignored" bitfld.long 0x40 29. " MSGVAL30 ,Message Valid Bit 30" "Ignored,Not ignored" textline " " bitfld.long 0x40 28. " MSGVAL29 ,Message Valid Bit 29" "Ignored,Not ignored" bitfld.long 0x40 27. " MSGVAL28 ,Message Valid Bit 28" "Ignored,Not ignored" bitfld.long 0x40 26. " MSGVAL27 ,Message Valid Bit 27" "Ignored,Not ignored" textline " " bitfld.long 0x40 25. " MSGVAL26 ,Message Valid Bit 26" "Ignored,Not ignored" bitfld.long 0x40 24. " MSGVAL25 ,Message Valid Bit 25" "Ignored,Not ignored" bitfld.long 0x40 23. " MSGVAL24 ,Message Valid Bit 24" "Ignored,Not ignored" textline " " bitfld.long 0x40 22. " MSGVAL23 ,Message Valid Bit 23" "Ignored,Not ignored" bitfld.long 0x40 21. " MSGVAL22 ,Message Valid Bit 22" "Ignored,Not ignored" bitfld.long 0x40 20. " MSGVAL21 ,Message Valid Bit 21" "Ignored,Not ignored" textline " " bitfld.long 0x40 19. " MSGVAL20 ,Message Valid Bit 20" "Ignored,Not ignored" bitfld.long 0x40 18. " MSGVAL19 ,Message Valid Bit 19" "Ignored,Not ignored" bitfld.long 0x40 17. " MSGVAL18 ,Message Valid Bit 18" "Ignored,Not ignored" textline " " bitfld.long 0x40 16. " MSGVAL17 ,Message Valid Bit 17" "Ignored,Not ignored" bitfld.long 0x40 15. " MSGVAL16 ,Message Valid Bit 16" "Ignored,Not ignored" bitfld.long 0x40 14. " MSGVAL15 ,Message Valid Bit 15" "Ignored,Not ignored" textline " " bitfld.long 0x40 13. " MSGVAL14 ,Message Valid Bit 14" "Ignored,Not ignored" bitfld.long 0x40 12. " MSGVAL13 ,Message Valid Bit 13" "Ignored,Not ignored" bitfld.long 0x40 11. " MSGVAL12 ,Message Valid Bit 12" "Ignored,Not ignored" textline " " bitfld.long 0x40 10. " MSGVAL11 ,Message Valid Bit 11" "Ignored,Not ignored" bitfld.long 0x40 9. " MSGVAL10 ,Message Valid Bit 10" "Ignored,Not ignored" bitfld.long 0x40 8. " MSGVAL9 ,Message Valid Bit 9" "Ignored,Not ignored" textline " " bitfld.long 0x40 7. " MSGVAL8 ,Message Valid Bit 8" "Ignored,Not ignored" bitfld.long 0x40 6. " MSGVAL7 ,Message Valid Bit 7" "Ignored,Not ignored" bitfld.long 0x40 5. " MSGVAL6 ,Message Valid Bit 6" "Ignored,Not ignored" textline " " bitfld.long 0x40 4. " MSGVAL5 ,Message Valid Bit 5" "Ignored,Not ignored" bitfld.long 0x40 3. " MSGVAL4 ,Message Valid Bit 4" "Ignored,Not ignored" bitfld.long 0x40 2. " MSGVAL3 ,Message Valid Bit 3" "Ignored,Not ignored" textline " " bitfld.long 0x40 1. " MSGVAL2 ,Message Valid Bit 2" "Ignored,Not ignored" bitfld.long 0x40 0. " MSGVAL1 ,Message Valid Bit 1" "Ignored,Not ignored" line.long 0x44 "DCAN_MSGVAL34,Message Valid 3_4 Register" bitfld.long 0x44 31. " MSGVAL64 ,Message Valid Bit 64" "Ignored,Not ignored" bitfld.long 0x44 30. " MSGVAL63 ,Message Valid Bit 63" "Ignored,Not ignored" bitfld.long 0x44 29. " MSGVAL62 ,Message Valid Bit 62" "Ignored,Not ignored" textline " " bitfld.long 0x44 28. " MSGVAL61 ,Message Valid Bit 61" "Ignored,Not ignored" bitfld.long 0x44 27. " MSGVAL60 ,Message Valid Bit 60" "Ignored,Not ignored" bitfld.long 0x44 26. " MSGVAL59 ,Message Valid Bit 59" "Ignored,Not ignored" textline " " bitfld.long 0x44 25. " MSGVAL58 ,Message Valid Bit 58" "Ignored,Not ignored" bitfld.long 0x44 24. " MSGVAL57 ,Message Valid Bit 57" "Ignored,Not ignored" bitfld.long 0x44 23. " MSGVAL56 ,Message Valid Bit 56" "Ignored,Not ignored" textline " " bitfld.long 0x44 22. " MSGVAL55 ,Message Valid Bit 55" "Ignored,Not ignored" bitfld.long 0x44 21. " MSGVAL54 ,Message Valid Bit 54" "Ignored,Not ignored" bitfld.long 0x44 20. " MSGVAL53 ,Message Valid Bit 53" "Ignored,Not ignored" textline " " bitfld.long 0x44 19. " MSGVAL52 ,Message Valid Bit 52" "Ignored,Not ignored" bitfld.long 0x44 18. " MSGVAL51 ,Message Valid Bit 51" "Ignored,Not ignored" bitfld.long 0x44 17. " MSGVAL50 ,Message Valid Bit 50" "Ignored,Not ignored" textline " " bitfld.long 0x44 16. " MSGVAL49 ,Message Valid Bit 49" "Ignored,Not ignored" bitfld.long 0x44 15. " MSGVAL48 ,Message Valid Bit 48" "Ignored,Not ignored" bitfld.long 0x44 14. " MSGVAL47 ,Message Valid Bit 47" "Ignored,Not ignored" textline " " bitfld.long 0x44 13. " MSGVAL46 ,Message Valid Bit 46" "Ignored,Not ignored" bitfld.long 0x44 12. " MSGVAL45 ,Message Valid Bit 45" "Ignored,Not ignored" bitfld.long 0x44 11. " MSGVAL44 ,Message Valid Bit 44" "Ignored,Not ignored" textline " " bitfld.long 0x44 10. " MSGVAL43 ,Message Valid Bit 43" "Ignored,Not ignored" bitfld.long 0x44 9. " MSGVAL42 ,Message Valid Bit 42" "Ignored,Not ignored" bitfld.long 0x44 8. " MSGVAL41 ,Message Valid Bit 41" "Ignored,Not ignored" textline " " bitfld.long 0x44 7. " MSGVAL40 ,Message Valid Bit 40" "Ignored,Not ignored" bitfld.long 0x44 6. " MSGVAL39 ,Message Valid Bit 39" "Ignored,Not ignored" bitfld.long 0x44 5. " MSGVAL38 ,Message Valid Bit 38" "Ignored,Not ignored" textline " " bitfld.long 0x44 4. " MSGVAL37 ,Message Valid Bit 37" "Ignored,Not ignored" bitfld.long 0x44 3. " MSGVAL36 ,Message Valid Bit 36" "Ignored,Not ignored" bitfld.long 0x44 2. " MSGVAL35 ,Message Valid Bit 35" "Ignored,Not ignored" textline " " bitfld.long 0x44 1. " MSGVAL34 ,Message Valid Bit 34" "Ignored,Not ignored" bitfld.long 0x44 0. " MSGVAL33 ,Message Valid Bit 33" "Ignored,Not ignored" line.long 0x48 "DCAN_MSGVAL56,Message Valid 5_6 Register" bitfld.long 0x48 31. " MSGVAL96 ,Message Valid Bit 96" "Ignored,Not ignored" bitfld.long 0x48 30. " MSGVAL95 ,Message Valid Bit 95" "Ignored,Not ignored" bitfld.long 0x48 29. " MSGVAL94 ,Message Valid Bit 94" "Ignored,Not ignored" textline " " bitfld.long 0x48 28. " MSGVAL93 ,Message Valid Bit 93" "Ignored,Not ignored" bitfld.long 0x48 27. " MSGVAL92 ,Message Valid Bit 92" "Ignored,Not ignored" bitfld.long 0x48 26. " MSGVAL91 ,Message Valid Bit 91" "Ignored,Not ignored" textline " " bitfld.long 0x48 25. " MSGVAL90 ,Message Valid Bit 90" "Ignored,Not ignored" bitfld.long 0x48 24. " MSGVAL89 ,Message Valid Bit 89" "Ignored,Not ignored" bitfld.long 0x48 23. " MSGVAL88 ,Message Valid Bit 88" "Ignored,Not ignored" textline " " bitfld.long 0x48 22. " MSGVAL87 ,Message Valid Bit 87" "Ignored,Not ignored" bitfld.long 0x48 21. " MSGVAL86 ,Message Valid Bit 86" "Ignored,Not ignored" bitfld.long 0x48 20. " MSGVAL85 ,Message Valid Bit 85" "Ignored,Not ignored" textline " " bitfld.long 0x48 19. " MSGVAL84 ,Message Valid Bit 84" "Ignored,Not ignored" bitfld.long 0x48 18. " MSGVAL83 ,Message Valid Bit 83" "Ignored,Not ignored" bitfld.long 0x48 17. " MSGVAL82 ,Message Valid Bit 82" "Ignored,Not ignored" textline " " bitfld.long 0x48 16. " MSGVAL81 ,Message Valid Bit 81" "Ignored,Not ignored" bitfld.long 0x48 15. " MSGVAL80 ,Message Valid Bit 80" "Ignored,Not ignored" bitfld.long 0x48 14. " MSGVAL79 ,Message Valid Bit 79" "Ignored,Not ignored" textline " " bitfld.long 0x48 13. " MSGVAL78 ,Message Valid Bit 78" "Ignored,Not ignored" bitfld.long 0x48 12. " MSGVAL77 ,Message Valid Bit 77" "Ignored,Not ignored" bitfld.long 0x48 11. " MSGVAL76 ,Message Valid Bit 76" "Ignored,Not ignored" textline " " bitfld.long 0x48 10. " MSGVAL75 ,Message Valid Bit 75" "Ignored,Not ignored" bitfld.long 0x48 9. " MSGVAL74 ,Message Valid Bit 74" "Ignored,Not ignored" bitfld.long 0x48 8. " MSGVAL73 ,Message Valid Bit 73" "Ignored,Not ignored" textline " " bitfld.long 0x48 7. " MSGVAL72 ,Message Valid Bit 72" "Ignored,Not ignored" bitfld.long 0x48 6. " MSGVAL71 ,Message Valid Bit 71" "Ignored,Not ignored" bitfld.long 0x48 5. " MSGVAL70 ,Message Valid Bit 70" "Ignored,Not ignored" textline " " bitfld.long 0x48 4. " MSGVAL69 ,Message Valid Bit 69" "Ignored,Not ignored" bitfld.long 0x48 3. " MSGVAL68 ,Message Valid Bit 68" "Ignored,Not ignored" bitfld.long 0x48 2. " MSGVAL67 ,Message Valid Bit 67" "Ignored,Not ignored" textline " " bitfld.long 0x48 1. " MSGVAL66 ,Message Valid Bit 66" "Ignored,Not ignored" bitfld.long 0x48 0. " MSGVAL65 ,Message Valid Bit 65" "Ignored,Not ignored" line.long 0x4C "DCAN_MSGVAL78,Message Valid 7_8 Register" bitfld.long 0x4C 31. " MSGVAL128 ,Message Valid Bit 128" "Ignored,Not ignored" bitfld.long 0x4C 30. " MSGVAL127 ,Message Valid Bit 127" "Ignored,Not ignored" bitfld.long 0x4C 29. " MSGVAL126 ,Message Valid Bit 126" "Ignored,Not ignored" textline " " bitfld.long 0x4C 28. " MSGVAL125 ,Message Valid Bit 125" "Ignored,Not ignored" bitfld.long 0x4C 27. " MSGVAL124 ,Message Valid Bit 124" "Ignored,Not ignored" bitfld.long 0x4C 26. " MSGVAL123 ,Message Valid Bit 123" "Ignored,Not ignored" textline " " bitfld.long 0x4C 25. " MSGVAL122 ,Message Valid Bit 122" "Ignored,Not ignored" bitfld.long 0x4C 24. " MSGVAL121 ,Message Valid Bit 121" "Ignored,Not ignored" bitfld.long 0x4C 23. " MSGVAL120 ,Message Valid Bit 120" "Ignored,Not ignored" textline " " bitfld.long 0x4C 22. " MSGVAL119 ,Message Valid Bit 119" "Ignored,Not ignored" bitfld.long 0x4C 21. " MSGVAL118 ,Message Valid Bit 118" "Ignored,Not ignored" bitfld.long 0x4C 20. " MSGVAL117 ,Message Valid Bit 117" "Ignored,Not ignored" textline " " bitfld.long 0x4C 19. " MSGVAL116 ,Message Valid Bit 116" "Ignored,Not ignored" bitfld.long 0x4C 18. " MSGVAL115 ,Message Valid Bit 115" "Ignored,Not ignored" bitfld.long 0x4C 17. " MSGVAL114 ,Message Valid Bit 114" "Ignored,Not ignored" textline " " bitfld.long 0x4C 16. " MSGVAL113 ,Message Valid Bit 113" "Ignored,Not ignored" bitfld.long 0x4C 15. " MSGVAL112 ,Message Valid Bit 112" "Ignored,Not ignored" bitfld.long 0x4C 14. " MSGVAL111 ,Message Valid Bit 111" "Ignored,Not ignored" textline " " bitfld.long 0x4C 13. " MSGVAL110 ,Message Valid Bit 110" "Ignored,Not ignored" bitfld.long 0x4C 12. " MSGVAL109 ,Message Valid Bit 109" "Ignored,Not ignored" bitfld.long 0x4C 11. " MSGVAL108 ,Message Valid Bit 108" "Ignored,Not ignored" textline " " bitfld.long 0x4C 10. " MSGVAL107 ,Message Valid Bit 107" "Ignored,Not ignored" bitfld.long 0x4C 9. " MSGVAL106 ,Message Valid Bit 106" "Ignored,Not ignored" bitfld.long 0x4C 8. " MSGVAL105 ,Message Valid Bit 105" "Ignored,Not ignored" textline " " bitfld.long 0x4C 7. " MSGVAL104 ,Message Valid Bit 104" "Ignored,Not ignored" bitfld.long 0x4C 6. " MSGVAL103 ,Message Valid Bit 103" "Ignored,Not ignored" bitfld.long 0x4C 5. " MSGVAL102 ,Message Valid Bit 102" "Ignored,Not ignored" textline " " bitfld.long 0x4C 4. " MSGVAL101 ,Message Valid Bit 101" "Ignored,Not ignored" bitfld.long 0x4C 3. " MSGVAL100 ,Message Valid Bit 100" "Ignored,Not ignored" bitfld.long 0x4C 2. " MSGVAL99 ,Message Valid Bit 99" "Ignored,Not ignored" textline " " bitfld.long 0x4C 1. " MSGVAL98 ,Message Valid Bit 98" "Ignored,Not ignored" bitfld.long 0x4C 0. " MSGVAL97 ,Message Valid Bit 97" "Ignored,Not ignored" group.long 0xD8--0xE7 sif (cpuis("DRA62*")) line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer 1_2 Register" bitfld.long 0x00 31. " INTMUX32 ,Multiplexes IntPnd value to one of two interrupt line 32" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX31 ,Multiplexes IntPnd value to one of two interrupt line 31" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX30 ,Multiplexes IntPnd value to one of two interrupt line 30" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 28. " INTMUX29 ,Multiplexes IntPnd value to one of two interrupt line 29" "DCAN0INT,DCAN1INT" bitfld.long 0x00 27. " INTMUX28 ,Multiplexes IntPnd value to one of two interrupt line 28" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX27 ,Multiplexes IntPnd value to one of two interrupt line 27" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTMUX26 ,Multiplexes IntPnd value to one of two interrupt line 26" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX25 ,Multiplexes IntPnd value to one of two interrupt line 25" "DCAN0INT,DCAN1INT" bitfld.long 0x00 23. " INTMUX24 ,Multiplexes IntPnd value to one of two interrupt line 24" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 22. " INTMUX23 ,Multiplexes IntPnd value to one of two interrupt line 23" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX22 ,Multiplexes IntPnd value to one of two interrupt line 22" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX21 ,Multiplexes IntPnd value to one of two interrupt line 21" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX20 ,Multiplexes IntPnd value to one of two interrupt line 20" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX19 ,Multiplexes IntPnd value to one of two interrupt line 19" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX18 ,Multiplexes IntPnd value to one of two interrupt line 18" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 16. " INTMUX17 ,Multiplexes IntPnd value to one of two interrupt line 17" "DCAN0INT,DCAN1INT" bitfld.long 0x00 15. " INTMUX16 ,Multiplexes IntPnd value to one of two interrupt line 16" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX15 ,Multiplexes IntPnd value to one of two interrupt line 15" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTMUX14 ,Multiplexes IntPnd value to one of two interrupt line 14" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX13 ,Multiplexes IntPnd value to one of two interrupt line 13" "DCAN0INT,DCAN1INT" bitfld.long 0x00 11. " INTMUX12 ,Multiplexes IntPnd value to one of two interrupt line 12" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 10. " INTMUX11 ,Multiplexes IntPnd value to one of two interrupt line 11" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX10 ,Multiplexes IntPnd value to one of two interrupt line 10" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX9 ,Multiplexes IntPnd value to one of two interrupt line 9" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX8 ,Multiplexes IntPnd value to one of two interrupt line 8" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX7 ,Multiplexes IntPnd value to one of two interrupt line 7" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX6 ,Multiplexes IntPnd value to one of two interrupt line 6" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 4. " INTMUX5 ,Multiplexes IntPnd value to one of two interrupt line 5" "DCAN0INT,DCAN1INT" bitfld.long 0x00 3. " INTMUX4 ,Multiplexes IntPnd value to one of two interrupt line 4" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX3 ,Multiplexes IntPnd value to one of two interrupt line 3" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTMUX2 ,Multiplexes IntPnd value to one of two interrupt line 2" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX1 ,Multiplexes IntPnd value to one of two interrupt line 1" "DCAN0INT,DCAN1INT" line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer 3_4 Register" bitfld.long 0x04 31. " INTMUX64 ,Multiplexes IntPnd value to one of two interrupt line 64" "DCAN0INT,DCAN1INT" bitfld.long 0x04 30. " INTMUX63 ,Multiplexes IntPnd value to one of two interrupt line 63" "DCAN0INT,DCAN1INT" bitfld.long 0x04 29. " INTMUX62 ,Multiplexes IntPnd value to one of two interrupt line 62" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 28. " INTMUX61 ,Multiplexes IntPnd value to one of two interrupt line 61" "DCAN0INT,DCAN1INT" bitfld.long 0x04 27. " INTMUX60 ,Multiplexes IntPnd value to one of two interrupt line 60" "DCAN0INT,DCAN1INT" bitfld.long 0x04 26. " INTMUX59 ,Multiplexes IntPnd value to one of two interrupt line 59" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 25. " INTMUX58 ,Multiplexes IntPnd value to one of two interrupt line 58" "DCAN0INT,DCAN1INT" bitfld.long 0x04 24. " INTMUX57 ,Multiplexes IntPnd value to one of two interrupt line 57" "DCAN0INT,DCAN1INT" bitfld.long 0x04 23. " INTMUX56 ,Multiplexes IntPnd value to one of two interrupt line 56" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 22. " INTMUX55 ,Multiplexes IntPnd value to one of two interrupt line 55" "DCAN0INT,DCAN1INT" bitfld.long 0x04 21. " INTMUX54 ,Multiplexes IntPnd value to one of two interrupt line 54" "DCAN0INT,DCAN1INT" bitfld.long 0x04 20. " INTMUX53 ,Multiplexes IntPnd value to one of two interrupt line 53" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 19. " INTMUX52 ,Multiplexes IntPnd value to one of two interrupt line 52" "DCAN0INT,DCAN1INT" bitfld.long 0x04 18. " INTMUX51 ,Multiplexes IntPnd value to one of two interrupt line 51" "DCAN0INT,DCAN1INT" bitfld.long 0x04 17. " INTMUX50 ,Multiplexes IntPnd value to one of two interrupt line 50" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 16. " INTMUX49 ,Multiplexes IntPnd value to one of two interrupt line 49" "DCAN0INT,DCAN1INT" bitfld.long 0x04 15. " INTMUX48 ,Multiplexes IntPnd value to one of two interrupt line 48" "DCAN0INT,DCAN1INT" bitfld.long 0x04 14. " INTMUX47 ,Multiplexes IntPnd value to one of two interrupt line 47" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 13. " INTMUX46 ,Multiplexes IntPnd value to one of two interrupt line 46" "DCAN0INT,DCAN1INT" bitfld.long 0x04 12. " INTMUX45 ,Multiplexes IntPnd value to one of two interrupt line 45" "DCAN0INT,DCAN1INT" bitfld.long 0x04 11. " INTMUX44 ,Multiplexes IntPnd value to one of two interrupt line 44" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 10. " INTMUX43 ,Multiplexes IntPnd value to one of two interrupt line 43" "DCAN0INT,DCAN1INT" bitfld.long 0x04 9. " INTMUX42 ,Multiplexes IntPnd value to one of two interrupt line 42" "DCAN0INT,DCAN1INT" bitfld.long 0x04 8. " INTMUX41 ,Multiplexes IntPnd value to one of two interrupt line 41" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 7. " INTMUX40 ,Multiplexes IntPnd value to one of two interrupt line 40" "DCAN0INT,DCAN1INT" bitfld.long 0x04 6. " INTMUX39 ,Multiplexes IntPnd value to one of two interrupt line 39" "DCAN0INT,DCAN1INT" bitfld.long 0x04 5. " INTMUX38 ,Multiplexes IntPnd value to one of two interrupt line 38" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 4. " INTMUX37 ,Multiplexes IntPnd value to one of two interrupt line 37" "DCAN0INT,DCAN1INT" bitfld.long 0x04 3. " INTMUX36 ,Multiplexes IntPnd value to one of two interrupt line 36" "DCAN0INT,DCAN1INT" bitfld.long 0x04 2. " INTMUX35 ,Multiplexes IntPnd value to one of two interrupt line 35" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 1. " INTMUX34 ,Multiplexes IntPnd value to one of two interrupt line 34" "DCAN0INT,DCAN1INT" bitfld.long 0x04 0. " INTMUX33 ,Multiplexes IntPnd value to one of two interrupt line 33" "DCAN0INT,DCAN1INT" line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer 5_6 Register" bitfld.long 0x08 31. " INTMUX96 ,Multiplexes IntPnd value to one of two interrupt line 96" "DCAN0INT,DCAN1INT" bitfld.long 0x08 30. " INTMUX95 ,Multiplexes IntPnd value to one of two interrupt line 95" "DCAN0INT,DCAN1INT" bitfld.long 0x08 29. " INTMUX94 ,Multiplexes IntPnd value to one of two interrupt line 94" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 28. " INTMUX93 ,Multiplexes IntPnd value to one of two interrupt line 93" "DCAN0INT,DCAN1INT" bitfld.long 0x08 27. " INTMUX92 ,Multiplexes IntPnd value to one of two interrupt line 92" "DCAN0INT,DCAN1INT" bitfld.long 0x08 26. " INTMUX91 ,Multiplexes IntPnd value to one of two interrupt line 91" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 25. " INTMUX90 ,Multiplexes IntPnd value to one of two interrupt line 90" "DCAN0INT,DCAN1INT" bitfld.long 0x08 24. " INTMUX89 ,Multiplexes IntPnd value to one of two interrupt line 89" "DCAN0INT,DCAN1INT" bitfld.long 0x08 23. " INTMUX88 ,Multiplexes IntPnd value to one of two interrupt line 88" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 22. " INTMUX87 ,Multiplexes IntPnd value to one of two interrupt line 87" "DCAN0INT,DCAN1INT" bitfld.long 0x08 21. " INTMUX86 ,Multiplexes IntPnd value to one of two interrupt line 86" "DCAN0INT,DCAN1INT" bitfld.long 0x08 20. " INTMUX85 ,Multiplexes IntPnd value to one of two interrupt line 85" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 19. " INTMUX84 ,Multiplexes IntPnd value to one of two interrupt line 84" "DCAN0INT,DCAN1INT" bitfld.long 0x08 18. " INTMUX83 ,Multiplexes IntPnd value to one of two interrupt line 83" "DCAN0INT,DCAN1INT" bitfld.long 0x08 17. " INTMUX82 ,Multiplexes IntPnd value to one of two interrupt line 82" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 16. " INTMUX81 ,Multiplexes IntPnd value to one of two interrupt line 81" "DCAN0INT,DCAN1INT" bitfld.long 0x08 15. " INTMUX80 ,Multiplexes IntPnd value to one of two interrupt line 80" "DCAN0INT,DCAN1INT" bitfld.long 0x08 14. " INTMUX79 ,Multiplexes IntPnd value to one of two interrupt line 79" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 13. " INTMUX78 ,Multiplexes IntPnd value to one of two interrupt line 78" "DCAN0INT,DCAN1INT" bitfld.long 0x08 12. " INTMUX77 ,Multiplexes IntPnd value to one of two interrupt line 77" "DCAN0INT,DCAN1INT" bitfld.long 0x08 11. " INTMUX76 ,Multiplexes IntPnd value to one of two interrupt line 76" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 10. " INTMUX75 ,Multiplexes IntPnd value to one of two interrupt line 75" "DCAN0INT,DCAN1INT" bitfld.long 0x08 9. " INTMUX74 ,Multiplexes IntPnd value to one of two interrupt line 74" "DCAN0INT,DCAN1INT" bitfld.long 0x08 8. " INTMUX73 ,Multiplexes IntPnd value to one of two interrupt line 73" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 7. " INTMUX72 ,Multiplexes IntPnd value to one of two interrupt line 72" "DCAN0INT,DCAN1INT" bitfld.long 0x08 6. " INTMUX71 ,Multiplexes IntPnd value to one of two interrupt line 71" "DCAN0INT,DCAN1INT" bitfld.long 0x08 5. " INTMUX70 ,Multiplexes IntPnd value to one of two interrupt line 70" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 4. " INTMUX69 ,Multiplexes IntPnd value to one of two interrupt line 69" "DCAN0INT,DCAN1INT" bitfld.long 0x08 3. " INTMUX68 ,Multiplexes IntPnd value to one of two interrupt line 68" "DCAN0INT,DCAN1INT" bitfld.long 0x08 2. " INTMUX67 ,Multiplexes IntPnd value to one of two interrupt line 67" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 1. " INTMUX66 ,Multiplexes IntPnd value to one of two interrupt line 66" "DCAN0INT,DCAN1INT" bitfld.long 0x08 0. " INTMUX65 ,Multiplexes IntPnd value to one of two interrupt line 65" "DCAN0INT,DCAN1INT" line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer 7_8 Register" bitfld.long 0x0C 31. " INTMUX128 ,Multiplexes IntPnd value to one of two interrupt line 128" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 30. " INTMUX127 ,Multiplexes IntPnd value to one of two interrupt line 127" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 29. " INTMUX126 ,Multiplexes IntPnd value to one of two interrupt line 126" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 28. " INTMUX125 ,Multiplexes IntPnd value to one of two interrupt line 125" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 27. " INTMUX124 ,Multiplexes IntPnd value to one of two interrupt line 124" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 26. " INTMUX123 ,Multiplexes IntPnd value to one of two interrupt line 123" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 25. " INTMUX122 ,Multiplexes IntPnd value to one of two interrupt line 122" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 24. " INTMUX121 ,Multiplexes IntPnd value to one of two interrupt line 121" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 23. " INTMUX120 ,Multiplexes IntPnd value to one of two interrupt line 120" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 22. " INTMUX119 ,Multiplexes IntPnd value to one of two interrupt line 119" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 21. " INTMUX118 ,Multiplexes IntPnd value to one of two interrupt line 118" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 20. " INTMUX117 ,Multiplexes IntPnd value to one of two interrupt line 117" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 19. " INTMUX116 ,Multiplexes IntPnd value to one of two interrupt line 116" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 18. " INTMUX115 ,Multiplexes IntPnd value to one of two interrupt line 115" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 17. " INTMUX114 ,Multiplexes IntPnd value to one of two interrupt line 114" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 16. " INTMUX113 ,Multiplexes IntPnd value to one of two interrupt line 113" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 15. " INTMUX112 ,Multiplexes IntPnd value to one of two interrupt line 112" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 14. " INTMUX111 ,Multiplexes IntPnd value to one of two interrupt line 111" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 13. " INTMUX110 ,Multiplexes IntPnd value to one of two interrupt line 110" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 12. " INTMUX109 ,Multiplexes IntPnd value to one of two interrupt line 109" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 11. " INTMUX108 ,Multiplexes IntPnd value to one of two interrupt line 108" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 10. " INTMUX107 ,Multiplexes IntPnd value to one of two interrupt line 107" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 9. " INTMUX106 ,Multiplexes IntPnd value to one of two interrupt line 106" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 8. " INTMUX105 ,Multiplexes IntPnd value to one of two interrupt line 105" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 7. " INTMUX104 ,Multiplexes IntPnd value to one of two interrupt line 104" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 6. " INTMUX103 ,Multiplexes IntPnd value to one of two interrupt line 103" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 5. " INTMUX102 ,Multiplexes IntPnd value to one of two interrupt line 102" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 4. " INTMUX101 ,Multiplexes IntPnd value to one of two interrupt line 101" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 3. " INTMUX100 ,Multiplexes IntPnd value to one of two interrupt line 100" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 2. " INTMUX99 ,Multiplexes IntPnd value to one of two interrupt line 99" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 1. " INTMUX98 ,Multiplexes IntPnd value to one of two interrupt line 98" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 0. " INTMUX97 ,Multiplexes IntPnd value to one of two interrupt line 97" "DCAN0INT,DCAN1INT" else line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer 1_2 Register" bitfld.long 0x00 31. " INTPNDMUX32 ,Multiplexes IntPnd value to one of two interrupt line 32" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX31 ,Multiplexes IntPnd value to one of two interrupt line 31" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTPNDMUX30 ,Multiplexes IntPnd value to one of two interrupt line 30" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 28. " INTPNDMUX29 ,Multiplexes IntPnd value to one of two interrupt line 29" "DCAN0INT,DCAN1INT" bitfld.long 0x00 27. " INTPNDMUX28 ,Multiplexes IntPnd value to one of two interrupt line 28" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX27 ,Multiplexes IntPnd value to one of two interrupt line 27" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX26 ,Multiplexes IntPnd value to one of two interrupt line 26" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX25 ,Multiplexes IntPnd value to one of two interrupt line 25" "DCAN0INT,DCAN1INT" bitfld.long 0x00 23. " INTPNDMUX24 ,Multiplexes IntPnd value to one of two interrupt line 24" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 22. " INTPNDMUX23 ,Multiplexes IntPnd value to one of two interrupt line 23" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTPNDMUX22 ,Multiplexes IntPnd value to one of two interrupt line 22" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX21 ,Multiplexes IntPnd value to one of two interrupt line 21" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX20 ,Multiplexes IntPnd value to one of two interrupt line 20" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX19 ,Multiplexes IntPnd value to one of two interrupt line 19" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTPNDMUX18 ,Multiplexes IntPnd value to one of two interrupt line 18" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 16. " INTPNDMUX17 ,Multiplexes IntPnd value to one of two interrupt line 17" "DCAN0INT,DCAN1INT" bitfld.long 0x00 15. " INTPNDMUX16 ,Multiplexes IntPnd value to one of two interrupt line 16" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX15 ,Multiplexes IntPnd value to one of two interrupt line 15" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX14 ,Multiplexes IntPnd value to one of two interrupt line 14" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX13 ,Multiplexes IntPnd value to one of two interrupt line 13" "DCAN0INT,DCAN1INT" bitfld.long 0x00 11. " INTPNDMUX12 ,Multiplexes IntPnd value to one of two interrupt line 12" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 10. " INTPNDMUX11 ,Multiplexes IntPnd value to one of two interrupt line 11" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTPNDMUX10 ,Multiplexes IntPnd value to one of two interrupt line 10" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX9 ,Multiplexes IntPnd value to one of two interrupt line 9" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX8 ,Multiplexes IntPnd value to one of two interrupt line 8" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX7 ,Multiplexes IntPnd value to one of two interrupt line 7" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTPNDMUX6 ,Multiplexes IntPnd value to one of two interrupt line 6" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 4. " INTPNDMUX5 ,Multiplexes IntPnd value to one of two interrupt line 5" "DCAN0INT,DCAN1INT" bitfld.long 0x00 3. " INTPNDMUX4 ,Multiplexes IntPnd value to one of two interrupt line 4" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX3 ,Multiplexes IntPnd value to one of two interrupt line 3" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX2 ,Multiplexes IntPnd value to one of two interrupt line 2" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX1 ,Multiplexes IntPnd value to one of two interrupt line 1" "DCAN0INT,DCAN1INT" line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer 3_4 Register" bitfld.long 0x04 31. " INTPNDMUX64 ,Multiplexes IntPnd value to one of two interrupt line 64" "DCAN0INT,DCAN1INT" bitfld.long 0x04 30. " INTPNDMUX63 ,Multiplexes IntPnd value to one of two interrupt line 63" "DCAN0INT,DCAN1INT" bitfld.long 0x04 29. " INTPNDMUX62 ,Multiplexes IntPnd value to one of two interrupt line 62" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 28. " INTPNDMUX61 ,Multiplexes IntPnd value to one of two interrupt line 61" "DCAN0INT,DCAN1INT" bitfld.long 0x04 27. " INTPNDMUX60 ,Multiplexes IntPnd value to one of two interrupt line 60" "DCAN0INT,DCAN1INT" bitfld.long 0x04 26. " INTPNDMUX59 ,Multiplexes IntPnd value to one of two interrupt line 59" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 25. " INTPNDMUX58 ,Multiplexes IntPnd value to one of two interrupt line 58" "DCAN0INT,DCAN1INT" bitfld.long 0x04 24. " INTPNDMUX57 ,Multiplexes IntPnd value to one of two interrupt line 57" "DCAN0INT,DCAN1INT" bitfld.long 0x04 23. " INTPNDMUX56 ,Multiplexes IntPnd value to one of two interrupt line 56" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 22. " INTPNDMUX55 ,Multiplexes IntPnd value to one of two interrupt line 55" "DCAN0INT,DCAN1INT" bitfld.long 0x04 21. " INTPNDMUX54 ,Multiplexes IntPnd value to one of two interrupt line 54" "DCAN0INT,DCAN1INT" bitfld.long 0x04 20. " INTPNDMUX53 ,Multiplexes IntPnd value to one of two interrupt line 53" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 19. " INTPNDMUX52 ,Multiplexes IntPnd value to one of two interrupt line 52" "DCAN0INT,DCAN1INT" bitfld.long 0x04 18. " INTPNDMUX51 ,Multiplexes IntPnd value to one of two interrupt line 51" "DCAN0INT,DCAN1INT" bitfld.long 0x04 17. " INTPNDMUX50 ,Multiplexes IntPnd value to one of two interrupt line 50" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 16. " INTPNDMUX49 ,Multiplexes IntPnd value to one of two interrupt line 49" "DCAN0INT,DCAN1INT" bitfld.long 0x04 15. " INTPNDMUX48 ,Multiplexes IntPnd value to one of two interrupt line 48" "DCAN0INT,DCAN1INT" bitfld.long 0x04 14. " INTPNDMUX47 ,Multiplexes IntPnd value to one of two interrupt line 47" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 13. " INTPNDMUX46 ,Multiplexes IntPnd value to one of two interrupt line 46" "DCAN0INT,DCAN1INT" bitfld.long 0x04 12. " INTPNDMUX45 ,Multiplexes IntPnd value to one of two interrupt line 45" "DCAN0INT,DCAN1INT" bitfld.long 0x04 11. " INTPNDMUX44 ,Multiplexes IntPnd value to one of two interrupt line 44" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 10. " INTPNDMUX43 ,Multiplexes IntPnd value to one of two interrupt line 43" "DCAN0INT,DCAN1INT" bitfld.long 0x04 9. " INTPNDMUX42 ,Multiplexes IntPnd value to one of two interrupt line 42" "DCAN0INT,DCAN1INT" bitfld.long 0x04 8. " INTPNDMUX41 ,Multiplexes IntPnd value to one of two interrupt line 41" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 7. " INTPNDMUX40 ,Multiplexes IntPnd value to one of two interrupt line 40" "DCAN0INT,DCAN1INT" bitfld.long 0x04 6. " INTPNDMUX39 ,Multiplexes IntPnd value to one of two interrupt line 39" "DCAN0INT,DCAN1INT" bitfld.long 0x04 5. " INTPNDMUX38 ,Multiplexes IntPnd value to one of two interrupt line 38" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 4. " INTPNDMUX37 ,Multiplexes IntPnd value to one of two interrupt line 37" "DCAN0INT,DCAN1INT" bitfld.long 0x04 3. " INTPNDMUX36 ,Multiplexes IntPnd value to one of two interrupt line 36" "DCAN0INT,DCAN1INT" bitfld.long 0x04 2. " INTPNDMUX35 ,Multiplexes IntPnd value to one of two interrupt line 35" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 1. " INTPNDMUX34 ,Multiplexes IntPnd value to one of two interrupt line 34" "DCAN0INT,DCAN1INT" bitfld.long 0x04 0. " INTPNDMUX33 ,Multiplexes IntPnd value to one of two interrupt line 33" "DCAN0INT,DCAN1INT" line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer 5_6 Register" bitfld.long 0x08 31. " INTPNDMUX96 ,Multiplexes IntPnd value to one of two interrupt line 96" "DCAN0INT,DCAN1INT" bitfld.long 0x08 30. " INTPNDMUX95 ,Multiplexes IntPnd value to one of two interrupt line 95" "DCAN0INT,DCAN1INT" bitfld.long 0x08 29. " INTPNDMUX94 ,Multiplexes IntPnd value to one of two interrupt line 94" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 28. " INTPNDMUX93 ,Multiplexes IntPnd value to one of two interrupt line 93" "DCAN0INT,DCAN1INT" bitfld.long 0x08 27. " INTPNDMUX92 ,Multiplexes IntPnd value to one of two interrupt line 92" "DCAN0INT,DCAN1INT" bitfld.long 0x08 26. " INTPNDMUX91 ,Multiplexes IntPnd value to one of two interrupt line 91" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 25. " INTPNDMUX90 ,Multiplexes IntPnd value to one of two interrupt line 90" "DCAN0INT,DCAN1INT" bitfld.long 0x08 24. " INTPNDMUX89 ,Multiplexes IntPnd value to one of two interrupt line 89" "DCAN0INT,DCAN1INT" bitfld.long 0x08 23. " INTPNDMUX88 ,Multiplexes IntPnd value to one of two interrupt line 88" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 22. " INTPNDMUX87 ,Multiplexes IntPnd value to one of two interrupt line 87" "DCAN0INT,DCAN1INT" bitfld.long 0x08 21. " INTPNDMUX86 ,Multiplexes IntPnd value to one of two interrupt line 86" "DCAN0INT,DCAN1INT" bitfld.long 0x08 20. " INTPNDMUX85 ,Multiplexes IntPnd value to one of two interrupt line 85" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 19. " INTPNDMUX84 ,Multiplexes IntPnd value to one of two interrupt line 84" "DCAN0INT,DCAN1INT" bitfld.long 0x08 18. " INTPNDMUX83 ,Multiplexes IntPnd value to one of two interrupt line 83" "DCAN0INT,DCAN1INT" bitfld.long 0x08 17. " INTPNDMUX82 ,Multiplexes IntPnd value to one of two interrupt line 82" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 16. " INTPNDMUX81 ,Multiplexes IntPnd value to one of two interrupt line 81" "DCAN0INT,DCAN1INT" bitfld.long 0x08 15. " INTPNDMUX80 ,Multiplexes IntPnd value to one of two interrupt line 80" "DCAN0INT,DCAN1INT" bitfld.long 0x08 14. " INTPNDMUX79 ,Multiplexes IntPnd value to one of two interrupt line 79" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 13. " INTPNDMUX78 ,Multiplexes IntPnd value to one of two interrupt line 78" "DCAN0INT,DCAN1INT" bitfld.long 0x08 12. " INTPNDMUX77 ,Multiplexes IntPnd value to one of two interrupt line 77" "DCAN0INT,DCAN1INT" bitfld.long 0x08 11. " INTPNDMUX76 ,Multiplexes IntPnd value to one of two interrupt line 76" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 10. " INTPNDMUX75 ,Multiplexes IntPnd value to one of two interrupt line 75" "DCAN0INT,DCAN1INT" bitfld.long 0x08 9. " INTPNDMUX74 ,Multiplexes IntPnd value to one of two interrupt line 74" "DCAN0INT,DCAN1INT" bitfld.long 0x08 8. " INTPNDMUX73 ,Multiplexes IntPnd value to one of two interrupt line 73" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 7. " INTPNDMUX72 ,Multiplexes IntPnd value to one of two interrupt line 72" "DCAN0INT,DCAN1INT" bitfld.long 0x08 6. " INTPNDMUX71 ,Multiplexes IntPnd value to one of two interrupt line 71" "DCAN0INT,DCAN1INT" bitfld.long 0x08 5. " INTPNDMUX70 ,Multiplexes IntPnd value to one of two interrupt line 70" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 4. " INTPNDMUX69 ,Multiplexes IntPnd value to one of two interrupt line 69" "DCAN0INT,DCAN1INT" bitfld.long 0x08 3. " INTPNDMUX68 ,Multiplexes IntPnd value to one of two interrupt line 68" "DCAN0INT,DCAN1INT" bitfld.long 0x08 2. " INTPNDMUX67 ,Multiplexes IntPnd value to one of two interrupt line 67" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 1. " INTPNDMUX66 ,Multiplexes IntPnd value to one of two interrupt line 66" "DCAN0INT,DCAN1INT" bitfld.long 0x08 0. " INTPNDMUX65 ,Multiplexes IntPnd value to one of two interrupt line 65" "DCAN0INT,DCAN1INT" line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer 7_8 Register" bitfld.long 0x0C 31. " INTPNDMUX128 ,Multiplexes IntPnd value to one of two interrupt line 128" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 30. " INTPNDMUX127 ,Multiplexes IntPnd value to one of two interrupt line 127" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 29. " INTPNDMUX126 ,Multiplexes IntPnd value to one of two interrupt line 126" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 28. " INTPNDMUX125 ,Multiplexes IntPnd value to one of two interrupt line 125" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 27. " INTPNDMUX124 ,Multiplexes IntPnd value to one of two interrupt line 124" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 26. " INTPNDMUX123 ,Multiplexes IntPnd value to one of two interrupt line 123" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 25. " INTPNDMUX122 ,Multiplexes IntPnd value to one of two interrupt line 122" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 24. " INTPNDMUX121 ,Multiplexes IntPnd value to one of two interrupt line 121" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 23. " INTPNDMUX120 ,Multiplexes IntPnd value to one of two interrupt line 120" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 22. " INTPNDMUX119 ,Multiplexes IntPnd value to one of two interrupt line 119" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 21. " INTPNDMUX118 ,Multiplexes IntPnd value to one of two interrupt line 118" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 20. " INTPNDMUX117 ,Multiplexes IntPnd value to one of two interrupt line 117" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 19. " INTPNDMUX116 ,Multiplexes IntPnd value to one of two interrupt line 116" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 18. " INTPNDMUX115 ,Multiplexes IntPnd value to one of two interrupt line 115" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 17. " INTPNDMUX114 ,Multiplexes IntPnd value to one of two interrupt line 114" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 16. " INTPNDMUX113 ,Multiplexes IntPnd value to one of two interrupt line 113" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 15. " INTPNDMUX112 ,Multiplexes IntPnd value to one of two interrupt line 112" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 14. " INTPNDMUX111 ,Multiplexes IntPnd value to one of two interrupt line 111" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 13. " INTPNDMUX110 ,Multiplexes IntPnd value to one of two interrupt line 110" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 12. " INTPNDMUX109 ,Multiplexes IntPnd value to one of two interrupt line 109" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 11. " INTPNDMUX108 ,Multiplexes IntPnd value to one of two interrupt line 108" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 10. " INTPNDMUX107 ,Multiplexes IntPnd value to one of two interrupt line 107" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 9. " INTPNDMUX106 ,Multiplexes IntPnd value to one of two interrupt line 106" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 8. " INTPNDMUX105 ,Multiplexes IntPnd value to one of two interrupt line 105" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 7. " INTPNDMUX104 ,Multiplexes IntPnd value to one of two interrupt line 104" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 6. " INTPNDMUX103 ,Multiplexes IntPnd value to one of two interrupt line 103" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 5. " INTPNDMUX102 ,Multiplexes IntPnd value to one of two interrupt line 102" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 4. " INTPNDMUX101 ,Multiplexes IntPnd value to one of two interrupt line 101" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 3. " INTPNDMUX100 ,Multiplexes IntPnd value to one of two interrupt line 100" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 2. " INTPNDMUX99 ,Multiplexes IntPnd value to one of two interrupt line 99" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 1. " INTPNDMUX98 ,Multiplexes IntPnd value to one of two interrupt line 98" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 0. " INTPNDMUX97 ,Multiplexes IntPnd value to one of two interrupt line 97" "DCAN0INT,DCAN1INT" endif if (((data.long(ad:0x481CC000+0x100))&0x800000)==0x800000) group.long 0x100++0x03 "IF1 Registers" line.long 0x00 "DCAN_IF1CMD,IF1 Command Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered" bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered" textline " " bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered" sif (cpuis("DRA62*")) bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,?..." bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Handled,Set" else bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Cleared,Set" endif textline " " bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered" bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" textline " " bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active" hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" else group.long 0x100++0x03 "IF1 Registers" line.long 0x00 "DCAN_IF1CMD,IF1 Command Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered" bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered" textline " " bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Unchanged,Cleared" textline " " bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered" bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" textline " " bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active" hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" endif if ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x40000000)) rgroup.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" elif ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x40000000)) group.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" elif ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x00)) rgroup.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK10-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" else group.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK10-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" endif if ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x40000000)) rgroup.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" elif ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x40000000)) group.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" elif ((((data.long(ad:0x481CC000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x108))&0x40000000)==0x00000000)) group.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" else rgroup.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" endif if (((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000) rgroup.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" else group.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" endif if (((data.long(ad:0x481CC000+0x100))&0x8000)==0x8000) rgroup.long 0x110++0x07 line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF1DATB,IF1 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" else group.long 0x110++0x07 line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF1DATB,IF1 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" endif if (((data.long(ad:0x481CC000+0x120))&0x800000)==0x800000) group.long 0x120++0x03 "IF2 Registers" line.long 0x00 "DCAN_IF2CMD,IF2 Command Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered" bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered" textline " " bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered" sif (cpuis("DRA62*")) bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,?..." bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Handled,Set" else bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Cleared,Set" endif textline " " bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered" bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" textline " " bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active" hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" else group.long 0x120++0x03 "IF2 Registers" line.long 0x00 "DCAN_IF2CMD,IF2 Command Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered" bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered" textline " " bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Unchanged,Cleared" textline " " bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered" bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" textline " " bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active" hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" endif if ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x40000000)) rgroup.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" elif ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x40000000)) group.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" elif ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x00)) rgroup.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-18 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" else group.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-18 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" endif if ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x40000000)) rgroup.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" elif ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x40000000)) group.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" elif ((((data.long(ad:0x481CC000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481CC000+0x128))&0x40000000)==0x00000000)) group.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" else rgroup.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" endif if (((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000) rgroup.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" else group.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" endif if (((data.long(ad:0x481CC000+0x120))&0x8000)==0x8000) rgroup.long 0x130++0x07 line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF2DATB,IF2 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" else group.long 0x130++0x07 line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF2DATB,IF2 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" endif group.long 0x140++0x03 "IF3 Registers" line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register" bitfld.long 0x00 15. " IF3UPD ,IF3 Update Data" "Not updated,Updated" bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B read access" "All read,Not all read" textline " " bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A read access" "All read,Not all read" bitfld.long 0x00 10. " IF3SC ,IF3 Status of control bits read access" "All read,Not all read" textline " " bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration data read access" "All read,Not all read" bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask data read access" "All read,Not all read" textline " " bitfld.long 0x00 4. " DATAB ,Data B read observation" "Not read,Read" bitfld.long 0x00 3. " DATAA ,Data A read observation" "Not read,Read" bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "Not read,Read" textline " " bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "Not read,Read" bitfld.long 0x00 0. " MASK ,Mask data read observation" "Not read,Read" if (((data.long(ad:0x481CC000+0x148))&0x40000000)==0x40000000) rgroup.long 0x144++0x3 line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" else rgroup.long 0x144++0x3 line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MSK10-0 ,Identifier Mask" "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" endif if (((data.long(ad:0x481CC000+0x148))&0x40000000)==0x40000000) group.long 0x148++0x03 line.long 0x00 "DCAN_IF3ARB,IF3 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" else group.long 0x148++0x03 line.long 0x00 "DCAN_IF3ARB,IF3 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" endif rgroup.long 0x14C++0x03 line.long 0x00 "DCAN_IF3MCTL,IF3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" rgroup.long 0x150++0x07 line.long 0x00 "DCAN_IF3DATA,IF3 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF3DATB,IF3 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" group.long 0x160--0x16F line.long 0x00 "IF3UPD12,Update Enable 1_2 Register" bitfld.long 0x00 31. " IF3UPDATEEN32 ,IF3 Update enabled 32" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN31 ,IF3 Update enabled 31" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDATEEN30 ,IF3 Update enabled 30" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " IF3UPDATEEN29 ,IF3 Update enabled 29" "Disabled,Enabled" bitfld.long 0x00 27. " IF3UPDATEEN28 ,IF3 Update enabled 28" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN27 ,IF3 Update enabled 27" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN26 ,IF3 Update enabled 26" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN25 ,IF3 Update enabled 25" "Disabled,Enabled" bitfld.long 0x00 23. " IF3UPDATEEN24 ,IF3 Update enabled 24" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " IF3UPDATEEN23 ,IF3 Update enabled 23" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDATEEN22 ,IF3 Update enabled 22" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN21 ,IF3 Update enabled 21" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN20 ,IF3 Update enabled 20" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN19 ,IF3 Update enabled 19" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDATEEN18 ,IF3 Update enabled 18" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " IF3UPDATEEN17 ,IF3 Update enabled 17" "Disabled,Enabled" bitfld.long 0x00 15. " IF3UPDATEEN16 ,IF3 Update enabled 16" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN15 ,IF3 Update enabled 15" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN14 ,IF3 Update enabled 14" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN13 ,IF3 Update enabled 13" "Disabled,Enabled" bitfld.long 0x00 11. " IF3UPDATEEN12 ,IF3 Update enabled 12" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " IF3UPDATEEN11 ,IF3 Update enabled 11" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDATEEN10 ,IF3 Update enabled 10" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN9 ,IF3 Update enabled 9" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN8 ,IF3 Update enabled 8" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN7 ,IF3 Update enabled 7" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDATEEN6 ,IF3 Update enabled 6" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IF3UPDATEEN5 ,IF3 Update enabled 5" "Disabled,Enabled" bitfld.long 0x00 3. " IF3UPDATEEN4 ,IF3 Update enabled 4" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN3 ,IF3 Update enabled 3" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN2 ,IF3 Update enabled 2" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN1 ,IF3 Update enabled 1" "Disabled,Enabled" line.long 0x04 "IF3UPD3_4,Update Enable 3_4 Register" bitfld.long 0x04 31. " IF3UPDATEEN64 ,IF3 Update enabled 64" "Disabled,Enabled" bitfld.long 0x04 30. " IF3UPDATEEN63 ,IF3 Update enabled 63" "Disabled,Enabled" bitfld.long 0x04 29. " IF3UPDATEEN62 ,IF3 Update enabled 62" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " IF3UPDATEEN61 ,IF3 Update enabled 61" "Disabled,Enabled" bitfld.long 0x04 27. " IF3UPDATEEN60 ,IF3 Update enabled 60" "Disabled,Enabled" bitfld.long 0x04 26. " IF3UPDATEEN59 ,IF3 Update enabled 59" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " IF3UPDATEEN58 ,IF3 Update enabled 58" "Disabled,Enabled" bitfld.long 0x04 24. " IF3UPDATEEN57 ,IF3 Update enabled 57" "Disabled,Enabled" bitfld.long 0x04 23. " IF3UPDATEEN56 ,IF3 Update enabled 56" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " IF3UPDATEEN55 ,IF3 Update enabled 55" "Disabled,Enabled" bitfld.long 0x04 21. " IF3UPDATEEN54 ,IF3 Update enabled 54" "Disabled,Enabled" bitfld.long 0x04 20. " IF3UPDATEEN53 ,IF3 Update enabled 53" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " IF3UPDATEEN52 ,IF3 Update enabled 52" "Disabled,Enabled" bitfld.long 0x04 18. " IF3UPDATEEN51 ,IF3 Update enabled 51" "Disabled,Enabled" bitfld.long 0x04 17. " IF3UPDATEEN50 ,IF3 Update enabled 50" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " IF3UPDATEEN49 ,IF3 Update enabled 49" "Disabled,Enabled" bitfld.long 0x04 15. " IF3UPDATEEN48 ,IF3 Update enabled 48" "Disabled,Enabled" bitfld.long 0x04 14. " IF3UPDATEEN47 ,IF3 Update enabled 47" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " IF3UPDATEEN46 ,IF3 Update enabled 46" "Disabled,Enabled" bitfld.long 0x04 12. " IF3UPDATEEN45 ,IF3 Update enabled 45" "Disabled,Enabled" bitfld.long 0x04 11. " IF3UPDATEEN44 ,IF3 Update enabled 44" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " IF3UPDATEEN43 ,IF3 Update enabled 43" "Disabled,Enabled" bitfld.long 0x04 9. " IF3UPDATEEN42 ,IF3 Update enabled 42" "Disabled,Enabled" bitfld.long 0x04 8. " IF3UPDATEEN41 ,IF3 Update enabled 41" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " IF3UPDATEEN40 ,IF3 Update enabled 40" "Disabled,Enabled" bitfld.long 0x04 6. " IF3UPDATEEN39 ,IF3 Update enabled 39" "Disabled,Enabled" bitfld.long 0x04 5. " IF3UPDATEEN38 ,IF3 Update enabled 38" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " IF3UPDATEEN37 ,IF3 Update enabled 37" "Disabled,Enabled" bitfld.long 0x04 3. " IF3UPDATEEN36 ,IF3 Update enabled 36" "Disabled,Enabled" bitfld.long 0x04 2. " IF3UPDATEEN35 ,IF3 Update enabled 35" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " IF3UPDATEEN34 ,IF3 Update enabled 34" "Disabled,Enabled" bitfld.long 0x04 0. " IF3UPDATEEN33 ,IF3 Update enabled 33" "Disabled,Enabled" line.long 0x08 "IF3UPD5_6,Update Enable 5_6 Register" bitfld.long 0x08 31. " IF3UPDATEEN96 ,IF3 Update enabled 96" "Disabled,Enabled" bitfld.long 0x08 30. " IF3UPDATEEN95 ,IF3 Update enabled 95" "Disabled,Enabled" bitfld.long 0x08 29. " IF3UPDATEEN94 ,IF3 Update enabled 94" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " IF3UPDATEEN93 ,IF3 Update enabled 93" "Disabled,Enabled" bitfld.long 0x08 27. " IF3UPDATEEN92 ,IF3 Update enabled 92" "Disabled,Enabled" bitfld.long 0x08 26. " IF3UPDATEEN91 ,IF3 Update enabled 91" "Disabled,Enabled" textline " " bitfld.long 0x08 25. " IF3UPDATEEN90 ,IF3 Update enabled 90" "Disabled,Enabled" bitfld.long 0x08 24. " IF3UPDATEEN89 ,IF3 Update enabled 89" "Disabled,Enabled" bitfld.long 0x08 23. " IF3UPDATEEN88 ,IF3 Update enabled 88" "Disabled,Enabled" textline " " bitfld.long 0x08 22. " IF3UPDATEEN87 ,IF3 Update enabled 87" "Disabled,Enabled" bitfld.long 0x08 21. " IF3UPDATEEN86 ,IF3 Update enabled 86" "Disabled,Enabled" bitfld.long 0x08 20. " IF3UPDATEEN85 ,IF3 Update enabled 85" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " IF3UPDATEEN84 ,IF3 Update enabled 84" "Disabled,Enabled" bitfld.long 0x08 18. " IF3UPDATEEN83 ,IF3 Update enabled 83" "Disabled,Enabled" bitfld.long 0x08 17. " IF3UPDATEEN82 ,IF3 Update enabled 82" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " IF3UPDATEEN81 ,IF3 Update enabled 81" "Disabled,Enabled" bitfld.long 0x08 15. " IF3UPDATEEN80 ,IF3 Update enabled 80" "Disabled,Enabled" bitfld.long 0x08 14. " IF3UPDATEEN79 ,IF3 Update enabled 79" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " IF3UPDATEEN78 ,IF3 Update enabled 78" "Disabled,Enabled" bitfld.long 0x08 12. " IF3UPDATEEN77 ,IF3 Update enabled 77" "Disabled,Enabled" bitfld.long 0x08 11. " IF3UPDATEEN76 ,IF3 Update enabled 76" "Disabled,Enabled" textline " " bitfld.long 0x08 10. " IF3UPDATEEN75 ,IF3 Update enabled 75" "Disabled,Enabled" bitfld.long 0x08 9. " IF3UPDATEEN74 ,IF3 Update enabled 74" "Disabled,Enabled" bitfld.long 0x08 8. " IF3UPDATEEN73 ,IF3 Update enabled 73" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " IF3UPDATEEN72 ,IF3 Update enabled 72" "Disabled,Enabled" bitfld.long 0x08 6. " IF3UPDATEEN71 ,IF3 Update enabled 71" "Disabled,Enabled" bitfld.long 0x08 5. " IF3UPDATEEN70 ,IF3 Update enabled 70" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " IF3UPDATEEN69 ,IF3 Update enabled 69" "Disabled,Enabled" bitfld.long 0x08 3. " IF3UPDATEEN68 ,IF3 Update enabled 68" "Disabled,Enabled" bitfld.long 0x08 2. " IF3UPDATEEN67 ,IF3 Update enabled 67" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " IF3UPDATEEN66 ,IF3 Update enabled 66" "Disabled,Enabled" bitfld.long 0x08 0. " IF3UPDATEEN65 ,IF3 Update enabled 65" "Disabled,Enabled" line.long 0x0C "IF3UPD7_8,Update Enable 7_8 Register" bitfld.long 0x0C 31. " IF3UPDATEEN128 ,IF3 Update enabled 128" "Disabled,Enabled" bitfld.long 0x0C 30. " IF3UPDATEEN127 ,IF3 Update enabled 127" "Disabled,Enabled" bitfld.long 0x0C 29. " IF3UPDATEEN126 ,IF3 Update enabled 126" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " IF3UPDATEEN125 ,IF3 Update enabled 125" "Disabled,Enabled" bitfld.long 0x0C 27. " IF3UPDATEEN124 ,IF3 Update enabled 124" "Disabled,Enabled" bitfld.long 0x0C 26. " IF3UPDATEEN123 ,IF3 Update enabled 123" "Disabled,Enabled" textline " " bitfld.long 0x0C 25. " IF3UPDATEEN122 ,IF3 Update enabled 122" "Disabled,Enabled" bitfld.long 0x0C 24. " IF3UPDATEEN121 ,IF3 Update enabled 121" "Disabled,Enabled" bitfld.long 0x0C 23. " IF3UPDATEEN120 ,IF3 Update enabled 120" "Disabled,Enabled" textline " " bitfld.long 0x0C 22. " IF3UPDATEEN119 ,IF3 Update enabled 119" "Disabled,Enabled" bitfld.long 0x0C 21. " IF3UPDATEEN118 ,IF3 Update enabled 118" "Disabled,Enabled" bitfld.long 0x0C 20. " IF3UPDATEEN117 ,IF3 Update enabled 117" "Disabled,Enabled" textline " " bitfld.long 0x0C 19. " IF3UPDATEEN116 ,IF3 Update enabled 116" "Disabled,Enabled" bitfld.long 0x0C 18. " IF3UPDATEEN115 ,IF3 Update enabled 115" "Disabled,Enabled" bitfld.long 0x0C 17. " IF3UPDATEEN114 ,IF3 Update enabled 114" "Disabled,Enabled" textline " " bitfld.long 0x0C 16. " IF3UPDATEEN113 ,IF3 Update enabled 113" "Disabled,Enabled" bitfld.long 0x0C 15. " IF3UPDATEEN112 ,IF3 Update enabled 112" "Disabled,Enabled" bitfld.long 0x0C 14. " IF3UPDATEEN111 ,IF3 Update enabled 111" "Disabled,Enabled" textline " " bitfld.long 0x0C 13. " IF3UPDATEEN110 ,IF3 Update enabled 110" "Disabled,Enabled" bitfld.long 0x0C 12. " IF3UPDATEEN109 ,IF3 Update enabled 109" "Disabled,Enabled" bitfld.long 0x0C 11. " IF3UPDATEEN108 ,IF3 Update enabled 108" "Disabled,Enabled" textline " " bitfld.long 0x0C 10. " IF3UPDATEEN107 ,IF3 Update enabled 107" "Disabled,Enabled" bitfld.long 0x0C 9. " IF3UPDATEEN106 ,IF3 Update enabled 106" "Disabled,Enabled" bitfld.long 0x0C 8. " IF3UPDATEEN105 ,IF3 Update enabled 105" "Disabled,Enabled" textline " " bitfld.long 0x0C 7. " IF3UPDATEEN104 ,IF3 Update enabled 104" "Disabled,Enabled" bitfld.long 0x0C 6. " IF3UPDATEEN103 ,IF3 Update enabled 103" "Disabled,Enabled" bitfld.long 0x0C 5. " IF3UPDATEEN102 ,IF3 Update enabled 102" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " IF3UPDATEEN101 ,IF3 Update enabled 101" "Disabled,Enabled" bitfld.long 0x0C 3. " IF3UPDATEEN100 ,IF3 Update enabled 100" "Disabled,Enabled" bitfld.long 0x0C 2. " IF3UPDATEEN99 ,IF3 Update enabled 99" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " IF3UPDATEEN98 ,IF3 Update enabled 98" "Disabled,Enabled" bitfld.long 0x0C 0. " IF3UPDATEEN97 ,IF3 Update enabled 97" "Disabled,Enabled" width 12. if (((d.l(ad:0x481CC000))&0x1)==0x1) // DCAN_CTL.Init == 1 group.long 0x1E0++0x07 line.long 0x00 "DCAN_TIOC,TX IO Control Register" bitfld.long 0x00 18. " PU ,Selection of pull direction" "Pull-down,Pull-up" bitfld.long 0x00 17. " PD ,Pull functionality disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " OD ,Open drain mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " FUNC ,Functionality of pin" "GPIO,CAN" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,Output" else bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,I/O" endif textline " " bitfld.long 0x00 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of pin" "Low,High" line.long 0x04 "DCAN_RIOC,RX IO Control Register" bitfld.long 0x04 18. " PU ,Selection of pull direction" "Pull-down,Pull-up" bitfld.long 0x04 17. " PD ,Pull functionality disable" "Enabled,Disabled" textline " " bitfld.long 0x04 16. " OD ,Open drain mode enable" "Disabled,Enabled" bitfld.long 0x04 3. " FUNC ,Functionality of pin" "GPIO,CAN" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,Output" else bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,I/O" endif textline " " bitfld.long 0x04 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High" bitfld.long 0x04 0. " IN ,Value of pin" "Low,High" else rgroup.long 0x1E0++0x07 line.long 0x00 "DCAN_TIOC,TX IO Control Register" bitfld.long 0x00 18. " PU ,Selection of pull direction" "Pull-down,Pull-up" bitfld.long 0x00 17. " PD ,Pull functionality disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " OD ,Open drain mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " FUNC ,Functionality of pin" "GPIO,CAN" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,Output" else bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,I/O" endif textline " " bitfld.long 0x00 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of pin" "Low,High" line.long 0x04 "DCAN_RIOC,RX IO Control Register" bitfld.long 0x04 18. " PU ,Selection of pull direction" "Pull-down,Pull-up" bitfld.long 0x04 17. " PD ,Pull functionality disable" "Enabled,Disabled" textline " " bitfld.long 0x04 16. " OD ,Open drain mode enable" "Disabled,Enabled" bitfld.long 0x04 3. " FUNC ,Functionality of pin" "GPIO,CAN" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,Output" else bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,I/O" endif textline " " bitfld.long 0x04 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High" bitfld.long 0x04 0. " IN ,Value of pin" "Low,High" endif width 0xb tree.end tree "CAN 1" base ad:0x481D0000 width 23. group.long 0x00++0x03 line.long 0x00 "DCAN_CTL,CAN Control Register" sif (cpuis("AM335*")) bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity" "No wake up,Wake up" bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "Not requested,Requested" else bitfld.long 0x00 26. " WUBA ,Automatic wake up on bus activity" "No wake up,Wake up" bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "Not requested,Requested" endif textline " " bitfld.long 0x00 20. " DE3 ,DMA enable for IF3" "Disabled,Enabled" bitfld.long 0x00 19. " DE2 ,DMA enable for IF2" "Disabled,Enabled" bitfld.long 0x00 18. " DE1 ,DMA enable for IF1" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IE1 ,DCAN1INT Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. " INITDBG ,Internal init state while debug access" "Not entered,Entered" bitfld.long 0x00 15. " SWR ,SW Reset Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 9. " ABO ,Auto Bus On Enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled" bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "Disabled,Enabled" bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SIE ,Status Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE0 ,DCAN0INT Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization" hgroup.long 0x04++0x03 hide.long 0x00 "DCAN_ES/PARITYERR_EOI,Error and Status/Parity Error EOI Register" in rgroup.long 0x08++0x03 line.long 0x00 "DCAN_ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive Error Passive" "No error,Error" hexmask.long.byte 0x00 8.--14. 1. " REC6-0 ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC7-0 ,Transmit Error Counter" if (((data.long(ad:0x481D0000))&0x41)==0x41) group.long 0x0c++0x03 sif (cpuis("DRA62*")||cpuis("AM335*")) line.long 0x00 "DCAN_BTR,Bit Timing Register" else line.long 0x00 "DCAN_BTBRP,Bit Timing_BRP Extension Register" endif bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The time segment after the sample point" "0,1,2,3,4,5,6,7" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline " " bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x0c++0x03 sif (cpuis("DRA62*")||cpuis("AM335*")) line.long 0x00 "DCAN_BTR,Bit Timing Register" else line.long 0x00 "DCAN_BTBRP,Bit Timing_BRP Extension Register" endif bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,The time segment after the sample point" "0,1,2,3,4,5,6,7" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "Reerved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.long 0x00 8.--11. " TSEG1 ,The time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif textline " " bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif rgroup.long 0x10++0x03 line.long 0x00 "DCAN_INTR,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID7-0 ,Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INT0ID15-0 ,Interrupt Identifier" if (((data.long(ad:0x481D0000))&0x80)==0x80) group.long 0x14++0x03 line.long 0x00 "DCAN_TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Direct access" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" textline " " bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,Dominant,Recessive" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled" else rgroup.long 0x14++0x03 line.long 0x00 "DCAN_TEST,Test Register" sif (cpuis("DRA62*")) bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Direct access" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive" textline " " bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,Dominant,Recessive" textline " " else bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Normal,Test" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Normal,External" bitfld.long 0x00 7. " RX ,Receive Pin" "0,1" textline " " bitfld.long 0x00 5.--6. " TX1-0 ,Control of CAN_TX pin" "Normal,Monitored,0,1" endif bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled" endif rgroup.long 0x1C++0x03 line.long 0x00 "DCAN_PERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WN ,Word Number" "Reserved,1,2,3,4,5,?..." hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" group.long 0x80++0x3 line.long 0x00 "DCAN_ABOTR,Auto Bus On Time Register" rgroup.long 0x84--0xD3 line.long 0x00 "DCAN_TXRQX,Transmission Request X Register" bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request X 8" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request X 7" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request X 6" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request X 5" "0,1,2,3" bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request X 4" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request X 3" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request X 2" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request X 1" "0,1,2,3" line.long 0x04 "DCAN_TXRQ12,Transmission Request 1_2 Register" bitfld.long 0x04 31. " TXRQST32 ,Transmission Request Bit 32" "Not requested,Requested" bitfld.long 0x04 30. " TXRQST31 ,Transmission Request Bit 31" "Not requested,Requested" bitfld.long 0x04 29. " TXRQST30 ,Transmission Request Bit 30" "Not requested,Requested" textline " " bitfld.long 0x04 28. " TXRQST29 ,Transmission Request Bit 29" "Not requested,Requested" bitfld.long 0x04 27. " TXRQST28 ,Transmission Request Bit 28" "Not requested,Requested" bitfld.long 0x04 26. " TXRQST27 ,Transmission Request Bit 27" "Not requested,Requested" textline " " bitfld.long 0x04 25. " TXRQST26 ,Transmission Request Bit 26" "Not requested,Requested" bitfld.long 0x04 24. " TXRQST25 ,Transmission Request Bit 25" "Not requested,Requested" bitfld.long 0x04 23. " TXRQST24 ,Transmission Request Bit 24" "Not requested,Requested" textline " " bitfld.long 0x04 22. " TXRQST23 ,Transmission Request Bit 23" "Not requested,Requested" bitfld.long 0x04 21. " TXRQST22 ,Transmission Request Bit 22" "Not requested,Requested" bitfld.long 0x04 20. " TXRQST21 ,Transmission Request Bit 21" "Not requested,Requested" textline " " bitfld.long 0x04 19. " TXRQST20 ,Transmission Request Bit 20" "Not requested,Requested" bitfld.long 0x04 18. " TXRQST19 ,Transmission Request Bit 19" "Not requested,Requested" bitfld.long 0x04 17. " TXRQST18 ,Transmission Request Bit 18" "Not requested,Requested" textline " " bitfld.long 0x04 16. " TXRQST17 ,Transmission Request Bit 17" "Not requested,Requested" bitfld.long 0x04 15. " TXRQST16 ,Transmission Request Bit 16" "Not requested,Requested" bitfld.long 0x04 14. " TXRQST15 ,Transmission Request Bit 15" "Not requested,Requested" textline " " bitfld.long 0x04 13. " TXRQST14 ,Transmission Request Bit 14" "Not requested,Requested" bitfld.long 0x04 12. " TXRQST13 ,Transmission Request Bit 13" "Not requested,Requested" bitfld.long 0x04 11. " TXRQST12 ,Transmission Request Bit 12" "Not requested,Requested" textline " " bitfld.long 0x04 10. " TXRQST11 ,Transmission Request Bit 11" "Not requested,Requested" bitfld.long 0x04 9. " TXRQST10 ,Transmission Request Bit 10" "Not requested,Requested" bitfld.long 0x04 8. " TXRQST9 ,Transmission Request Bit 9" "Not requested,Requested" textline " " bitfld.long 0x04 7. " TXRQST8 ,Transmission Request Bit 8" "Not requested,Requested" bitfld.long 0x04 6. " TXRQST7 ,Transmission Request Bit 7" "Not requested,Requested" bitfld.long 0x04 5. " TXRQST6 ,Transmission Request Bit 6" "Not requested,Requested" textline " " bitfld.long 0x04 4. " TXRQST5 ,Transmission Request Bit 5" "Not requested,Requested" bitfld.long 0x04 3. " TXRQST4 ,Transmission Request Bit 4" "Not requested,Requested" bitfld.long 0x04 2. " TXRQST3 ,Transmission Request Bit 3" "Not requested,Requested" textline " " bitfld.long 0x04 1. " TXRQST2 ,Transmission Request Bit 2" "Not requested,Requested" bitfld.long 0x04 0. " TXRQST1 ,Transmission Request Bit 1" "Not requested,Requested" line.long 0x08 "DCAN_TXRQ34,Transmission Request 3_4 Register" bitfld.long 0x08 31. " TXRQST64 ,Transmission Request Bit 64" "Not requested,Requested" bitfld.long 0x08 30. " TXRQST63 ,Transmission Request Bit 63" "Not requested,Requested" bitfld.long 0x08 29. " TXRQST62 ,Transmission Request Bit 62" "Not requested,Requested" textline " " bitfld.long 0x08 28. " TXRQST61 ,Transmission Request Bit 61" "Not requested,Requested" bitfld.long 0x08 27. " TXRQST60 ,Transmission Request Bit 60" "Not requested,Requested" bitfld.long 0x08 26. " TXRQST59 ,Transmission Request Bit 59" "Not requested,Requested" textline " " bitfld.long 0x08 25. " TXRQST58 ,Transmission Request Bit 58" "Not requested,Requested" bitfld.long 0x08 24. " TXRQST57 ,Transmission Request Bit 57" "Not requested,Requested" bitfld.long 0x08 23. " TXRQST56 ,Transmission Request Bit 56" "Not requested,Requested" textline " " bitfld.long 0x08 22. " TXRQST55 ,Transmission Request Bit 55" "Not requested,Requested" bitfld.long 0x08 21. " TXRQST54 ,Transmission Request Bit 54" "Not requested,Requested" bitfld.long 0x08 20. " TXRQST53 ,Transmission Request Bit 53" "Not requested,Requested" textline " " bitfld.long 0x08 19. " TXRQST52 ,Transmission Request Bit 52" "Not requested,Requested" bitfld.long 0x08 18. " TXRQST51 ,Transmission Request Bit 51" "Not requested,Requested" bitfld.long 0x08 17. " TXRQST50 ,Transmission Request Bit 50" "Not requested,Requested" textline " " bitfld.long 0x08 16. " TXRQST49 ,Transmission Request Bit 49" "Not requested,Requested" bitfld.long 0x08 15. " TXRQST48 ,Transmission Request Bit 48" "Not requested,Requested" bitfld.long 0x08 14. " TXRQST47 ,Transmission Request Bit 47" "Not requested,Requested" textline " " bitfld.long 0x08 13. " TXRQST46 ,Transmission Request Bit 46" "Not requested,Requested" bitfld.long 0x08 12. " TXRQST45 ,Transmission Request Bit 45" "Not requested,Requested" bitfld.long 0x08 11. " TXRQST44 ,Transmission Request Bit 44" "Not requested,Requested" textline " " bitfld.long 0x08 10. " TXRQST43 ,Transmission Request Bit 43" "Not requested,Requested" bitfld.long 0x08 9. " TXRQST42 ,Transmission Request Bit 42" "Not requested,Requested" bitfld.long 0x08 8. " TXRQST41 ,Transmission Request Bit 41" "Not requested,Requested" textline " " bitfld.long 0x08 7. " TXRQST40 ,Transmission Request Bit 40" "Not requested,Requested" bitfld.long 0x08 6. " TXRQST39 ,Transmission Request Bit 39" "Not requested,Requested" bitfld.long 0x08 5. " TXRQST38 ,Transmission Request Bit 38" "Not requested,Requested" textline " " bitfld.long 0x08 4. " TXRQST37 ,Transmission Request Bit 37" "Not requested,Requested" bitfld.long 0x08 3. " TXRQST36 ,Transmission Request Bit 36" "Not requested,Requested" bitfld.long 0x08 2. " TXRQST35 ,Transmission Request Bit 35" "Not requested,Requested" textline " " bitfld.long 0x08 1. " TXRQST34 ,Transmission Request Bit 34" "Not requested,Requested" bitfld.long 0x08 0. " TXRQST33 ,Transmission Request Bit 33" "Not requested,Requested" line.long 0x0c "DCAN_TXRQ56,Transmission Request 5_6 Register" bitfld.long 0x0c 31. " TXRQST96 ,Transmission Request Bit 96" "Not requested,Requested" bitfld.long 0x0c 30. " TXRQST95 ,Transmission Request Bit 95" "Not requested,Requested" bitfld.long 0x0c 29. " TXRQST94 ,Transmission Request Bit 94" "Not requested,Requested" textline " " bitfld.long 0x0c 28. " TXRQST93 ,Transmission Request Bit 93" "Not requested,Requested" bitfld.long 0x0c 27. " TXRQST92 ,Transmission Request Bit 92" "Not requested,Requested" bitfld.long 0x0c 26. " TXRQST91 ,Transmission Request Bit 91" "Not requested,Requested" textline " " bitfld.long 0x0c 25. " TXRQST90 ,Transmission Request Bit 90" "Not requested,Requested" bitfld.long 0x0c 24. " TXRQST89 ,Transmission Request Bit 89" "Not requested,Requested" bitfld.long 0x0c 23. " TXRQST88 ,Transmission Request Bit 88" "Not requested,Requested" textline " " bitfld.long 0x0c 22. " TXRQST87 ,Transmission Request Bit 87" "Not requested,Requested" bitfld.long 0x0c 21. " TXRQST86 ,Transmission Request Bit 86" "Not requested,Requested" bitfld.long 0x0c 20. " TXRQST85 ,Transmission Request Bit 85" "Not requested,Requested" textline " " bitfld.long 0x0c 19. " TXRQST84 ,Transmission Request Bit 84" "Not requested,Requested" bitfld.long 0x0c 18. " TXRQST83 ,Transmission Request Bit 83" "Not requested,Requested" bitfld.long 0x0c 17. " TXRQST82 ,Transmission Request Bit 82" "Not requested,Requested" textline " " bitfld.long 0x0c 16. " TXRQST81 ,Transmission Request Bit 81" "Not requested,Requested" bitfld.long 0x0c 15. " TXRQST80 ,Transmission Request Bit 80" "Not requested,Requested" bitfld.long 0x0c 14. " TXRQST79 ,Transmission Request Bit 79" "Not requested,Requested" textline " " bitfld.long 0x0c 13. " TXRQST78 ,Transmission Request Bit 78" "Not requested,Requested" bitfld.long 0x0c 12. " TXRQST77 ,Transmission Request Bit 77" "Not requested,Requested" bitfld.long 0x0c 11. " TXRQST76 ,Transmission Request Bit 76" "Not requested,Requested" textline " " bitfld.long 0x0c 10. " TXRQST75 ,Transmission Request Bit 75" "Not requested,Requested" bitfld.long 0x0c 9. " TXRQST74 ,Transmission Request Bit 74" "Not requested,Requested" bitfld.long 0x0c 8. " TXRQST73 ,Transmission Request Bit 73" "Not requested,Requested" textline " " bitfld.long 0x0c 7. " TXRQST72 ,Transmission Request Bit 72" "Not requested,Requested" bitfld.long 0x0c 6. " TXRQST71 ,Transmission Request Bit 71" "Not requested,Requested" bitfld.long 0x0c 5. " TXRQST70 ,Transmission Request Bit 70" "Not requested,Requested" textline " " bitfld.long 0x0c 4. " TXRQST69 ,Transmission Request Bit 69" "Not requested,Requested" bitfld.long 0x0c 3. " TXRQST68 ,Transmission Request Bit 68" "Not requested,Requested" bitfld.long 0x0c 2. " TXRQST67 ,Transmission Request Bit 67" "Not requested,Requested" textline " " bitfld.long 0x0c 1. " TXRQST66 ,Transmission Request Bit 66" "Not requested,Requested" bitfld.long 0x0c 0. " TXRQST65 ,Transmission Request Bit 65" "Not requested,Requested" line.long 0x10 "DCAN_TXRQ78,Transmission Request 7_8 Register" bitfld.long 0x10 31. " TXRQST128 ,Transmission Request Bit 128" "Not requested,Requested" bitfld.long 0x10 30. " TXRQST127 ,Transmission Request Bit 127" "Not requested,Requested" bitfld.long 0x10 29. " TXRQST126 ,Transmission Request Bit 126" "Not requested,Requested" textline " " bitfld.long 0x10 28. " TXRQST125 ,Transmission Request Bit 125" "Not requested,Requested" bitfld.long 0x10 27. " TXRQST124 ,Transmission Request Bit 124" "Not requested,Requested" bitfld.long 0x10 26. " TXRQST123 ,Transmission Request Bit 123" "Not requested,Requested" textline " " bitfld.long 0x10 25. " TXRQST122 ,Transmission Request Bit 122" "Not requested,Requested" bitfld.long 0x10 24. " TXRQST121 ,Transmission Request Bit 121" "Not requested,Requested" bitfld.long 0x10 23. " TXRQST120 ,Transmission Request Bit 120" "Not requested,Requested" textline " " bitfld.long 0x10 22. " TXRQST119 ,Transmission Request Bit 119" "Not requested,Requested" bitfld.long 0x10 21. " TXRQST118 ,Transmission Request Bit 118" "Not requested,Requested" bitfld.long 0x10 20. " TXRQST117 ,Transmission Request Bit 117" "Not requested,Requested" textline " " bitfld.long 0x10 19. " TXRQST116 ,Transmission Request Bit 116" "Not requested,Requested" bitfld.long 0x10 18. " TXRQST115 ,Transmission Request Bit 115" "Not requested,Requested" bitfld.long 0x10 17. " TXRQST114 ,Transmission Request Bit 114" "Not requested,Requested" textline " " bitfld.long 0x10 16. " TXRQST113 ,Transmission Request Bit 113" "Not requested,Requested" bitfld.long 0x10 15. " TXRQST112 ,Transmission Request Bit 112" "Not requested,Requested" bitfld.long 0x10 14. " TXRQST111 ,Transmission Request Bit 111" "Not requested,Requested" textline " " bitfld.long 0x10 13. " TXRQST110 ,Transmission Request Bit 110" "Not requested,Requested" bitfld.long 0x10 12. " TXRQST109 ,Transmission Request Bit 109" "Not requested,Requested" bitfld.long 0x10 11. " TXRQST108 ,Transmission Request Bit 108" "Not requested,Requested" textline " " bitfld.long 0x10 10. " TXRQST107 ,Transmission Request Bit 107" "Not requested,Requested" bitfld.long 0x10 9. " TXRQST106 ,Transmission Request Bit 106" "Not requested,Requested" bitfld.long 0x10 8. " TXRQST105 ,Transmission Request Bit 105" "Not requested,Requested" textline " " bitfld.long 0x10 7. " TXRQST104 ,Transmission Request Bit 104" "Not requested,Requested" bitfld.long 0x10 6. " TXRQST103 ,Transmission Request Bit 103" "Not requested,Requested" bitfld.long 0x10 5. " TXRQST102 ,Transmission Request Bit 102" "Not requested,Requested" textline " " bitfld.long 0x10 4. " TXRQST101 ,Transmission Request Bit 101" "Not requested,Requested" bitfld.long 0x10 3. " TXRQST100 ,Transmission Request Bit 100" "Not requested,Requested" bitfld.long 0x10 2. " TXRQST99 ,Transmission Request Bit 99" "Not requested,Requested" textline " " bitfld.long 0x10 1. " TXRQST98 ,Transmission Request Bit 98" "Not requested,Requested" bitfld.long 0x10 0. " TXRQST97 ,Transmission Request Bit 97" "Not requested,Requested" line.long 0x14 "DCAN_NWDAT_X,New Data X Register" bitfld.long 0x14 14.--15. " NEWDATREG8 ,New Data X 8" "0,1,2,3" bitfld.long 0x14 12.--13. " NEWDATREG7 ,New Data X 7" "0,1,2,3" bitfld.long 0x14 10.--11. " NEWDATREG6 ,New Data X 6" "0,1,2,3" textline " " bitfld.long 0x14 8.--9. " NEWDATREG5 ,New Data X 5" "0,1,2,3" bitfld.long 0x14 6.--7. " NEWDATREG4 ,New Data X 4" "0,1,2,3" bitfld.long 0x14 4.--5. " NEWDATREG3 ,New Data X 3" "0,1,2,3" textline " " bitfld.long 0x14 2.--3. " NEWDATREG2 ,New Data X 2" "0,1,2,3" bitfld.long 0x14 0.--1. " NEWDATREG1 ,New Data X 1" "0,1,2,3" line.long 0x18 "DCAN_NWDAT12,New Data 1_2 Register" bitfld.long 0x18 31. " NEWDAT32 ,New Data Bit 32" "Not written,Written" bitfld.long 0x18 30. " NEWDAT31 ,New Data Bit 31" "Not written,Written" bitfld.long 0x18 29. " NEWDAT30 ,New Data Bit 30" "Not written,Written" textline " " bitfld.long 0x18 28. " NEWDAT29 ,New Data Bit 29" "Not written,Written" bitfld.long 0x18 27. " NEWDAT28 ,New Data Bit 28" "Not written,Written" bitfld.long 0x18 26. " NEWDAT27 ,New Data Bit 27" "Not written,Written" textline " " bitfld.long 0x18 25. " NEWDAT26 ,New Data Bit 26" "Not written,Written" bitfld.long 0x18 24. " NEWDAT25 ,New Data Bit 25" "Not written,Written" bitfld.long 0x18 23. " NEWDAT24 ,New Data Bit 24" "Not written,Written" textline " " bitfld.long 0x18 22. " NEWDAT23 ,New Data Bit 23" "Not written,Written" bitfld.long 0x18 21. " NEWDAT22 ,New Data Bit 22" "Not written,Written" bitfld.long 0x18 20. " NEWDAT21 ,New Data Bit 21" "Not written,Written" textline " " bitfld.long 0x18 19. " NEWDAT20 ,New Data Bit 20" "Not written,Written" bitfld.long 0x18 18. " NEWDAT19 ,New Data Bit 19" "Not written,Written" bitfld.long 0x18 17. " NEWDAT18 ,New Data Bit 18" "Not written,Written" textline " " bitfld.long 0x18 16. " NEWDAT17 ,New Data Bit 17" "Not written,Written" bitfld.long 0x18 15. " NEWDAT16 ,New Data Bit 16" "Not written,Written" bitfld.long 0x18 14. " NEWDAT15 ,New Data Bit 15" "Not written,Written" textline " " bitfld.long 0x18 13. " NEWDAT14 ,New Data Bit 14" "Not written,Written" bitfld.long 0x18 12. " NEWDAT13 ,New Data Bit 13" "Not written,Written" bitfld.long 0x18 11. " NewDat12 ,New Data Bit 12" "Not written,Written" textline " " bitfld.long 0x18 10. " NEWDAT11 ,New Data Bit 11" "Not written,Written" bitfld.long 0x18 9. " NEWDAT10 ,New Data Bit 10" "Not written,Written" bitfld.long 0x18 8. " NEWDAT9 ,New Data Bit 9" "Not written,Written" textline " " bitfld.long 0x18 7. " NEWDAT8 ,New Data Bit 8" "Not written,Written" bitfld.long 0x18 6. " NEWDAT7 ,New Data Bit 7" "Not written,Written" bitfld.long 0x18 5. " NEWDAT6 ,New Data Bit 6" "Not written,Written" textline " " bitfld.long 0x18 4. " NEWDAT5 ,New Data Bit 5" "Not written,Written" bitfld.long 0x18 3. " NEWDAT4 ,New Data Bit 4" "Not written,Written" bitfld.long 0x18 2. " NEWDAT3 ,New Data Bit 3" "Not written,Written" textline " " bitfld.long 0x18 1. " NEWDAT2 ,New Data Bit 2" "Not written,Written" bitfld.long 0x18 0. " NEWDAT1 ,New Data Bit 1" "Not written,Written" line.long 0x1c "DCAN_NWDAT34,New Data 3_4 Register" bitfld.long 0x1c 31. " NEWDAT64 ,New Data Bit 64" "Not written,Written" bitfld.long 0x1c 30. " NEWDAT63 ,New Data Bit 63" "Not written,Written" bitfld.long 0x1c 29. " NEWDAT62 ,New Data Bit 62" "Not written,Written" textline " " bitfld.long 0x1c 28. " NEWDAT61 ,New Data Bit 61" "Not written,Written" bitfld.long 0x1c 27. " NEWDAT60 ,New Data Bit 60" "Not written,Written" bitfld.long 0x1c 26. " NEWDAT59 ,New Data Bit 59" "Not written,Written" textline " " bitfld.long 0x1c 25. " NEWDAT58 ,New Data Bit 58" "Not written,Written" bitfld.long 0x1c 24. " NEWDAT57 ,New Data Bit 57" "Not written,Written" bitfld.long 0x1c 23. " NEWDAT56 ,New Data Bit 56" "Not written,Written" textline " " bitfld.long 0x1c 22. " NEWDAT55 ,New Data Bit 55" "Not written,Written" bitfld.long 0x1c 21. " NEWDAT54 ,New Data Bit 54" "Not written,Written" bitfld.long 0x1c 20. " NEWDAT53 ,New Data Bit 53" "Not written,Written" textline " " bitfld.long 0x1c 19. " NEWDAT52 ,New Data Bit 52" "Not written,Written" bitfld.long 0x1c 18. " NEWDAT51 ,New Data Bit 51" "Not written,Written" bitfld.long 0x1c 17. " NEWDAT50 ,New Data Bit 50" "Not written,Written" textline " " bitfld.long 0x1c 16. " NEWDAT49 ,New Data Bit 49" "Not written,Written" bitfld.long 0x1c 15. " NEWDAT48 ,New Data Bit 48" "Not written,Written" bitfld.long 0x1c 14. " NEWDAT47 ,New Data Bit 47" "Not written,Written" textline " " bitfld.long 0x1c 13. " NEWDAT46 ,New Data Bit 46" "Not written,Written" bitfld.long 0x1c 12. " NEWDAT45 ,New Data Bit 45" "Not written,Written" bitfld.long 0x1c 11. " NEWDAT44 ,New Data Bit 44" "Not written,Written" textline " " bitfld.long 0x1c 10. " NEWDAT43 ,New Data Bit 43" "Not written,Written" bitfld.long 0x1c 9. " NEWDAT42 ,New Data Bit 42" "Not written,Written" bitfld.long 0x1c 8. " NEWDAT41 ,New Data Bit 41" "Not written,Written" textline " " bitfld.long 0x1c 7. " NEWDAT40 ,New Data Bit 40" "Not written,Written" bitfld.long 0x1c 6. " NEWDAT39 ,New Data Bit 39" "Not written,Written" bitfld.long 0x1c 5. " NEWDAT38 ,New Data Bit 38" "Not written,Written" textline " " bitfld.long 0x1c 4. " NEWDAT37 ,New Data Bit 37" "Not written,Written" bitfld.long 0x1c 3. " NEWDAT36 ,New Data Bit 36" "Not written,Written" bitfld.long 0x1c 2. " NEWDAT35 ,New Data Bit 35" "Not written,Written" textline " " bitfld.long 0x1c 1. " NEWDAT34 ,New Data Bit 34" "Not written,Written" bitfld.long 0x1c 0. " NEWDAT33 ,New Data Bit 33" "Not written,Written" line.long 0x20 "DCAN_NWDAT56,New Data 5_6 Register" bitfld.long 0x20 31. " NEWDAT96 ,New Data Bit 96" "Not written,Written" bitfld.long 0x20 30. " NEWDAT95 ,New Data Bit 95" "Not written,Written" bitfld.long 0x20 29. " NEWDAT94 ,New Data Bit 94" "Not written,Written" textline " " bitfld.long 0x20 28. " NEWDAT93 ,New Data Bit 93" "Not written,Written" bitfld.long 0x20 27. " NEWDAT92 ,New Data Bit 92" "Not written,Written" bitfld.long 0x20 26. " NEWDAT91 ,New Data Bit 91" "Not written,Written" textline " " bitfld.long 0x20 25. " NEWDAT90 ,New Data Bit 90" "Not written,Written" bitfld.long 0x20 24. " NEWDAT89 ,New Data Bit 89" "Not written,Written" bitfld.long 0x20 23. " NEWDAT88 ,New Data Bit 88" "Not written,Written" textline " " bitfld.long 0x20 22. " NEWDAT87 ,New Data Bit 87" "Not written,Written" bitfld.long 0x20 21. " NEWDAT86 ,New Data Bit 86" "Not written,Written" bitfld.long 0x20 20. " NEWDAT85 ,New Data Bit 85" "Not written,Written" textline " " bitfld.long 0x20 19. " NEWDAT84 ,New Data Bit 84" "Not written,Written" bitfld.long 0x20 18. " NEWDAT83 ,New Data Bit 83" "Not written,Written" bitfld.long 0x20 17. " NEWDAT82 ,New Data Bit 82" "Not written,Written" textline " " bitfld.long 0x20 16. " NEWDAT81 ,New Data Bit 81" "Not written,Written" bitfld.long 0x20 15. " NEWDAT80 ,New Data Bit 80" "Not written,Written" bitfld.long 0x20 14. " NEWDAT79 ,New Data Bit 79" "Not written,Written" textline " " bitfld.long 0x20 13. " NEWDAT78 ,New Data Bit 78" "Not written,Written" bitfld.long 0x20 12. " NEWDAT77 ,New Data Bit 77" "Not written,Written" bitfld.long 0x20 11. " NEWDAT76 ,New Data Bit 76" "Not written,Written" textline " " bitfld.long 0x20 10. " NEWDAT75 ,New Data Bit 75" "Not written,Written" bitfld.long 0x20 9. " NEWDAT74 ,New Data Bit 74" "Not written,Written" bitfld.long 0x20 8. " NEWDAT73 ,New Data Bit 73" "Not written,Written" textline " " bitfld.long 0x20 7. " NEWDAT72 ,New Data Bit 72" "Not written,Written" bitfld.long 0x20 6. " NEWDAT71 ,New Data Bit 71" "Not written,Written" bitfld.long 0x20 5. " NEWDAT70 ,New Data Bit 70" "Not written,Written" textline " " bitfld.long 0x20 4. " NEWDAT69 ,New Data Bit 69" "Not written,Written" bitfld.long 0x20 3. " NEWDAT68 ,New Data Bit 68" "Not written,Written" bitfld.long 0x20 2. " NEWDAT67 ,New Data Bit 67" "Not written,Written" textline " " bitfld.long 0x20 1. " NEWDAT66 ,New Data Bit 66" "Not written,Written" bitfld.long 0x20 0. " NEWDAT65 ,New Data Bit 65" "Not written,Written" line.long 0x24 "DCAN_NWDAT78,New Data 7_8 Register" bitfld.long 0x24 31. " NEWDAT128 ,New Data Bit 128" "Not written,Written" bitfld.long 0x24 30. " NEWDAT127 ,New Data Bit 127" "Not written,Written" bitfld.long 0x24 29. " NEWDAT126 ,New Data Bit 126" "Not written,Written" textline " " bitfld.long 0x24 28. " NEWDAT125 ,New Data Bit 125" "Not written,Written" bitfld.long 0x24 27. " NEWDAT124 ,New Data Bit 124" "Not written,Written" bitfld.long 0x24 26. " NEWDAT123 ,New Data Bit 123" "Not written,Written" textline " " bitfld.long 0x24 25. " NEWDAT122 ,New Data Bit 122" "Not written,Written" bitfld.long 0x24 24. " NEWDAT121 ,New Data Bit 121" "Not written,Written" bitfld.long 0x24 23. " NEWDAT120 ,New Data Bit 120" "Not written,Written" textline " " bitfld.long 0x24 22. " NEWDAT119 ,New Data Bit 119" "Not written,Written" bitfld.long 0x24 21. " NEWDAT118 ,New Data Bit 118" "Not written,Written" bitfld.long 0x24 20. " NEWDAT117 ,New Data Bit 117" "Not written,Written" textline " " bitfld.long 0x24 19. " NEWDAT116 ,New Data Bit 116" "Not written,Written" bitfld.long 0x24 18. " NEWDAT115 ,New Data Bit 115" "Not written,Written" bitfld.long 0x24 17. " NEWDAT114 ,New Data Bit 114" "Not written,Written" textline " " bitfld.long 0x24 16. " NEWDAT113 ,New Data Bit 113" "Not written,Written" bitfld.long 0x24 15. " NEWDAT112 ,New Data Bit 112" "Not written,Written" bitfld.long 0x24 14. " NEWDAT111 ,New Data Bit 111" "Not written,Written" textline " " bitfld.long 0x24 13. " NEWDAT110 ,New Data Bit 110" "Not written,Written" bitfld.long 0x24 12. " NEWDAT109 ,New Data Bit 109" "Not written,Written" bitfld.long 0x24 11. " NEWDAT108 ,New Data Bit 108" "Not written,Written" textline " " bitfld.long 0x24 10. " NEWDAT107 ,New Data Bit 107" "Not written,Written" bitfld.long 0x24 9. " NEWDAT106 ,New Data Bit 106" "Not written,Written" bitfld.long 0x24 8. " NEWDAT105 ,New Data Bit 105" "Not written,Written" textline " " bitfld.long 0x24 7. " NEWDAT104 ,New Data Bit 104" "Not written,Written" bitfld.long 0x24 6. " NEWDAT103 ,New Data Bit 103" "Not written,Written" bitfld.long 0x24 5. " NEWDAT102 ,New Data Bit 102" "Not written,Written" textline " " bitfld.long 0x24 4. " NEWDAT101 ,New Data Bit 101" "Not written,Written" bitfld.long 0x24 3. " NEWDAT100 ,New Data Bit 100" "Not written,Written" bitfld.long 0x24 2. " NEWDAT99 ,New Data Bit 99" "Not written,Written" textline " " bitfld.long 0x24 1. " NEWDAT98 ,New Data Bit 98" "Not written,Written" bitfld.long 0x24 0. " NEWDAT97 ,New Data Bit 97" "Not written,Written" line.long 0x28 "DCAN_INTPND_X,Interrupt Pending X Register" bitfld.long 0x28 14.--15. " INTPNDREG8 ,Interrupt Pending X Register 8" "0,1,2,3" bitfld.long 0x28 12.--13. " INTPNDREG7 ,Interrupt Pending X Register 7" "0,1,2,3" bitfld.long 0x28 10.--11. " INTPNDREG6 ,Interrupt Pending X Register 6" "0,1,2,3" textline " " bitfld.long 0x28 8.--9. " INTPNDREG5 ,Interrupt Pending X Register 5" "0,1,2,3" bitfld.long 0x28 6.--7. " INTPNDREG4 ,Interrupt Pending X Register 4" "0,1,2,3" bitfld.long 0x28 4.--5. " INTPNDREG3 ,Interrupt Pending X Register 3" "0,1,2,3" textline " " bitfld.long 0x28 2.--3. " INTPNDREG2 ,Interrupt Pending X Register 2" "0,1,2,3" bitfld.long 0x28 0.--1. " INTPNDREG1 ,Interrupt Pending X Register 1" "0,1,2,3" line.long 0x2C "DCAN_INTPND12,Interrupt Pending 1_2 Register" bitfld.long 0x2c 31. " INTPND32 ,Interrupt Pending Bit 32" "Not pending,Pending" bitfld.long 0x2c 30. " INTPND31 ,Interrupt Pending Bit 31" "Not pending,Pending" bitfld.long 0x2c 29. " INTPND30 ,Interrupt Pending Bit 30" "Not pending,Pending" textline " " bitfld.long 0x2c 28. " INTPND29 ,Interrupt Pending Bit 29" "Not pending,Pending" bitfld.long 0x2c 27. " INTPND28 ,Interrupt Pending Bit 28" "Not pending,Pending" bitfld.long 0x2c 26. " INTPND27 ,Interrupt Pending Bit 27" "Not pending,Pending" textline " " bitfld.long 0x2c 25. " INTPND26 ,Interrupt Pending Bit 26" "Not pending,Pending" bitfld.long 0x2c 24. " INTPND25 ,Interrupt Pending Bit 25" "Not pending,Pending" bitfld.long 0x2c 23. " INTPND24 ,Interrupt Pending Bit 24" "Not pending,Pending" textline " " bitfld.long 0x2c 22. " INTPND23 ,Interrupt Pending Bit 23" "Not pending,Pending" bitfld.long 0x2c 21. " INTPND22 ,Interrupt Pending Bit 22" "Not pending,Pending" bitfld.long 0x2c 20. " INTPND21 ,Interrupt Pending Bit 21" "Not pending,Pending" textline " " bitfld.long 0x2c 19. " INTPND20 ,Interrupt Pending Bit 20" "Not pending,Pending" bitfld.long 0x2c 18. " INTPND19 ,Interrupt Pending Bit 19" "Not pending,Pending" bitfld.long 0x2c 17. " INTPND18 ,Interrupt Pending Bit 18" "Not pending,Pending" textline " " bitfld.long 0x2c 16. " INTPND17 ,Interrupt Pending Bit 17" "Not pending,Pending" bitfld.long 0x2c 15. " INTPND16 ,Interrupt Pending Bit 16" "Not pending,Pending" bitfld.long 0x2c 14. " INTPND15 ,Interrupt Pending Bit 15" "Not pending,Pending" textline " " bitfld.long 0x2c 13. " INTPND14 ,Interrupt Pending Bit 14" "Not pending,Pending" bitfld.long 0x2c 12. " INTPND13 ,Interrupt Pending Bit 13" "Not pending,Pending" bitfld.long 0x2c 11. " INTPND12 ,Interrupt Pending Bit 12" "Not pending,Pending" textline " " bitfld.long 0x2c 10. " INTPND11 ,Interrupt Pending Bit 11" "Not pending,Pending" bitfld.long 0x2c 9. " INTPND10 ,Interrupt Pending Bit 10" "Not pending,Pending" bitfld.long 0x2c 8. " INTPND9 ,Interrupt Pending Bit 9" "Not pending,Pending" textline " " bitfld.long 0x2c 7. " INTPND8 ,Interrupt Pending Bit 8" "Not pending,Pending" bitfld.long 0x2c 6. " INTPND7 ,Interrupt Pending Bit 7" "Not pending,Pending" bitfld.long 0x2c 5. " INTPND6 ,Interrupt Pending Bit 6" "Not pending,Pending" textline " " bitfld.long 0x2c 4. " INTPND5 ,Interrupt Pending Bit 5" "Not pending,Pending" bitfld.long 0x2c 3. " INTPND4 ,Interrupt Pending Bit 4" "Not pending,Pending" bitfld.long 0x2c 2. " INTPND3 ,Interrupt Pending Bit 3" "Not pending,Pending" textline " " bitfld.long 0x2c 1. " INTPND2 ,Interrupt Pending Bit 2" "Not pending,Pending" bitfld.long 0x2c 0. " INTPND1 ,Interrupt Pending Bit 1" "Not pending,Pending" line.long 0x30 "DCAN_INTPND34,Interrupt Pending 3_4 Register" bitfld.long 0x30 31. " INTPND64 ,Interrupt Pending Bit 64" "Not pending,Pending" bitfld.long 0x30 30. " INTPND63 ,Interrupt Pending Bit 63" "Not pending,Pending" bitfld.long 0x30 29. " INTPND62 ,Interrupt Pending Bit 62" "Not pending,Pending" textline " " bitfld.long 0x30 28. " INTPND61 ,Interrupt Pending Bit 61" "Not pending,Pending" bitfld.long 0x30 27. " INTPND60 ,Interrupt Pending Bit 60" "Not pending,Pending" bitfld.long 0x30 26. " INTPND59 ,Interrupt Pending Bit 59" "Not pending,Pending" textline " " bitfld.long 0x30 25. " INTPND58 ,Interrupt Pending Bit 58" "Not pending,Pending" bitfld.long 0x30 24. " INTPND57 ,Interrupt Pending Bit 57" "Not pending,Pending" bitfld.long 0x30 23. " INTPND56 ,Interrupt Pending Bit 56" "Not pending,Pending" textline " " bitfld.long 0x30 22. " INTPND55 ,Interrupt Pending Bit 55" "Not pending,Pending" bitfld.long 0x30 21. " INTPND54 ,Interrupt Pending Bit 54" "Not pending,Pending" bitfld.long 0x30 20. " INTPND53 ,Interrupt Pending Bit 53" "Not pending,Pending" textline " " bitfld.long 0x30 19. " INTPND52 ,Interrupt Pending Bit 52" "Not pending,Pending" bitfld.long 0x30 18. " INTPND51 ,Interrupt Pending Bit 51" "Not pending,Pending" bitfld.long 0x30 17. " INTPND50 ,Interrupt Pending Bit 50" "Not pending,Pending" textline " " bitfld.long 0x30 16. " INTPND49 ,Interrupt Pending Bit 49" "Not pending,Pending" bitfld.long 0x30 15. " INTPND48 ,Interrupt Pending Bit 48" "Not pending,Pending" bitfld.long 0x30 14. " INTPND47 ,Interrupt Pending Bit 47" "Not pending,Pending" textline " " bitfld.long 0x30 13. " INTPND46 ,Interrupt Pending Bit 46" "Not pending,Pending" bitfld.long 0x30 12. " INTPND45 ,Interrupt Pending Bit 45" "Not pending,Pending" bitfld.long 0x30 11. " INTPND44 ,Interrupt Pending Bit 44" "Not pending,Pending" textline " " bitfld.long 0x30 10. " INTPND43 ,Interrupt Pending Bit 43" "Not pending,Pending" bitfld.long 0x30 9. " INTPND42 ,Interrupt Pending Bit 42" "Not pending,Pending" bitfld.long 0x30 8. " INTPND41 ,Interrupt Pending Bit 41" "Not pending,Pending" textline " " bitfld.long 0x30 7. " INTPND40 ,Interrupt Pending Bit 40" "Not pending,Pending" bitfld.long 0x30 6. " INTPND39 ,Interrupt Pending Bit 39" "Not pending,Pending" bitfld.long 0x30 5. " INTPND38 ,Interrupt Pending Bit 38" "Not pending,Pending" textline " " bitfld.long 0x30 4. " INTPND37 ,Interrupt Pending Bit 37" "Not pending,Pending" bitfld.long 0x30 3. " INTPND36 ,Interrupt Pending Bit 36" "Not pending,Pending" bitfld.long 0x30 2. " INTPND35 ,Interrupt Pending Bit 35" "Not pending,Pending" textline " " bitfld.long 0x30 1. " INTPND34 ,Interrupt Pending Bit 34" "Not pending,Pending" bitfld.long 0x30 0. " INTPND33 ,Interrupt Pending Bit 33" "Not pending,Pending" line.long 0x34 "DCAN_INTPND56,Interrupt Pending 5_6 Register" bitfld.long 0x34 31. " INTPND96 ,Interrupt Pending Bit 96" "Not pending,Pending" bitfld.long 0x34 30. " INTPND95 ,Interrupt Pending Bit 95" "Not pending,Pending" bitfld.long 0x34 29. " INTPND94 ,Interrupt Pending Bit 94" "Not pending,Pending" textline " " bitfld.long 0x34 28. " INTPND93 ,Interrupt Pending Bit 93" "Not pending,Pending" bitfld.long 0x34 27. " INTPND92 ,Interrupt Pending Bit 92" "Not pending,Pending" bitfld.long 0x34 26. " INTPND91 ,Interrupt Pending Bit 91" "Not pending,Pending" textline " " bitfld.long 0x34 25. " INTPND90 ,Interrupt Pending Bit 90" "Not pending,Pending" bitfld.long 0x34 24. " INTPND89 ,Interrupt Pending Bit 89" "Not pending,Pending" bitfld.long 0x34 23. " INTPND88 ,Interrupt Pending Bit 88" "Not pending,Pending" textline " " bitfld.long 0x34 22. " INTPND87 ,Interrupt Pending Bit 87" "Not pending,Pending" bitfld.long 0x34 21. " INTPND86 ,Interrupt Pending Bit 86" "Not pending,Pending" bitfld.long 0x34 20. " INTPND85 ,Interrupt Pending Bit 85" "Not pending,Pending" textline " " bitfld.long 0x34 19. " INTPND84 ,Interrupt Pending Bit 84" "Not pending,Pending" bitfld.long 0x34 18. " INTPND83 ,Interrupt Pending Bit 83" "Not pending,Pending" bitfld.long 0x34 17. " INTPND82 ,Interrupt Pending Bit 82" "Not pending,Pending" textline " " bitfld.long 0x34 16. " INTPND81 ,Interrupt Pending Bit 81" "Not pending,Pending" bitfld.long 0x34 15. " INTPND80 ,Interrupt Pending Bit 80" "Not pending,Pending" bitfld.long 0x34 14. " INTPND79 ,Interrupt Pending Bit 79" "Not pending,Pending" textline " " bitfld.long 0x34 13. " INTPND78 ,Interrupt Pending Bit 78" "Not pending,Pending" bitfld.long 0x34 12. " INTPND77 ,Interrupt Pending Bit 77" "Not pending,Pending" bitfld.long 0x34 11. " INTPND76 ,Interrupt Pending Bit 76" "Not pending,Pending" textline " " bitfld.long 0x34 10. " INTPND75 ,Interrupt Pending Bit 75" "Not pending,Pending" bitfld.long 0x34 9. " INTPND74 ,Interrupt Pending Bit 74" "Not pending,Pending" bitfld.long 0x34 8. " INTPND73 ,Interrupt Pending Bit 73" "Not pending,Pending" textline " " bitfld.long 0x34 7. " INTPND72 ,Interrupt Pending Bit 72" "Not pending,Pending" bitfld.long 0x34 6. " INTPND71 ,Interrupt Pending Bit 71" "Not pending,Pending" bitfld.long 0x34 5. " INTPND70 ,Interrupt Pending Bit 70" "Not pending,Pending" textline " " bitfld.long 0x34 4. " INTPND69 ,Interrupt Pending Bit 69" "Not pending,Pending" bitfld.long 0x34 3. " INTPND68 ,Interrupt Pending Bit 68" "Not pending,Pending" bitfld.long 0x34 2. " INTPND67 ,Interrupt Pending Bit 67" "Not pending,Pending" textline " " bitfld.long 0x34 1. " INTPND66 ,Interrupt Pending Bit 66" "Not pending,Pending" bitfld.long 0x34 0. " INTPND65 ,Interrupt Pending Bit 65" "Not pending,Pending" line.long 0x38 "DCAN_INTPND78,Interrupt Pending 7_8 Register" bitfld.long 0x38 31. " INTPND128 ,Interrupt Pending Bit 128" "Not pending,Pending" bitfld.long 0x38 30. " INTPND127 ,Interrupt Pending Bit 127" "Not pending,Pending" bitfld.long 0x38 29. " INTPND126 ,Interrupt Pending Bit 126" "Not pending,Pending" textline " " bitfld.long 0x38 28. " INTPND125 ,Interrupt Pending Bit 125" "Not pending,Pending" bitfld.long 0x38 27. " INTPND124 ,Interrupt Pending Bit 124" "Not pending,Pending" bitfld.long 0x38 26. " INTPND123 ,Interrupt Pending Bit 123" "Not pending,Pending" textline " " bitfld.long 0x38 25. " INTPND122 ,Interrupt Pending Bit 122" "Not pending,Pending" bitfld.long 0x38 24. " INTPND121 ,Interrupt Pending Bit 121" "Not pending,Pending" bitfld.long 0x38 23. " INTPND120 ,Interrupt Pending Bit 120" "Not pending,Pending" textline " " bitfld.long 0x38 22. " INTPND119 ,Interrupt Pending Bit 119" "Not pending,Pending" bitfld.long 0x38 21. " INTPND118 ,Interrupt Pending Bit 118" "Not pending,Pending" bitfld.long 0x38 20. " INTPND117 ,Interrupt Pending Bit 117" "Not pending,Pending" textline " " bitfld.long 0x38 19. " INTPND116 ,Interrupt Pending Bit 116" "Not pending,Pending" bitfld.long 0x38 18. " INTPND115 ,Interrupt Pending Bit 115" "Not pending,Pending" bitfld.long 0x38 17. " INTPND114 ,Interrupt Pending Bit 114" "Not pending,Pending" textline " " bitfld.long 0x38 16. " INTPND113 ,Interrupt Pending Bit 113" "Not pending,Pending" bitfld.long 0x38 15. " INTPND112 ,Interrupt Pending Bit 112" "Not pending,Pending" bitfld.long 0x38 14. " INTPND111 ,Interrupt Pending Bit 111" "Not pending,Pending" textline " " bitfld.long 0x38 13. " INTPND110 ,Interrupt Pending Bit 110" "Not pending,Pending" bitfld.long 0x38 12. " INTPND109 ,Interrupt Pending Bit 109" "Not pending,Pending" bitfld.long 0x38 11. " INTPND108 ,Interrupt Pending Bit 108" "Not pending,Pending" textline " " bitfld.long 0x38 10. " INTPND107 ,Interrupt Pending Bit 107" "Not pending,Pending" bitfld.long 0x38 9. " INTPND106 ,Interrupt Pending Bit 106" "Not pending,Pending" bitfld.long 0x38 8. " INTPND105 ,Interrupt Pending Bit 105" "Not pending,Pending" textline " " bitfld.long 0x38 7. " INTPND104 ,Interrupt Pending Bit 104" "Not pending,Pending" bitfld.long 0x38 6. " INTPND103 ,Interrupt Pending Bit 103" "Not pending,Pending" bitfld.long 0x38 5. " INTPND102 ,Interrupt Pending Bit 102" "Not pending,Pending" textline " " bitfld.long 0x38 4. " INTPND101 ,Interrupt Pending Bit 101" "Not pending,Pending" bitfld.long 0x38 3. " INTPND100 ,Interrupt Pending Bit 100" "Not pending,Pending" bitfld.long 0x38 2. " INTPND99 ,Interrupt Pending Bit 99" "Not pending,Pending" textline " " bitfld.long 0x38 1. " INTPND98 ,Interrupt Pending Bit 98" "Not pending,Pending" bitfld.long 0x38 0. " INTPND97 ,Interrupt Pending Bit 97" "Not pending,Pending" line.long 0x3c "DCAN_MSGVAL_X,Message Valid X Register" bitfld.long 0x3c 14.--15. " MSGVALREG8 ,Message Valid X Register 8" "0,1,2,3" bitfld.long 0x3c 12.--13. " MSGVALREG7 ,Message Valid X Register 7" "0,1,2,3" bitfld.long 0x3c 10.--11. " MSGVALREG6 ,Message Valid X Register 6" "0,1,2,3" textline " " bitfld.long 0x3c 8.--9. " MSGVALREG5 ,Message Valid X Register 5" "0,1,2,3" bitfld.long 0x3c 6.--7. " MSGVALREG4 ,Message Valid X Register 4" "0,1,2,3" bitfld.long 0x3c 4.--5. " MSGVALREG3 ,Message Valid X Register 3" "0,1,2,3" textline " " bitfld.long 0x3c 2.--3. " MSGVALREG2 ,Message Valid X Register 2" "0,1,2,3" bitfld.long 0x3c 0.--1. " MSGVALREG1 ,Message Valid X Register 1" "0,1,2,3" line.long 0x40 "DCAN_MSGVAL12,Message Valid 1_2 Register" bitfld.long 0x40 31. " MSGVAL32 ,Message Valid Bit 32" "Ignored,Not ignored" bitfld.long 0x40 30. " MSGVAL31 ,Message Valid Bit 31" "Ignored,Not ignored" bitfld.long 0x40 29. " MSGVAL30 ,Message Valid Bit 30" "Ignored,Not ignored" textline " " bitfld.long 0x40 28. " MSGVAL29 ,Message Valid Bit 29" "Ignored,Not ignored" bitfld.long 0x40 27. " MSGVAL28 ,Message Valid Bit 28" "Ignored,Not ignored" bitfld.long 0x40 26. " MSGVAL27 ,Message Valid Bit 27" "Ignored,Not ignored" textline " " bitfld.long 0x40 25. " MSGVAL26 ,Message Valid Bit 26" "Ignored,Not ignored" bitfld.long 0x40 24. " MSGVAL25 ,Message Valid Bit 25" "Ignored,Not ignored" bitfld.long 0x40 23. " MSGVAL24 ,Message Valid Bit 24" "Ignored,Not ignored" textline " " bitfld.long 0x40 22. " MSGVAL23 ,Message Valid Bit 23" "Ignored,Not ignored" bitfld.long 0x40 21. " MSGVAL22 ,Message Valid Bit 22" "Ignored,Not ignored" bitfld.long 0x40 20. " MSGVAL21 ,Message Valid Bit 21" "Ignored,Not ignored" textline " " bitfld.long 0x40 19. " MSGVAL20 ,Message Valid Bit 20" "Ignored,Not ignored" bitfld.long 0x40 18. " MSGVAL19 ,Message Valid Bit 19" "Ignored,Not ignored" bitfld.long 0x40 17. " MSGVAL18 ,Message Valid Bit 18" "Ignored,Not ignored" textline " " bitfld.long 0x40 16. " MSGVAL17 ,Message Valid Bit 17" "Ignored,Not ignored" bitfld.long 0x40 15. " MSGVAL16 ,Message Valid Bit 16" "Ignored,Not ignored" bitfld.long 0x40 14. " MSGVAL15 ,Message Valid Bit 15" "Ignored,Not ignored" textline " " bitfld.long 0x40 13. " MSGVAL14 ,Message Valid Bit 14" "Ignored,Not ignored" bitfld.long 0x40 12. " MSGVAL13 ,Message Valid Bit 13" "Ignored,Not ignored" bitfld.long 0x40 11. " MSGVAL12 ,Message Valid Bit 12" "Ignored,Not ignored" textline " " bitfld.long 0x40 10. " MSGVAL11 ,Message Valid Bit 11" "Ignored,Not ignored" bitfld.long 0x40 9. " MSGVAL10 ,Message Valid Bit 10" "Ignored,Not ignored" bitfld.long 0x40 8. " MSGVAL9 ,Message Valid Bit 9" "Ignored,Not ignored" textline " " bitfld.long 0x40 7. " MSGVAL8 ,Message Valid Bit 8" "Ignored,Not ignored" bitfld.long 0x40 6. " MSGVAL7 ,Message Valid Bit 7" "Ignored,Not ignored" bitfld.long 0x40 5. " MSGVAL6 ,Message Valid Bit 6" "Ignored,Not ignored" textline " " bitfld.long 0x40 4. " MSGVAL5 ,Message Valid Bit 5" "Ignored,Not ignored" bitfld.long 0x40 3. " MSGVAL4 ,Message Valid Bit 4" "Ignored,Not ignored" bitfld.long 0x40 2. " MSGVAL3 ,Message Valid Bit 3" "Ignored,Not ignored" textline " " bitfld.long 0x40 1. " MSGVAL2 ,Message Valid Bit 2" "Ignored,Not ignored" bitfld.long 0x40 0. " MSGVAL1 ,Message Valid Bit 1" "Ignored,Not ignored" line.long 0x44 "DCAN_MSGVAL34,Message Valid 3_4 Register" bitfld.long 0x44 31. " MSGVAL64 ,Message Valid Bit 64" "Ignored,Not ignored" bitfld.long 0x44 30. " MSGVAL63 ,Message Valid Bit 63" "Ignored,Not ignored" bitfld.long 0x44 29. " MSGVAL62 ,Message Valid Bit 62" "Ignored,Not ignored" textline " " bitfld.long 0x44 28. " MSGVAL61 ,Message Valid Bit 61" "Ignored,Not ignored" bitfld.long 0x44 27. " MSGVAL60 ,Message Valid Bit 60" "Ignored,Not ignored" bitfld.long 0x44 26. " MSGVAL59 ,Message Valid Bit 59" "Ignored,Not ignored" textline " " bitfld.long 0x44 25. " MSGVAL58 ,Message Valid Bit 58" "Ignored,Not ignored" bitfld.long 0x44 24. " MSGVAL57 ,Message Valid Bit 57" "Ignored,Not ignored" bitfld.long 0x44 23. " MSGVAL56 ,Message Valid Bit 56" "Ignored,Not ignored" textline " " bitfld.long 0x44 22. " MSGVAL55 ,Message Valid Bit 55" "Ignored,Not ignored" bitfld.long 0x44 21. " MSGVAL54 ,Message Valid Bit 54" "Ignored,Not ignored" bitfld.long 0x44 20. " MSGVAL53 ,Message Valid Bit 53" "Ignored,Not ignored" textline " " bitfld.long 0x44 19. " MSGVAL52 ,Message Valid Bit 52" "Ignored,Not ignored" bitfld.long 0x44 18. " MSGVAL51 ,Message Valid Bit 51" "Ignored,Not ignored" bitfld.long 0x44 17. " MSGVAL50 ,Message Valid Bit 50" "Ignored,Not ignored" textline " " bitfld.long 0x44 16. " MSGVAL49 ,Message Valid Bit 49" "Ignored,Not ignored" bitfld.long 0x44 15. " MSGVAL48 ,Message Valid Bit 48" "Ignored,Not ignored" bitfld.long 0x44 14. " MSGVAL47 ,Message Valid Bit 47" "Ignored,Not ignored" textline " " bitfld.long 0x44 13. " MSGVAL46 ,Message Valid Bit 46" "Ignored,Not ignored" bitfld.long 0x44 12. " MSGVAL45 ,Message Valid Bit 45" "Ignored,Not ignored" bitfld.long 0x44 11. " MSGVAL44 ,Message Valid Bit 44" "Ignored,Not ignored" textline " " bitfld.long 0x44 10. " MSGVAL43 ,Message Valid Bit 43" "Ignored,Not ignored" bitfld.long 0x44 9. " MSGVAL42 ,Message Valid Bit 42" "Ignored,Not ignored" bitfld.long 0x44 8. " MSGVAL41 ,Message Valid Bit 41" "Ignored,Not ignored" textline " " bitfld.long 0x44 7. " MSGVAL40 ,Message Valid Bit 40" "Ignored,Not ignored" bitfld.long 0x44 6. " MSGVAL39 ,Message Valid Bit 39" "Ignored,Not ignored" bitfld.long 0x44 5. " MSGVAL38 ,Message Valid Bit 38" "Ignored,Not ignored" textline " " bitfld.long 0x44 4. " MSGVAL37 ,Message Valid Bit 37" "Ignored,Not ignored" bitfld.long 0x44 3. " MSGVAL36 ,Message Valid Bit 36" "Ignored,Not ignored" bitfld.long 0x44 2. " MSGVAL35 ,Message Valid Bit 35" "Ignored,Not ignored" textline " " bitfld.long 0x44 1. " MSGVAL34 ,Message Valid Bit 34" "Ignored,Not ignored" bitfld.long 0x44 0. " MSGVAL33 ,Message Valid Bit 33" "Ignored,Not ignored" line.long 0x48 "DCAN_MSGVAL56,Message Valid 5_6 Register" bitfld.long 0x48 31. " MSGVAL96 ,Message Valid Bit 96" "Ignored,Not ignored" bitfld.long 0x48 30. " MSGVAL95 ,Message Valid Bit 95" "Ignored,Not ignored" bitfld.long 0x48 29. " MSGVAL94 ,Message Valid Bit 94" "Ignored,Not ignored" textline " " bitfld.long 0x48 28. " MSGVAL93 ,Message Valid Bit 93" "Ignored,Not ignored" bitfld.long 0x48 27. " MSGVAL92 ,Message Valid Bit 92" "Ignored,Not ignored" bitfld.long 0x48 26. " MSGVAL91 ,Message Valid Bit 91" "Ignored,Not ignored" textline " " bitfld.long 0x48 25. " MSGVAL90 ,Message Valid Bit 90" "Ignored,Not ignored" bitfld.long 0x48 24. " MSGVAL89 ,Message Valid Bit 89" "Ignored,Not ignored" bitfld.long 0x48 23. " MSGVAL88 ,Message Valid Bit 88" "Ignored,Not ignored" textline " " bitfld.long 0x48 22. " MSGVAL87 ,Message Valid Bit 87" "Ignored,Not ignored" bitfld.long 0x48 21. " MSGVAL86 ,Message Valid Bit 86" "Ignored,Not ignored" bitfld.long 0x48 20. " MSGVAL85 ,Message Valid Bit 85" "Ignored,Not ignored" textline " " bitfld.long 0x48 19. " MSGVAL84 ,Message Valid Bit 84" "Ignored,Not ignored" bitfld.long 0x48 18. " MSGVAL83 ,Message Valid Bit 83" "Ignored,Not ignored" bitfld.long 0x48 17. " MSGVAL82 ,Message Valid Bit 82" "Ignored,Not ignored" textline " " bitfld.long 0x48 16. " MSGVAL81 ,Message Valid Bit 81" "Ignored,Not ignored" bitfld.long 0x48 15. " MSGVAL80 ,Message Valid Bit 80" "Ignored,Not ignored" bitfld.long 0x48 14. " MSGVAL79 ,Message Valid Bit 79" "Ignored,Not ignored" textline " " bitfld.long 0x48 13. " MSGVAL78 ,Message Valid Bit 78" "Ignored,Not ignored" bitfld.long 0x48 12. " MSGVAL77 ,Message Valid Bit 77" "Ignored,Not ignored" bitfld.long 0x48 11. " MSGVAL76 ,Message Valid Bit 76" "Ignored,Not ignored" textline " " bitfld.long 0x48 10. " MSGVAL75 ,Message Valid Bit 75" "Ignored,Not ignored" bitfld.long 0x48 9. " MSGVAL74 ,Message Valid Bit 74" "Ignored,Not ignored" bitfld.long 0x48 8. " MSGVAL73 ,Message Valid Bit 73" "Ignored,Not ignored" textline " " bitfld.long 0x48 7. " MSGVAL72 ,Message Valid Bit 72" "Ignored,Not ignored" bitfld.long 0x48 6. " MSGVAL71 ,Message Valid Bit 71" "Ignored,Not ignored" bitfld.long 0x48 5. " MSGVAL70 ,Message Valid Bit 70" "Ignored,Not ignored" textline " " bitfld.long 0x48 4. " MSGVAL69 ,Message Valid Bit 69" "Ignored,Not ignored" bitfld.long 0x48 3. " MSGVAL68 ,Message Valid Bit 68" "Ignored,Not ignored" bitfld.long 0x48 2. " MSGVAL67 ,Message Valid Bit 67" "Ignored,Not ignored" textline " " bitfld.long 0x48 1. " MSGVAL66 ,Message Valid Bit 66" "Ignored,Not ignored" bitfld.long 0x48 0. " MSGVAL65 ,Message Valid Bit 65" "Ignored,Not ignored" line.long 0x4C "DCAN_MSGVAL78,Message Valid 7_8 Register" bitfld.long 0x4C 31. " MSGVAL128 ,Message Valid Bit 128" "Ignored,Not ignored" bitfld.long 0x4C 30. " MSGVAL127 ,Message Valid Bit 127" "Ignored,Not ignored" bitfld.long 0x4C 29. " MSGVAL126 ,Message Valid Bit 126" "Ignored,Not ignored" textline " " bitfld.long 0x4C 28. " MSGVAL125 ,Message Valid Bit 125" "Ignored,Not ignored" bitfld.long 0x4C 27. " MSGVAL124 ,Message Valid Bit 124" "Ignored,Not ignored" bitfld.long 0x4C 26. " MSGVAL123 ,Message Valid Bit 123" "Ignored,Not ignored" textline " " bitfld.long 0x4C 25. " MSGVAL122 ,Message Valid Bit 122" "Ignored,Not ignored" bitfld.long 0x4C 24. " MSGVAL121 ,Message Valid Bit 121" "Ignored,Not ignored" bitfld.long 0x4C 23. " MSGVAL120 ,Message Valid Bit 120" "Ignored,Not ignored" textline " " bitfld.long 0x4C 22. " MSGVAL119 ,Message Valid Bit 119" "Ignored,Not ignored" bitfld.long 0x4C 21. " MSGVAL118 ,Message Valid Bit 118" "Ignored,Not ignored" bitfld.long 0x4C 20. " MSGVAL117 ,Message Valid Bit 117" "Ignored,Not ignored" textline " " bitfld.long 0x4C 19. " MSGVAL116 ,Message Valid Bit 116" "Ignored,Not ignored" bitfld.long 0x4C 18. " MSGVAL115 ,Message Valid Bit 115" "Ignored,Not ignored" bitfld.long 0x4C 17. " MSGVAL114 ,Message Valid Bit 114" "Ignored,Not ignored" textline " " bitfld.long 0x4C 16. " MSGVAL113 ,Message Valid Bit 113" "Ignored,Not ignored" bitfld.long 0x4C 15. " MSGVAL112 ,Message Valid Bit 112" "Ignored,Not ignored" bitfld.long 0x4C 14. " MSGVAL111 ,Message Valid Bit 111" "Ignored,Not ignored" textline " " bitfld.long 0x4C 13. " MSGVAL110 ,Message Valid Bit 110" "Ignored,Not ignored" bitfld.long 0x4C 12. " MSGVAL109 ,Message Valid Bit 109" "Ignored,Not ignored" bitfld.long 0x4C 11. " MSGVAL108 ,Message Valid Bit 108" "Ignored,Not ignored" textline " " bitfld.long 0x4C 10. " MSGVAL107 ,Message Valid Bit 107" "Ignored,Not ignored" bitfld.long 0x4C 9. " MSGVAL106 ,Message Valid Bit 106" "Ignored,Not ignored" bitfld.long 0x4C 8. " MSGVAL105 ,Message Valid Bit 105" "Ignored,Not ignored" textline " " bitfld.long 0x4C 7. " MSGVAL104 ,Message Valid Bit 104" "Ignored,Not ignored" bitfld.long 0x4C 6. " MSGVAL103 ,Message Valid Bit 103" "Ignored,Not ignored" bitfld.long 0x4C 5. " MSGVAL102 ,Message Valid Bit 102" "Ignored,Not ignored" textline " " bitfld.long 0x4C 4. " MSGVAL101 ,Message Valid Bit 101" "Ignored,Not ignored" bitfld.long 0x4C 3. " MSGVAL100 ,Message Valid Bit 100" "Ignored,Not ignored" bitfld.long 0x4C 2. " MSGVAL99 ,Message Valid Bit 99" "Ignored,Not ignored" textline " " bitfld.long 0x4C 1. " MSGVAL98 ,Message Valid Bit 98" "Ignored,Not ignored" bitfld.long 0x4C 0. " MSGVAL97 ,Message Valid Bit 97" "Ignored,Not ignored" group.long 0xD8--0xE7 sif (cpuis("DRA62*")) line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer 1_2 Register" bitfld.long 0x00 31. " INTMUX32 ,Multiplexes IntPnd value to one of two interrupt line 32" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTMUX31 ,Multiplexes IntPnd value to one of two interrupt line 31" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTMUX30 ,Multiplexes IntPnd value to one of two interrupt line 30" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 28. " INTMUX29 ,Multiplexes IntPnd value to one of two interrupt line 29" "DCAN0INT,DCAN1INT" bitfld.long 0x00 27. " INTMUX28 ,Multiplexes IntPnd value to one of two interrupt line 28" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTMUX27 ,Multiplexes IntPnd value to one of two interrupt line 27" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTMUX26 ,Multiplexes IntPnd value to one of two interrupt line 26" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTMUX25 ,Multiplexes IntPnd value to one of two interrupt line 25" "DCAN0INT,DCAN1INT" bitfld.long 0x00 23. " INTMUX24 ,Multiplexes IntPnd value to one of two interrupt line 24" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 22. " INTMUX23 ,Multiplexes IntPnd value to one of two interrupt line 23" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTMUX22 ,Multiplexes IntPnd value to one of two interrupt line 22" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTMUX21 ,Multiplexes IntPnd value to one of two interrupt line 21" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTMUX20 ,Multiplexes IntPnd value to one of two interrupt line 20" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTMUX19 ,Multiplexes IntPnd value to one of two interrupt line 19" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTMUX18 ,Multiplexes IntPnd value to one of two interrupt line 18" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 16. " INTMUX17 ,Multiplexes IntPnd value to one of two interrupt line 17" "DCAN0INT,DCAN1INT" bitfld.long 0x00 15. " INTMUX16 ,Multiplexes IntPnd value to one of two interrupt line 16" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTMUX15 ,Multiplexes IntPnd value to one of two interrupt line 15" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTMUX14 ,Multiplexes IntPnd value to one of two interrupt line 14" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTMUX13 ,Multiplexes IntPnd value to one of two interrupt line 13" "DCAN0INT,DCAN1INT" bitfld.long 0x00 11. " INTMUX12 ,Multiplexes IntPnd value to one of two interrupt line 12" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 10. " INTMUX11 ,Multiplexes IntPnd value to one of two interrupt line 11" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTMUX10 ,Multiplexes IntPnd value to one of two interrupt line 10" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTMUX9 ,Multiplexes IntPnd value to one of two interrupt line 9" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTMUX8 ,Multiplexes IntPnd value to one of two interrupt line 8" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTMUX7 ,Multiplexes IntPnd value to one of two interrupt line 7" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTMUX6 ,Multiplexes IntPnd value to one of two interrupt line 6" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 4. " INTMUX5 ,Multiplexes IntPnd value to one of two interrupt line 5" "DCAN0INT,DCAN1INT" bitfld.long 0x00 3. " INTMUX4 ,Multiplexes IntPnd value to one of two interrupt line 4" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTMUX3 ,Multiplexes IntPnd value to one of two interrupt line 3" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTMUX2 ,Multiplexes IntPnd value to one of two interrupt line 2" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTMUX1 ,Multiplexes IntPnd value to one of two interrupt line 1" "DCAN0INT,DCAN1INT" line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer 3_4 Register" bitfld.long 0x04 31. " INTMUX64 ,Multiplexes IntPnd value to one of two interrupt line 64" "DCAN0INT,DCAN1INT" bitfld.long 0x04 30. " INTMUX63 ,Multiplexes IntPnd value to one of two interrupt line 63" "DCAN0INT,DCAN1INT" bitfld.long 0x04 29. " INTMUX62 ,Multiplexes IntPnd value to one of two interrupt line 62" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 28. " INTMUX61 ,Multiplexes IntPnd value to one of two interrupt line 61" "DCAN0INT,DCAN1INT" bitfld.long 0x04 27. " INTMUX60 ,Multiplexes IntPnd value to one of two interrupt line 60" "DCAN0INT,DCAN1INT" bitfld.long 0x04 26. " INTMUX59 ,Multiplexes IntPnd value to one of two interrupt line 59" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 25. " INTMUX58 ,Multiplexes IntPnd value to one of two interrupt line 58" "DCAN0INT,DCAN1INT" bitfld.long 0x04 24. " INTMUX57 ,Multiplexes IntPnd value to one of two interrupt line 57" "DCAN0INT,DCAN1INT" bitfld.long 0x04 23. " INTMUX56 ,Multiplexes IntPnd value to one of two interrupt line 56" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 22. " INTMUX55 ,Multiplexes IntPnd value to one of two interrupt line 55" "DCAN0INT,DCAN1INT" bitfld.long 0x04 21. " INTMUX54 ,Multiplexes IntPnd value to one of two interrupt line 54" "DCAN0INT,DCAN1INT" bitfld.long 0x04 20. " INTMUX53 ,Multiplexes IntPnd value to one of two interrupt line 53" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 19. " INTMUX52 ,Multiplexes IntPnd value to one of two interrupt line 52" "DCAN0INT,DCAN1INT" bitfld.long 0x04 18. " INTMUX51 ,Multiplexes IntPnd value to one of two interrupt line 51" "DCAN0INT,DCAN1INT" bitfld.long 0x04 17. " INTMUX50 ,Multiplexes IntPnd value to one of two interrupt line 50" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 16. " INTMUX49 ,Multiplexes IntPnd value to one of two interrupt line 49" "DCAN0INT,DCAN1INT" bitfld.long 0x04 15. " INTMUX48 ,Multiplexes IntPnd value to one of two interrupt line 48" "DCAN0INT,DCAN1INT" bitfld.long 0x04 14. " INTMUX47 ,Multiplexes IntPnd value to one of two interrupt line 47" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 13. " INTMUX46 ,Multiplexes IntPnd value to one of two interrupt line 46" "DCAN0INT,DCAN1INT" bitfld.long 0x04 12. " INTMUX45 ,Multiplexes IntPnd value to one of two interrupt line 45" "DCAN0INT,DCAN1INT" bitfld.long 0x04 11. " INTMUX44 ,Multiplexes IntPnd value to one of two interrupt line 44" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 10. " INTMUX43 ,Multiplexes IntPnd value to one of two interrupt line 43" "DCAN0INT,DCAN1INT" bitfld.long 0x04 9. " INTMUX42 ,Multiplexes IntPnd value to one of two interrupt line 42" "DCAN0INT,DCAN1INT" bitfld.long 0x04 8. " INTMUX41 ,Multiplexes IntPnd value to one of two interrupt line 41" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 7. " INTMUX40 ,Multiplexes IntPnd value to one of two interrupt line 40" "DCAN0INT,DCAN1INT" bitfld.long 0x04 6. " INTMUX39 ,Multiplexes IntPnd value to one of two interrupt line 39" "DCAN0INT,DCAN1INT" bitfld.long 0x04 5. " INTMUX38 ,Multiplexes IntPnd value to one of two interrupt line 38" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 4. " INTMUX37 ,Multiplexes IntPnd value to one of two interrupt line 37" "DCAN0INT,DCAN1INT" bitfld.long 0x04 3. " INTMUX36 ,Multiplexes IntPnd value to one of two interrupt line 36" "DCAN0INT,DCAN1INT" bitfld.long 0x04 2. " INTMUX35 ,Multiplexes IntPnd value to one of two interrupt line 35" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 1. " INTMUX34 ,Multiplexes IntPnd value to one of two interrupt line 34" "DCAN0INT,DCAN1INT" bitfld.long 0x04 0. " INTMUX33 ,Multiplexes IntPnd value to one of two interrupt line 33" "DCAN0INT,DCAN1INT" line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer 5_6 Register" bitfld.long 0x08 31. " INTMUX96 ,Multiplexes IntPnd value to one of two interrupt line 96" "DCAN0INT,DCAN1INT" bitfld.long 0x08 30. " INTMUX95 ,Multiplexes IntPnd value to one of two interrupt line 95" "DCAN0INT,DCAN1INT" bitfld.long 0x08 29. " INTMUX94 ,Multiplexes IntPnd value to one of two interrupt line 94" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 28. " INTMUX93 ,Multiplexes IntPnd value to one of two interrupt line 93" "DCAN0INT,DCAN1INT" bitfld.long 0x08 27. " INTMUX92 ,Multiplexes IntPnd value to one of two interrupt line 92" "DCAN0INT,DCAN1INT" bitfld.long 0x08 26. " INTMUX91 ,Multiplexes IntPnd value to one of two interrupt line 91" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 25. " INTMUX90 ,Multiplexes IntPnd value to one of two interrupt line 90" "DCAN0INT,DCAN1INT" bitfld.long 0x08 24. " INTMUX89 ,Multiplexes IntPnd value to one of two interrupt line 89" "DCAN0INT,DCAN1INT" bitfld.long 0x08 23. " INTMUX88 ,Multiplexes IntPnd value to one of two interrupt line 88" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 22. " INTMUX87 ,Multiplexes IntPnd value to one of two interrupt line 87" "DCAN0INT,DCAN1INT" bitfld.long 0x08 21. " INTMUX86 ,Multiplexes IntPnd value to one of two interrupt line 86" "DCAN0INT,DCAN1INT" bitfld.long 0x08 20. " INTMUX85 ,Multiplexes IntPnd value to one of two interrupt line 85" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 19. " INTMUX84 ,Multiplexes IntPnd value to one of two interrupt line 84" "DCAN0INT,DCAN1INT" bitfld.long 0x08 18. " INTMUX83 ,Multiplexes IntPnd value to one of two interrupt line 83" "DCAN0INT,DCAN1INT" bitfld.long 0x08 17. " INTMUX82 ,Multiplexes IntPnd value to one of two interrupt line 82" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 16. " INTMUX81 ,Multiplexes IntPnd value to one of two interrupt line 81" "DCAN0INT,DCAN1INT" bitfld.long 0x08 15. " INTMUX80 ,Multiplexes IntPnd value to one of two interrupt line 80" "DCAN0INT,DCAN1INT" bitfld.long 0x08 14. " INTMUX79 ,Multiplexes IntPnd value to one of two interrupt line 79" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 13. " INTMUX78 ,Multiplexes IntPnd value to one of two interrupt line 78" "DCAN0INT,DCAN1INT" bitfld.long 0x08 12. " INTMUX77 ,Multiplexes IntPnd value to one of two interrupt line 77" "DCAN0INT,DCAN1INT" bitfld.long 0x08 11. " INTMUX76 ,Multiplexes IntPnd value to one of two interrupt line 76" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 10. " INTMUX75 ,Multiplexes IntPnd value to one of two interrupt line 75" "DCAN0INT,DCAN1INT" bitfld.long 0x08 9. " INTMUX74 ,Multiplexes IntPnd value to one of two interrupt line 74" "DCAN0INT,DCAN1INT" bitfld.long 0x08 8. " INTMUX73 ,Multiplexes IntPnd value to one of two interrupt line 73" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 7. " INTMUX72 ,Multiplexes IntPnd value to one of two interrupt line 72" "DCAN0INT,DCAN1INT" bitfld.long 0x08 6. " INTMUX71 ,Multiplexes IntPnd value to one of two interrupt line 71" "DCAN0INT,DCAN1INT" bitfld.long 0x08 5. " INTMUX70 ,Multiplexes IntPnd value to one of two interrupt line 70" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 4. " INTMUX69 ,Multiplexes IntPnd value to one of two interrupt line 69" "DCAN0INT,DCAN1INT" bitfld.long 0x08 3. " INTMUX68 ,Multiplexes IntPnd value to one of two interrupt line 68" "DCAN0INT,DCAN1INT" bitfld.long 0x08 2. " INTMUX67 ,Multiplexes IntPnd value to one of two interrupt line 67" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 1. " INTMUX66 ,Multiplexes IntPnd value to one of two interrupt line 66" "DCAN0INT,DCAN1INT" bitfld.long 0x08 0. " INTMUX65 ,Multiplexes IntPnd value to one of two interrupt line 65" "DCAN0INT,DCAN1INT" line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer 7_8 Register" bitfld.long 0x0C 31. " INTMUX128 ,Multiplexes IntPnd value to one of two interrupt line 128" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 30. " INTMUX127 ,Multiplexes IntPnd value to one of two interrupt line 127" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 29. " INTMUX126 ,Multiplexes IntPnd value to one of two interrupt line 126" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 28. " INTMUX125 ,Multiplexes IntPnd value to one of two interrupt line 125" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 27. " INTMUX124 ,Multiplexes IntPnd value to one of two interrupt line 124" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 26. " INTMUX123 ,Multiplexes IntPnd value to one of two interrupt line 123" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 25. " INTMUX122 ,Multiplexes IntPnd value to one of two interrupt line 122" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 24. " INTMUX121 ,Multiplexes IntPnd value to one of two interrupt line 121" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 23. " INTMUX120 ,Multiplexes IntPnd value to one of two interrupt line 120" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 22. " INTMUX119 ,Multiplexes IntPnd value to one of two interrupt line 119" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 21. " INTMUX118 ,Multiplexes IntPnd value to one of two interrupt line 118" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 20. " INTMUX117 ,Multiplexes IntPnd value to one of two interrupt line 117" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 19. " INTMUX116 ,Multiplexes IntPnd value to one of two interrupt line 116" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 18. " INTMUX115 ,Multiplexes IntPnd value to one of two interrupt line 115" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 17. " INTMUX114 ,Multiplexes IntPnd value to one of two interrupt line 114" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 16. " INTMUX113 ,Multiplexes IntPnd value to one of two interrupt line 113" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 15. " INTMUX112 ,Multiplexes IntPnd value to one of two interrupt line 112" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 14. " INTMUX111 ,Multiplexes IntPnd value to one of two interrupt line 111" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 13. " INTMUX110 ,Multiplexes IntPnd value to one of two interrupt line 110" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 12. " INTMUX109 ,Multiplexes IntPnd value to one of two interrupt line 109" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 11. " INTMUX108 ,Multiplexes IntPnd value to one of two interrupt line 108" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 10. " INTMUX107 ,Multiplexes IntPnd value to one of two interrupt line 107" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 9. " INTMUX106 ,Multiplexes IntPnd value to one of two interrupt line 106" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 8. " INTMUX105 ,Multiplexes IntPnd value to one of two interrupt line 105" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 7. " INTMUX104 ,Multiplexes IntPnd value to one of two interrupt line 104" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 6. " INTMUX103 ,Multiplexes IntPnd value to one of two interrupt line 103" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 5. " INTMUX102 ,Multiplexes IntPnd value to one of two interrupt line 102" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 4. " INTMUX101 ,Multiplexes IntPnd value to one of two interrupt line 101" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 3. " INTMUX100 ,Multiplexes IntPnd value to one of two interrupt line 100" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 2. " INTMUX99 ,Multiplexes IntPnd value to one of two interrupt line 99" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 1. " INTMUX98 ,Multiplexes IntPnd value to one of two interrupt line 98" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 0. " INTMUX97 ,Multiplexes IntPnd value to one of two interrupt line 97" "DCAN0INT,DCAN1INT" else line.long 0x00 "DCAN_INTMUX12,Interrupt Multiplexer 1_2 Register" bitfld.long 0x00 31. " INTPNDMUX32 ,Multiplexes IntPnd value to one of two interrupt line 32" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX31 ,Multiplexes IntPnd value to one of two interrupt line 31" "DCAN0INT,DCAN1INT" bitfld.long 0x00 29. " INTPNDMUX30 ,Multiplexes IntPnd value to one of two interrupt line 30" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 28. " INTPNDMUX29 ,Multiplexes IntPnd value to one of two interrupt line 29" "DCAN0INT,DCAN1INT" bitfld.long 0x00 27. " INTPNDMUX28 ,Multiplexes IntPnd value to one of two interrupt line 28" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX27 ,Multiplexes IntPnd value to one of two interrupt line 27" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX26 ,Multiplexes IntPnd value to one of two interrupt line 26" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX25 ,Multiplexes IntPnd value to one of two interrupt line 25" "DCAN0INT,DCAN1INT" bitfld.long 0x00 23. " INTPNDMUX24 ,Multiplexes IntPnd value to one of two interrupt line 24" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 22. " INTPNDMUX23 ,Multiplexes IntPnd value to one of two interrupt line 23" "DCAN0INT,DCAN1INT" bitfld.long 0x00 21. " INTPNDMUX22 ,Multiplexes IntPnd value to one of two interrupt line 22" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX21 ,Multiplexes IntPnd value to one of two interrupt line 21" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX20 ,Multiplexes IntPnd value to one of two interrupt line 20" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX19 ,Multiplexes IntPnd value to one of two interrupt line 19" "DCAN0INT,DCAN1INT" bitfld.long 0x00 17. " INTPNDMUX18 ,Multiplexes IntPnd value to one of two interrupt line 18" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 16. " INTPNDMUX17 ,Multiplexes IntPnd value to one of two interrupt line 17" "DCAN0INT,DCAN1INT" bitfld.long 0x00 15. " INTPNDMUX16 ,Multiplexes IntPnd value to one of two interrupt line 16" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX15 ,Multiplexes IntPnd value to one of two interrupt line 15" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX14 ,Multiplexes IntPnd value to one of two interrupt line 14" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX13 ,Multiplexes IntPnd value to one of two interrupt line 13" "DCAN0INT,DCAN1INT" bitfld.long 0x00 11. " INTPNDMUX12 ,Multiplexes IntPnd value to one of two interrupt line 12" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 10. " INTPNDMUX11 ,Multiplexes IntPnd value to one of two interrupt line 11" "DCAN0INT,DCAN1INT" bitfld.long 0x00 9. " INTPNDMUX10 ,Multiplexes IntPnd value to one of two interrupt line 10" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX9 ,Multiplexes IntPnd value to one of two interrupt line 9" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX8 ,Multiplexes IntPnd value to one of two interrupt line 8" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX7 ,Multiplexes IntPnd value to one of two interrupt line 7" "DCAN0INT,DCAN1INT" bitfld.long 0x00 5. " INTPNDMUX6 ,Multiplexes IntPnd value to one of two interrupt line 6" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 4. " INTPNDMUX5 ,Multiplexes IntPnd value to one of two interrupt line 5" "DCAN0INT,DCAN1INT" bitfld.long 0x00 3. " INTPNDMUX4 ,Multiplexes IntPnd value to one of two interrupt line 4" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX3 ,Multiplexes IntPnd value to one of two interrupt line 3" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX2 ,Multiplexes IntPnd value to one of two interrupt line 2" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX1 ,Multiplexes IntPnd value to one of two interrupt line 1" "DCAN0INT,DCAN1INT" line.long 0x04 "DCAN_INTMUX34,Interrupt Multiplexer 3_4 Register" bitfld.long 0x04 31. " INTPNDMUX64 ,Multiplexes IntPnd value to one of two interrupt line 64" "DCAN0INT,DCAN1INT" bitfld.long 0x04 30. " INTPNDMUX63 ,Multiplexes IntPnd value to one of two interrupt line 63" "DCAN0INT,DCAN1INT" bitfld.long 0x04 29. " INTPNDMUX62 ,Multiplexes IntPnd value to one of two interrupt line 62" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 28. " INTPNDMUX61 ,Multiplexes IntPnd value to one of two interrupt line 61" "DCAN0INT,DCAN1INT" bitfld.long 0x04 27. " INTPNDMUX60 ,Multiplexes IntPnd value to one of two interrupt line 60" "DCAN0INT,DCAN1INT" bitfld.long 0x04 26. " INTPNDMUX59 ,Multiplexes IntPnd value to one of two interrupt line 59" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 25. " INTPNDMUX58 ,Multiplexes IntPnd value to one of two interrupt line 58" "DCAN0INT,DCAN1INT" bitfld.long 0x04 24. " INTPNDMUX57 ,Multiplexes IntPnd value to one of two interrupt line 57" "DCAN0INT,DCAN1INT" bitfld.long 0x04 23. " INTPNDMUX56 ,Multiplexes IntPnd value to one of two interrupt line 56" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 22. " INTPNDMUX55 ,Multiplexes IntPnd value to one of two interrupt line 55" "DCAN0INT,DCAN1INT" bitfld.long 0x04 21. " INTPNDMUX54 ,Multiplexes IntPnd value to one of two interrupt line 54" "DCAN0INT,DCAN1INT" bitfld.long 0x04 20. " INTPNDMUX53 ,Multiplexes IntPnd value to one of two interrupt line 53" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 19. " INTPNDMUX52 ,Multiplexes IntPnd value to one of two interrupt line 52" "DCAN0INT,DCAN1INT" bitfld.long 0x04 18. " INTPNDMUX51 ,Multiplexes IntPnd value to one of two interrupt line 51" "DCAN0INT,DCAN1INT" bitfld.long 0x04 17. " INTPNDMUX50 ,Multiplexes IntPnd value to one of two interrupt line 50" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 16. " INTPNDMUX49 ,Multiplexes IntPnd value to one of two interrupt line 49" "DCAN0INT,DCAN1INT" bitfld.long 0x04 15. " INTPNDMUX48 ,Multiplexes IntPnd value to one of two interrupt line 48" "DCAN0INT,DCAN1INT" bitfld.long 0x04 14. " INTPNDMUX47 ,Multiplexes IntPnd value to one of two interrupt line 47" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 13. " INTPNDMUX46 ,Multiplexes IntPnd value to one of two interrupt line 46" "DCAN0INT,DCAN1INT" bitfld.long 0x04 12. " INTPNDMUX45 ,Multiplexes IntPnd value to one of two interrupt line 45" "DCAN0INT,DCAN1INT" bitfld.long 0x04 11. " INTPNDMUX44 ,Multiplexes IntPnd value to one of two interrupt line 44" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 10. " INTPNDMUX43 ,Multiplexes IntPnd value to one of two interrupt line 43" "DCAN0INT,DCAN1INT" bitfld.long 0x04 9. " INTPNDMUX42 ,Multiplexes IntPnd value to one of two interrupt line 42" "DCAN0INT,DCAN1INT" bitfld.long 0x04 8. " INTPNDMUX41 ,Multiplexes IntPnd value to one of two interrupt line 41" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 7. " INTPNDMUX40 ,Multiplexes IntPnd value to one of two interrupt line 40" "DCAN0INT,DCAN1INT" bitfld.long 0x04 6. " INTPNDMUX39 ,Multiplexes IntPnd value to one of two interrupt line 39" "DCAN0INT,DCAN1INT" bitfld.long 0x04 5. " INTPNDMUX38 ,Multiplexes IntPnd value to one of two interrupt line 38" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 4. " INTPNDMUX37 ,Multiplexes IntPnd value to one of two interrupt line 37" "DCAN0INT,DCAN1INT" bitfld.long 0x04 3. " INTPNDMUX36 ,Multiplexes IntPnd value to one of two interrupt line 36" "DCAN0INT,DCAN1INT" bitfld.long 0x04 2. " INTPNDMUX35 ,Multiplexes IntPnd value to one of two interrupt line 35" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x04 1. " INTPNDMUX34 ,Multiplexes IntPnd value to one of two interrupt line 34" "DCAN0INT,DCAN1INT" bitfld.long 0x04 0. " INTPNDMUX33 ,Multiplexes IntPnd value to one of two interrupt line 33" "DCAN0INT,DCAN1INT" line.long 0x08 "DCAN_INTMUX56,Interrupt Multiplexer 5_6 Register" bitfld.long 0x08 31. " INTPNDMUX96 ,Multiplexes IntPnd value to one of two interrupt line 96" "DCAN0INT,DCAN1INT" bitfld.long 0x08 30. " INTPNDMUX95 ,Multiplexes IntPnd value to one of two interrupt line 95" "DCAN0INT,DCAN1INT" bitfld.long 0x08 29. " INTPNDMUX94 ,Multiplexes IntPnd value to one of two interrupt line 94" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 28. " INTPNDMUX93 ,Multiplexes IntPnd value to one of two interrupt line 93" "DCAN0INT,DCAN1INT" bitfld.long 0x08 27. " INTPNDMUX92 ,Multiplexes IntPnd value to one of two interrupt line 92" "DCAN0INT,DCAN1INT" bitfld.long 0x08 26. " INTPNDMUX91 ,Multiplexes IntPnd value to one of two interrupt line 91" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 25. " INTPNDMUX90 ,Multiplexes IntPnd value to one of two interrupt line 90" "DCAN0INT,DCAN1INT" bitfld.long 0x08 24. " INTPNDMUX89 ,Multiplexes IntPnd value to one of two interrupt line 89" "DCAN0INT,DCAN1INT" bitfld.long 0x08 23. " INTPNDMUX88 ,Multiplexes IntPnd value to one of two interrupt line 88" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 22. " INTPNDMUX87 ,Multiplexes IntPnd value to one of two interrupt line 87" "DCAN0INT,DCAN1INT" bitfld.long 0x08 21. " INTPNDMUX86 ,Multiplexes IntPnd value to one of two interrupt line 86" "DCAN0INT,DCAN1INT" bitfld.long 0x08 20. " INTPNDMUX85 ,Multiplexes IntPnd value to one of two interrupt line 85" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 19. " INTPNDMUX84 ,Multiplexes IntPnd value to one of two interrupt line 84" "DCAN0INT,DCAN1INT" bitfld.long 0x08 18. " INTPNDMUX83 ,Multiplexes IntPnd value to one of two interrupt line 83" "DCAN0INT,DCAN1INT" bitfld.long 0x08 17. " INTPNDMUX82 ,Multiplexes IntPnd value to one of two interrupt line 82" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 16. " INTPNDMUX81 ,Multiplexes IntPnd value to one of two interrupt line 81" "DCAN0INT,DCAN1INT" bitfld.long 0x08 15. " INTPNDMUX80 ,Multiplexes IntPnd value to one of two interrupt line 80" "DCAN0INT,DCAN1INT" bitfld.long 0x08 14. " INTPNDMUX79 ,Multiplexes IntPnd value to one of two interrupt line 79" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 13. " INTPNDMUX78 ,Multiplexes IntPnd value to one of two interrupt line 78" "DCAN0INT,DCAN1INT" bitfld.long 0x08 12. " INTPNDMUX77 ,Multiplexes IntPnd value to one of two interrupt line 77" "DCAN0INT,DCAN1INT" bitfld.long 0x08 11. " INTPNDMUX76 ,Multiplexes IntPnd value to one of two interrupt line 76" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 10. " INTPNDMUX75 ,Multiplexes IntPnd value to one of two interrupt line 75" "DCAN0INT,DCAN1INT" bitfld.long 0x08 9. " INTPNDMUX74 ,Multiplexes IntPnd value to one of two interrupt line 74" "DCAN0INT,DCAN1INT" bitfld.long 0x08 8. " INTPNDMUX73 ,Multiplexes IntPnd value to one of two interrupt line 73" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 7. " INTPNDMUX72 ,Multiplexes IntPnd value to one of two interrupt line 72" "DCAN0INT,DCAN1INT" bitfld.long 0x08 6. " INTPNDMUX71 ,Multiplexes IntPnd value to one of two interrupt line 71" "DCAN0INT,DCAN1INT" bitfld.long 0x08 5. " INTPNDMUX70 ,Multiplexes IntPnd value to one of two interrupt line 70" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 4. " INTPNDMUX69 ,Multiplexes IntPnd value to one of two interrupt line 69" "DCAN0INT,DCAN1INT" bitfld.long 0x08 3. " INTPNDMUX68 ,Multiplexes IntPnd value to one of two interrupt line 68" "DCAN0INT,DCAN1INT" bitfld.long 0x08 2. " INTPNDMUX67 ,Multiplexes IntPnd value to one of two interrupt line 67" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x08 1. " INTPNDMUX66 ,Multiplexes IntPnd value to one of two interrupt line 66" "DCAN0INT,DCAN1INT" bitfld.long 0x08 0. " INTPNDMUX65 ,Multiplexes IntPnd value to one of two interrupt line 65" "DCAN0INT,DCAN1INT" line.long 0x0C "DCAN_INTMUX78,Interrupt Multiplexer 7_8 Register" bitfld.long 0x0C 31. " INTPNDMUX128 ,Multiplexes IntPnd value to one of two interrupt line 128" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 30. " INTPNDMUX127 ,Multiplexes IntPnd value to one of two interrupt line 127" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 29. " INTPNDMUX126 ,Multiplexes IntPnd value to one of two interrupt line 126" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 28. " INTPNDMUX125 ,Multiplexes IntPnd value to one of two interrupt line 125" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 27. " INTPNDMUX124 ,Multiplexes IntPnd value to one of two interrupt line 124" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 26. " INTPNDMUX123 ,Multiplexes IntPnd value to one of two interrupt line 123" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 25. " INTPNDMUX122 ,Multiplexes IntPnd value to one of two interrupt line 122" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 24. " INTPNDMUX121 ,Multiplexes IntPnd value to one of two interrupt line 121" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 23. " INTPNDMUX120 ,Multiplexes IntPnd value to one of two interrupt line 120" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 22. " INTPNDMUX119 ,Multiplexes IntPnd value to one of two interrupt line 119" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 21. " INTPNDMUX118 ,Multiplexes IntPnd value to one of two interrupt line 118" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 20. " INTPNDMUX117 ,Multiplexes IntPnd value to one of two interrupt line 117" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 19. " INTPNDMUX116 ,Multiplexes IntPnd value to one of two interrupt line 116" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 18. " INTPNDMUX115 ,Multiplexes IntPnd value to one of two interrupt line 115" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 17. " INTPNDMUX114 ,Multiplexes IntPnd value to one of two interrupt line 114" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 16. " INTPNDMUX113 ,Multiplexes IntPnd value to one of two interrupt line 113" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 15. " INTPNDMUX112 ,Multiplexes IntPnd value to one of two interrupt line 112" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 14. " INTPNDMUX111 ,Multiplexes IntPnd value to one of two interrupt line 111" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 13. " INTPNDMUX110 ,Multiplexes IntPnd value to one of two interrupt line 110" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 12. " INTPNDMUX109 ,Multiplexes IntPnd value to one of two interrupt line 109" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 11. " INTPNDMUX108 ,Multiplexes IntPnd value to one of two interrupt line 108" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 10. " INTPNDMUX107 ,Multiplexes IntPnd value to one of two interrupt line 107" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 9. " INTPNDMUX106 ,Multiplexes IntPnd value to one of two interrupt line 106" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 8. " INTPNDMUX105 ,Multiplexes IntPnd value to one of two interrupt line 105" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 7. " INTPNDMUX104 ,Multiplexes IntPnd value to one of two interrupt line 104" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 6. " INTPNDMUX103 ,Multiplexes IntPnd value to one of two interrupt line 103" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 5. " INTPNDMUX102 ,Multiplexes IntPnd value to one of two interrupt line 102" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 4. " INTPNDMUX101 ,Multiplexes IntPnd value to one of two interrupt line 101" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 3. " INTPNDMUX100 ,Multiplexes IntPnd value to one of two interrupt line 100" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 2. " INTPNDMUX99 ,Multiplexes IntPnd value to one of two interrupt line 99" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x0C 1. " INTPNDMUX98 ,Multiplexes IntPnd value to one of two interrupt line 98" "DCAN0INT,DCAN1INT" bitfld.long 0x0C 0. " INTPNDMUX97 ,Multiplexes IntPnd value to one of two interrupt line 97" "DCAN0INT,DCAN1INT" endif if (((data.long(ad:0x481D0000+0x100))&0x800000)==0x800000) group.long 0x100++0x03 "IF1 Registers" line.long 0x00 "DCAN_IF1CMD,IF1 Command Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered" bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered" textline " " bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered" sif (cpuis("DRA62*")) bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,?..." bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Handled,Set" else bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Cleared,Set" endif textline " " bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered" bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" textline " " bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active" hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" else group.long 0x100++0x03 "IF1 Registers" line.long 0x00 "DCAN_IF1CMD,IF1 Command Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered" bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered" textline " " bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Unchanged,Cleared" textline " " bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered" bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" textline " " bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active" hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" endif if ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x40000000)) rgroup.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" elif ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x40000000)) group.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" elif ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x00)) rgroup.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK10-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" else group.long 0x104++0x03 line.long 0x00 "DCAN_IF1MSK,IF1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK10-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" endif if ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x40000000)) rgroup.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" elif ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x40000000)) group.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" elif ((((data.long(ad:0x481D0000+0x100))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x108))&0x40000000)==0x00000000)) group.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" else rgroup.long 0x108++0x03 line.long 0x00 "DCAN_IF1ARB,IF1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" endif if (((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000) rgroup.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" else group.long 0x10C++0x03 line.long 0x00 "DCAN_IF1MCTL,IF1 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" endif if (((data.long(ad:0x481D0000+0x100))&0x8000)==0x8000) rgroup.long 0x110++0x07 line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF1DATB,IF1 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" else group.long 0x110++0x07 line.long 0x00 "DCAN_IF1DATA,IF1 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF1DATB,IF1 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" endif if (((data.long(ad:0x481D0000+0x120))&0x800000)==0x800000) group.long 0x120++0x03 "IF2 Registers" line.long 0x00 "DCAN_IF2CMD,IF2 Command Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered" bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered" textline " " bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered" sif (cpuis("DRA62*")) bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,?..." bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Handled,Set" else bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Cleared,Set" endif textline " " bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered" bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" textline " " bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active" hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" else group.long 0x120++0x03 "IF2 Registers" line.long 0x00 "DCAN_IF2CMD,IF2 Command Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Unchanged,Transfered" bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Unchanged,Transfered" textline " " bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Transfered" bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Not cleared,Cleared" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Unchanged,Cleared" textline " " bitfld.long 0x00 17. " DATAA ,Access Data Bytes 0-3" "Unchanged,Transfered" bitfld.long 0x00 16. " DATAB ,Access Data Bytes 4-7" "Unchanged,Transfered" bitfld.long 0x00 15. " BUSY ,Busy Flag" "Not busy,Busy" textline " " bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1/2 update" "Not active,Active" hexmask.long.byte 0x00 0.--7. 1. " MN ,Message Number" endif if ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x40000000)) rgroup.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" elif ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x40000000)) group.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" elif ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x00)) rgroup.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-18 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" else group.long 0x124++0x03 line.long 0x00 "DCAN_IF2MSK,IF2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-18 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" endif if ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x40000000)) rgroup.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" elif ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x40000000)) group.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" elif ((((data.long(ad:0x481D0000+0x120))&0x8000)==0x0000)&&(((data.long(ad:0x481D0000+0x128))&0x40000000)==0x00000000)) group.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" else rgroup.long 0x128++0x03 line.long 0x00 "DCAN_IF2ARB,IF2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" endif if (((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000) rgroup.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" else group.long 0x12C++0x03 line.long 0x00 "DCAN_IF2MCTL,IF2 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" endif if (((data.long(ad:0x481D0000+0x120))&0x8000)==0x8000) rgroup.long 0x130++0x07 line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF2DATB,IF2 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" else group.long 0x130++0x07 line.long 0x00 "DCAN_IF2DATA,IF2 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF2DATB,IF2 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" endif group.long 0x140++0x03 "IF3 Registers" line.long 0x00 "DCAN_IF3OBS,IF3 Observation Register" bitfld.long 0x00 15. " IF3UPD ,IF3 Update Data" "Not updated,Updated" bitfld.long 0x00 12. " IF3SDB ,IF3 Status of Data B read access" "All read,Not all read" textline " " bitfld.long 0x00 11. " IF3SDA ,IF3 Status of Data A read access" "All read,Not all read" bitfld.long 0x00 10. " IF3SC ,IF3 Status of control bits read access" "All read,Not all read" textline " " bitfld.long 0x00 9. " IF3SA ,IF3 Status of Arbitration data read access" "All read,Not all read" bitfld.long 0x00 8. " IF3SM ,IF3 Status of Mask data read access" "All read,Not all read" textline " " bitfld.long 0x00 4. " DATAB ,Data B read observation" "Not read,Read" bitfld.long 0x00 3. " DATAA ,Data A read observation" "Not read,Read" bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "Not read,Read" textline " " bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "Not read,Read" bitfld.long 0x00 0. " MASK ,Mask data read observation" "Not read,Read" if (((data.long(ad:0x481D0000+0x148))&0x40000000)==0x40000000) rgroup.long 0x144++0x3 line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSK28-0 ,Identifier Mask" "0,1" bitfld.long 0x00 27. " ," "0,1" bitfld.long 0x00 26. " ," "0,1" bitfld.long 0x00 25. " ," "0,1" bitfld.long 0x00 24. " ," "0,1" bitfld.long 0x00 23. " ," "0,1" bitfld.long 0x00 22. " ," "0,1" bitfld.long 0x00 21. " ," "0,1" bitfld.long 0x00 20. " ," "0,1" bitfld.long 0x00 19. " ," "0,1" bitfld.long 0x00 18. " ," "0,1" bitfld.long 0x00 17. " ," "0,1" bitfld.long 0x00 16. " ," "0,1" bitfld.long 0x00 15. " ," "0,1" bitfld.long 0x00 14. " ," "0,1" bitfld.long 0x00 13. " ," "0,1" bitfld.long 0x00 12. " ," "0,1" bitfld.long 0x00 11. " ," "0,1" bitfld.long 0x00 10. " ," "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" else rgroup.long 0x144++0x3 line.long 0x00 "DCAN_IF3MSK,IF3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Disabled,Enabled" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MSK10-0 ,Identifier Mask" "0,1" bitfld.long 0x00 9. " ," "0,1" bitfld.long 0x00 8. " ," "0,1" bitfld.long 0x00 7. " ," "0,1" bitfld.long 0x00 6. " ," "0,1" bitfld.long 0x00 5. " ," "0,1" bitfld.long 0x00 4. " ," "0,1" bitfld.long 0x00 3. " ," "0,1" bitfld.long 0x00 2. " ," "0,1" bitfld.long 0x00 1. " ," "0,1" bitfld.long 0x00 0. " ," "0,1" endif if (((data.long(ad:0x481D0000+0x148))&0x40000000)==0x40000000) group.long 0x148++0x03 line.long 0x00 "DCAN_IF3ARB,IF3 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long 0x00 0.--28. 1. " ID28-0 ,Message Identifier 29-bit Identifier" else group.long 0x148++0x03 line.long 0x00 "DCAN_IF3ARB,IF3 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Not valid,Valid" bitfld.long 0x00 30. " XTD ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 29. " DIR ,Message Direction" "Receive,Transmit" hexmask.long.word 0x00 18.--28. 1. " ID28-18 ,Message Identifier 11-bit Identifier" endif rgroup.long 0x14C++0x03 line.long 0x00 "DCAN_IF3MCTL,IF3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Written" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,End of Block" "Not end,End" textline " " bitfld.long 0x00 0.--3. " DLC3-0 ,Data Length Code" "0 bytes,1 bytes,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes" rgroup.long 0x150++0x07 line.long 0x00 "DCAN_IF3DATA,IF3 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA(3) ,Data 3 Value" hexmask.long.byte 0x00 16.--23. 1. " DATA(2) ,Data 2 Value" hexmask.long.byte 0x00 8.--15. 1. " DATA(1) ,Data 1 Value" hexmask.long.byte 0x00 0.--7. 1. " DATA(0) ,Data 0 Value" line.long 0x04 "DCAN_IF3DATB,IF3 Data B Register" hexmask.long.byte 0x04 24.--31. 1. " DATA(7) ,Data 7 Value" hexmask.long.byte 0x04 16.--23. 1. " DATA(6) ,Data 6 Value" hexmask.long.byte 0x04 8.--15. 1. " DATA(5) ,Data 5 Value" hexmask.long.byte 0x04 0.--7. 1. " DATA(4) ,Data 4 Value" group.long 0x160--0x16F line.long 0x00 "IF3UPD12,Update Enable 1_2 Register" bitfld.long 0x00 31. " IF3UPDATEEN32 ,IF3 Update enabled 32" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN31 ,IF3 Update enabled 31" "Disabled,Enabled" bitfld.long 0x00 29. " IF3UPDATEEN30 ,IF3 Update enabled 30" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " IF3UPDATEEN29 ,IF3 Update enabled 29" "Disabled,Enabled" bitfld.long 0x00 27. " IF3UPDATEEN28 ,IF3 Update enabled 28" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN27 ,IF3 Update enabled 27" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN26 ,IF3 Update enabled 26" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN25 ,IF3 Update enabled 25" "Disabled,Enabled" bitfld.long 0x00 23. " IF3UPDATEEN24 ,IF3 Update enabled 24" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " IF3UPDATEEN23 ,IF3 Update enabled 23" "Disabled,Enabled" bitfld.long 0x00 21. " IF3UPDATEEN22 ,IF3 Update enabled 22" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN21 ,IF3 Update enabled 21" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN20 ,IF3 Update enabled 20" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN19 ,IF3 Update enabled 19" "Disabled,Enabled" bitfld.long 0x00 17. " IF3UPDATEEN18 ,IF3 Update enabled 18" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " IF3UPDATEEN17 ,IF3 Update enabled 17" "Disabled,Enabled" bitfld.long 0x00 15. " IF3UPDATEEN16 ,IF3 Update enabled 16" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN15 ,IF3 Update enabled 15" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN14 ,IF3 Update enabled 14" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN13 ,IF3 Update enabled 13" "Disabled,Enabled" bitfld.long 0x00 11. " IF3UPDATEEN12 ,IF3 Update enabled 12" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " IF3UPDATEEN11 ,IF3 Update enabled 11" "Disabled,Enabled" bitfld.long 0x00 9. " IF3UPDATEEN10 ,IF3 Update enabled 10" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN9 ,IF3 Update enabled 9" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN8 ,IF3 Update enabled 8" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN7 ,IF3 Update enabled 7" "Disabled,Enabled" bitfld.long 0x00 5. " IF3UPDATEEN6 ,IF3 Update enabled 6" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IF3UPDATEEN5 ,IF3 Update enabled 5" "Disabled,Enabled" bitfld.long 0x00 3. " IF3UPDATEEN4 ,IF3 Update enabled 4" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN3 ,IF3 Update enabled 3" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN2 ,IF3 Update enabled 2" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN1 ,IF3 Update enabled 1" "Disabled,Enabled" line.long 0x04 "IF3UPD3_4,Update Enable 3_4 Register" bitfld.long 0x04 31. " IF3UPDATEEN64 ,IF3 Update enabled 64" "Disabled,Enabled" bitfld.long 0x04 30. " IF3UPDATEEN63 ,IF3 Update enabled 63" "Disabled,Enabled" bitfld.long 0x04 29. " IF3UPDATEEN62 ,IF3 Update enabled 62" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " IF3UPDATEEN61 ,IF3 Update enabled 61" "Disabled,Enabled" bitfld.long 0x04 27. " IF3UPDATEEN60 ,IF3 Update enabled 60" "Disabled,Enabled" bitfld.long 0x04 26. " IF3UPDATEEN59 ,IF3 Update enabled 59" "Disabled,Enabled" textline " " bitfld.long 0x04 25. " IF3UPDATEEN58 ,IF3 Update enabled 58" "Disabled,Enabled" bitfld.long 0x04 24. " IF3UPDATEEN57 ,IF3 Update enabled 57" "Disabled,Enabled" bitfld.long 0x04 23. " IF3UPDATEEN56 ,IF3 Update enabled 56" "Disabled,Enabled" textline " " bitfld.long 0x04 22. " IF3UPDATEEN55 ,IF3 Update enabled 55" "Disabled,Enabled" bitfld.long 0x04 21. " IF3UPDATEEN54 ,IF3 Update enabled 54" "Disabled,Enabled" bitfld.long 0x04 20. " IF3UPDATEEN53 ,IF3 Update enabled 53" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " IF3UPDATEEN52 ,IF3 Update enabled 52" "Disabled,Enabled" bitfld.long 0x04 18. " IF3UPDATEEN51 ,IF3 Update enabled 51" "Disabled,Enabled" bitfld.long 0x04 17. " IF3UPDATEEN50 ,IF3 Update enabled 50" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " IF3UPDATEEN49 ,IF3 Update enabled 49" "Disabled,Enabled" bitfld.long 0x04 15. " IF3UPDATEEN48 ,IF3 Update enabled 48" "Disabled,Enabled" bitfld.long 0x04 14. " IF3UPDATEEN47 ,IF3 Update enabled 47" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " IF3UPDATEEN46 ,IF3 Update enabled 46" "Disabled,Enabled" bitfld.long 0x04 12. " IF3UPDATEEN45 ,IF3 Update enabled 45" "Disabled,Enabled" bitfld.long 0x04 11. " IF3UPDATEEN44 ,IF3 Update enabled 44" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " IF3UPDATEEN43 ,IF3 Update enabled 43" "Disabled,Enabled" bitfld.long 0x04 9. " IF3UPDATEEN42 ,IF3 Update enabled 42" "Disabled,Enabled" bitfld.long 0x04 8. " IF3UPDATEEN41 ,IF3 Update enabled 41" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " IF3UPDATEEN40 ,IF3 Update enabled 40" "Disabled,Enabled" bitfld.long 0x04 6. " IF3UPDATEEN39 ,IF3 Update enabled 39" "Disabled,Enabled" bitfld.long 0x04 5. " IF3UPDATEEN38 ,IF3 Update enabled 38" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " IF3UPDATEEN37 ,IF3 Update enabled 37" "Disabled,Enabled" bitfld.long 0x04 3. " IF3UPDATEEN36 ,IF3 Update enabled 36" "Disabled,Enabled" bitfld.long 0x04 2. " IF3UPDATEEN35 ,IF3 Update enabled 35" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " IF3UPDATEEN34 ,IF3 Update enabled 34" "Disabled,Enabled" bitfld.long 0x04 0. " IF3UPDATEEN33 ,IF3 Update enabled 33" "Disabled,Enabled" line.long 0x08 "IF3UPD5_6,Update Enable 5_6 Register" bitfld.long 0x08 31. " IF3UPDATEEN96 ,IF3 Update enabled 96" "Disabled,Enabled" bitfld.long 0x08 30. " IF3UPDATEEN95 ,IF3 Update enabled 95" "Disabled,Enabled" bitfld.long 0x08 29. " IF3UPDATEEN94 ,IF3 Update enabled 94" "Disabled,Enabled" textline " " bitfld.long 0x08 28. " IF3UPDATEEN93 ,IF3 Update enabled 93" "Disabled,Enabled" bitfld.long 0x08 27. " IF3UPDATEEN92 ,IF3 Update enabled 92" "Disabled,Enabled" bitfld.long 0x08 26. " IF3UPDATEEN91 ,IF3 Update enabled 91" "Disabled,Enabled" textline " " bitfld.long 0x08 25. " IF3UPDATEEN90 ,IF3 Update enabled 90" "Disabled,Enabled" bitfld.long 0x08 24. " IF3UPDATEEN89 ,IF3 Update enabled 89" "Disabled,Enabled" bitfld.long 0x08 23. " IF3UPDATEEN88 ,IF3 Update enabled 88" "Disabled,Enabled" textline " " bitfld.long 0x08 22. " IF3UPDATEEN87 ,IF3 Update enabled 87" "Disabled,Enabled" bitfld.long 0x08 21. " IF3UPDATEEN86 ,IF3 Update enabled 86" "Disabled,Enabled" bitfld.long 0x08 20. " IF3UPDATEEN85 ,IF3 Update enabled 85" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " IF3UPDATEEN84 ,IF3 Update enabled 84" "Disabled,Enabled" bitfld.long 0x08 18. " IF3UPDATEEN83 ,IF3 Update enabled 83" "Disabled,Enabled" bitfld.long 0x08 17. " IF3UPDATEEN82 ,IF3 Update enabled 82" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " IF3UPDATEEN81 ,IF3 Update enabled 81" "Disabled,Enabled" bitfld.long 0x08 15. " IF3UPDATEEN80 ,IF3 Update enabled 80" "Disabled,Enabled" bitfld.long 0x08 14. " IF3UPDATEEN79 ,IF3 Update enabled 79" "Disabled,Enabled" textline " " bitfld.long 0x08 13. " IF3UPDATEEN78 ,IF3 Update enabled 78" "Disabled,Enabled" bitfld.long 0x08 12. " IF3UPDATEEN77 ,IF3 Update enabled 77" "Disabled,Enabled" bitfld.long 0x08 11. " IF3UPDATEEN76 ,IF3 Update enabled 76" "Disabled,Enabled" textline " " bitfld.long 0x08 10. " IF3UPDATEEN75 ,IF3 Update enabled 75" "Disabled,Enabled" bitfld.long 0x08 9. " IF3UPDATEEN74 ,IF3 Update enabled 74" "Disabled,Enabled" bitfld.long 0x08 8. " IF3UPDATEEN73 ,IF3 Update enabled 73" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " IF3UPDATEEN72 ,IF3 Update enabled 72" "Disabled,Enabled" bitfld.long 0x08 6. " IF3UPDATEEN71 ,IF3 Update enabled 71" "Disabled,Enabled" bitfld.long 0x08 5. " IF3UPDATEEN70 ,IF3 Update enabled 70" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " IF3UPDATEEN69 ,IF3 Update enabled 69" "Disabled,Enabled" bitfld.long 0x08 3. " IF3UPDATEEN68 ,IF3 Update enabled 68" "Disabled,Enabled" bitfld.long 0x08 2. " IF3UPDATEEN67 ,IF3 Update enabled 67" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " IF3UPDATEEN66 ,IF3 Update enabled 66" "Disabled,Enabled" bitfld.long 0x08 0. " IF3UPDATEEN65 ,IF3 Update enabled 65" "Disabled,Enabled" line.long 0x0C "IF3UPD7_8,Update Enable 7_8 Register" bitfld.long 0x0C 31. " IF3UPDATEEN128 ,IF3 Update enabled 128" "Disabled,Enabled" bitfld.long 0x0C 30. " IF3UPDATEEN127 ,IF3 Update enabled 127" "Disabled,Enabled" bitfld.long 0x0C 29. " IF3UPDATEEN126 ,IF3 Update enabled 126" "Disabled,Enabled" textline " " bitfld.long 0x0C 28. " IF3UPDATEEN125 ,IF3 Update enabled 125" "Disabled,Enabled" bitfld.long 0x0C 27. " IF3UPDATEEN124 ,IF3 Update enabled 124" "Disabled,Enabled" bitfld.long 0x0C 26. " IF3UPDATEEN123 ,IF3 Update enabled 123" "Disabled,Enabled" textline " " bitfld.long 0x0C 25. " IF3UPDATEEN122 ,IF3 Update enabled 122" "Disabled,Enabled" bitfld.long 0x0C 24. " IF3UPDATEEN121 ,IF3 Update enabled 121" "Disabled,Enabled" bitfld.long 0x0C 23. " IF3UPDATEEN120 ,IF3 Update enabled 120" "Disabled,Enabled" textline " " bitfld.long 0x0C 22. " IF3UPDATEEN119 ,IF3 Update enabled 119" "Disabled,Enabled" bitfld.long 0x0C 21. " IF3UPDATEEN118 ,IF3 Update enabled 118" "Disabled,Enabled" bitfld.long 0x0C 20. " IF3UPDATEEN117 ,IF3 Update enabled 117" "Disabled,Enabled" textline " " bitfld.long 0x0C 19. " IF3UPDATEEN116 ,IF3 Update enabled 116" "Disabled,Enabled" bitfld.long 0x0C 18. " IF3UPDATEEN115 ,IF3 Update enabled 115" "Disabled,Enabled" bitfld.long 0x0C 17. " IF3UPDATEEN114 ,IF3 Update enabled 114" "Disabled,Enabled" textline " " bitfld.long 0x0C 16. " IF3UPDATEEN113 ,IF3 Update enabled 113" "Disabled,Enabled" bitfld.long 0x0C 15. " IF3UPDATEEN112 ,IF3 Update enabled 112" "Disabled,Enabled" bitfld.long 0x0C 14. " IF3UPDATEEN111 ,IF3 Update enabled 111" "Disabled,Enabled" textline " " bitfld.long 0x0C 13. " IF3UPDATEEN110 ,IF3 Update enabled 110" "Disabled,Enabled" bitfld.long 0x0C 12. " IF3UPDATEEN109 ,IF3 Update enabled 109" "Disabled,Enabled" bitfld.long 0x0C 11. " IF3UPDATEEN108 ,IF3 Update enabled 108" "Disabled,Enabled" textline " " bitfld.long 0x0C 10. " IF3UPDATEEN107 ,IF3 Update enabled 107" "Disabled,Enabled" bitfld.long 0x0C 9. " IF3UPDATEEN106 ,IF3 Update enabled 106" "Disabled,Enabled" bitfld.long 0x0C 8. " IF3UPDATEEN105 ,IF3 Update enabled 105" "Disabled,Enabled" textline " " bitfld.long 0x0C 7. " IF3UPDATEEN104 ,IF3 Update enabled 104" "Disabled,Enabled" bitfld.long 0x0C 6. " IF3UPDATEEN103 ,IF3 Update enabled 103" "Disabled,Enabled" bitfld.long 0x0C 5. " IF3UPDATEEN102 ,IF3 Update enabled 102" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " IF3UPDATEEN101 ,IF3 Update enabled 101" "Disabled,Enabled" bitfld.long 0x0C 3. " IF3UPDATEEN100 ,IF3 Update enabled 100" "Disabled,Enabled" bitfld.long 0x0C 2. " IF3UPDATEEN99 ,IF3 Update enabled 99" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " IF3UPDATEEN98 ,IF3 Update enabled 98" "Disabled,Enabled" bitfld.long 0x0C 0. " IF3UPDATEEN97 ,IF3 Update enabled 97" "Disabled,Enabled" width 12. if (((d.l(ad:0x481D0000))&0x1)==0x1) // DCAN_CTL.Init == 1 group.long 0x1E0++0x07 line.long 0x00 "DCAN_TIOC,TX IO Control Register" bitfld.long 0x00 18. " PU ,Selection of pull direction" "Pull-down,Pull-up" bitfld.long 0x00 17. " PD ,Pull functionality disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " OD ,Open drain mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " FUNC ,Functionality of pin" "GPIO,CAN" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,Output" else bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,I/O" endif textline " " bitfld.long 0x00 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of pin" "Low,High" line.long 0x04 "DCAN_RIOC,RX IO Control Register" bitfld.long 0x04 18. " PU ,Selection of pull direction" "Pull-down,Pull-up" bitfld.long 0x04 17. " PD ,Pull functionality disable" "Enabled,Disabled" textline " " bitfld.long 0x04 16. " OD ,Open drain mode enable" "Disabled,Enabled" bitfld.long 0x04 3. " FUNC ,Functionality of pin" "GPIO,CAN" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,Output" else bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,I/O" endif textline " " bitfld.long 0x04 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High" bitfld.long 0x04 0. " IN ,Value of pin" "Low,High" else rgroup.long 0x1E0++0x07 line.long 0x00 "DCAN_TIOC,TX IO Control Register" bitfld.long 0x00 18. " PU ,Selection of pull direction" "Pull-down,Pull-up" bitfld.long 0x00 17. " PD ,Pull functionality disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " OD ,Open drain mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " FUNC ,Functionality of pin" "GPIO,CAN" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,Output" else bitfld.long 0x00 2. " DIR ,Direction of pin" "Input,I/O" endif textline " " bitfld.long 0x00 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High" bitfld.long 0x00 0. " IN ,Value of pin" "Low,High" line.long 0x04 "DCAN_RIOC,RX IO Control Register" bitfld.long 0x04 18. " PU ,Selection of pull direction" "Pull-down,Pull-up" bitfld.long 0x04 17. " PD ,Pull functionality disable" "Enabled,Disabled" textline " " bitfld.long 0x04 16. " OD ,Open drain mode enable" "Disabled,Enabled" bitfld.long 0x04 3. " FUNC ,Functionality of pin" "GPIO,CAN" sif (cpuis("DRA62*")||cpuis("AM335*")) bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,Output" else bitfld.long 0x04 2. " DIR ,Direction of pin" "Input,I/O" endif textline " " bitfld.long 0x04 1. " OUT ,Value to drive to pin if configured for I/O" "Low,High" bitfld.long 0x04 0. " IN ,Value of pin" "Low,High" endif width 0xb tree.end tree.end tree "MCSPI (Multichannel Serial Port Interface)" tree "MCSPI 0" base ad:0x48030000 width 17. rgroup.long 0x00++0x03 line.long 0x00 "MCSPI_REVISION,McSPI Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old Scheme and current" "ASP or WTBU,Revision 0.8,?..." hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional Number" bitfld.long 0x00 11.--15. " RTL ,RTL revision. Will vary depending on release. " "0,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1c,0x1D,0x1E,0x1F" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor revision" group.long 0x110++0x0f line.long 0x00 "MCSPI_SYSCONFIG,McSPI System Configuration Register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period" "OCP off/Clock off,OCP on/Clock off,OCP off/Clock on,OCP on/Clock on" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Ignored IDLE,Smart-idle,?..." bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal mode,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,OCP Clock gating strategy" "Free-running,Automatic OCP" line.long 0x04 "MCSPI_SYSSTATUS,McSPI System Status Register" bitfld.long 0x04 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" line.long 0x08 "MCSPI_IRQSTATUS,McSPI Interrupt Status Registerster" bitfld.long 0x08 17. " EOW ,End of word count event" "False,Pending" bitfld.long 0x08 14. " RX3_FULL ,Receiver register is full or almost full" "False,Pending" bitfld.long 0x08 13. " TX3_UNDERFLOW ,Transmitter register underflow" "False,Pending" textline " " bitfld.long 0x08 12. " TX3_EMPTY ,Transmitter register is empty or almost empty" "False,Pending" bitfld.long 0x08 10. " RX2_FULL ,Receiver register full or almost full" "False,Pending" bitfld.long 0x08 9. " TX2_UNDERFLOW ,Transmitter register underflow" "False,Pending" textline " " bitfld.long 0x08 8. " TX2_EMPTY ,Transmitter register empty or almost empty" "False,Pending" bitfld.long 0x08 6. " RX1_FULL ,Receiver register full or almost full" "False,Pending" bitfld.long 0x08 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending" textline " " bitfld.long 0x08 4. " TX1_EMPTY ,Transmitter register empty or almost empty" "False,Pending" bitfld.long 0x08 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only)" "False,Pending" bitfld.long 0x08 2. " RX0_FULL ,Receiver register full or almost full" "False,Pending" textline " " bitfld.long 0x08 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending" bitfld.long 0x08 0. " TX0_EMPTY ,Transmitter register empty or almost empty" "False,Pending" line.long 0x0c "MCSPI_IRQENABLE,McSPI Interrupt Enable Register" bitfld.long 0x0C 17. " EOWKE ,End of word count interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " RX3_FULL_ENABLE ,MCSPI_RX3 receiver register full or almost full interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 13. " TX3_UNDERFLOW_ENABLE ,MCSPI_TX3 transmitter register underflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " TX3_EMPTY_ENABLE ,MCSPI_TX3 transmitter register empty or almost empty interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 10. " RX2_FULL_ENABLE ,MCSPI_RX2 receiver register full or almost full interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 9. " TX2_UNDERFLOW_ENABLE ,MCSPI_TX2 transmitter register underflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 8. " TX2_EMPTY_ENABLE ,MCSPI_TX2 transmitter register empty or almost empty interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " RX1_FULL_ENABLE ,MCSPI_RX1 receiver register full or almost full interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 5. " TX1_UNDERFLOW_ENABLE ,MCSPI_TX1 transmitter register underflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " TX1_EMPTY_ENABLE ,MCSPI_TX1 transmitter register empty or almost empty interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " RX0_OVERFLOW_ENABLE ,MCSPI_RX0 receivier register overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " RX0_FULL_ENABLE ,MCSPI_RX0 receiver register full or almost full interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " TX0_UNDERFLOW_ENABLE ,MCSPI_TX0 transmitter register underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TX0_EMPTY_ENABLE ,MCSPI_TX0 transmitter register empty or almost empty interrupt enable" "Disabled,Enabled" group.long 0x124++0x03 line.long 0x00 "MCSPI_SYST,McSPI System Register" bitfld.long 0x00 11. " SSB ,Set status bit" "No effect,Sets all status bits" bitfld.long 0x00 10. " SPIENDIR ,Sets the direction of the SPIEN[3:0] lines and SPICLK line" "Output,Input" bitfld.long 0x00 9. " SPIDATDIR1 ,Sets the direction of the SPIDAT[1]." "Output,Input" textline " " bitfld.long 0x00 8. " SPIDATDIR0 ,Sets the direction of the SPIDAT[0]." "Output,Input" bitfld.long 0x00 6. " SPICLK ,SPICLK line" "Output,Input" bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT 1 line" "Low,HI" textline " " bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT 0 line" "Low,HI" bitfld.long 0x00 3. " SPIEN_3 ,SPIEN 3 line" "Low,HI" bitfld.long 0x00 2. " SPIEN_2 ,SPIEN 2 line" "Low,HI" textline " " bitfld.long 0x00 1. " SPIEN_1 ,SPIEN 1 line" "Low,HI" bitfld.long 0x00 0. " SPIEN_0 ,SPIEN 0 line" "Low,HI" if (((d.l(ad:0x48030000+0x128))&0x4)==0x4) group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,McSPI Module Control Register" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI TX/RX,MCSPI_DAF TX/RX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled with FIFO" bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer (SPI bus clock) " "No delay,4,8,16,32,?..." textline " " bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,SPIEN Pin mode selection " "Used,Not used" else group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,McSPI Module Control Register" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI TX/RX,MCSPI_DAF TX/RX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer (SPI bus clock)" "No delay,4,8,16,32,?..." textline " " bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,SPIEN Pin mode selection " "Used,Not used" textline " " bitfld.long 0x00 0. " SINGLE ,Single / Multi Channel" "Multi,Single" endif tree "channel 0" if (((d.l(ad:0x48030000+0x128))&0x4)==0x4) group.long 0x12c++0x03 line.long 0x00 "MCSPI_CH0CONF,McSPI Channel 0 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" textline " " bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" else group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,McSPI Channel 0 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" textline " " bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" textline " " bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif group.long 0x130++0x0b line.long 0x00 "MCSPI_CH0STAT,McSPI channel 0 status register register" bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO receive buffer full status" "No Full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO receive buffer empty status" "No empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO transmit buffer full status" "No Full,Full" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO transmit buffer empty status" "No empty,Empty" bitfld.long 0x00 2. " EOT ,Channel 0 end-of-transfer status" "Automatically cleared,Automatically set" bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty" textline " " bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full" line.long 0x04 "MCSPI_CH0CTRL,Channel 0 Control Registert" hexmask.long.byte 0x04 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x04 0. " EN ,Channel 0 enable" "Disabled,Enabled" line.long 0x08 "MCSPI_TX2,MCSPI Channel 1 Transmit Register" hgroup.long 0x13C++0x03 in tree.end tree "channel 1" if (((d.l(ad:0x48030000+0x140))&0x4)==0x4) group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,McSPI Channel 1 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" textline " " bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" else group.long 0x128++0x03 line.long 0x00 "MCSPI_CH1CONF,McSPI channel 1 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control (clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" textline " " bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" textline " " bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif group.long 0x144++0x0b line.long 0x00 "MCSPI_CH1STAT,McSPI channel 1 status register register" bitfld.long 0x00 6. " RXFFF ,channel 1 FIFO receive buffer full status" "No Full,Full" bitfld.long 0x00 5. " RXFFE ,channel 1 FIFO receive buffer empty status" "No empty,Empty" bitfld.long 0x00 4. " TXFFF ,channel 1 FIFO transmit buffer full status" "No Full,Full" textline " " bitfld.long 0x00 3. " TXFFE ,channel 1 FIFO transmit buffer empty status" "No empty,Empty" bitfld.long 0x00 2. " EOT ,channel 1 end-of-transfer status" "Automatically cleared,Automatically set" bitfld.long 0x00 1. " TXS ,channel 1 transmitter register status" "Full,Empty" textline " " bitfld.long 0x00 0. " RXS ,channel 1 receiver register status" "Empty,Full" line.long 0x04 "MCSPI_CH1CTRL,channel 1 Control Registert" hexmask.long.byte 0x04 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x04 0. " EN ,Channel 1 enable" "Disabled,Enabled" line.long 0x08 "MCSPI_TX2,MCSPI Channel 1 Transmit Register" hgroup.long 0x150++0x03 in tree.end tree "channel 2" if (((d.l(ad:0x48030000+0x154))&0x4)==0x4) group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,McSPI channel 1 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" textline " " bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" else group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,McSPI channel 1 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" textline " " bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" textline " " bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif group.long 0x158++0x0b line.long 0x00 "MCSPI_CH2STAT,McSPI channel 1 status register register" bitfld.long 0x00 6. " RXFFF ,channel 1 FIFO receive buffer full status" "No Full,Full" bitfld.long 0x00 5. " RXFFE ,channel 1 FIFO receive buffer empty status" "No empty,Empty" bitfld.long 0x00 4. " TXFFF ,channel 1 FIFO transmit buffer full status" "No Full,Full" textline " " bitfld.long 0x00 3. " TXFFE ,channel 1 FIFO transmit buffer empty status" "No empty,Empty" bitfld.long 0x00 2. " EOT ,channel 1 end-of-transfer status" "Automatically cleared,Automatically set" bitfld.long 0x00 1. " TXS ,channel 1 transmitter register status" "Full,Empty" textline " " bitfld.long 0x00 0. " RXS ,channel 1 receiver register status" "Empty,Full" line.long 0x04 "MCSPI_CH2CTRL,channel 1 Control Registert" hexmask.long.byte 0x04 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x04 0. " EN ,channel 1 enable" "Disabled,Enabled" line.long 0x08 "MCSPI_TX2,MCSPI Channel 2 Transmit Register" hgroup.long 0x164++0x03 in tree.end tree "channel 3" if (((d.l(ad:0x48030000+0x168))&0x4)==0x4) group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,McSPI channel 3 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control(clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" textline " " bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit/Receive,Receive,Transmit,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" else group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,McSPI channel 3 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" textline " " bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" textline " " bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif group.long 0x170++0x0b line.long 0x00 "MCSPI_CH3STAT,McSPI channel 3 status register register" bitfld.long 0x00 6. " RXFFF ,channel 3 FIFO receive buffer full status" "No Full,Full" bitfld.long 0x00 5. " RXFFE ,channel 3 FIFO receive buffer empty status" "No empty,Empty" bitfld.long 0x00 4. " TXFFF ,channel 3 FIFO transmit buffer full status" "No Full,Full" textline " " bitfld.long 0x00 3. " TXFFE ,channel 3 FIFO transmit buffer empty status" "No empty,Empty" bitfld.long 0x00 2. " EOT ,channel 3 end-of-transfer status" "Cleared,Set" bitfld.long 0x00 1. " TXS ,channel 3 transmitter register status" "Full,Empty" textline " " bitfld.long 0x00 0. " RXS ,channel 3 receiver register status" "Empty,Full" line.long 0x04 "MCSPI_CH2CTRL,channel 3 Control Registert" hexmask.long.byte 0x04 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x04 0. " EN ,channel 3 enable" "Disabled,Enabled" line.long 0x08 "MCSPI_TX3,MCSPI Channel 3 Transmit Register" hgroup.long 0x17C++0x03 in tree.end group.long 0x17c++0x07 line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register" hexmask.long.word 0x00 16.--31. 1. " WCNT ,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer almost full" hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer almost empty" line.long 0x04 "MCSPI_DAFTX,Address Aligned FIFO Transmitter Register" hgroup.long 0x1A0++0x03 in width 0xb tree.end tree "MCSPI 1" base ad:0x481A0000 width 17. rgroup.long 0x00++0x03 line.long 0x00 "MCSPI_REVISION,McSPI Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old Scheme and current" "ASP or WTBU,Revision 0.8,?..." hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional Number" bitfld.long 0x00 11.--15. " RTL ,RTL revision. Will vary depending on release. " "0,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1c,0x1D,0x1E,0x1F" textline " " bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor revision" group.long 0x110++0x0f line.long 0x00 "MCSPI_SYSCONFIG,McSPI System Configuration Register" bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period" "OCP off/Clock off,OCP on/Clock off,OCP off/Clock on,OCP on/Clock on" bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Ignored IDLE,Smart-idle,?..." bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal mode,Reset" textline " " bitfld.long 0x00 0. " AUTOIDLE ,OCP Clock gating strategy" "Free-running,Automatic OCP" line.long 0x04 "MCSPI_SYSSTATUS,McSPI System Status Register" bitfld.long 0x04 0. " RESETDONE ,Internal Reset Monitoring" "On-going,Completed" line.long 0x08 "MCSPI_IRQSTATUS,McSPI Interrupt Status Registerster" bitfld.long 0x08 17. " EOW ,End of word count event" "False,Pending" bitfld.long 0x08 14. " RX3_FULL ,Receiver register is full or almost full" "False,Pending" bitfld.long 0x08 13. " TX3_UNDERFLOW ,Transmitter register underflow" "False,Pending" textline " " bitfld.long 0x08 12. " TX3_EMPTY ,Transmitter register is empty or almost empty" "False,Pending" bitfld.long 0x08 10. " RX2_FULL ,Receiver register full or almost full" "False,Pending" bitfld.long 0x08 9. " TX2_UNDERFLOW ,Transmitter register underflow" "False,Pending" textline " " bitfld.long 0x08 8. " TX2_EMPTY ,Transmitter register empty or almost empty" "False,Pending" bitfld.long 0x08 6. " RX1_FULL ,Receiver register full or almost full" "False,Pending" bitfld.long 0x08 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending" textline " " bitfld.long 0x08 4. " TX1_EMPTY ,Transmitter register empty or almost empty" "False,Pending" bitfld.long 0x08 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only)" "False,Pending" bitfld.long 0x08 2. " RX0_FULL ,Receiver register full or almost full" "False,Pending" textline " " bitfld.long 0x08 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending" bitfld.long 0x08 0. " TX0_EMPTY ,Transmitter register empty or almost empty" "False,Pending" line.long 0x0c "MCSPI_IRQENABLE,McSPI Interrupt Enable Register" bitfld.long 0x0C 17. " EOWKE ,End of word count interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 14. " RX3_FULL_ENABLE ,MCSPI_RX3 receiver register full or almost full interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 13. " TX3_UNDERFLOW_ENABLE ,MCSPI_TX3 transmitter register underflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 12. " TX3_EMPTY_ENABLE ,MCSPI_TX3 transmitter register empty or almost empty interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 10. " RX2_FULL_ENABLE ,MCSPI_RX2 receiver register full or almost full interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 9. " TX2_UNDERFLOW_ENABLE ,MCSPI_TX2 transmitter register underflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 8. " TX2_EMPTY_ENABLE ,MCSPI_TX2 transmitter register empty or almost empty interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 6. " RX1_FULL_ENABLE ,MCSPI_RX1 receiver register full or almost full interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 5. " TX1_UNDERFLOW_ENABLE ,MCSPI_TX1 transmitter register underflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " TX1_EMPTY_ENABLE ,MCSPI_TX1 transmitter register empty or almost empty interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " RX0_OVERFLOW_ENABLE ,MCSPI_RX0 receivier register overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " RX0_FULL_ENABLE ,MCSPI_RX0 receiver register full or almost full interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " TX0_UNDERFLOW_ENABLE ,MCSPI_TX0 transmitter register underflow interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 0. " TX0_EMPTY_ENABLE ,MCSPI_TX0 transmitter register empty or almost empty interrupt enable" "Disabled,Enabled" group.long 0x124++0x03 line.long 0x00 "MCSPI_SYST,McSPI System Register" bitfld.long 0x00 11. " SSB ,Set status bit" "No effect,Sets all status bits" bitfld.long 0x00 10. " SPIENDIR ,Sets the direction of the SPIEN[3:0] lines and SPICLK line" "Output,Input" bitfld.long 0x00 9. " SPIDATDIR1 ,Sets the direction of the SPIDAT[1]." "Output,Input" textline " " bitfld.long 0x00 8. " SPIDATDIR0 ,Sets the direction of the SPIDAT[0]." "Output,Input" bitfld.long 0x00 6. " SPICLK ,SPICLK line" "Output,Input" bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT 1 line" "Low,HI" textline " " bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT 0 line" "Low,HI" bitfld.long 0x00 3. " SPIEN_3 ,SPIEN 3 line" "Low,HI" bitfld.long 0x00 2. " SPIEN_2 ,SPIEN 2 line" "Low,HI" textline " " bitfld.long 0x00 1. " SPIEN_1 ,SPIEN 1 line" "Low,HI" bitfld.long 0x00 0. " SPIEN_0 ,SPIEN 0 line" "Low,HI" if (((d.l(ad:0x481A0000+0x128))&0x4)==0x4) group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,McSPI Module Control Register" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI TX/RX,MCSPI_DAF TX/RX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled with FIFO" bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer (SPI bus clock) " "No delay,4,8,16,32,?..." textline " " bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,SPIEN Pin mode selection " "Used,Not used" else group.long 0x128++0x03 line.long 0x00 "MCSPI_MODULCTRL,McSPI Module Control Register" bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI TX/RX,MCSPI_DAF TX/RX" bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled" bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer (SPI bus clock)" "No delay,4,8,16,32,?..." textline " " bitfld.long 0x00 3. " SYSTEM_TEST ,Enables the system test mode" "Functional,System test" bitfld.long 0x00 2. " MS ,Master/ Slave" "Master,Slave" bitfld.long 0x00 1. " PIN34 ,SPIEN Pin mode selection " "Used,Not used" textline " " bitfld.long 0x00 0. " SINGLE ,Single / Multi Channel" "Multi,Single" endif tree "channel 0" if (((d.l(ad:0x481A0000+0x128))&0x4)==0x4) group.long 0x12c++0x03 line.long 0x00 "MCSPI_CH0CONF,McSPI Channel 0 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" textline " " bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" else group.long 0x12C++0x03 line.long 0x00 "MCSPI_CH0CONF,McSPI Channel 0 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" textline " " bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" textline " " bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif group.long 0x130++0x0b line.long 0x00 "MCSPI_CH0STAT,McSPI channel 0 status register register" bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO receive buffer full status" "No Full,Full" bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO receive buffer empty status" "No empty,Empty" bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO transmit buffer full status" "No Full,Full" textline " " bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO transmit buffer empty status" "No empty,Empty" bitfld.long 0x00 2. " EOT ,Channel 0 end-of-transfer status" "Automatically cleared,Automatically set" bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty" textline " " bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full" line.long 0x04 "MCSPI_CH0CTRL,Channel 0 Control Registert" hexmask.long.byte 0x04 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x04 0. " EN ,Channel 0 enable" "Disabled,Enabled" line.long 0x08 "MCSPI_TX2,MCSPI Channel 1 Transmit Register" hgroup.long 0x13C++0x03 in tree.end tree "channel 1" if (((d.l(ad:0x481A0000+0x140))&0x4)==0x4) group.long 0x140++0x03 line.long 0x00 "MCSPI_CH1CONF,McSPI Channel 1 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" textline " " bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" else group.long 0x128++0x03 line.long 0x00 "MCSPI_CH1CONF,McSPI channel 1 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control (clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" textline " " bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" textline " " bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif group.long 0x144++0x0b line.long 0x00 "MCSPI_CH1STAT,McSPI channel 1 status register register" bitfld.long 0x00 6. " RXFFF ,channel 1 FIFO receive buffer full status" "No Full,Full" bitfld.long 0x00 5. " RXFFE ,channel 1 FIFO receive buffer empty status" "No empty,Empty" bitfld.long 0x00 4. " TXFFF ,channel 1 FIFO transmit buffer full status" "No Full,Full" textline " " bitfld.long 0x00 3. " TXFFE ,channel 1 FIFO transmit buffer empty status" "No empty,Empty" bitfld.long 0x00 2. " EOT ,channel 1 end-of-transfer status" "Automatically cleared,Automatically set" bitfld.long 0x00 1. " TXS ,channel 1 transmitter register status" "Full,Empty" textline " " bitfld.long 0x00 0. " RXS ,channel 1 receiver register status" "Empty,Full" line.long 0x04 "MCSPI_CH1CTRL,channel 1 Control Registert" hexmask.long.byte 0x04 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x04 0. " EN ,Channel 1 enable" "Disabled,Enabled" line.long 0x08 "MCSPI_TX2,MCSPI Channel 1 Transmit Register" hgroup.long 0x150++0x03 in tree.end tree "channel 2" if (((d.l(ad:0x481A0000+0x154))&0x4)==0x4) group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,McSPI channel 1 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" textline " " bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" else group.long 0x154++0x03 line.long 0x00 "MCSPI_CH2CONF,McSPI channel 1 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" textline " " bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" textline " " bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif group.long 0x158++0x0b line.long 0x00 "MCSPI_CH2STAT,McSPI channel 1 status register register" bitfld.long 0x00 6. " RXFFF ,channel 1 FIFO receive buffer full status" "No Full,Full" bitfld.long 0x00 5. " RXFFE ,channel 1 FIFO receive buffer empty status" "No empty,Empty" bitfld.long 0x00 4. " TXFFF ,channel 1 FIFO transmit buffer full status" "No Full,Full" textline " " bitfld.long 0x00 3. " TXFFE ,channel 1 FIFO transmit buffer empty status" "No empty,Empty" bitfld.long 0x00 2. " EOT ,channel 1 end-of-transfer status" "Automatically cleared,Automatically set" bitfld.long 0x00 1. " TXS ,channel 1 transmitter register status" "Full,Empty" textline " " bitfld.long 0x00 0. " RXS ,channel 1 receiver register status" "Empty,Full" line.long 0x04 "MCSPI_CH2CTRL,channel 1 Control Registert" hexmask.long.byte 0x04 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x04 0. " EN ,channel 1 enable" "Disabled,Enabled" line.long 0x08 "MCSPI_TX2,MCSPI Channel 2 Transmit Register" hgroup.long 0x164++0x03 in tree.end tree "channel 3" if (((d.l(ad:0x481A0000+0x168))&0x4)==0x4) group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,McSPI channel 3 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control(clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX" textline " " bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]" bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" textline " " bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,Disabled" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" textline " " bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit/Receive,Receive,Transmit,?..." textline " " bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" textline " " bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" else group.long 0x168++0x03 line.long 0x00 "MCSPI_CH3CONF,McSPI channel 3 Configuration Register" bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "2,1" bitfld.long 0x00 28. " FFER ,FIFO enabled for receive" "Not used,Used" bitfld.long 0x00 27. " FFEW ,FIFO enabled for transmit" "Not used,Used" textline " " bitfld.long 0x00 25.--26. " TCS ,Chip select time control ( clock cycles)" "0.5,1.5,2.5,3.5" bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0 during SPI transfer,1 during SPI transfer" bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default SPI transfe,D/CX" textline " " bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words" "Not asserted,Asserted" bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated" bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1" textline " " bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Line 1,No transmission" bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Line 0,No transmission" bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled" bitfld.long 0x00 12.--13. " TRM ,Transmit/receive modes" "Transmit and receive,Receive,Transmit,?..." bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bits long,5-bits long,6-bits long,7-bits long,8-bits long,9-bits long,10-bits long,11-bits long,12-bits long,13-bits long,14-bits long,15-bits long,16-bits long,17-bits long,18-bits long,19-bits long,20-bits long,21-bits long,22-bits long,23-bits long,24-bits long,25-bits long,26-bits long,27-bits long,28-bits long,29-bits long,30-bits long,31-bits long,32-bits long" textline " " bitfld.long 0x00 6. " EPOL ,SPIEN polarity(Active)" "High,Low" bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x00 1. " POL ,SPICLK polarity(Active)" "High,Low" textline " " bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even" endif group.long 0x170++0x0b line.long 0x00 "MCSPI_CH3STAT,McSPI channel 3 status register register" bitfld.long 0x00 6. " RXFFF ,channel 3 FIFO receive buffer full status" "No Full,Full" bitfld.long 0x00 5. " RXFFE ,channel 3 FIFO receive buffer empty status" "No empty,Empty" bitfld.long 0x00 4. " TXFFF ,channel 3 FIFO transmit buffer full status" "No Full,Full" textline " " bitfld.long 0x00 3. " TXFFE ,channel 3 FIFO transmit buffer empty status" "No empty,Empty" bitfld.long 0x00 2. " EOT ,channel 3 end-of-transfer status" "Cleared,Set" bitfld.long 0x00 1. " TXS ,channel 3 transmitter register status" "Full,Empty" textline " " bitfld.long 0x00 0. " RXS ,channel 3 receiver register status" "Empty,Full" line.long 0x04 "MCSPI_CH2CTRL,channel 3 Control Registert" hexmask.long.byte 0x04 8.--15. 1. " EXTCLK ,Clock ratio extension" bitfld.long 0x04 0. " EN ,channel 3 enable" "Disabled,Enabled" line.long 0x08 "MCSPI_TX3,MCSPI Channel 3 Transmit Register" hgroup.long 0x17C++0x03 in tree.end group.long 0x17c++0x07 line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register" hexmask.long.word 0x00 16.--31. 1. " WCNT ,SPI word counter" hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer almost full" hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer almost empty" line.long 0x04 "MCSPI_DAFTX,Address Aligned FIFO Transmitter Register" hgroup.long 0x1A0++0x03 in width 0xb tree.end tree.end tree "GPIO (General-Purpose Input/Output)" tree "Port 0" base ad:0x44E07000 width 22. rgroup.long 0x00++0x03 line.long 0x00 "GPIO_REVISION,GPIO Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional Number" bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Major revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision" group.long 0x10++0x03 line.long 0x00 "GPIO_SYSCONFIG,GPIO SysConfig Register" bitfld.long 0x00 3.--4. " IDLEMODE ,Select IDLE mode" "Force Idle,No Idle Mode,Smart-Idle,Smart Idle/Wakeup" bitfld.long 0x00 1. " SOFTRESET ,Software reset mode" "Normal,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "free-running,OCP" group.long 0x20++0x3 line.long 0x00 "GPIO_EOI,GPIO_EOI register provides software end of interrupt" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledgement" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt control" "0,1" endif group.long 0x24++0xf line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Status Raw Register for interrupt 1" bitfld.long 0x00 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" bitfld.long 0x00 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" bitfld.long 0x00 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" bitfld.long 0x00 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " bitfld.long 0x00 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" bitfld.long 0x00 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" bitfld.long 0x00 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" bitfld.long 0x00 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " bitfld.long 0x00 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" bitfld.long 0x00 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" bitfld.long 0x00 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" bitfld.long 0x00 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " bitfld.long 0x00 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" bitfld.long 0x00 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" bitfld.long 0x00 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" bitfld.long 0x00 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " bitfld.long 0x00 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" bitfld.long 0x00 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" bitfld.long 0x00 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" bitfld.long 0x00 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " bitfld.long 0x00 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" bitfld.long 0x00 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" bitfld.long 0x00 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" bitfld.long 0x00 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " bitfld.long 0x00 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" bitfld.long 0x00 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" bitfld.long 0x00 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" bitfld.long 0x00 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " bitfld.long 0x00 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" bitfld.long 0x00 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" bitfld.long 0x00 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" bitfld.long 0x00 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x04 "GPIO_IRQSTATUS_RAW_1,Status Raw Register for interrupt 1" bitfld.long 0x04 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" bitfld.long 0x04 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" bitfld.long 0x04 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" bitfld.long 0x04 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " bitfld.long 0x04 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" bitfld.long 0x04 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" bitfld.long 0x04 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" bitfld.long 0x04 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " bitfld.long 0x04 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" bitfld.long 0x04 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" bitfld.long 0x04 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" bitfld.long 0x04 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " bitfld.long 0x04 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" bitfld.long 0x04 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" bitfld.long 0x04 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" bitfld.long 0x04 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " bitfld.long 0x04 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" bitfld.long 0x04 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" bitfld.long 0x04 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" bitfld.long 0x04 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " bitfld.long 0x04 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" bitfld.long 0x04 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" bitfld.long 0x04 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" bitfld.long 0x04 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " bitfld.long 0x04 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" bitfld.long 0x04 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" bitfld.long 0x04 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" bitfld.long 0x04 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " bitfld.long 0x04 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" bitfld.long 0x04 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" bitfld.long 0x04 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" bitfld.long 0x04 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x08 "GPIO_IRQSTATUS_0,GPIO_IRQSTATUS_0 register provides core status information for the interrupt handling" setclrfld.long 0x08 31. 0x08 31. 0x10 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" setclrfld.long 0x08 30. 0x08 30. 0x10 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" setclrfld.long 0x08 29. 0x08 29. 0x10 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" setclrfld.long 0x08 28. 0x08 28. 0x10 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " setclrfld.long 0x08 27. 0x08 27. 0x10 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" setclrfld.long 0x08 26. 0x08 26. 0x10 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" setclrfld.long 0x08 25. 0x08 25. 0x10 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" setclrfld.long 0x08 24. 0x08 24. 0x10 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " setclrfld.long 0x08 23. 0x08 23. 0x10 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" setclrfld.long 0x08 22. 0x08 22. 0x10 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" setclrfld.long 0x08 21. 0x08 21. 0x10 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" setclrfld.long 0x08 20. 0x08 20. 0x10 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " setclrfld.long 0x08 19. 0x08 19. 0x10 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" setclrfld.long 0x08 18. 0x08 18. 0x10 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" setclrfld.long 0x08 17. 0x08 17. 0x10 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" setclrfld.long 0x08 16. 0x08 16. 0x10 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " setclrfld.long 0x08 15. 0x08 15. 0x10 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" setclrfld.long 0x08 14. 0x08 14. 0x10 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" setclrfld.long 0x08 13. 0x08 13. 0x10 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" setclrfld.long 0x08 12. 0x08 12. 0x10 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " setclrfld.long 0x08 11. 0x08 11. 0x10 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" setclrfld.long 0x08 10. 0x08 10. 0x10 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" setclrfld.long 0x08 9. 0x08 9. 0x10 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" setclrfld.long 0x08 8. 0x08 8. 0x10 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " setclrfld.long 0x08 7. 0x08 7. 0x10 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" setclrfld.long 0x08 6. 0x08 6. 0x10 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" setclrfld.long 0x08 5. 0x08 5. 0x10 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" setclrfld.long 0x08 4. 0x08 4. 0x10 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " setclrfld.long 0x08 3. 0x08 3. 0x10 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" setclrfld.long 0x08 2. 0x08 2. 0x10 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" setclrfld.long 0x08 1. 0x08 1. 0x10 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" setclrfld.long 0x08 0. 0x08 0. 0x10 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x0c "GPIO_IRQSTATUS_1,GPIO_IRQSTATUS_1 register provides core status information for the interrupt handling" setclrfld.long 0x0c 31. 0x08 31. 0x0c 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" setclrfld.long 0x0c 30. 0x08 30. 0x0c 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" setclrfld.long 0x0c 29. 0x08 29. 0x0c 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" setclrfld.long 0x0c 28. 0x08 28. 0x0c 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 27. 0x08 27. 0x0c 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" setclrfld.long 0x0c 26. 0x08 26. 0x0c 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" setclrfld.long 0x0c 25. 0x08 25. 0x0c 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" setclrfld.long 0x0c 24. 0x08 24. 0x0c 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 23. 0x08 23. 0x0c 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" setclrfld.long 0x0c 22. 0x08 22. 0x0c 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" setclrfld.long 0x0c 21. 0x08 21. 0x0c 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" setclrfld.long 0x0c 20. 0x08 20. 0x0c 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 19. 0x08 19. 0x0c 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" setclrfld.long 0x0c 18. 0x08 18. 0x0c 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" setclrfld.long 0x0c 17. 0x08 17. 0x0c 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" setclrfld.long 0x0c 16. 0x08 16. 0x0c 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 15. 0x08 15. 0x0c 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" setclrfld.long 0x0c 14. 0x08 14. 0x0c 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" setclrfld.long 0x0c 13. 0x08 13. 0x0c 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" setclrfld.long 0x0c 12. 0x08 12. 0x0c 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 11. 0x08 11. 0x0c 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" setclrfld.long 0x0c 10. 0x08 10. 0x0c 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" setclrfld.long 0x0c 9. 0x08 9. 0x0c 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" setclrfld.long 0x0c 8. 0x08 8. 0x0c 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 7. 0x08 7. 0x0c 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" setclrfld.long 0x0c 6. 0x08 6. 0x0c 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" setclrfld.long 0x0c 5. 0x08 5. 0x0c 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" setclrfld.long 0x0c 4. 0x08 4. 0x0c 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 3. 0x08 3. 0x0c 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" setclrfld.long 0x0c 2. 0x08 2. 0x0c 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" setclrfld.long 0x0c 1. 0x08 1. 0x0c 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" setclrfld.long 0x0c 0. 0x08 0. 0x0c 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" group.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x07 line.long 0x00 "GPIO_CTRL,module control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Controls the clock gating for the event detection logic (divider)" "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" line.long 0x04 "GPIO_OE,GPIO output enable register" bitfld.long 0x04 31. " OUTPUTEN31 ,GPIO 31 Output Data Enable" "Output,Input" bitfld.long 0x04 30. " OUTPUTEN30 ,GPIO 30 Output Data Enable" "Output,Input" bitfld.long 0x04 29. " OUTPUTEN29 ,GPIO 29 Output Data Enable" "Output,Input" bitfld.long 0x04 28. " OUTPUTEN28 ,GPIO 28 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 27. " OUTPUTEN27 ,GPIO 27 Output Data Enable" "Output,Input" bitfld.long 0x04 26. " OUTPUTEN26 ,GPIO 26 Output Data Enable" "Output,Input" bitfld.long 0x04 25. " OUTPUTEN25 ,GPIO 25 Output Data Enable" "Output,Input" bitfld.long 0x04 24. " OUTPUTEN24 ,GPIO 24 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 23. " OUTPUTEN23 ,GPIO 23 Output Data Enable" "Output,Input" bitfld.long 0x04 22. " OUTPUTEN22 ,GPIO 22 Output Data Enable" "Output,Input" bitfld.long 0x04 21. " OUTPUTEN21 ,GPIO 21 Output Data Enable" "Output,Input" bitfld.long 0x04 20. " OUTPUTEN20 ,GPIO 20 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 19. " OUTPUTEN19 ,GPIO 19 Output Data Enable" "Output,Input" bitfld.long 0x04 18. " OUTPUTEN18 ,GPIO 18 Output Data Enable" "Output,Input" bitfld.long 0x04 17. " OUTPUTEN17 ,GPIO 17 Output Data Enable" "Output,Input" bitfld.long 0x04 16. " OUTPUTEN16 ,GPIO 16 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 15. " OUTPUTEN15 ,GPIO 15 Output Data Enable" "Output,Input" bitfld.long 0x04 14. " OUTPUTEN14 ,GPIO 14 Output Data Enable" "Output,Input" bitfld.long 0x04 13. " OUTPUTEN13 ,GPIO 13 Output Data Enable" "Output,Input" bitfld.long 0x04 12. " OUTPUTEN12 ,GPIO 12 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 11. " OUTPUTEN11 ,GPIO 11 Output Data Enable" "Output,Input" bitfld.long 0x04 10. " OUTPUTEN10 ,GPIO 10 Output Data Enable" "Output,Input" bitfld.long 0x04 9. " OUTPUTEN9 ,GPIO 9 Output Data Enable" "Output,Input" bitfld.long 0x04 8. " OUTPUTEN8 ,GPIO 8 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 7. " OUTPUTEN7 ,GPIO 7 Output Data Enable" "Output,Input" bitfld.long 0x04 6. " OUTPUTEN6 ,GPIO 6 Output Data Enable" "Output,Input" bitfld.long 0x04 5. " OUTPUTEN5 ,GPIO 5 Output Data Enable" "Output,Input" bitfld.long 0x04 4. " OUTPUTEN4 ,GPIO 4 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 3. " OUTPUTEN3 ,GPIO 3 Output Data Enable" "Output,Input" bitfld.long 0x04 2. " OUTPUTEN2 ,GPIO 2 Output Data Enable" "Output,Input" bitfld.long 0x04 1. " OUTPUTEN1 ,GPIO 1 Output Data Enable" "Output,Input" bitfld.long 0x04 0. " OUTPUTEN0 ,GPIO 0 Output Data Enable" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,Sampled Input Data" group.long 0x13c++0x1b line.long 0x00 "GPIO_DATAOUT,Data to set on output pins" line.long 0x04 "GPIO_LEVELDETECT0,low-level detection to be used for the interrupt request generation" bitfld.long 0x04 31. " LEVELDETECT031 ,LEVELDETECT0[31] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 30. " LEVELDETECT030 ,LEVELDETECT0[30] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 29. " LEVELDETECT029 ,LEVELDETECT0[29] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 28. " LEVELDETECT028 ,LEVELDETECT0[28] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 27. " LEVELDETECT027 ,LEVELDETECT0[27] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 26. " LEVELDETECT026 ,LEVELDETECT0[26] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 25. " LEVELDETECT025 ,LEVELDETECT0[25] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 24. " LEVELDETECT024 ,LEVELDETECT0[24] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 23. " LEVELDETECT023 ,LEVELDETECT0[23] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 22. " LEVELDETECT022 ,LEVELDETECT0[22] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 21. " LEVELDETECT021 ,LEVELDETECT0[21] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 20. " LEVELDETECT020 ,LEVELDETECT0[20] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 19. " LEVELDETECT019 ,LEVELDETECT0[19] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 18. " LEVELDETECT018 ,LEVELDETECT0[18] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 17. " LEVELDETECT017 ,LEVELDETECT0[17] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 16. " LEVELDETECT016 ,LEVELDETECT0[16] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 15. " LEVELDETECT015 ,LEVELDETECT0[15] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 14. " LEVELDETECT014 ,LEVELDETECT0[14] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 13. " LEVELDETECT013 ,LEVELDETECT0[13] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 12. " LEVELDETECT012 ,LEVELDETECT0[12] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 11. " LEVELDETECT011 ,LEVELDETECT0[11] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 10. " LEVELDETECT010 ,LEVELDETECT0[10] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 9. " LEVELDETECT09 ,LEVELDETECT0[9] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 8. " LEVELDETECT08 ,LEVELDETECT0[8] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 7. " LEVELDETECT07 ,LEVELDETECT0[7] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 6. " LEVELDETECT06 ,LEVELDETECT0[6] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 5. " LEVELDETECT05 ,LEVELDETECT0[5] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 4. " LEVELDETECT04 ,LEVELDETECT0[4] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 3. " LEVELDETECT03 ,LEVELDETECT0[3] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 2. " LEVELDETECT02 ,LEVELDETECT0[2] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 1. " LEVELDETECT01 ,LEVELDETECT0[1] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 0. " LEVELDETECT00 ,LEVELDETECT0[0] Low Level Interrupt 31 Enable " "Disabled,Enabled" line.long 0x08 "GPIO_LEVELDETECT1,low-level detection to be used for the interrupt request generation" bitfld.long 0x08 31. " LEVELDETECT131 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 30. " LEVELDETECT130 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 29. " LEVELDETECT129 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 28. " LEVELDETECT128 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 27. " LEVELDETECT127 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 26. " LEVELDETECT126 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 25. " LEVELDETECT125 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 24. " LEVELDETECT124 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 23. " LEVELDETECT123 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 22. " LEVELDETECT122 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 21. " LEVELDETECT121 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 20. " LEVELDETECT120 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 19. " LEVELDETECT119 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 18. " LEVELDETECT118 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 17. " LEVELDETECT117 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 16. " LEVELDETECT116 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 15. " LEVELDETECT115 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 14. " LEVELDETECT114 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 13. " LEVELDETECT113 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 12. " LEVELDETECT112 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 11. " LEVELDETECT111 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 10. " LEVELDETECT110 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 9. " LEVELDETECT11 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 8. " LEVELDETECT18 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 7. " LEVELDETECT17 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 6. " LEVELDETECT16 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 5. " LEVELDETECT15 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 4. " LEVELDETECT14 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 3. " LEVELDETECT13 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 2. " LEVELDETECT12 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 1. " LEVELDETECT11 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 0. " LEVELDETECT10 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" line.long 0x0c "GPIO_RISINGDETECT,rising-edge detection to be used for the interrupt request generation" bitfld.long 0x0c 31. " RISINGDETECT31 ,Rising Edge Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x0c 30. " RISINGDETECT30 ,Rising Edge Interrupt 30 Enable " "Disabled,Enabled" bitfld.long 0x0c 29. " RISINGDETECT29 ,Rising Edge Interrupt 29 Enable " "Disabled,Enabled" bitfld.long 0x0c 28. " RISINGDETECT28 ,Rising Edge Interrupt 28 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 27. " RISINGDETECT27 ,Rising Edge Interrupt 27 Enable " "Disabled,Enabled" bitfld.long 0x0c 26. " RISINGDETECT26 ,Rising Edge Interrupt 26 Enable " "Disabled,Enabled" bitfld.long 0x0c 25. " RISINGDETECT25 ,Rising Edge Interrupt 25 Enable " "Disabled,Enabled" bitfld.long 0x0c 24. " RISINGDETECT24 ,Rising Edge Interrupt 24 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 23. " RISINGDETECT23 ,Rising Edge Interrupt 23 Enable " "Disabled,Enabled" bitfld.long 0x0c 22. " RISINGDETECT22 ,Rising Edge Interrupt 22 Enable " "Disabled,Enabled" bitfld.long 0x0c 21. " RISINGDETECT21 ,Rising Edge Interrupt 21 Enable " "Disabled,Enabled" bitfld.long 0x0c 20. " RISINGDETECT20 ,Rising Edge Interrupt 20 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 19. " RISINGDETECT19 ,Rising Edge Interrupt 19 Enable " "Disabled,Enabled" bitfld.long 0x0c 18. " RISINGDETECT18 ,Rising Edge Interrupt 18 Enable " "Disabled,Enabled" bitfld.long 0x0c 17. " RISINGDETECT17 ,Rising Edge Interrupt 17 Enable " "Disabled,Enabled" bitfld.long 0x0c 16. " RISINGDETECT16 ,Rising Edge Interrupt 16 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 15. " RISINGDETECT15 ,Rising Edge Interrupt 15 Enable " "Disabled,Enabled" bitfld.long 0x0c 14. " RISINGDETECT14 ,Rising Edge Interrupt 14 Enable " "Disabled,Enabled" bitfld.long 0x0c 13. " RISINGDETECT13 ,Rising Edge Interrupt 13 Enable " "Disabled,Enabled" bitfld.long 0x0c 12. " RISINGDETECT12 ,Rising Edge Interrupt 12 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 11. " RISINGDETECT11 ,Rising Edge Interrupt 11 Enable " "Disabled,Enabled" bitfld.long 0x0c 10. " RISINGDETECT10 ,Rising Edge Interrupt 10 Enable " "Disabled,Enabled" bitfld.long 0x0c 9. " RISINGDETECT9 ,Rising Edge Interrupt 9 Enable " "Disabled,Enabled" bitfld.long 0x0c 8. " RISINGDETECT8 ,Rising Edge Interrupt 8 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 7. " RISINGDETECT7 ,Rising Edge Interrupt 7 Enable " "Disabled,Enabled" bitfld.long 0x0c 6. " RISINGDETECT6 ,Rising Edge Interrupt 6 Enable " "Disabled,Enabled" bitfld.long 0x0c 5. " RISINGDETECT5 ,Rising Edge Interrupt 5 Enable " "Disabled,Enabled" bitfld.long 0x0c 4. " RISINGDETECT4 ,Rising Edge Interrupt 4 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 3. " RISINGDETECT3 ,Rising Edge Interrupt 3 Enable " "Disabled,Enabled" bitfld.long 0x0c 2. " RISINGDETECT2 ,Rising Edge Interrupt 2 Enable " "Disabled,Enabled" bitfld.long 0x0c 1. " RISINGDETECT1 ,Rising Edge Interrupt 1 Enable " "Disabled,Enabled" bitfld.long 0x0c 0. " RISINGDETECT0 ,Rising Edge Interrupt 0 Enable " "Disabled,Enabled" line.long 0x10 "GPIO_FALLINGDETECT,falling-edge detection to be used for the interrupt request generation" bitfld.long 0x10 31. " FALLINGDETECT31 ,falling-edge detection 31" "Disabled,Enabled" bitfld.long 0x10 30. " FALLINGDETECT30 ,falling-edge detection 30" "Disabled,Enabled" bitfld.long 0x10 29. " FALLINGDETECT29 ,falling-edge detection 29" "Disabled,Enabled" bitfld.long 0x10 28. " FALLINGDETECT28 ,falling-edge detection 28" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " FALLINGDETECT27 ,falling-edge detection 27" "Disabled,Enabled" bitfld.long 0x10 26. " FALLINGDETECT26 ,falling-edge detection 26" "Disabled,Enabled" bitfld.long 0x10 25. " FALLINGDETECT25 ,falling-edge detection 25" "Disabled,Enabled" bitfld.long 0x10 24. " FALLINGDETECT24 ,falling-edge detection 24" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " FALLINGDETECT23 ,falling-edge detection 23" "Disabled,Enabled" bitfld.long 0x10 22. " FALLINGDETECT22 ,falling-edge detection 22" "Disabled,Enabled" bitfld.long 0x10 21. " FALLINGDETECT21 ,falling-edge detection 21" "Disabled,Enabled" bitfld.long 0x10 20. " FALLINGDETECT20 ,falling-edge detection 20" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " FALLINGDETECT19 ,falling-edge detection 19" "Disabled,Enabled" bitfld.long 0x10 18. " FALLINGDETECT18 ,falling-edge detection 18" "Disabled,Enabled" bitfld.long 0x10 17. " FALLINGDETECT17 ,falling-edge detection 17" "Disabled,Enabled" bitfld.long 0x10 16. " FALLINGDETECT16 ,falling-edge detection 16" "Disabled,Enabled" textline " " bitfld.long 0x10 15. " FALLINGDETECT15 ,falling-edge detection 15" "Disabled,Enabled" bitfld.long 0x10 14. " FALLINGDETECT14 ,falling-edge detection 14" "Disabled,Enabled" bitfld.long 0x10 13. " FALLINGDETECT13 ,falling-edge detection 13" "Disabled,Enabled" bitfld.long 0x10 12. " FALLINGDETECT12 ,falling-edge detection 12" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " FALLINGDETECT11 ,falling-edge detection 11" "Disabled,Enabled" bitfld.long 0x10 10. " FALLINGDETECT10 ,falling-edge detection 10" "Disabled,Enabled" bitfld.long 0x10 9. " FALLINGDETECT9 ,falling-edge detection 9" "Disabled,Enabled" bitfld.long 0x10 8. " FALLINGDETECT8 ,falling-edge detection 8" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " FALLINGDETECT7 ,falling-edge detection 7" "Disabled,Enabled" bitfld.long 0x10 6. " FALLINGDETECT6 ,falling-edge detection 6" "Disabled,Enabled" bitfld.long 0x10 5. " FALLINGDETECT5 ,falling-edge detection 5" "Disabled,Enabled" bitfld.long 0x10 4. " FALLINGDETECT4 ,falling-edge detection 4" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " FALLINGDETECT3 ,falling-edge detection 3" "Disabled,Enabled" bitfld.long 0x10 2. " FALLINGDETECT2 ,falling-edge detection 2" "Disabled,Enabled" bitfld.long 0x10 1. " FALLINGDETECT1 ,falling-edge detection 1" "Disabled,Enabled" bitfld.long 0x10 0. " FALLINGDETECT0 ,falling-edge detection 0" "Disabled,Enabled" line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable register" bitfld.long 0x14 31. " DEBOUNCEENABLE31 ,Input 31 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 30. " DEBOUNCEENABLE30 ,Input 30 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 29. " DEBOUNCEENABLE29 ,Input 29 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 28. " DEBOUNCEENABLE28 ,Input 28 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " DEBOUNCEENABLE27 ,Input 27 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 26. " DEBOUNCEENABLE26 ,Input 26 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 25. " DEBOUNCEENABLE25 ,Input 25 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 24. " DEBOUNCEENABLE24 ,Input 24 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " DEBOUNCEENABLE23 ,Input 23 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 22. " DEBOUNCEENABLE22 ,Input 22 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 21. " DEBOUNCEENABLE21 ,Input 21 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 20. " DEBOUNCEENABLE20 ,Input 20 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " DEBOUNCEENABLE19 ,Input 19 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 18. " DEBOUNCEENABLE18 ,Input 18 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 17. " DEBOUNCEENABLE17 ,Input 17 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 16. " DEBOUNCEENABLE16 ,Input 16 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " DEBOUNCEENABLE15 ,Input 15 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 14. " DEBOUNCEENABLE14 ,Input 14 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 13. " DEBOUNCEENABLE13 ,Input 13 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 12. " DEBOUNCEENABLE12 ,Input 12 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " DEBOUNCEENABLE11 ,Input 11 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 10. " DEBOUNCEENABLE10 ,Input 10 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 9. " DEBOUNCEENABLE9 ,Input 9 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 8. " DEBOUNCEENABLE8 ,Input 8 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " DEBOUNCEENABLE7 ,Input 7 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 6. " DEBOUNCEENABLE6 ,Input 6 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 5. " DEBOUNCEENABLE5 ,Input 5 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 4. " DEBOUNCEENABLE4 ,Input 4 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " DEBOUNCEENABLE3 ,Input 3 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 2. " DEBOUNCEENABLE2 ,Input 2 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 1. " DEBOUNCEENABLE1 ,Input 1 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 0. " DEBOUNCEENABLE0 ,Input 0 Debounce Enable" "Disabled,Enabled" line.long 0x18 "GPIO_DEBOUNCINGTIME,GPIO debouncing time Register" hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value in 31 microsecond steps" group.long 0x190++0x07 line.long 0x00 "GPIO_CLEARDATAOUT,Clear Data Output Register" bitfld.long 0x00 31. " GPIO_CLEARDATAOUT31 ,Clear Data 31 Output Register" "No effect,Clear" bitfld.long 0x00 30. " GPIO_CLEARDATAOUT30 ,Clear Data 30 Output Register" "No effect,Clear" bitfld.long 0x00 29. " GPIO_CLEARDATAOUT29 ,Clear Data 29 Output Register" "No effect,Clear" bitfld.long 0x00 28. " GPIO_CLEARDATAOUT28 ,Clear Data 28 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 27. " GPIO_CLEARDATAOUT27 ,Clear Data 27 Output Register" "No effect,Clear" bitfld.long 0x00 26. " GPIO_CLEARDATAOUT26 ,Clear Data 26 Output Register" "No effect,Clear" bitfld.long 0x00 25. " GPIO_CLEARDATAOUT25 ,Clear Data 25 Output Register" "No effect,Clear" bitfld.long 0x00 24. " GPIO_CLEARDATAOUT24 ,Clear Data 24 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 23. " GPIO_CLEARDATAOUT23 ,Clear Data 23 Output Register" "No effect,Clear" bitfld.long 0x00 22. " GPIO_CLEARDATAOUT22 ,Clear Data 22 Output Register" "No effect,Clear" bitfld.long 0x00 21. " GPIO_CLEARDATAOUT21 ,Clear Data 21 Output Register" "No effect,Clear" bitfld.long 0x00 20. " GPIO_CLEARDATAOUT20 ,Clear Data 20 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 19. " GPIO_CLEARDATAOUT19 ,Clear Data Output 19 Register" "No effect,Clear" bitfld.long 0x00 18. " GPIO_CLEARDATAOUT18 ,Clear Data 18 Output Register" "No effect,Clear" bitfld.long 0x00 17. " GPIO_CLEARDATAOUT17 ,Clear Data 17 Output Register" "No effect,Clear" bitfld.long 0x00 16. " GPIO_CLEARDATAOUT16 ,Clear Data 16 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 15. " GPIO_CLEARDATAOUT15 ,Clear Data 15 Output Register" "No effect,Clear" bitfld.long 0x00 14. " GPIO_CLEARDATAOUT14 ,Clear Data 14 Output Register" "No effect,Clear" bitfld.long 0x00 13. " GPIO_CLEARDATAOUT13 ,Clear Data 13 Output Register" "No effect,Clear" bitfld.long 0x00 12. " GPIO_CLEARDATAOUT12 ,Clear Data 12 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 11. " GPIO_CLEARDATAOUT11 ,Clear Data 11 Output Register" "No effect,Clear" bitfld.long 0x00 10. " GPIO_CLEARDATAOUT10 ,Clear Data 10 Output Register" "No effect,Clear" bitfld.long 0x00 9. " GPIO_CLEARDATAOUT9 ,Clear Data Output 9 Register" "No effect,Clear" bitfld.long 0x00 8. " GPIO_CLEARDATAOUT8 ,Clear Data 8 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 7. " GPIO_CLEARDATAOUT7 ,Clear Data 7 Output Register" "No effect,Clear" bitfld.long 0x00 6. " GPIO_CLEARDATAOUT6 ,Clear Data 6 Output Register" "No effect,Clear" bitfld.long 0x00 5. " GPIO_CLEARDATAOUT5 ,Clear Data 5 Output Register" "No effect,Clear" bitfld.long 0x00 4. " GPIO_CLEARDATAOUT4 ,Clear Data 4 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 3. " GPIO_CLEARDATAOUT3 ,Clear Data 3 Output Register" "No effect,Clear" bitfld.long 0x00 2. " GPIO_CLEARDATAOUT2 ,Clear Data 2 Output Register" "No effect,Clear" bitfld.long 0x00 1. " GPIO_CLEARDATAOUT1 ,Clear Data 1 Output Register" "No effect,Clear" bitfld.long 0x00 0. " GPIO_CLEARDATAOUT0 ,Clear Data 0 Output Register" "No effect,Clear" line.long 0x04 "GPIO_SETDATAOUT,Set Data Output Register" bitfld.long 0x04 31. " GPIO_SETDATAOUT31 ,Set Data 31 Output Register" "No effect,Set" bitfld.long 0x04 30. " GPIO_SETDATAOUT30 ,Set Data 30 Output Register" "No effect,Set" bitfld.long 0x04 29. " GPIO_SETDATAOUT29 ,Set Data 29 Output Register" "No effect,Set" bitfld.long 0x04 28. " GPIO_SETDATAOUT28 ,Set Data 28 Output Register" "No effect,Set" textline " " bitfld.long 0x04 27. " GPIO_SETDATAOUT27 ,Set Data 27 Output Register" "No effect,Set" bitfld.long 0x04 26. " GPIO_SETDATAOUT26 ,Set Data 26 Output Register" "No effect,Set" bitfld.long 0x04 25. " GPIO_SETDATAOUT25 ,Set Data 25 Output Register" "No effect,Set" bitfld.long 0x04 24. " GPIO_SETDATAOUT24 ,Set Data 24 Output Register" "No effect,Set" textline " " bitfld.long 0x04 23. " GPIO_SETDATAOUT23 ,Set Data 23 Output Register" "No effect,Set" bitfld.long 0x04 22. " GPIO_SETDATAOUT22 ,Set Data 22 Output Register" "No effect,Set" bitfld.long 0x04 21. " GPIO_SETDATAOUT21 ,Set Data 21 Output Register" "No effect,Set" bitfld.long 0x04 20. " GPIO_SETDATAOUT20 ,Set Data 20 Output Register" "No effect,Set" textline " " bitfld.long 0x04 19. " GPIO_SETDATAOUT19 ,Set Data 19 Output Register" "No effect,Set" bitfld.long 0x04 18. " GPIO_SETDATAOUT18 ,Set Data 18 Output Register" "No effect,Set" bitfld.long 0x04 17. " GPIO_SETDATAOUT17 ,Set Data 17 Output Register" "No effect,Set" bitfld.long 0x04 16. " GPIO_SETDATAOUT16 ,Set Data 16 Output Register" "No effect,Set" textline " " bitfld.long 0x04 15. " GPIO_SETDATAOUT15 ,Set Data 15 Output Register" "No effect,Set" bitfld.long 0x04 14. " GPIO_SETDATAOUT14 ,Set Data 14 Output Register" "No effect,Set" bitfld.long 0x04 13. " GPIO_SETDATAOUT13 ,Set Data 13 Output Register" "No effect,Set" bitfld.long 0x04 12. " GPIO_SETDATAOUT12 ,Set Data 12 Output Register" "No effect,Set" textline " " bitfld.long 0x04 11. " GPIO_SETDATAOUT11 ,Set Data 11 Output Register" "No effect,Set" bitfld.long 0x04 10. " GPIO_SETDATAOUT10 ,Set Data 10 Output Register" "No effect,Set" bitfld.long 0x04 9. " GPIO_SETDATAOUT9 ,Set Data 9 Output Register" "No effect,Set" bitfld.long 0x04 8. " GPIO_SETDATAOUT8 ,Set Data 8 Output Register" "No effect,Set" textline " " bitfld.long 0x04 7. " GPIO_SETDATAOUT7 ,Set Data 7 Output Register" "No effect,Set" bitfld.long 0x04 6. " GPIO_SETDATAOUT6 ,Set Data 6 Output Register" "No effect,Set" bitfld.long 0x04 5. " GPIO_SETDATAOUT5 ,Set Data 5 Output Register" "No effect,Set" bitfld.long 0x04 4. " GPIO_SETDATAOUT4 ,Set Data 4 Output Register" "No effect,Set" textline " " bitfld.long 0x04 3. " GPIO_SETDATAOUT3 ,Set Data 3 Output Register" "No effect,Set" bitfld.long 0x04 2. " GPIO_SETDATAOUT2 ,Set Data 2 Output Register" "No effect,Set" bitfld.long 0x04 1. " GPIO_SETDATAOUT1 ,Set Data 1 Output Register" "No effect,Set" bitfld.long 0x04 0. " GPIO_SETDATAOUT0 ,Set Data 0 Output Register" "No effect,Set" width 0xb tree.end tree "Port 1" base ad:0x4804C000 width 22. rgroup.long 0x00++0x03 line.long 0x00 "GPIO_REVISION,GPIO Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional Number" bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Major revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision" group.long 0x10++0x03 line.long 0x00 "GPIO_SYSCONFIG,GPIO SysConfig Register" bitfld.long 0x00 3.--4. " IDLEMODE ,Select IDLE mode" "Force Idle,No Idle Mode,Smart-Idle,Smart Idle/Wakeup" bitfld.long 0x00 1. " SOFTRESET ,Software reset mode" "Normal,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "free-running,OCP" group.long 0x20++0x3 line.long 0x00 "GPIO_EOI,GPIO_EOI register provides software end of interrupt" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledgement" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt control" "0,1" endif group.long 0x24++0xf line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Status Raw Register for interrupt 1" bitfld.long 0x00 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" bitfld.long 0x00 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" bitfld.long 0x00 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" bitfld.long 0x00 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " bitfld.long 0x00 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" bitfld.long 0x00 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" bitfld.long 0x00 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" bitfld.long 0x00 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " bitfld.long 0x00 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" bitfld.long 0x00 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" bitfld.long 0x00 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" bitfld.long 0x00 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " bitfld.long 0x00 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" bitfld.long 0x00 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" bitfld.long 0x00 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" bitfld.long 0x00 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " bitfld.long 0x00 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" bitfld.long 0x00 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" bitfld.long 0x00 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" bitfld.long 0x00 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " bitfld.long 0x00 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" bitfld.long 0x00 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" bitfld.long 0x00 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" bitfld.long 0x00 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " bitfld.long 0x00 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" bitfld.long 0x00 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" bitfld.long 0x00 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" bitfld.long 0x00 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " bitfld.long 0x00 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" bitfld.long 0x00 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" bitfld.long 0x00 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" bitfld.long 0x00 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x04 "GPIO_IRQSTATUS_RAW_1,Status Raw Register for interrupt 1" bitfld.long 0x04 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" bitfld.long 0x04 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" bitfld.long 0x04 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" bitfld.long 0x04 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " bitfld.long 0x04 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" bitfld.long 0x04 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" bitfld.long 0x04 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" bitfld.long 0x04 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " bitfld.long 0x04 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" bitfld.long 0x04 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" bitfld.long 0x04 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" bitfld.long 0x04 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " bitfld.long 0x04 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" bitfld.long 0x04 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" bitfld.long 0x04 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" bitfld.long 0x04 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " bitfld.long 0x04 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" bitfld.long 0x04 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" bitfld.long 0x04 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" bitfld.long 0x04 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " bitfld.long 0x04 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" bitfld.long 0x04 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" bitfld.long 0x04 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" bitfld.long 0x04 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " bitfld.long 0x04 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" bitfld.long 0x04 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" bitfld.long 0x04 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" bitfld.long 0x04 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " bitfld.long 0x04 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" bitfld.long 0x04 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" bitfld.long 0x04 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" bitfld.long 0x04 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x08 "GPIO_IRQSTATUS_0,GPIO_IRQSTATUS_0 register provides core status information for the interrupt handling" setclrfld.long 0x08 31. 0x08 31. 0x10 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" setclrfld.long 0x08 30. 0x08 30. 0x10 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" setclrfld.long 0x08 29. 0x08 29. 0x10 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" setclrfld.long 0x08 28. 0x08 28. 0x10 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " setclrfld.long 0x08 27. 0x08 27. 0x10 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" setclrfld.long 0x08 26. 0x08 26. 0x10 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" setclrfld.long 0x08 25. 0x08 25. 0x10 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" setclrfld.long 0x08 24. 0x08 24. 0x10 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " setclrfld.long 0x08 23. 0x08 23. 0x10 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" setclrfld.long 0x08 22. 0x08 22. 0x10 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" setclrfld.long 0x08 21. 0x08 21. 0x10 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" setclrfld.long 0x08 20. 0x08 20. 0x10 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " setclrfld.long 0x08 19. 0x08 19. 0x10 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" setclrfld.long 0x08 18. 0x08 18. 0x10 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" setclrfld.long 0x08 17. 0x08 17. 0x10 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" setclrfld.long 0x08 16. 0x08 16. 0x10 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " setclrfld.long 0x08 15. 0x08 15. 0x10 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" setclrfld.long 0x08 14. 0x08 14. 0x10 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" setclrfld.long 0x08 13. 0x08 13. 0x10 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" setclrfld.long 0x08 12. 0x08 12. 0x10 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " setclrfld.long 0x08 11. 0x08 11. 0x10 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" setclrfld.long 0x08 10. 0x08 10. 0x10 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" setclrfld.long 0x08 9. 0x08 9. 0x10 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" setclrfld.long 0x08 8. 0x08 8. 0x10 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " setclrfld.long 0x08 7. 0x08 7. 0x10 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" setclrfld.long 0x08 6. 0x08 6. 0x10 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" setclrfld.long 0x08 5. 0x08 5. 0x10 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" setclrfld.long 0x08 4. 0x08 4. 0x10 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " setclrfld.long 0x08 3. 0x08 3. 0x10 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" setclrfld.long 0x08 2. 0x08 2. 0x10 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" setclrfld.long 0x08 1. 0x08 1. 0x10 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" setclrfld.long 0x08 0. 0x08 0. 0x10 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x0c "GPIO_IRQSTATUS_1,GPIO_IRQSTATUS_1 register provides core status information for the interrupt handling" setclrfld.long 0x0c 31. 0x08 31. 0x0c 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" setclrfld.long 0x0c 30. 0x08 30. 0x0c 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" setclrfld.long 0x0c 29. 0x08 29. 0x0c 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" setclrfld.long 0x0c 28. 0x08 28. 0x0c 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 27. 0x08 27. 0x0c 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" setclrfld.long 0x0c 26. 0x08 26. 0x0c 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" setclrfld.long 0x0c 25. 0x08 25. 0x0c 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" setclrfld.long 0x0c 24. 0x08 24. 0x0c 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 23. 0x08 23. 0x0c 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" setclrfld.long 0x0c 22. 0x08 22. 0x0c 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" setclrfld.long 0x0c 21. 0x08 21. 0x0c 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" setclrfld.long 0x0c 20. 0x08 20. 0x0c 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 19. 0x08 19. 0x0c 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" setclrfld.long 0x0c 18. 0x08 18. 0x0c 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" setclrfld.long 0x0c 17. 0x08 17. 0x0c 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" setclrfld.long 0x0c 16. 0x08 16. 0x0c 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 15. 0x08 15. 0x0c 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" setclrfld.long 0x0c 14. 0x08 14. 0x0c 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" setclrfld.long 0x0c 13. 0x08 13. 0x0c 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" setclrfld.long 0x0c 12. 0x08 12. 0x0c 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 11. 0x08 11. 0x0c 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" setclrfld.long 0x0c 10. 0x08 10. 0x0c 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" setclrfld.long 0x0c 9. 0x08 9. 0x0c 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" setclrfld.long 0x0c 8. 0x08 8. 0x0c 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 7. 0x08 7. 0x0c 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" setclrfld.long 0x0c 6. 0x08 6. 0x0c 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" setclrfld.long 0x0c 5. 0x08 5. 0x0c 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" setclrfld.long 0x0c 4. 0x08 4. 0x0c 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 3. 0x08 3. 0x0c 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" setclrfld.long 0x0c 2. 0x08 2. 0x0c 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" setclrfld.long 0x0c 1. 0x08 1. 0x0c 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" setclrfld.long 0x0c 0. 0x08 0. 0x0c 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" group.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x07 line.long 0x00 "GPIO_CTRL,module control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Controls the clock gating for the event detection logic (divider)" "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" line.long 0x04 "GPIO_OE,GPIO output enable register" bitfld.long 0x04 31. " OUTPUTEN31 ,GPIO 31 Output Data Enable" "Output,Input" bitfld.long 0x04 30. " OUTPUTEN30 ,GPIO 30 Output Data Enable" "Output,Input" bitfld.long 0x04 29. " OUTPUTEN29 ,GPIO 29 Output Data Enable" "Output,Input" bitfld.long 0x04 28. " OUTPUTEN28 ,GPIO 28 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 27. " OUTPUTEN27 ,GPIO 27 Output Data Enable" "Output,Input" bitfld.long 0x04 26. " OUTPUTEN26 ,GPIO 26 Output Data Enable" "Output,Input" bitfld.long 0x04 25. " OUTPUTEN25 ,GPIO 25 Output Data Enable" "Output,Input" bitfld.long 0x04 24. " OUTPUTEN24 ,GPIO 24 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 23. " OUTPUTEN23 ,GPIO 23 Output Data Enable" "Output,Input" bitfld.long 0x04 22. " OUTPUTEN22 ,GPIO 22 Output Data Enable" "Output,Input" bitfld.long 0x04 21. " OUTPUTEN21 ,GPIO 21 Output Data Enable" "Output,Input" bitfld.long 0x04 20. " OUTPUTEN20 ,GPIO 20 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 19. " OUTPUTEN19 ,GPIO 19 Output Data Enable" "Output,Input" bitfld.long 0x04 18. " OUTPUTEN18 ,GPIO 18 Output Data Enable" "Output,Input" bitfld.long 0x04 17. " OUTPUTEN17 ,GPIO 17 Output Data Enable" "Output,Input" bitfld.long 0x04 16. " OUTPUTEN16 ,GPIO 16 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 15. " OUTPUTEN15 ,GPIO 15 Output Data Enable" "Output,Input" bitfld.long 0x04 14. " OUTPUTEN14 ,GPIO 14 Output Data Enable" "Output,Input" bitfld.long 0x04 13. " OUTPUTEN13 ,GPIO 13 Output Data Enable" "Output,Input" bitfld.long 0x04 12. " OUTPUTEN12 ,GPIO 12 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 11. " OUTPUTEN11 ,GPIO 11 Output Data Enable" "Output,Input" bitfld.long 0x04 10. " OUTPUTEN10 ,GPIO 10 Output Data Enable" "Output,Input" bitfld.long 0x04 9. " OUTPUTEN9 ,GPIO 9 Output Data Enable" "Output,Input" bitfld.long 0x04 8. " OUTPUTEN8 ,GPIO 8 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 7. " OUTPUTEN7 ,GPIO 7 Output Data Enable" "Output,Input" bitfld.long 0x04 6. " OUTPUTEN6 ,GPIO 6 Output Data Enable" "Output,Input" bitfld.long 0x04 5. " OUTPUTEN5 ,GPIO 5 Output Data Enable" "Output,Input" bitfld.long 0x04 4. " OUTPUTEN4 ,GPIO 4 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 3. " OUTPUTEN3 ,GPIO 3 Output Data Enable" "Output,Input" bitfld.long 0x04 2. " OUTPUTEN2 ,GPIO 2 Output Data Enable" "Output,Input" bitfld.long 0x04 1. " OUTPUTEN1 ,GPIO 1 Output Data Enable" "Output,Input" bitfld.long 0x04 0. " OUTPUTEN0 ,GPIO 0 Output Data Enable" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,Sampled Input Data" group.long 0x13c++0x1b line.long 0x00 "GPIO_DATAOUT,Data to set on output pins" line.long 0x04 "GPIO_LEVELDETECT0,low-level detection to be used for the interrupt request generation" bitfld.long 0x04 31. " LEVELDETECT031 ,LEVELDETECT0[31] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 30. " LEVELDETECT030 ,LEVELDETECT0[30] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 29. " LEVELDETECT029 ,LEVELDETECT0[29] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 28. " LEVELDETECT028 ,LEVELDETECT0[28] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 27. " LEVELDETECT027 ,LEVELDETECT0[27] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 26. " LEVELDETECT026 ,LEVELDETECT0[26] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 25. " LEVELDETECT025 ,LEVELDETECT0[25] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 24. " LEVELDETECT024 ,LEVELDETECT0[24] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 23. " LEVELDETECT023 ,LEVELDETECT0[23] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 22. " LEVELDETECT022 ,LEVELDETECT0[22] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 21. " LEVELDETECT021 ,LEVELDETECT0[21] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 20. " LEVELDETECT020 ,LEVELDETECT0[20] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 19. " LEVELDETECT019 ,LEVELDETECT0[19] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 18. " LEVELDETECT018 ,LEVELDETECT0[18] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 17. " LEVELDETECT017 ,LEVELDETECT0[17] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 16. " LEVELDETECT016 ,LEVELDETECT0[16] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 15. " LEVELDETECT015 ,LEVELDETECT0[15] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 14. " LEVELDETECT014 ,LEVELDETECT0[14] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 13. " LEVELDETECT013 ,LEVELDETECT0[13] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 12. " LEVELDETECT012 ,LEVELDETECT0[12] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 11. " LEVELDETECT011 ,LEVELDETECT0[11] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 10. " LEVELDETECT010 ,LEVELDETECT0[10] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 9. " LEVELDETECT09 ,LEVELDETECT0[9] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 8. " LEVELDETECT08 ,LEVELDETECT0[8] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 7. " LEVELDETECT07 ,LEVELDETECT0[7] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 6. " LEVELDETECT06 ,LEVELDETECT0[6] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 5. " LEVELDETECT05 ,LEVELDETECT0[5] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 4. " LEVELDETECT04 ,LEVELDETECT0[4] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 3. " LEVELDETECT03 ,LEVELDETECT0[3] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 2. " LEVELDETECT02 ,LEVELDETECT0[2] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 1. " LEVELDETECT01 ,LEVELDETECT0[1] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 0. " LEVELDETECT00 ,LEVELDETECT0[0] Low Level Interrupt 31 Enable " "Disabled,Enabled" line.long 0x08 "GPIO_LEVELDETECT1,low-level detection to be used for the interrupt request generation" bitfld.long 0x08 31. " LEVELDETECT131 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 30. " LEVELDETECT130 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 29. " LEVELDETECT129 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 28. " LEVELDETECT128 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 27. " LEVELDETECT127 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 26. " LEVELDETECT126 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 25. " LEVELDETECT125 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 24. " LEVELDETECT124 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 23. " LEVELDETECT123 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 22. " LEVELDETECT122 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 21. " LEVELDETECT121 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 20. " LEVELDETECT120 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 19. " LEVELDETECT119 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 18. " LEVELDETECT118 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 17. " LEVELDETECT117 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 16. " LEVELDETECT116 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 15. " LEVELDETECT115 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 14. " LEVELDETECT114 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 13. " LEVELDETECT113 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 12. " LEVELDETECT112 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 11. " LEVELDETECT111 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 10. " LEVELDETECT110 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 9. " LEVELDETECT11 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 8. " LEVELDETECT18 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 7. " LEVELDETECT17 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 6. " LEVELDETECT16 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 5. " LEVELDETECT15 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 4. " LEVELDETECT14 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 3. " LEVELDETECT13 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 2. " LEVELDETECT12 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 1. " LEVELDETECT11 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 0. " LEVELDETECT10 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" line.long 0x0c "GPIO_RISINGDETECT,rising-edge detection to be used for the interrupt request generation" bitfld.long 0x0c 31. " RISINGDETECT31 ,Rising Edge Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x0c 30. " RISINGDETECT30 ,Rising Edge Interrupt 30 Enable " "Disabled,Enabled" bitfld.long 0x0c 29. " RISINGDETECT29 ,Rising Edge Interrupt 29 Enable " "Disabled,Enabled" bitfld.long 0x0c 28. " RISINGDETECT28 ,Rising Edge Interrupt 28 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 27. " RISINGDETECT27 ,Rising Edge Interrupt 27 Enable " "Disabled,Enabled" bitfld.long 0x0c 26. " RISINGDETECT26 ,Rising Edge Interrupt 26 Enable " "Disabled,Enabled" bitfld.long 0x0c 25. " RISINGDETECT25 ,Rising Edge Interrupt 25 Enable " "Disabled,Enabled" bitfld.long 0x0c 24. " RISINGDETECT24 ,Rising Edge Interrupt 24 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 23. " RISINGDETECT23 ,Rising Edge Interrupt 23 Enable " "Disabled,Enabled" bitfld.long 0x0c 22. " RISINGDETECT22 ,Rising Edge Interrupt 22 Enable " "Disabled,Enabled" bitfld.long 0x0c 21. " RISINGDETECT21 ,Rising Edge Interrupt 21 Enable " "Disabled,Enabled" bitfld.long 0x0c 20. " RISINGDETECT20 ,Rising Edge Interrupt 20 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 19. " RISINGDETECT19 ,Rising Edge Interrupt 19 Enable " "Disabled,Enabled" bitfld.long 0x0c 18. " RISINGDETECT18 ,Rising Edge Interrupt 18 Enable " "Disabled,Enabled" bitfld.long 0x0c 17. " RISINGDETECT17 ,Rising Edge Interrupt 17 Enable " "Disabled,Enabled" bitfld.long 0x0c 16. " RISINGDETECT16 ,Rising Edge Interrupt 16 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 15. " RISINGDETECT15 ,Rising Edge Interrupt 15 Enable " "Disabled,Enabled" bitfld.long 0x0c 14. " RISINGDETECT14 ,Rising Edge Interrupt 14 Enable " "Disabled,Enabled" bitfld.long 0x0c 13. " RISINGDETECT13 ,Rising Edge Interrupt 13 Enable " "Disabled,Enabled" bitfld.long 0x0c 12. " RISINGDETECT12 ,Rising Edge Interrupt 12 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 11. " RISINGDETECT11 ,Rising Edge Interrupt 11 Enable " "Disabled,Enabled" bitfld.long 0x0c 10. " RISINGDETECT10 ,Rising Edge Interrupt 10 Enable " "Disabled,Enabled" bitfld.long 0x0c 9. " RISINGDETECT9 ,Rising Edge Interrupt 9 Enable " "Disabled,Enabled" bitfld.long 0x0c 8. " RISINGDETECT8 ,Rising Edge Interrupt 8 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 7. " RISINGDETECT7 ,Rising Edge Interrupt 7 Enable " "Disabled,Enabled" bitfld.long 0x0c 6. " RISINGDETECT6 ,Rising Edge Interrupt 6 Enable " "Disabled,Enabled" bitfld.long 0x0c 5. " RISINGDETECT5 ,Rising Edge Interrupt 5 Enable " "Disabled,Enabled" bitfld.long 0x0c 4. " RISINGDETECT4 ,Rising Edge Interrupt 4 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 3. " RISINGDETECT3 ,Rising Edge Interrupt 3 Enable " "Disabled,Enabled" bitfld.long 0x0c 2. " RISINGDETECT2 ,Rising Edge Interrupt 2 Enable " "Disabled,Enabled" bitfld.long 0x0c 1. " RISINGDETECT1 ,Rising Edge Interrupt 1 Enable " "Disabled,Enabled" bitfld.long 0x0c 0. " RISINGDETECT0 ,Rising Edge Interrupt 0 Enable " "Disabled,Enabled" line.long 0x10 "GPIO_FALLINGDETECT,falling-edge detection to be used for the interrupt request generation" bitfld.long 0x10 31. " FALLINGDETECT31 ,falling-edge detection 31" "Disabled,Enabled" bitfld.long 0x10 30. " FALLINGDETECT30 ,falling-edge detection 30" "Disabled,Enabled" bitfld.long 0x10 29. " FALLINGDETECT29 ,falling-edge detection 29" "Disabled,Enabled" bitfld.long 0x10 28. " FALLINGDETECT28 ,falling-edge detection 28" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " FALLINGDETECT27 ,falling-edge detection 27" "Disabled,Enabled" bitfld.long 0x10 26. " FALLINGDETECT26 ,falling-edge detection 26" "Disabled,Enabled" bitfld.long 0x10 25. " FALLINGDETECT25 ,falling-edge detection 25" "Disabled,Enabled" bitfld.long 0x10 24. " FALLINGDETECT24 ,falling-edge detection 24" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " FALLINGDETECT23 ,falling-edge detection 23" "Disabled,Enabled" bitfld.long 0x10 22. " FALLINGDETECT22 ,falling-edge detection 22" "Disabled,Enabled" bitfld.long 0x10 21. " FALLINGDETECT21 ,falling-edge detection 21" "Disabled,Enabled" bitfld.long 0x10 20. " FALLINGDETECT20 ,falling-edge detection 20" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " FALLINGDETECT19 ,falling-edge detection 19" "Disabled,Enabled" bitfld.long 0x10 18. " FALLINGDETECT18 ,falling-edge detection 18" "Disabled,Enabled" bitfld.long 0x10 17. " FALLINGDETECT17 ,falling-edge detection 17" "Disabled,Enabled" bitfld.long 0x10 16. " FALLINGDETECT16 ,falling-edge detection 16" "Disabled,Enabled" textline " " bitfld.long 0x10 15. " FALLINGDETECT15 ,falling-edge detection 15" "Disabled,Enabled" bitfld.long 0x10 14. " FALLINGDETECT14 ,falling-edge detection 14" "Disabled,Enabled" bitfld.long 0x10 13. " FALLINGDETECT13 ,falling-edge detection 13" "Disabled,Enabled" bitfld.long 0x10 12. " FALLINGDETECT12 ,falling-edge detection 12" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " FALLINGDETECT11 ,falling-edge detection 11" "Disabled,Enabled" bitfld.long 0x10 10. " FALLINGDETECT10 ,falling-edge detection 10" "Disabled,Enabled" bitfld.long 0x10 9. " FALLINGDETECT9 ,falling-edge detection 9" "Disabled,Enabled" bitfld.long 0x10 8. " FALLINGDETECT8 ,falling-edge detection 8" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " FALLINGDETECT7 ,falling-edge detection 7" "Disabled,Enabled" bitfld.long 0x10 6. " FALLINGDETECT6 ,falling-edge detection 6" "Disabled,Enabled" bitfld.long 0x10 5. " FALLINGDETECT5 ,falling-edge detection 5" "Disabled,Enabled" bitfld.long 0x10 4. " FALLINGDETECT4 ,falling-edge detection 4" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " FALLINGDETECT3 ,falling-edge detection 3" "Disabled,Enabled" bitfld.long 0x10 2. " FALLINGDETECT2 ,falling-edge detection 2" "Disabled,Enabled" bitfld.long 0x10 1. " FALLINGDETECT1 ,falling-edge detection 1" "Disabled,Enabled" bitfld.long 0x10 0. " FALLINGDETECT0 ,falling-edge detection 0" "Disabled,Enabled" line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable register" bitfld.long 0x14 31. " DEBOUNCEENABLE31 ,Input 31 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 30. " DEBOUNCEENABLE30 ,Input 30 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 29. " DEBOUNCEENABLE29 ,Input 29 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 28. " DEBOUNCEENABLE28 ,Input 28 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " DEBOUNCEENABLE27 ,Input 27 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 26. " DEBOUNCEENABLE26 ,Input 26 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 25. " DEBOUNCEENABLE25 ,Input 25 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 24. " DEBOUNCEENABLE24 ,Input 24 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " DEBOUNCEENABLE23 ,Input 23 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 22. " DEBOUNCEENABLE22 ,Input 22 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 21. " DEBOUNCEENABLE21 ,Input 21 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 20. " DEBOUNCEENABLE20 ,Input 20 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " DEBOUNCEENABLE19 ,Input 19 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 18. " DEBOUNCEENABLE18 ,Input 18 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 17. " DEBOUNCEENABLE17 ,Input 17 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 16. " DEBOUNCEENABLE16 ,Input 16 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " DEBOUNCEENABLE15 ,Input 15 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 14. " DEBOUNCEENABLE14 ,Input 14 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 13. " DEBOUNCEENABLE13 ,Input 13 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 12. " DEBOUNCEENABLE12 ,Input 12 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " DEBOUNCEENABLE11 ,Input 11 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 10. " DEBOUNCEENABLE10 ,Input 10 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 9. " DEBOUNCEENABLE9 ,Input 9 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 8. " DEBOUNCEENABLE8 ,Input 8 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " DEBOUNCEENABLE7 ,Input 7 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 6. " DEBOUNCEENABLE6 ,Input 6 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 5. " DEBOUNCEENABLE5 ,Input 5 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 4. " DEBOUNCEENABLE4 ,Input 4 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " DEBOUNCEENABLE3 ,Input 3 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 2. " DEBOUNCEENABLE2 ,Input 2 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 1. " DEBOUNCEENABLE1 ,Input 1 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 0. " DEBOUNCEENABLE0 ,Input 0 Debounce Enable" "Disabled,Enabled" line.long 0x18 "GPIO_DEBOUNCINGTIME,GPIO debouncing time Register" hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value in 31 microsecond steps" group.long 0x190++0x07 line.long 0x00 "GPIO_CLEARDATAOUT,Clear Data Output Register" bitfld.long 0x00 31. " GPIO_CLEARDATAOUT31 ,Clear Data 31 Output Register" "No effect,Clear" bitfld.long 0x00 30. " GPIO_CLEARDATAOUT30 ,Clear Data 30 Output Register" "No effect,Clear" bitfld.long 0x00 29. " GPIO_CLEARDATAOUT29 ,Clear Data 29 Output Register" "No effect,Clear" bitfld.long 0x00 28. " GPIO_CLEARDATAOUT28 ,Clear Data 28 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 27. " GPIO_CLEARDATAOUT27 ,Clear Data 27 Output Register" "No effect,Clear" bitfld.long 0x00 26. " GPIO_CLEARDATAOUT26 ,Clear Data 26 Output Register" "No effect,Clear" bitfld.long 0x00 25. " GPIO_CLEARDATAOUT25 ,Clear Data 25 Output Register" "No effect,Clear" bitfld.long 0x00 24. " GPIO_CLEARDATAOUT24 ,Clear Data 24 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 23. " GPIO_CLEARDATAOUT23 ,Clear Data 23 Output Register" "No effect,Clear" bitfld.long 0x00 22. " GPIO_CLEARDATAOUT22 ,Clear Data 22 Output Register" "No effect,Clear" bitfld.long 0x00 21. " GPIO_CLEARDATAOUT21 ,Clear Data 21 Output Register" "No effect,Clear" bitfld.long 0x00 20. " GPIO_CLEARDATAOUT20 ,Clear Data 20 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 19. " GPIO_CLEARDATAOUT19 ,Clear Data Output 19 Register" "No effect,Clear" bitfld.long 0x00 18. " GPIO_CLEARDATAOUT18 ,Clear Data 18 Output Register" "No effect,Clear" bitfld.long 0x00 17. " GPIO_CLEARDATAOUT17 ,Clear Data 17 Output Register" "No effect,Clear" bitfld.long 0x00 16. " GPIO_CLEARDATAOUT16 ,Clear Data 16 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 15. " GPIO_CLEARDATAOUT15 ,Clear Data 15 Output Register" "No effect,Clear" bitfld.long 0x00 14. " GPIO_CLEARDATAOUT14 ,Clear Data 14 Output Register" "No effect,Clear" bitfld.long 0x00 13. " GPIO_CLEARDATAOUT13 ,Clear Data 13 Output Register" "No effect,Clear" bitfld.long 0x00 12. " GPIO_CLEARDATAOUT12 ,Clear Data 12 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 11. " GPIO_CLEARDATAOUT11 ,Clear Data 11 Output Register" "No effect,Clear" bitfld.long 0x00 10. " GPIO_CLEARDATAOUT10 ,Clear Data 10 Output Register" "No effect,Clear" bitfld.long 0x00 9. " GPIO_CLEARDATAOUT9 ,Clear Data Output 9 Register" "No effect,Clear" bitfld.long 0x00 8. " GPIO_CLEARDATAOUT8 ,Clear Data 8 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 7. " GPIO_CLEARDATAOUT7 ,Clear Data 7 Output Register" "No effect,Clear" bitfld.long 0x00 6. " GPIO_CLEARDATAOUT6 ,Clear Data 6 Output Register" "No effect,Clear" bitfld.long 0x00 5. " GPIO_CLEARDATAOUT5 ,Clear Data 5 Output Register" "No effect,Clear" bitfld.long 0x00 4. " GPIO_CLEARDATAOUT4 ,Clear Data 4 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 3. " GPIO_CLEARDATAOUT3 ,Clear Data 3 Output Register" "No effect,Clear" bitfld.long 0x00 2. " GPIO_CLEARDATAOUT2 ,Clear Data 2 Output Register" "No effect,Clear" bitfld.long 0x00 1. " GPIO_CLEARDATAOUT1 ,Clear Data 1 Output Register" "No effect,Clear" bitfld.long 0x00 0. " GPIO_CLEARDATAOUT0 ,Clear Data 0 Output Register" "No effect,Clear" line.long 0x04 "GPIO_SETDATAOUT,Set Data Output Register" bitfld.long 0x04 31. " GPIO_SETDATAOUT31 ,Set Data 31 Output Register" "No effect,Set" bitfld.long 0x04 30. " GPIO_SETDATAOUT30 ,Set Data 30 Output Register" "No effect,Set" bitfld.long 0x04 29. " GPIO_SETDATAOUT29 ,Set Data 29 Output Register" "No effect,Set" bitfld.long 0x04 28. " GPIO_SETDATAOUT28 ,Set Data 28 Output Register" "No effect,Set" textline " " bitfld.long 0x04 27. " GPIO_SETDATAOUT27 ,Set Data 27 Output Register" "No effect,Set" bitfld.long 0x04 26. " GPIO_SETDATAOUT26 ,Set Data 26 Output Register" "No effect,Set" bitfld.long 0x04 25. " GPIO_SETDATAOUT25 ,Set Data 25 Output Register" "No effect,Set" bitfld.long 0x04 24. " GPIO_SETDATAOUT24 ,Set Data 24 Output Register" "No effect,Set" textline " " bitfld.long 0x04 23. " GPIO_SETDATAOUT23 ,Set Data 23 Output Register" "No effect,Set" bitfld.long 0x04 22. " GPIO_SETDATAOUT22 ,Set Data 22 Output Register" "No effect,Set" bitfld.long 0x04 21. " GPIO_SETDATAOUT21 ,Set Data 21 Output Register" "No effect,Set" bitfld.long 0x04 20. " GPIO_SETDATAOUT20 ,Set Data 20 Output Register" "No effect,Set" textline " " bitfld.long 0x04 19. " GPIO_SETDATAOUT19 ,Set Data 19 Output Register" "No effect,Set" bitfld.long 0x04 18. " GPIO_SETDATAOUT18 ,Set Data 18 Output Register" "No effect,Set" bitfld.long 0x04 17. " GPIO_SETDATAOUT17 ,Set Data 17 Output Register" "No effect,Set" bitfld.long 0x04 16. " GPIO_SETDATAOUT16 ,Set Data 16 Output Register" "No effect,Set" textline " " bitfld.long 0x04 15. " GPIO_SETDATAOUT15 ,Set Data 15 Output Register" "No effect,Set" bitfld.long 0x04 14. " GPIO_SETDATAOUT14 ,Set Data 14 Output Register" "No effect,Set" bitfld.long 0x04 13. " GPIO_SETDATAOUT13 ,Set Data 13 Output Register" "No effect,Set" bitfld.long 0x04 12. " GPIO_SETDATAOUT12 ,Set Data 12 Output Register" "No effect,Set" textline " " bitfld.long 0x04 11. " GPIO_SETDATAOUT11 ,Set Data 11 Output Register" "No effect,Set" bitfld.long 0x04 10. " GPIO_SETDATAOUT10 ,Set Data 10 Output Register" "No effect,Set" bitfld.long 0x04 9. " GPIO_SETDATAOUT9 ,Set Data 9 Output Register" "No effect,Set" bitfld.long 0x04 8. " GPIO_SETDATAOUT8 ,Set Data 8 Output Register" "No effect,Set" textline " " bitfld.long 0x04 7. " GPIO_SETDATAOUT7 ,Set Data 7 Output Register" "No effect,Set" bitfld.long 0x04 6. " GPIO_SETDATAOUT6 ,Set Data 6 Output Register" "No effect,Set" bitfld.long 0x04 5. " GPIO_SETDATAOUT5 ,Set Data 5 Output Register" "No effect,Set" bitfld.long 0x04 4. " GPIO_SETDATAOUT4 ,Set Data 4 Output Register" "No effect,Set" textline " " bitfld.long 0x04 3. " GPIO_SETDATAOUT3 ,Set Data 3 Output Register" "No effect,Set" bitfld.long 0x04 2. " GPIO_SETDATAOUT2 ,Set Data 2 Output Register" "No effect,Set" bitfld.long 0x04 1. " GPIO_SETDATAOUT1 ,Set Data 1 Output Register" "No effect,Set" bitfld.long 0x04 0. " GPIO_SETDATAOUT0 ,Set Data 0 Output Register" "No effect,Set" width 0xb tree.end tree "Port 2" base ad:0x481AC000 width 22. rgroup.long 0x00++0x03 line.long 0x00 "GPIO_REVISION,GPIO Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional Number" bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Major revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision" group.long 0x10++0x03 line.long 0x00 "GPIO_SYSCONFIG,GPIO SysConfig Register" bitfld.long 0x00 3.--4. " IDLEMODE ,Select IDLE mode" "Force Idle,No Idle Mode,Smart-Idle,Smart Idle/Wakeup" bitfld.long 0x00 1. " SOFTRESET ,Software reset mode" "Normal,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "free-running,OCP" group.long 0x20++0x3 line.long 0x00 "GPIO_EOI,GPIO_EOI register provides software end of interrupt" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledgement" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt control" "0,1" endif group.long 0x24++0xf line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Status Raw Register for interrupt 1" bitfld.long 0x00 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" bitfld.long 0x00 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" bitfld.long 0x00 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" bitfld.long 0x00 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " bitfld.long 0x00 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" bitfld.long 0x00 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" bitfld.long 0x00 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" bitfld.long 0x00 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " bitfld.long 0x00 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" bitfld.long 0x00 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" bitfld.long 0x00 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" bitfld.long 0x00 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " bitfld.long 0x00 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" bitfld.long 0x00 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" bitfld.long 0x00 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" bitfld.long 0x00 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " bitfld.long 0x00 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" bitfld.long 0x00 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" bitfld.long 0x00 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" bitfld.long 0x00 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " bitfld.long 0x00 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" bitfld.long 0x00 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" bitfld.long 0x00 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" bitfld.long 0x00 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " bitfld.long 0x00 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" bitfld.long 0x00 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" bitfld.long 0x00 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" bitfld.long 0x00 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " bitfld.long 0x00 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" bitfld.long 0x00 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" bitfld.long 0x00 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" bitfld.long 0x00 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x04 "GPIO_IRQSTATUS_RAW_1,Status Raw Register for interrupt 1" bitfld.long 0x04 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" bitfld.long 0x04 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" bitfld.long 0x04 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" bitfld.long 0x04 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " bitfld.long 0x04 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" bitfld.long 0x04 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" bitfld.long 0x04 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" bitfld.long 0x04 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " bitfld.long 0x04 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" bitfld.long 0x04 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" bitfld.long 0x04 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" bitfld.long 0x04 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " bitfld.long 0x04 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" bitfld.long 0x04 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" bitfld.long 0x04 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" bitfld.long 0x04 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " bitfld.long 0x04 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" bitfld.long 0x04 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" bitfld.long 0x04 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" bitfld.long 0x04 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " bitfld.long 0x04 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" bitfld.long 0x04 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" bitfld.long 0x04 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" bitfld.long 0x04 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " bitfld.long 0x04 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" bitfld.long 0x04 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" bitfld.long 0x04 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" bitfld.long 0x04 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " bitfld.long 0x04 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" bitfld.long 0x04 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" bitfld.long 0x04 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" bitfld.long 0x04 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x08 "GPIO_IRQSTATUS_0,GPIO_IRQSTATUS_0 register provides core status information for the interrupt handling" setclrfld.long 0x08 31. 0x08 31. 0x10 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" setclrfld.long 0x08 30. 0x08 30. 0x10 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" setclrfld.long 0x08 29. 0x08 29. 0x10 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" setclrfld.long 0x08 28. 0x08 28. 0x10 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " setclrfld.long 0x08 27. 0x08 27. 0x10 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" setclrfld.long 0x08 26. 0x08 26. 0x10 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" setclrfld.long 0x08 25. 0x08 25. 0x10 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" setclrfld.long 0x08 24. 0x08 24. 0x10 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " setclrfld.long 0x08 23. 0x08 23. 0x10 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" setclrfld.long 0x08 22. 0x08 22. 0x10 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" setclrfld.long 0x08 21. 0x08 21. 0x10 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" setclrfld.long 0x08 20. 0x08 20. 0x10 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " setclrfld.long 0x08 19. 0x08 19. 0x10 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" setclrfld.long 0x08 18. 0x08 18. 0x10 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" setclrfld.long 0x08 17. 0x08 17. 0x10 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" setclrfld.long 0x08 16. 0x08 16. 0x10 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " setclrfld.long 0x08 15. 0x08 15. 0x10 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" setclrfld.long 0x08 14. 0x08 14. 0x10 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" setclrfld.long 0x08 13. 0x08 13. 0x10 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" setclrfld.long 0x08 12. 0x08 12. 0x10 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " setclrfld.long 0x08 11. 0x08 11. 0x10 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" setclrfld.long 0x08 10. 0x08 10. 0x10 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" setclrfld.long 0x08 9. 0x08 9. 0x10 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" setclrfld.long 0x08 8. 0x08 8. 0x10 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " setclrfld.long 0x08 7. 0x08 7. 0x10 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" setclrfld.long 0x08 6. 0x08 6. 0x10 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" setclrfld.long 0x08 5. 0x08 5. 0x10 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" setclrfld.long 0x08 4. 0x08 4. 0x10 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " setclrfld.long 0x08 3. 0x08 3. 0x10 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" setclrfld.long 0x08 2. 0x08 2. 0x10 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" setclrfld.long 0x08 1. 0x08 1. 0x10 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" setclrfld.long 0x08 0. 0x08 0. 0x10 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x0c "GPIO_IRQSTATUS_1,GPIO_IRQSTATUS_1 register provides core status information for the interrupt handling" setclrfld.long 0x0c 31. 0x08 31. 0x0c 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" setclrfld.long 0x0c 30. 0x08 30. 0x0c 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" setclrfld.long 0x0c 29. 0x08 29. 0x0c 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" setclrfld.long 0x0c 28. 0x08 28. 0x0c 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 27. 0x08 27. 0x0c 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" setclrfld.long 0x0c 26. 0x08 26. 0x0c 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" setclrfld.long 0x0c 25. 0x08 25. 0x0c 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" setclrfld.long 0x0c 24. 0x08 24. 0x0c 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 23. 0x08 23. 0x0c 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" setclrfld.long 0x0c 22. 0x08 22. 0x0c 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" setclrfld.long 0x0c 21. 0x08 21. 0x0c 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" setclrfld.long 0x0c 20. 0x08 20. 0x0c 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 19. 0x08 19. 0x0c 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" setclrfld.long 0x0c 18. 0x08 18. 0x0c 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" setclrfld.long 0x0c 17. 0x08 17. 0x0c 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" setclrfld.long 0x0c 16. 0x08 16. 0x0c 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 15. 0x08 15. 0x0c 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" setclrfld.long 0x0c 14. 0x08 14. 0x0c 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" setclrfld.long 0x0c 13. 0x08 13. 0x0c 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" setclrfld.long 0x0c 12. 0x08 12. 0x0c 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 11. 0x08 11. 0x0c 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" setclrfld.long 0x0c 10. 0x08 10. 0x0c 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" setclrfld.long 0x0c 9. 0x08 9. 0x0c 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" setclrfld.long 0x0c 8. 0x08 8. 0x0c 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 7. 0x08 7. 0x0c 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" setclrfld.long 0x0c 6. 0x08 6. 0x0c 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" setclrfld.long 0x0c 5. 0x08 5. 0x0c 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" setclrfld.long 0x0c 4. 0x08 4. 0x0c 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 3. 0x08 3. 0x0c 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" setclrfld.long 0x0c 2. 0x08 2. 0x0c 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" setclrfld.long 0x0c 1. 0x08 1. 0x0c 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" setclrfld.long 0x0c 0. 0x08 0. 0x0c 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" group.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x07 line.long 0x00 "GPIO_CTRL,module control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Controls the clock gating for the event detection logic (divider)" "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" line.long 0x04 "GPIO_OE,GPIO output enable register" bitfld.long 0x04 31. " OUTPUTEN31 ,GPIO 31 Output Data Enable" "Output,Input" bitfld.long 0x04 30. " OUTPUTEN30 ,GPIO 30 Output Data Enable" "Output,Input" bitfld.long 0x04 29. " OUTPUTEN29 ,GPIO 29 Output Data Enable" "Output,Input" bitfld.long 0x04 28. " OUTPUTEN28 ,GPIO 28 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 27. " OUTPUTEN27 ,GPIO 27 Output Data Enable" "Output,Input" bitfld.long 0x04 26. " OUTPUTEN26 ,GPIO 26 Output Data Enable" "Output,Input" bitfld.long 0x04 25. " OUTPUTEN25 ,GPIO 25 Output Data Enable" "Output,Input" bitfld.long 0x04 24. " OUTPUTEN24 ,GPIO 24 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 23. " OUTPUTEN23 ,GPIO 23 Output Data Enable" "Output,Input" bitfld.long 0x04 22. " OUTPUTEN22 ,GPIO 22 Output Data Enable" "Output,Input" bitfld.long 0x04 21. " OUTPUTEN21 ,GPIO 21 Output Data Enable" "Output,Input" bitfld.long 0x04 20. " OUTPUTEN20 ,GPIO 20 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 19. " OUTPUTEN19 ,GPIO 19 Output Data Enable" "Output,Input" bitfld.long 0x04 18. " OUTPUTEN18 ,GPIO 18 Output Data Enable" "Output,Input" bitfld.long 0x04 17. " OUTPUTEN17 ,GPIO 17 Output Data Enable" "Output,Input" bitfld.long 0x04 16. " OUTPUTEN16 ,GPIO 16 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 15. " OUTPUTEN15 ,GPIO 15 Output Data Enable" "Output,Input" bitfld.long 0x04 14. " OUTPUTEN14 ,GPIO 14 Output Data Enable" "Output,Input" bitfld.long 0x04 13. " OUTPUTEN13 ,GPIO 13 Output Data Enable" "Output,Input" bitfld.long 0x04 12. " OUTPUTEN12 ,GPIO 12 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 11. " OUTPUTEN11 ,GPIO 11 Output Data Enable" "Output,Input" bitfld.long 0x04 10. " OUTPUTEN10 ,GPIO 10 Output Data Enable" "Output,Input" bitfld.long 0x04 9. " OUTPUTEN9 ,GPIO 9 Output Data Enable" "Output,Input" bitfld.long 0x04 8. " OUTPUTEN8 ,GPIO 8 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 7. " OUTPUTEN7 ,GPIO 7 Output Data Enable" "Output,Input" bitfld.long 0x04 6. " OUTPUTEN6 ,GPIO 6 Output Data Enable" "Output,Input" bitfld.long 0x04 5. " OUTPUTEN5 ,GPIO 5 Output Data Enable" "Output,Input" bitfld.long 0x04 4. " OUTPUTEN4 ,GPIO 4 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 3. " OUTPUTEN3 ,GPIO 3 Output Data Enable" "Output,Input" bitfld.long 0x04 2. " OUTPUTEN2 ,GPIO 2 Output Data Enable" "Output,Input" bitfld.long 0x04 1. " OUTPUTEN1 ,GPIO 1 Output Data Enable" "Output,Input" bitfld.long 0x04 0. " OUTPUTEN0 ,GPIO 0 Output Data Enable" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,Sampled Input Data" group.long 0x13c++0x1b line.long 0x00 "GPIO_DATAOUT,Data to set on output pins" line.long 0x04 "GPIO_LEVELDETECT0,low-level detection to be used for the interrupt request generation" bitfld.long 0x04 31. " LEVELDETECT031 ,LEVELDETECT0[31] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 30. " LEVELDETECT030 ,LEVELDETECT0[30] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 29. " LEVELDETECT029 ,LEVELDETECT0[29] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 28. " LEVELDETECT028 ,LEVELDETECT0[28] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 27. " LEVELDETECT027 ,LEVELDETECT0[27] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 26. " LEVELDETECT026 ,LEVELDETECT0[26] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 25. " LEVELDETECT025 ,LEVELDETECT0[25] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 24. " LEVELDETECT024 ,LEVELDETECT0[24] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 23. " LEVELDETECT023 ,LEVELDETECT0[23] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 22. " LEVELDETECT022 ,LEVELDETECT0[22] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 21. " LEVELDETECT021 ,LEVELDETECT0[21] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 20. " LEVELDETECT020 ,LEVELDETECT0[20] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 19. " LEVELDETECT019 ,LEVELDETECT0[19] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 18. " LEVELDETECT018 ,LEVELDETECT0[18] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 17. " LEVELDETECT017 ,LEVELDETECT0[17] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 16. " LEVELDETECT016 ,LEVELDETECT0[16] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 15. " LEVELDETECT015 ,LEVELDETECT0[15] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 14. " LEVELDETECT014 ,LEVELDETECT0[14] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 13. " LEVELDETECT013 ,LEVELDETECT0[13] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 12. " LEVELDETECT012 ,LEVELDETECT0[12] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 11. " LEVELDETECT011 ,LEVELDETECT0[11] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 10. " LEVELDETECT010 ,LEVELDETECT0[10] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 9. " LEVELDETECT09 ,LEVELDETECT0[9] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 8. " LEVELDETECT08 ,LEVELDETECT0[8] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 7. " LEVELDETECT07 ,LEVELDETECT0[7] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 6. " LEVELDETECT06 ,LEVELDETECT0[6] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 5. " LEVELDETECT05 ,LEVELDETECT0[5] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 4. " LEVELDETECT04 ,LEVELDETECT0[4] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 3. " LEVELDETECT03 ,LEVELDETECT0[3] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 2. " LEVELDETECT02 ,LEVELDETECT0[2] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 1. " LEVELDETECT01 ,LEVELDETECT0[1] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 0. " LEVELDETECT00 ,LEVELDETECT0[0] Low Level Interrupt 31 Enable " "Disabled,Enabled" line.long 0x08 "GPIO_LEVELDETECT1,low-level detection to be used for the interrupt request generation" bitfld.long 0x08 31. " LEVELDETECT131 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 30. " LEVELDETECT130 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 29. " LEVELDETECT129 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 28. " LEVELDETECT128 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 27. " LEVELDETECT127 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 26. " LEVELDETECT126 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 25. " LEVELDETECT125 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 24. " LEVELDETECT124 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 23. " LEVELDETECT123 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 22. " LEVELDETECT122 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 21. " LEVELDETECT121 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 20. " LEVELDETECT120 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 19. " LEVELDETECT119 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 18. " LEVELDETECT118 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 17. " LEVELDETECT117 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 16. " LEVELDETECT116 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 15. " LEVELDETECT115 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 14. " LEVELDETECT114 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 13. " LEVELDETECT113 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 12. " LEVELDETECT112 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 11. " LEVELDETECT111 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 10. " LEVELDETECT110 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 9. " LEVELDETECT11 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 8. " LEVELDETECT18 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 7. " LEVELDETECT17 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 6. " LEVELDETECT16 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 5. " LEVELDETECT15 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 4. " LEVELDETECT14 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 3. " LEVELDETECT13 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 2. " LEVELDETECT12 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 1. " LEVELDETECT11 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 0. " LEVELDETECT10 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" line.long 0x0c "GPIO_RISINGDETECT,rising-edge detection to be used for the interrupt request generation" bitfld.long 0x0c 31. " RISINGDETECT31 ,Rising Edge Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x0c 30. " RISINGDETECT30 ,Rising Edge Interrupt 30 Enable " "Disabled,Enabled" bitfld.long 0x0c 29. " RISINGDETECT29 ,Rising Edge Interrupt 29 Enable " "Disabled,Enabled" bitfld.long 0x0c 28. " RISINGDETECT28 ,Rising Edge Interrupt 28 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 27. " RISINGDETECT27 ,Rising Edge Interrupt 27 Enable " "Disabled,Enabled" bitfld.long 0x0c 26. " RISINGDETECT26 ,Rising Edge Interrupt 26 Enable " "Disabled,Enabled" bitfld.long 0x0c 25. " RISINGDETECT25 ,Rising Edge Interrupt 25 Enable " "Disabled,Enabled" bitfld.long 0x0c 24. " RISINGDETECT24 ,Rising Edge Interrupt 24 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 23. " RISINGDETECT23 ,Rising Edge Interrupt 23 Enable " "Disabled,Enabled" bitfld.long 0x0c 22. " RISINGDETECT22 ,Rising Edge Interrupt 22 Enable " "Disabled,Enabled" bitfld.long 0x0c 21. " RISINGDETECT21 ,Rising Edge Interrupt 21 Enable " "Disabled,Enabled" bitfld.long 0x0c 20. " RISINGDETECT20 ,Rising Edge Interrupt 20 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 19. " RISINGDETECT19 ,Rising Edge Interrupt 19 Enable " "Disabled,Enabled" bitfld.long 0x0c 18. " RISINGDETECT18 ,Rising Edge Interrupt 18 Enable " "Disabled,Enabled" bitfld.long 0x0c 17. " RISINGDETECT17 ,Rising Edge Interrupt 17 Enable " "Disabled,Enabled" bitfld.long 0x0c 16. " RISINGDETECT16 ,Rising Edge Interrupt 16 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 15. " RISINGDETECT15 ,Rising Edge Interrupt 15 Enable " "Disabled,Enabled" bitfld.long 0x0c 14. " RISINGDETECT14 ,Rising Edge Interrupt 14 Enable " "Disabled,Enabled" bitfld.long 0x0c 13. " RISINGDETECT13 ,Rising Edge Interrupt 13 Enable " "Disabled,Enabled" bitfld.long 0x0c 12. " RISINGDETECT12 ,Rising Edge Interrupt 12 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 11. " RISINGDETECT11 ,Rising Edge Interrupt 11 Enable " "Disabled,Enabled" bitfld.long 0x0c 10. " RISINGDETECT10 ,Rising Edge Interrupt 10 Enable " "Disabled,Enabled" bitfld.long 0x0c 9. " RISINGDETECT9 ,Rising Edge Interrupt 9 Enable " "Disabled,Enabled" bitfld.long 0x0c 8. " RISINGDETECT8 ,Rising Edge Interrupt 8 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 7. " RISINGDETECT7 ,Rising Edge Interrupt 7 Enable " "Disabled,Enabled" bitfld.long 0x0c 6. " RISINGDETECT6 ,Rising Edge Interrupt 6 Enable " "Disabled,Enabled" bitfld.long 0x0c 5. " RISINGDETECT5 ,Rising Edge Interrupt 5 Enable " "Disabled,Enabled" bitfld.long 0x0c 4. " RISINGDETECT4 ,Rising Edge Interrupt 4 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 3. " RISINGDETECT3 ,Rising Edge Interrupt 3 Enable " "Disabled,Enabled" bitfld.long 0x0c 2. " RISINGDETECT2 ,Rising Edge Interrupt 2 Enable " "Disabled,Enabled" bitfld.long 0x0c 1. " RISINGDETECT1 ,Rising Edge Interrupt 1 Enable " "Disabled,Enabled" bitfld.long 0x0c 0. " RISINGDETECT0 ,Rising Edge Interrupt 0 Enable " "Disabled,Enabled" line.long 0x10 "GPIO_FALLINGDETECT,falling-edge detection to be used for the interrupt request generation" bitfld.long 0x10 31. " FALLINGDETECT31 ,falling-edge detection 31" "Disabled,Enabled" bitfld.long 0x10 30. " FALLINGDETECT30 ,falling-edge detection 30" "Disabled,Enabled" bitfld.long 0x10 29. " FALLINGDETECT29 ,falling-edge detection 29" "Disabled,Enabled" bitfld.long 0x10 28. " FALLINGDETECT28 ,falling-edge detection 28" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " FALLINGDETECT27 ,falling-edge detection 27" "Disabled,Enabled" bitfld.long 0x10 26. " FALLINGDETECT26 ,falling-edge detection 26" "Disabled,Enabled" bitfld.long 0x10 25. " FALLINGDETECT25 ,falling-edge detection 25" "Disabled,Enabled" bitfld.long 0x10 24. " FALLINGDETECT24 ,falling-edge detection 24" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " FALLINGDETECT23 ,falling-edge detection 23" "Disabled,Enabled" bitfld.long 0x10 22. " FALLINGDETECT22 ,falling-edge detection 22" "Disabled,Enabled" bitfld.long 0x10 21. " FALLINGDETECT21 ,falling-edge detection 21" "Disabled,Enabled" bitfld.long 0x10 20. " FALLINGDETECT20 ,falling-edge detection 20" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " FALLINGDETECT19 ,falling-edge detection 19" "Disabled,Enabled" bitfld.long 0x10 18. " FALLINGDETECT18 ,falling-edge detection 18" "Disabled,Enabled" bitfld.long 0x10 17. " FALLINGDETECT17 ,falling-edge detection 17" "Disabled,Enabled" bitfld.long 0x10 16. " FALLINGDETECT16 ,falling-edge detection 16" "Disabled,Enabled" textline " " bitfld.long 0x10 15. " FALLINGDETECT15 ,falling-edge detection 15" "Disabled,Enabled" bitfld.long 0x10 14. " FALLINGDETECT14 ,falling-edge detection 14" "Disabled,Enabled" bitfld.long 0x10 13. " FALLINGDETECT13 ,falling-edge detection 13" "Disabled,Enabled" bitfld.long 0x10 12. " FALLINGDETECT12 ,falling-edge detection 12" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " FALLINGDETECT11 ,falling-edge detection 11" "Disabled,Enabled" bitfld.long 0x10 10. " FALLINGDETECT10 ,falling-edge detection 10" "Disabled,Enabled" bitfld.long 0x10 9. " FALLINGDETECT9 ,falling-edge detection 9" "Disabled,Enabled" bitfld.long 0x10 8. " FALLINGDETECT8 ,falling-edge detection 8" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " FALLINGDETECT7 ,falling-edge detection 7" "Disabled,Enabled" bitfld.long 0x10 6. " FALLINGDETECT6 ,falling-edge detection 6" "Disabled,Enabled" bitfld.long 0x10 5. " FALLINGDETECT5 ,falling-edge detection 5" "Disabled,Enabled" bitfld.long 0x10 4. " FALLINGDETECT4 ,falling-edge detection 4" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " FALLINGDETECT3 ,falling-edge detection 3" "Disabled,Enabled" bitfld.long 0x10 2. " FALLINGDETECT2 ,falling-edge detection 2" "Disabled,Enabled" bitfld.long 0x10 1. " FALLINGDETECT1 ,falling-edge detection 1" "Disabled,Enabled" bitfld.long 0x10 0. " FALLINGDETECT0 ,falling-edge detection 0" "Disabled,Enabled" line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable register" bitfld.long 0x14 31. " DEBOUNCEENABLE31 ,Input 31 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 30. " DEBOUNCEENABLE30 ,Input 30 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 29. " DEBOUNCEENABLE29 ,Input 29 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 28. " DEBOUNCEENABLE28 ,Input 28 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " DEBOUNCEENABLE27 ,Input 27 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 26. " DEBOUNCEENABLE26 ,Input 26 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 25. " DEBOUNCEENABLE25 ,Input 25 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 24. " DEBOUNCEENABLE24 ,Input 24 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " DEBOUNCEENABLE23 ,Input 23 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 22. " DEBOUNCEENABLE22 ,Input 22 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 21. " DEBOUNCEENABLE21 ,Input 21 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 20. " DEBOUNCEENABLE20 ,Input 20 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " DEBOUNCEENABLE19 ,Input 19 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 18. " DEBOUNCEENABLE18 ,Input 18 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 17. " DEBOUNCEENABLE17 ,Input 17 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 16. " DEBOUNCEENABLE16 ,Input 16 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " DEBOUNCEENABLE15 ,Input 15 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 14. " DEBOUNCEENABLE14 ,Input 14 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 13. " DEBOUNCEENABLE13 ,Input 13 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 12. " DEBOUNCEENABLE12 ,Input 12 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " DEBOUNCEENABLE11 ,Input 11 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 10. " DEBOUNCEENABLE10 ,Input 10 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 9. " DEBOUNCEENABLE9 ,Input 9 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 8. " DEBOUNCEENABLE8 ,Input 8 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " DEBOUNCEENABLE7 ,Input 7 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 6. " DEBOUNCEENABLE6 ,Input 6 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 5. " DEBOUNCEENABLE5 ,Input 5 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 4. " DEBOUNCEENABLE4 ,Input 4 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " DEBOUNCEENABLE3 ,Input 3 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 2. " DEBOUNCEENABLE2 ,Input 2 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 1. " DEBOUNCEENABLE1 ,Input 1 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 0. " DEBOUNCEENABLE0 ,Input 0 Debounce Enable" "Disabled,Enabled" line.long 0x18 "GPIO_DEBOUNCINGTIME,GPIO debouncing time Register" hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value in 31 microsecond steps" group.long 0x190++0x07 line.long 0x00 "GPIO_CLEARDATAOUT,Clear Data Output Register" bitfld.long 0x00 31. " GPIO_CLEARDATAOUT31 ,Clear Data 31 Output Register" "No effect,Clear" bitfld.long 0x00 30. " GPIO_CLEARDATAOUT30 ,Clear Data 30 Output Register" "No effect,Clear" bitfld.long 0x00 29. " GPIO_CLEARDATAOUT29 ,Clear Data 29 Output Register" "No effect,Clear" bitfld.long 0x00 28. " GPIO_CLEARDATAOUT28 ,Clear Data 28 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 27. " GPIO_CLEARDATAOUT27 ,Clear Data 27 Output Register" "No effect,Clear" bitfld.long 0x00 26. " GPIO_CLEARDATAOUT26 ,Clear Data 26 Output Register" "No effect,Clear" bitfld.long 0x00 25. " GPIO_CLEARDATAOUT25 ,Clear Data 25 Output Register" "No effect,Clear" bitfld.long 0x00 24. " GPIO_CLEARDATAOUT24 ,Clear Data 24 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 23. " GPIO_CLEARDATAOUT23 ,Clear Data 23 Output Register" "No effect,Clear" bitfld.long 0x00 22. " GPIO_CLEARDATAOUT22 ,Clear Data 22 Output Register" "No effect,Clear" bitfld.long 0x00 21. " GPIO_CLEARDATAOUT21 ,Clear Data 21 Output Register" "No effect,Clear" bitfld.long 0x00 20. " GPIO_CLEARDATAOUT20 ,Clear Data 20 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 19. " GPIO_CLEARDATAOUT19 ,Clear Data Output 19 Register" "No effect,Clear" bitfld.long 0x00 18. " GPIO_CLEARDATAOUT18 ,Clear Data 18 Output Register" "No effect,Clear" bitfld.long 0x00 17. " GPIO_CLEARDATAOUT17 ,Clear Data 17 Output Register" "No effect,Clear" bitfld.long 0x00 16. " GPIO_CLEARDATAOUT16 ,Clear Data 16 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 15. " GPIO_CLEARDATAOUT15 ,Clear Data 15 Output Register" "No effect,Clear" bitfld.long 0x00 14. " GPIO_CLEARDATAOUT14 ,Clear Data 14 Output Register" "No effect,Clear" bitfld.long 0x00 13. " GPIO_CLEARDATAOUT13 ,Clear Data 13 Output Register" "No effect,Clear" bitfld.long 0x00 12. " GPIO_CLEARDATAOUT12 ,Clear Data 12 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 11. " GPIO_CLEARDATAOUT11 ,Clear Data 11 Output Register" "No effect,Clear" bitfld.long 0x00 10. " GPIO_CLEARDATAOUT10 ,Clear Data 10 Output Register" "No effect,Clear" bitfld.long 0x00 9. " GPIO_CLEARDATAOUT9 ,Clear Data Output 9 Register" "No effect,Clear" bitfld.long 0x00 8. " GPIO_CLEARDATAOUT8 ,Clear Data 8 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 7. " GPIO_CLEARDATAOUT7 ,Clear Data 7 Output Register" "No effect,Clear" bitfld.long 0x00 6. " GPIO_CLEARDATAOUT6 ,Clear Data 6 Output Register" "No effect,Clear" bitfld.long 0x00 5. " GPIO_CLEARDATAOUT5 ,Clear Data 5 Output Register" "No effect,Clear" bitfld.long 0x00 4. " GPIO_CLEARDATAOUT4 ,Clear Data 4 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 3. " GPIO_CLEARDATAOUT3 ,Clear Data 3 Output Register" "No effect,Clear" bitfld.long 0x00 2. " GPIO_CLEARDATAOUT2 ,Clear Data 2 Output Register" "No effect,Clear" bitfld.long 0x00 1. " GPIO_CLEARDATAOUT1 ,Clear Data 1 Output Register" "No effect,Clear" bitfld.long 0x00 0. " GPIO_CLEARDATAOUT0 ,Clear Data 0 Output Register" "No effect,Clear" line.long 0x04 "GPIO_SETDATAOUT,Set Data Output Register" bitfld.long 0x04 31. " GPIO_SETDATAOUT31 ,Set Data 31 Output Register" "No effect,Set" bitfld.long 0x04 30. " GPIO_SETDATAOUT30 ,Set Data 30 Output Register" "No effect,Set" bitfld.long 0x04 29. " GPIO_SETDATAOUT29 ,Set Data 29 Output Register" "No effect,Set" bitfld.long 0x04 28. " GPIO_SETDATAOUT28 ,Set Data 28 Output Register" "No effect,Set" textline " " bitfld.long 0x04 27. " GPIO_SETDATAOUT27 ,Set Data 27 Output Register" "No effect,Set" bitfld.long 0x04 26. " GPIO_SETDATAOUT26 ,Set Data 26 Output Register" "No effect,Set" bitfld.long 0x04 25. " GPIO_SETDATAOUT25 ,Set Data 25 Output Register" "No effect,Set" bitfld.long 0x04 24. " GPIO_SETDATAOUT24 ,Set Data 24 Output Register" "No effect,Set" textline " " bitfld.long 0x04 23. " GPIO_SETDATAOUT23 ,Set Data 23 Output Register" "No effect,Set" bitfld.long 0x04 22. " GPIO_SETDATAOUT22 ,Set Data 22 Output Register" "No effect,Set" bitfld.long 0x04 21. " GPIO_SETDATAOUT21 ,Set Data 21 Output Register" "No effect,Set" bitfld.long 0x04 20. " GPIO_SETDATAOUT20 ,Set Data 20 Output Register" "No effect,Set" textline " " bitfld.long 0x04 19. " GPIO_SETDATAOUT19 ,Set Data 19 Output Register" "No effect,Set" bitfld.long 0x04 18. " GPIO_SETDATAOUT18 ,Set Data 18 Output Register" "No effect,Set" bitfld.long 0x04 17. " GPIO_SETDATAOUT17 ,Set Data 17 Output Register" "No effect,Set" bitfld.long 0x04 16. " GPIO_SETDATAOUT16 ,Set Data 16 Output Register" "No effect,Set" textline " " bitfld.long 0x04 15. " GPIO_SETDATAOUT15 ,Set Data 15 Output Register" "No effect,Set" bitfld.long 0x04 14. " GPIO_SETDATAOUT14 ,Set Data 14 Output Register" "No effect,Set" bitfld.long 0x04 13. " GPIO_SETDATAOUT13 ,Set Data 13 Output Register" "No effect,Set" bitfld.long 0x04 12. " GPIO_SETDATAOUT12 ,Set Data 12 Output Register" "No effect,Set" textline " " bitfld.long 0x04 11. " GPIO_SETDATAOUT11 ,Set Data 11 Output Register" "No effect,Set" bitfld.long 0x04 10. " GPIO_SETDATAOUT10 ,Set Data 10 Output Register" "No effect,Set" bitfld.long 0x04 9. " GPIO_SETDATAOUT9 ,Set Data 9 Output Register" "No effect,Set" bitfld.long 0x04 8. " GPIO_SETDATAOUT8 ,Set Data 8 Output Register" "No effect,Set" textline " " bitfld.long 0x04 7. " GPIO_SETDATAOUT7 ,Set Data 7 Output Register" "No effect,Set" bitfld.long 0x04 6. " GPIO_SETDATAOUT6 ,Set Data 6 Output Register" "No effect,Set" bitfld.long 0x04 5. " GPIO_SETDATAOUT5 ,Set Data 5 Output Register" "No effect,Set" bitfld.long 0x04 4. " GPIO_SETDATAOUT4 ,Set Data 4 Output Register" "No effect,Set" textline " " bitfld.long 0x04 3. " GPIO_SETDATAOUT3 ,Set Data 3 Output Register" "No effect,Set" bitfld.long 0x04 2. " GPIO_SETDATAOUT2 ,Set Data 2 Output Register" "No effect,Set" bitfld.long 0x04 1. " GPIO_SETDATAOUT1 ,Set Data 1 Output Register" "No effect,Set" bitfld.long 0x04 0. " GPIO_SETDATAOUT0 ,Set Data 0 Output Register" "No effect,Set" width 0xb tree.end tree "Port 3" base ad:0x481AE000 width 22. rgroup.long 0x00++0x03 line.long 0x00 "GPIO_REVISION,GPIO Revision Register" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old Scheme and current" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional Number" bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Major revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3" hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision" group.long 0x10++0x03 line.long 0x00 "GPIO_SYSCONFIG,GPIO SysConfig Register" bitfld.long 0x00 3.--4. " IDLEMODE ,Select IDLE mode" "Force Idle,No Idle Mode,Smart-Idle,Smart Idle/Wakeup" bitfld.long 0x00 1. " SOFTRESET ,Software reset mode" "Normal,Reset" bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "free-running,OCP" group.long 0x20++0x3 line.long 0x00 "GPIO_EOI,GPIO_EOI register provides software end of interrupt" sif (cpuis("AM335*")) bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledgement" "Acknowledged,No effect" else bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt control" "0,1" endif group.long 0x24++0xf line.long 0x00 "GPIO_IRQSTATUS_RAW_0,Status Raw Register for interrupt 1" bitfld.long 0x00 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" bitfld.long 0x00 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" bitfld.long 0x00 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" bitfld.long 0x00 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " bitfld.long 0x00 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" bitfld.long 0x00 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" bitfld.long 0x00 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" bitfld.long 0x00 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " bitfld.long 0x00 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" bitfld.long 0x00 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" bitfld.long 0x00 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" bitfld.long 0x00 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " bitfld.long 0x00 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" bitfld.long 0x00 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" bitfld.long 0x00 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" bitfld.long 0x00 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " bitfld.long 0x00 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" bitfld.long 0x00 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" bitfld.long 0x00 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" bitfld.long 0x00 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " bitfld.long 0x00 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" bitfld.long 0x00 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" bitfld.long 0x00 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" bitfld.long 0x00 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " bitfld.long 0x00 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" bitfld.long 0x00 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" bitfld.long 0x00 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" bitfld.long 0x00 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " bitfld.long 0x00 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" bitfld.long 0x00 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" bitfld.long 0x00 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" bitfld.long 0x00 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x04 "GPIO_IRQSTATUS_RAW_1,Status Raw Register for interrupt 1" bitfld.long 0x04 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" bitfld.long 0x04 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" bitfld.long 0x04 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" bitfld.long 0x04 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " bitfld.long 0x04 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" bitfld.long 0x04 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" bitfld.long 0x04 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" bitfld.long 0x04 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " bitfld.long 0x04 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" bitfld.long 0x04 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" bitfld.long 0x04 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" bitfld.long 0x04 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " bitfld.long 0x04 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" bitfld.long 0x04 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" bitfld.long 0x04 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" bitfld.long 0x04 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " bitfld.long 0x04 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" bitfld.long 0x04 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" bitfld.long 0x04 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" bitfld.long 0x04 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " bitfld.long 0x04 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" bitfld.long 0x04 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" bitfld.long 0x04 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" bitfld.long 0x04 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " bitfld.long 0x04 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" bitfld.long 0x04 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" bitfld.long 0x04 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" bitfld.long 0x04 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " bitfld.long 0x04 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" bitfld.long 0x04 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" bitfld.long 0x04 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" bitfld.long 0x04 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x08 "GPIO_IRQSTATUS_0,GPIO_IRQSTATUS_0 register provides core status information for the interrupt handling" setclrfld.long 0x08 31. 0x08 31. 0x10 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" setclrfld.long 0x08 30. 0x08 30. 0x10 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" setclrfld.long 0x08 29. 0x08 29. 0x10 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" setclrfld.long 0x08 28. 0x08 28. 0x10 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " setclrfld.long 0x08 27. 0x08 27. 0x10 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" setclrfld.long 0x08 26. 0x08 26. 0x10 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" setclrfld.long 0x08 25. 0x08 25. 0x10 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" setclrfld.long 0x08 24. 0x08 24. 0x10 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " setclrfld.long 0x08 23. 0x08 23. 0x10 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" setclrfld.long 0x08 22. 0x08 22. 0x10 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" setclrfld.long 0x08 21. 0x08 21. 0x10 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" setclrfld.long 0x08 20. 0x08 20. 0x10 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " setclrfld.long 0x08 19. 0x08 19. 0x10 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" setclrfld.long 0x08 18. 0x08 18. 0x10 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" setclrfld.long 0x08 17. 0x08 17. 0x10 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" setclrfld.long 0x08 16. 0x08 16. 0x10 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " setclrfld.long 0x08 15. 0x08 15. 0x10 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" setclrfld.long 0x08 14. 0x08 14. 0x10 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" setclrfld.long 0x08 13. 0x08 13. 0x10 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" setclrfld.long 0x08 12. 0x08 12. 0x10 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " setclrfld.long 0x08 11. 0x08 11. 0x10 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" setclrfld.long 0x08 10. 0x08 10. 0x10 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" setclrfld.long 0x08 9. 0x08 9. 0x10 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" setclrfld.long 0x08 8. 0x08 8. 0x10 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " setclrfld.long 0x08 7. 0x08 7. 0x10 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" setclrfld.long 0x08 6. 0x08 6. 0x10 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" setclrfld.long 0x08 5. 0x08 5. 0x10 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" setclrfld.long 0x08 4. 0x08 4. 0x10 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " setclrfld.long 0x08 3. 0x08 3. 0x10 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" setclrfld.long 0x08 2. 0x08 2. 0x10 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" setclrfld.long 0x08 1. 0x08 1. 0x10 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" setclrfld.long 0x08 0. 0x08 0. 0x10 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" line.long 0x0c "GPIO_IRQSTATUS_1,GPIO_IRQSTATUS_1 register provides core status information for the interrupt handling" setclrfld.long 0x0c 31. 0x08 31. 0x0c 31. " INTLINE31 ,Interrupt 31 status" "No effect,Triggered" setclrfld.long 0x0c 30. 0x08 30. 0x0c 30. " INTLINE30 ,Interrupt 30 status" "No effect,Triggered" setclrfld.long 0x0c 29. 0x08 29. 0x0c 29. " INTLINE29 ,Interrupt 29 status" "No effect,Triggered" setclrfld.long 0x0c 28. 0x08 28. 0x0c 28. " INTLINE28 ,Interrupt 28 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 27. 0x08 27. 0x0c 27. " INTLINE27 ,Interrupt 27 status" "No effect,Triggered" setclrfld.long 0x0c 26. 0x08 26. 0x0c 26. " INTLINE26 ,Interrupt 26 status" "No effect,Triggered" setclrfld.long 0x0c 25. 0x08 25. 0x0c 25. " INTLINE25 ,Interrupt 25 status" "No effect,Triggered" setclrfld.long 0x0c 24. 0x08 24. 0x0c 24. " INTLINE24 ,Interrupt 24 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 23. 0x08 23. 0x0c 23. " INTLINE23 ,Interrupt 23 status" "No effect,Triggered" setclrfld.long 0x0c 22. 0x08 22. 0x0c 22. " INTLINE22 ,Interrupt 22 status" "No effect,Triggered" setclrfld.long 0x0c 21. 0x08 21. 0x0c 21. " INTLINE21 ,Interrupt 21 status" "No effect,Triggered" setclrfld.long 0x0c 20. 0x08 20. 0x0c 20. " INTLINE20 ,Interrupt 20 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 19. 0x08 19. 0x0c 19. " INTLINE19 ,Interrupt 19 status" "No effect,Triggered" setclrfld.long 0x0c 18. 0x08 18. 0x0c 18. " INTLINE18 ,Interrupt 18 status" "No effect,Triggered" setclrfld.long 0x0c 17. 0x08 17. 0x0c 17. " INTLINE17 ,Interrupt 17 status" "No effect,Triggered" setclrfld.long 0x0c 16. 0x08 16. 0x0c 16. " INTLINE16 ,Interrupt 16 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 15. 0x08 15. 0x0c 15. " INTLINE15 ,Interrupt 15 status" "No effect,Triggered" setclrfld.long 0x0c 14. 0x08 14. 0x0c 14. " INTLINE14 ,Interrupt 14 status" "No effect,Triggered" setclrfld.long 0x0c 13. 0x08 13. 0x0c 13. " INTLINE13 ,Interrupt 13 status" "No effect,Triggered" setclrfld.long 0x0c 12. 0x08 12. 0x0c 12. " INTLINE12 ,Interrupt 12 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 11. 0x08 11. 0x0c 11. " INTLINE11 ,Interrupt 11 status" "No effect,Triggered" setclrfld.long 0x0c 10. 0x08 10. 0x0c 10. " INTLINE10 ,Interrupt 10 status" "No effect,Triggered" setclrfld.long 0x0c 9. 0x08 9. 0x0c 9. " INTLINE9 ,Interrupt 9 status" "No effect,Triggered" setclrfld.long 0x0c 8. 0x08 8. 0x0c 8. " INTLINE8 ,Interrupt 8 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 7. 0x08 7. 0x0c 7. " INTLINE7 ,Interrupt 7 status" "No effect,Triggered" setclrfld.long 0x0c 6. 0x08 6. 0x0c 6. " INTLINE6 ,Interrupt 6 status" "No effect,Triggered" setclrfld.long 0x0c 5. 0x08 5. 0x0c 5. " INTLINE5 ,Interrupt 5 status" "No effect,Triggered" setclrfld.long 0x0c 4. 0x08 4. 0x0c 4. " INTLINE4 ,Interrupt 4 status" "No effect,Triggered" textline " " setclrfld.long 0x0c 3. 0x08 3. 0x0c 3. " INTLINE3 ,Interrupt 3 status" "No effect,Triggered" setclrfld.long 0x0c 2. 0x08 2. 0x0c 2. " INTLINE2 ,Interrupt 2 status" "No effect,Triggered" setclrfld.long 0x0c 1. 0x08 1. 0x0c 1. " INTLINE1 ,Interrupt 1 status" "No effect,Triggered" setclrfld.long 0x0c 0. 0x08 0. 0x0c 0. " INTLINE0 ,Interrupt 0 status" "No effect,Triggered" group.long 0x114++0x03 line.long 0x00 "GPIO_SYSSTATUS,System status register" bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed" group.long 0x130++0x07 line.long 0x00 "GPIO_CTRL,module control register" bitfld.long 0x00 1.--2. " GATINGRATIO ,Controls the clock gating for the event detection logic (divider)" "1,2,4,8" bitfld.long 0x00 0. " DISABLEMODULE ,Module Disable" "No,Yes" line.long 0x04 "GPIO_OE,GPIO output enable register" bitfld.long 0x04 31. " OUTPUTEN31 ,GPIO 31 Output Data Enable" "Output,Input" bitfld.long 0x04 30. " OUTPUTEN30 ,GPIO 30 Output Data Enable" "Output,Input" bitfld.long 0x04 29. " OUTPUTEN29 ,GPIO 29 Output Data Enable" "Output,Input" bitfld.long 0x04 28. " OUTPUTEN28 ,GPIO 28 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 27. " OUTPUTEN27 ,GPIO 27 Output Data Enable" "Output,Input" bitfld.long 0x04 26. " OUTPUTEN26 ,GPIO 26 Output Data Enable" "Output,Input" bitfld.long 0x04 25. " OUTPUTEN25 ,GPIO 25 Output Data Enable" "Output,Input" bitfld.long 0x04 24. " OUTPUTEN24 ,GPIO 24 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 23. " OUTPUTEN23 ,GPIO 23 Output Data Enable" "Output,Input" bitfld.long 0x04 22. " OUTPUTEN22 ,GPIO 22 Output Data Enable" "Output,Input" bitfld.long 0x04 21. " OUTPUTEN21 ,GPIO 21 Output Data Enable" "Output,Input" bitfld.long 0x04 20. " OUTPUTEN20 ,GPIO 20 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 19. " OUTPUTEN19 ,GPIO 19 Output Data Enable" "Output,Input" bitfld.long 0x04 18. " OUTPUTEN18 ,GPIO 18 Output Data Enable" "Output,Input" bitfld.long 0x04 17. " OUTPUTEN17 ,GPIO 17 Output Data Enable" "Output,Input" bitfld.long 0x04 16. " OUTPUTEN16 ,GPIO 16 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 15. " OUTPUTEN15 ,GPIO 15 Output Data Enable" "Output,Input" bitfld.long 0x04 14. " OUTPUTEN14 ,GPIO 14 Output Data Enable" "Output,Input" bitfld.long 0x04 13. " OUTPUTEN13 ,GPIO 13 Output Data Enable" "Output,Input" bitfld.long 0x04 12. " OUTPUTEN12 ,GPIO 12 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 11. " OUTPUTEN11 ,GPIO 11 Output Data Enable" "Output,Input" bitfld.long 0x04 10. " OUTPUTEN10 ,GPIO 10 Output Data Enable" "Output,Input" bitfld.long 0x04 9. " OUTPUTEN9 ,GPIO 9 Output Data Enable" "Output,Input" bitfld.long 0x04 8. " OUTPUTEN8 ,GPIO 8 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 7. " OUTPUTEN7 ,GPIO 7 Output Data Enable" "Output,Input" bitfld.long 0x04 6. " OUTPUTEN6 ,GPIO 6 Output Data Enable" "Output,Input" bitfld.long 0x04 5. " OUTPUTEN5 ,GPIO 5 Output Data Enable" "Output,Input" bitfld.long 0x04 4. " OUTPUTEN4 ,GPIO 4 Output Data Enable" "Output,Input" textline " " bitfld.long 0x04 3. " OUTPUTEN3 ,GPIO 3 Output Data Enable" "Output,Input" bitfld.long 0x04 2. " OUTPUTEN2 ,GPIO 2 Output Data Enable" "Output,Input" bitfld.long 0x04 1. " OUTPUTEN1 ,GPIO 1 Output Data Enable" "Output,Input" bitfld.long 0x04 0. " OUTPUTEN0 ,GPIO 0 Output Data Enable" "Output,Input" rgroup.long 0x138++0x03 line.long 0x00 "GPIO_DATAIN,Sampled Input Data" group.long 0x13c++0x1b line.long 0x00 "GPIO_DATAOUT,Data to set on output pins" line.long 0x04 "GPIO_LEVELDETECT0,low-level detection to be used for the interrupt request generation" bitfld.long 0x04 31. " LEVELDETECT031 ,LEVELDETECT0[31] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 30. " LEVELDETECT030 ,LEVELDETECT0[30] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 29. " LEVELDETECT029 ,LEVELDETECT0[29] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 28. " LEVELDETECT028 ,LEVELDETECT0[28] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 27. " LEVELDETECT027 ,LEVELDETECT0[27] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 26. " LEVELDETECT026 ,LEVELDETECT0[26] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 25. " LEVELDETECT025 ,LEVELDETECT0[25] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 24. " LEVELDETECT024 ,LEVELDETECT0[24] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 23. " LEVELDETECT023 ,LEVELDETECT0[23] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 22. " LEVELDETECT022 ,LEVELDETECT0[22] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 21. " LEVELDETECT021 ,LEVELDETECT0[21] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 20. " LEVELDETECT020 ,LEVELDETECT0[20] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 19. " LEVELDETECT019 ,LEVELDETECT0[19] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 18. " LEVELDETECT018 ,LEVELDETECT0[18] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 17. " LEVELDETECT017 ,LEVELDETECT0[17] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 16. " LEVELDETECT016 ,LEVELDETECT0[16] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 15. " LEVELDETECT015 ,LEVELDETECT0[15] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 14. " LEVELDETECT014 ,LEVELDETECT0[14] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 13. " LEVELDETECT013 ,LEVELDETECT0[13] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 12. " LEVELDETECT012 ,LEVELDETECT0[12] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 11. " LEVELDETECT011 ,LEVELDETECT0[11] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 10. " LEVELDETECT010 ,LEVELDETECT0[10] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 9. " LEVELDETECT09 ,LEVELDETECT0[9] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 8. " LEVELDETECT08 ,LEVELDETECT0[8] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 7. " LEVELDETECT07 ,LEVELDETECT0[7] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 6. " LEVELDETECT06 ,LEVELDETECT0[6] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 5. " LEVELDETECT05 ,LEVELDETECT0[5] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 4. " LEVELDETECT04 ,LEVELDETECT0[4] Low Level Interrupt 31 Enable " "Disabled,Enabled" textline " " bitfld.long 0x04 3. " LEVELDETECT03 ,LEVELDETECT0[3] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 2. " LEVELDETECT02 ,LEVELDETECT0[2] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 1. " LEVELDETECT01 ,LEVELDETECT0[1] Low Level Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x04 0. " LEVELDETECT00 ,LEVELDETECT0[0] Low Level Interrupt 31 Enable " "Disabled,Enabled" line.long 0x08 "GPIO_LEVELDETECT1,low-level detection to be used for the interrupt request generation" bitfld.long 0x08 31. " LEVELDETECT131 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 30. " LEVELDETECT130 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 29. " LEVELDETECT129 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 28. " LEVELDETECT128 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 27. " LEVELDETECT127 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 26. " LEVELDETECT126 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 25. " LEVELDETECT125 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 24. " LEVELDETECT124 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 23. " LEVELDETECT123 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 22. " LEVELDETECT122 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 21. " LEVELDETECT121 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 20. " LEVELDETECT120 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 19. " LEVELDETECT119 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 18. " LEVELDETECT118 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 17. " LEVELDETECT117 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 16. " LEVELDETECT116 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 15. " LEVELDETECT115 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 14. " LEVELDETECT114 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 13. " LEVELDETECT113 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 12. " LEVELDETECT112 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 11. " LEVELDETECT111 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 10. " LEVELDETECT110 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 9. " LEVELDETECT11 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 8. " LEVELDETECT18 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 7. " LEVELDETECT17 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 6. " LEVELDETECT16 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 5. " LEVELDETECT15 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 4. " LEVELDETECT14 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" textline " " bitfld.long 0x08 3. " LEVELDETECT13 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 2. " LEVELDETECT12 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 1. " LEVELDETECT11 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" bitfld.long 0x08 0. " LEVELDETECT10 ,low-level detection to be used for the interrupt request generation " "Disabled,Enabled" line.long 0x0c "GPIO_RISINGDETECT,rising-edge detection to be used for the interrupt request generation" bitfld.long 0x0c 31. " RISINGDETECT31 ,Rising Edge Interrupt 31 Enable " "Disabled,Enabled" bitfld.long 0x0c 30. " RISINGDETECT30 ,Rising Edge Interrupt 30 Enable " "Disabled,Enabled" bitfld.long 0x0c 29. " RISINGDETECT29 ,Rising Edge Interrupt 29 Enable " "Disabled,Enabled" bitfld.long 0x0c 28. " RISINGDETECT28 ,Rising Edge Interrupt 28 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 27. " RISINGDETECT27 ,Rising Edge Interrupt 27 Enable " "Disabled,Enabled" bitfld.long 0x0c 26. " RISINGDETECT26 ,Rising Edge Interrupt 26 Enable " "Disabled,Enabled" bitfld.long 0x0c 25. " RISINGDETECT25 ,Rising Edge Interrupt 25 Enable " "Disabled,Enabled" bitfld.long 0x0c 24. " RISINGDETECT24 ,Rising Edge Interrupt 24 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 23. " RISINGDETECT23 ,Rising Edge Interrupt 23 Enable " "Disabled,Enabled" bitfld.long 0x0c 22. " RISINGDETECT22 ,Rising Edge Interrupt 22 Enable " "Disabled,Enabled" bitfld.long 0x0c 21. " RISINGDETECT21 ,Rising Edge Interrupt 21 Enable " "Disabled,Enabled" bitfld.long 0x0c 20. " RISINGDETECT20 ,Rising Edge Interrupt 20 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 19. " RISINGDETECT19 ,Rising Edge Interrupt 19 Enable " "Disabled,Enabled" bitfld.long 0x0c 18. " RISINGDETECT18 ,Rising Edge Interrupt 18 Enable " "Disabled,Enabled" bitfld.long 0x0c 17. " RISINGDETECT17 ,Rising Edge Interrupt 17 Enable " "Disabled,Enabled" bitfld.long 0x0c 16. " RISINGDETECT16 ,Rising Edge Interrupt 16 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 15. " RISINGDETECT15 ,Rising Edge Interrupt 15 Enable " "Disabled,Enabled" bitfld.long 0x0c 14. " RISINGDETECT14 ,Rising Edge Interrupt 14 Enable " "Disabled,Enabled" bitfld.long 0x0c 13. " RISINGDETECT13 ,Rising Edge Interrupt 13 Enable " "Disabled,Enabled" bitfld.long 0x0c 12. " RISINGDETECT12 ,Rising Edge Interrupt 12 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 11. " RISINGDETECT11 ,Rising Edge Interrupt 11 Enable " "Disabled,Enabled" bitfld.long 0x0c 10. " RISINGDETECT10 ,Rising Edge Interrupt 10 Enable " "Disabled,Enabled" bitfld.long 0x0c 9. " RISINGDETECT9 ,Rising Edge Interrupt 9 Enable " "Disabled,Enabled" bitfld.long 0x0c 8. " RISINGDETECT8 ,Rising Edge Interrupt 8 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 7. " RISINGDETECT7 ,Rising Edge Interrupt 7 Enable " "Disabled,Enabled" bitfld.long 0x0c 6. " RISINGDETECT6 ,Rising Edge Interrupt 6 Enable " "Disabled,Enabled" bitfld.long 0x0c 5. " RISINGDETECT5 ,Rising Edge Interrupt 5 Enable " "Disabled,Enabled" bitfld.long 0x0c 4. " RISINGDETECT4 ,Rising Edge Interrupt 4 Enable " "Disabled,Enabled" textline " " bitfld.long 0x0c 3. " RISINGDETECT3 ,Rising Edge Interrupt 3 Enable " "Disabled,Enabled" bitfld.long 0x0c 2. " RISINGDETECT2 ,Rising Edge Interrupt 2 Enable " "Disabled,Enabled" bitfld.long 0x0c 1. " RISINGDETECT1 ,Rising Edge Interrupt 1 Enable " "Disabled,Enabled" bitfld.long 0x0c 0. " RISINGDETECT0 ,Rising Edge Interrupt 0 Enable " "Disabled,Enabled" line.long 0x10 "GPIO_FALLINGDETECT,falling-edge detection to be used for the interrupt request generation" bitfld.long 0x10 31. " FALLINGDETECT31 ,falling-edge detection 31" "Disabled,Enabled" bitfld.long 0x10 30. " FALLINGDETECT30 ,falling-edge detection 30" "Disabled,Enabled" bitfld.long 0x10 29. " FALLINGDETECT29 ,falling-edge detection 29" "Disabled,Enabled" bitfld.long 0x10 28. " FALLINGDETECT28 ,falling-edge detection 28" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " FALLINGDETECT27 ,falling-edge detection 27" "Disabled,Enabled" bitfld.long 0x10 26. " FALLINGDETECT26 ,falling-edge detection 26" "Disabled,Enabled" bitfld.long 0x10 25. " FALLINGDETECT25 ,falling-edge detection 25" "Disabled,Enabled" bitfld.long 0x10 24. " FALLINGDETECT24 ,falling-edge detection 24" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " FALLINGDETECT23 ,falling-edge detection 23" "Disabled,Enabled" bitfld.long 0x10 22. " FALLINGDETECT22 ,falling-edge detection 22" "Disabled,Enabled" bitfld.long 0x10 21. " FALLINGDETECT21 ,falling-edge detection 21" "Disabled,Enabled" bitfld.long 0x10 20. " FALLINGDETECT20 ,falling-edge detection 20" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " FALLINGDETECT19 ,falling-edge detection 19" "Disabled,Enabled" bitfld.long 0x10 18. " FALLINGDETECT18 ,falling-edge detection 18" "Disabled,Enabled" bitfld.long 0x10 17. " FALLINGDETECT17 ,falling-edge detection 17" "Disabled,Enabled" bitfld.long 0x10 16. " FALLINGDETECT16 ,falling-edge detection 16" "Disabled,Enabled" textline " " bitfld.long 0x10 15. " FALLINGDETECT15 ,falling-edge detection 15" "Disabled,Enabled" bitfld.long 0x10 14. " FALLINGDETECT14 ,falling-edge detection 14" "Disabled,Enabled" bitfld.long 0x10 13. " FALLINGDETECT13 ,falling-edge detection 13" "Disabled,Enabled" bitfld.long 0x10 12. " FALLINGDETECT12 ,falling-edge detection 12" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " FALLINGDETECT11 ,falling-edge detection 11" "Disabled,Enabled" bitfld.long 0x10 10. " FALLINGDETECT10 ,falling-edge detection 10" "Disabled,Enabled" bitfld.long 0x10 9. " FALLINGDETECT9 ,falling-edge detection 9" "Disabled,Enabled" bitfld.long 0x10 8. " FALLINGDETECT8 ,falling-edge detection 8" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " FALLINGDETECT7 ,falling-edge detection 7" "Disabled,Enabled" bitfld.long 0x10 6. " FALLINGDETECT6 ,falling-edge detection 6" "Disabled,Enabled" bitfld.long 0x10 5. " FALLINGDETECT5 ,falling-edge detection 5" "Disabled,Enabled" bitfld.long 0x10 4. " FALLINGDETECT4 ,falling-edge detection 4" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " FALLINGDETECT3 ,falling-edge detection 3" "Disabled,Enabled" bitfld.long 0x10 2. " FALLINGDETECT2 ,falling-edge detection 2" "Disabled,Enabled" bitfld.long 0x10 1. " FALLINGDETECT1 ,falling-edge detection 1" "Disabled,Enabled" bitfld.long 0x10 0. " FALLINGDETECT0 ,falling-edge detection 0" "Disabled,Enabled" line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable register" bitfld.long 0x14 31. " DEBOUNCEENABLE31 ,Input 31 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 30. " DEBOUNCEENABLE30 ,Input 30 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 29. " DEBOUNCEENABLE29 ,Input 29 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 28. " DEBOUNCEENABLE28 ,Input 28 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 27. " DEBOUNCEENABLE27 ,Input 27 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 26. " DEBOUNCEENABLE26 ,Input 26 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 25. " DEBOUNCEENABLE25 ,Input 25 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 24. " DEBOUNCEENABLE24 ,Input 24 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 23. " DEBOUNCEENABLE23 ,Input 23 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 22. " DEBOUNCEENABLE22 ,Input 22 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 21. " DEBOUNCEENABLE21 ,Input 21 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 20. " DEBOUNCEENABLE20 ,Input 20 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 19. " DEBOUNCEENABLE19 ,Input 19 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 18. " DEBOUNCEENABLE18 ,Input 18 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 17. " DEBOUNCEENABLE17 ,Input 17 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 16. " DEBOUNCEENABLE16 ,Input 16 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 15. " DEBOUNCEENABLE15 ,Input 15 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 14. " DEBOUNCEENABLE14 ,Input 14 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 13. " DEBOUNCEENABLE13 ,Input 13 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 12. " DEBOUNCEENABLE12 ,Input 12 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 11. " DEBOUNCEENABLE11 ,Input 11 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 10. " DEBOUNCEENABLE10 ,Input 10 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 9. " DEBOUNCEENABLE9 ,Input 9 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 8. " DEBOUNCEENABLE8 ,Input 8 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 7. " DEBOUNCEENABLE7 ,Input 7 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 6. " DEBOUNCEENABLE6 ,Input 6 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 5. " DEBOUNCEENABLE5 ,Input 5 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 4. " DEBOUNCEENABLE4 ,Input 4 Debounce Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " DEBOUNCEENABLE3 ,Input 3 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 2. " DEBOUNCEENABLE2 ,Input 2 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 1. " DEBOUNCEENABLE1 ,Input 1 Debounce Enable" "Disabled,Enabled" bitfld.long 0x14 0. " DEBOUNCEENABLE0 ,Input 0 Debounce Enable" "Disabled,Enabled" line.long 0x18 "GPIO_DEBOUNCINGTIME,GPIO debouncing time Register" hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value in 31 microsecond steps" group.long 0x190++0x07 line.long 0x00 "GPIO_CLEARDATAOUT,Clear Data Output Register" bitfld.long 0x00 31. " GPIO_CLEARDATAOUT31 ,Clear Data 31 Output Register" "No effect,Clear" bitfld.long 0x00 30. " GPIO_CLEARDATAOUT30 ,Clear Data 30 Output Register" "No effect,Clear" bitfld.long 0x00 29. " GPIO_CLEARDATAOUT29 ,Clear Data 29 Output Register" "No effect,Clear" bitfld.long 0x00 28. " GPIO_CLEARDATAOUT28 ,Clear Data 28 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 27. " GPIO_CLEARDATAOUT27 ,Clear Data 27 Output Register" "No effect,Clear" bitfld.long 0x00 26. " GPIO_CLEARDATAOUT26 ,Clear Data 26 Output Register" "No effect,Clear" bitfld.long 0x00 25. " GPIO_CLEARDATAOUT25 ,Clear Data 25 Output Register" "No effect,Clear" bitfld.long 0x00 24. " GPIO_CLEARDATAOUT24 ,Clear Data 24 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 23. " GPIO_CLEARDATAOUT23 ,Clear Data 23 Output Register" "No effect,Clear" bitfld.long 0x00 22. " GPIO_CLEARDATAOUT22 ,Clear Data 22 Output Register" "No effect,Clear" bitfld.long 0x00 21. " GPIO_CLEARDATAOUT21 ,Clear Data 21 Output Register" "No effect,Clear" bitfld.long 0x00 20. " GPIO_CLEARDATAOUT20 ,Clear Data 20 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 19. " GPIO_CLEARDATAOUT19 ,Clear Data Output 19 Register" "No effect,Clear" bitfld.long 0x00 18. " GPIO_CLEARDATAOUT18 ,Clear Data 18 Output Register" "No effect,Clear" bitfld.long 0x00 17. " GPIO_CLEARDATAOUT17 ,Clear Data 17 Output Register" "No effect,Clear" bitfld.long 0x00 16. " GPIO_CLEARDATAOUT16 ,Clear Data 16 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 15. " GPIO_CLEARDATAOUT15 ,Clear Data 15 Output Register" "No effect,Clear" bitfld.long 0x00 14. " GPIO_CLEARDATAOUT14 ,Clear Data 14 Output Register" "No effect,Clear" bitfld.long 0x00 13. " GPIO_CLEARDATAOUT13 ,Clear Data 13 Output Register" "No effect,Clear" bitfld.long 0x00 12. " GPIO_CLEARDATAOUT12 ,Clear Data 12 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 11. " GPIO_CLEARDATAOUT11 ,Clear Data 11 Output Register" "No effect,Clear" bitfld.long 0x00 10. " GPIO_CLEARDATAOUT10 ,Clear Data 10 Output Register" "No effect,Clear" bitfld.long 0x00 9. " GPIO_CLEARDATAOUT9 ,Clear Data Output 9 Register" "No effect,Clear" bitfld.long 0x00 8. " GPIO_CLEARDATAOUT8 ,Clear Data 8 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 7. " GPIO_CLEARDATAOUT7 ,Clear Data 7 Output Register" "No effect,Clear" bitfld.long 0x00 6. " GPIO_CLEARDATAOUT6 ,Clear Data 6 Output Register" "No effect,Clear" bitfld.long 0x00 5. " GPIO_CLEARDATAOUT5 ,Clear Data 5 Output Register" "No effect,Clear" bitfld.long 0x00 4. " GPIO_CLEARDATAOUT4 ,Clear Data 4 Output Register" "No effect,Clear" textline " " bitfld.long 0x00 3. " GPIO_CLEARDATAOUT3 ,Clear Data 3 Output Register" "No effect,Clear" bitfld.long 0x00 2. " GPIO_CLEARDATAOUT2 ,Clear Data 2 Output Register" "No effect,Clear" bitfld.long 0x00 1. " GPIO_CLEARDATAOUT1 ,Clear Data 1 Output Register" "No effect,Clear" bitfld.long 0x00 0. " GPIO_CLEARDATAOUT0 ,Clear Data 0 Output Register" "No effect,Clear" line.long 0x04 "GPIO_SETDATAOUT,Set Data Output Register" bitfld.long 0x04 31. " GPIO_SETDATAOUT31 ,Set Data 31 Output Register" "No effect,Set" bitfld.long 0x04 30. " GPIO_SETDATAOUT30 ,Set Data 30 Output Register" "No effect,Set" bitfld.long 0x04 29. " GPIO_SETDATAOUT29 ,Set Data 29 Output Register" "No effect,Set" bitfld.long 0x04 28. " GPIO_SETDATAOUT28 ,Set Data 28 Output Register" "No effect,Set" textline " " bitfld.long 0x04 27. " GPIO_SETDATAOUT27 ,Set Data 27 Output Register" "No effect,Set" bitfld.long 0x04 26. " GPIO_SETDATAOUT26 ,Set Data 26 Output Register" "No effect,Set" bitfld.long 0x04 25. " GPIO_SETDATAOUT25 ,Set Data 25 Output Register" "No effect,Set" bitfld.long 0x04 24. " GPIO_SETDATAOUT24 ,Set Data 24 Output Register" "No effect,Set" textline " " bitfld.long 0x04 23. " GPIO_SETDATAOUT23 ,Set Data 23 Output Register" "No effect,Set" bitfld.long 0x04 22. " GPIO_SETDATAOUT22 ,Set Data 22 Output Register" "No effect,Set" bitfld.long 0x04 21. " GPIO_SETDATAOUT21 ,Set Data 21 Output Register" "No effect,Set" bitfld.long 0x04 20. " GPIO_SETDATAOUT20 ,Set Data 20 Output Register" "No effect,Set" textline " " bitfld.long 0x04 19. " GPIO_SETDATAOUT19 ,Set Data 19 Output Register" "No effect,Set" bitfld.long 0x04 18. " GPIO_SETDATAOUT18 ,Set Data 18 Output Register" "No effect,Set" bitfld.long 0x04 17. " GPIO_SETDATAOUT17 ,Set Data 17 Output Register" "No effect,Set" bitfld.long 0x04 16. " GPIO_SETDATAOUT16 ,Set Data 16 Output Register" "No effect,Set" textline " " bitfld.long 0x04 15. " GPIO_SETDATAOUT15 ,Set Data 15 Output Register" "No effect,Set" bitfld.long 0x04 14. " GPIO_SETDATAOUT14 ,Set Data 14 Output Register" "No effect,Set" bitfld.long 0x04 13. " GPIO_SETDATAOUT13 ,Set Data 13 Output Register" "No effect,Set" bitfld.long 0x04 12. " GPIO_SETDATAOUT12 ,Set Data 12 Output Register" "No effect,Set" textline " " bitfld.long 0x04 11. " GPIO_SETDATAOUT11 ,Set Data 11 Output Register" "No effect,Set" bitfld.long 0x04 10. " GPIO_SETDATAOUT10 ,Set Data 10 Output Register" "No effect,Set" bitfld.long 0x04 9. " GPIO_SETDATAOUT9 ,Set Data 9 Output Register" "No effect,Set" bitfld.long 0x04 8. " GPIO_SETDATAOUT8 ,Set Data 8 Output Register" "No effect,Set" textline " " bitfld.long 0x04 7. " GPIO_SETDATAOUT7 ,Set Data 7 Output Register" "No effect,Set" bitfld.long 0x04 6. " GPIO_SETDATAOUT6 ,Set Data 6 Output Register" "No effect,Set" bitfld.long 0x04 5. " GPIO_SETDATAOUT5 ,Set Data 5 Output Register" "No effect,Set" bitfld.long 0x04 4. " GPIO_SETDATAOUT4 ,Set Data 4 Output Register" "No effect,Set" textline " " bitfld.long 0x04 3. " GPIO_SETDATAOUT3 ,Set Data 3 Output Register" "No effect,Set" bitfld.long 0x04 2. " GPIO_SETDATAOUT2 ,Set Data 2 Output Register" "No effect,Set" bitfld.long 0x04 1. " GPIO_SETDATAOUT1 ,Set Data 1 Output Register" "No effect,Set" bitfld.long 0x04 0. " GPIO_SETDATAOUT0 ,Set Data 0 Output Register" "No effect,Set" width 0xb tree.end tree.end textline ""